Semiconductor structure and formation method thereof

Abstract

A method includes: forming a gate stack over a semiconductor region; performing an epitaxial process to form a source / drain region adjacent to the gate stack; forming a source / drain contact plug over and electrically coupled to the source / drain region; forming a gate contact plug over and electrically coupled to the gate stack; and selectively forming an inhibitor film on a dielectric layer adjacent to a conductive feature. The conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug. An etch stop layer is selectively deposited on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from depositing on the conductive feature. The inhibitor film is then removed.

Description

Prior Art

[0001] Transistors are basic building blocks in integrated circuits. In the development of integrated circuits, Fin Field-Effect Transistors (FinFETs) and Gate-All-Around (GAA) transistors have been used to replace planar transistors. In FinFET formation, semiconductor fins are formed, and dummy gates are formed on the semiconductor fins. The formation of the dummy gates may include depositing a dummy layer such as a polysilicon layer and then patterning the dummy layer as a dummy gate. Gate spacers are formed on the sidewalls of the dummy gate stack. Source / drain regions are formed on the semiconductor fins via epitaxy. The dummy gate stack is then removed to form a trench between the gate spacers. A replacement gate is then formed in the trench. Simple diagram description

[0002] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion. Figures 1 to 8, Figure 9A, Figure 9B, Figure 9C, Figure 10A, Figure 10B, Figure 11A, Figure 11B, Figure 12A, Figure 12B, Figure 12C, Figures 13 to 15, Figures 16A, Figure 16B, Figure 17A, Figure 17B, Figure 18A, Figure 18B, Figure 19A-1, Figure 19A-2 and Figure 19B illustrate views of intermediate stages in the formation of Fin Field-Effect Transistor (FinFET) and contact plugs according to some embodiments. FIG20 is a cross-sectional view of a Gate All-Around (GAA) transistor according to some embodiments. FIG. 21 illustrates a top view of some features according to some embodiments. FIG. 22 illustrates a process flow for forming a transistor according to some embodiments. Implementation

[0003] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0004] Additionally, spatially relative terms, such as "underlying," "beneath," "lower," "overlying," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0005] Transistors, respective contact plugs, and methods of forming transistors and contact plugs are provided. According to some embodiments, conductive features such as epitaxial source / drain, gate contact plugs, and source / drain contact plugs are formed. An inhibitor film is selectively formed on a dielectric region adjacent to the conductive features. An etch stop layer is selectively formed on the conductive features. Due to the presence of the inhibitor film, the etch stop layer is formed away from the dielectric region. Since the etch stop layer can have a higher dielectric row number (k value) than the adjacent dielectric region, by reducing the size of the etch stop layer, parasitic capacitance between the conductive features can be reduced. The resistance of the conductive plug can also be reduced.

[0006] It should be understood that although Fin Field-Effect Transistor (FinFET) is discussed as an example, the embodiments may also be applicable to other types of transistors, such as planar transistors, Gate-All-Around (GAA) transistors, or the like. The embodiments discussed herein provide examples to enable the manufacture or use of the subject matter of the present disclosure, and those skilled in the art will readily understand that modifications may be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, similar reference numbers are used to designate similar elements. Although method embodiments may be discussed as being performed in a particular order, other methods may be performed in any logical order.

[0007] 1-8, 9A, 9B, 9C, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13-15, 16A, 16B, 17A, 17B, 18A, 18B, 19A-1, 19A-2, and 19B illustrate views of intermediate stages in the formation of FinFETs and contact plugs according to some embodiments. The corresponding processes are also schematically reflected in the process flow 200 as shown in FIG. 22.

[0008] Referring to FIG. 1 , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be part of a wafer 10, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; a compound semiconductor including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof.

[0009] Referring to FIG. 2 , an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. The isolation region 24 is hereinafter alternatively referred to as a shallow trench isolation (STI) region. The respective process diagrams are process 202 in the process flow 200 as shown in FIG. 22 . The portion between adjacent STI regions 24 of the substrate 20 is collectively referred to as a semiconductor strip 26. To form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. The hard mask layer 30 may be formed of silicon nitride.

[0010] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with a dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process may then be performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material are the STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, or the like formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. The dielectric material over the liner dielectric may include silicon oxide according to some embodiments.

[0011] Semiconductor strips 26 are between adjacent STI regions 24. According to some embodiments, semiconductor strips 26 are portions of the initial substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 between STI regions 24 to form recesses, and performing epitaxy in the recesses to regrow another semiconductor material. Thus, semiconductor strips 26 are formed of a semiconductor material different from the material of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, carbon-doped silicon, or III-V compound semiconductor materials.

[0012] Referring to FIG. 3 , the STI region 24 is recessed. The top portion of the semiconductor strip 26 thus protrudes above the top surface 24T of the remaining portion of the STI region 24 to form a protruding fin 36. The respective process diagram is process 204 in the process flow 200 as shown in FIG. 22 . The etching can be performed using a dry etching process, wherein HF and NH 3 are used as etching gases, for example. During the etching process, a plasma can be generated. Argon can also be included. According to an alternative embodiment, the recessing of the STI region 24 is performed using a wet etching process. For example, the etching chemical can include HF. The top surface and the bottom surface of the STI region 24 are referred to as 24T and 24B, respectively.

[0013] In the embodiments illustrated above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more optical lithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine optical lithography and self-alignment processes, thereby allowing patterns to be produced that have, for example, spacings that are smaller than would otherwise be obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0014] FIGS. 4-6 illustrate forming a dummy gate stack 44 according to some embodiments. Referring to FIG. 4 , a dummy dielectric layer 38 is formed on the sidewalls and top surface of the protruding fin 36 and may be on the top surface of the STI region 24. The respective process diagrams are process 206 in the process flow 200 as shown in FIG. 22 . According to some embodiments, the dummy dielectric layer 38 is formed by a deposition process, which may include chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The material of the dummy dielectric layer 38 may include silicon oxide, but other dielectric materials such as silicon nitride, silicon oxynitride, or the like may also be used.

[0015] FIG. 5 illustrates the deposition of the dummy gate electrode layer 40. Respective process diagrams are shown as process 208 in the process flow 200 as shown in FIG. 22. The dummy gate electrode layer 40 may be formed of or include polycrystalline silicon or amorphous silicon, but other materials may also be used. The formation process may include a deposition process followed by a planarization process. A hard mask layer 42 is then deposited on the dummy gate electrode layer 40. Respective process diagrams are shown as process 212 in the process flow 200 as shown in FIG. 22. The hard mask layer 42 may be formed of or include silicon nitride, silicon oxide, silicon oxycarbonitride, or multiple layers thereof.

[0016] FIG. 6 illustrates a patterning process for forming the dummy gate stack 44. The respective process diagram is process 210 as depicted in the process flow 200 in FIG. 22. According to some embodiments, the hard mask layer 42 is first patterned, for example, using a patterned photoresist (not shown) as an etch mask. The resulting hard mask is referred to as hard mask 42'. The hard mask 42' is then used as an etch mask to etch the underlying dummy gate electrode layer 40 to form the dummy gate electrode 40'. The etching is performed using an anisotropic etching process.

[0017] According to an alternative embodiment, the patterning of the dummy gate electrode layer 40 stops on the dummy gate dielectric layer 38, and the dummy gate dielectric layer 38 is not patterned. The gate spacers formed subsequently will be formed on the unpatterned dummy gate dielectric layer 38.

[0018] Next, as shown in FIG. 7 , a gate spacer 46 is formed on the sidewalls of the dummy gate stack 44. The respective process diagrams are process 212 in the process flow 200 as shown in FIG. 22 . According to some embodiments, the gate spacer 46 is formed of a dielectric material such as silicon nitride, silicon carbonitride, or the like and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0019] Referring to FIG. 8 , an etching process is performed to recess the protruding fin 36 . The respective process diagram is process 214 in the process flow 200 as depicted in FIG. 22 . If there is any portion of the dummy gate dielectric layer 38 that is not directly underlying the dummy gate stack 44 and the gate spacer 46 , the exposed portion of the dummy gate dielectric layer 38 is also removed. Portions of the protruding fin 36 that are not covered by the dummy gate stack 44 and the gate spacer 46 are also etched. The recess may be anisotropic, and thus portions of the protruding fin 36 that are directly underlying the dummy gate stack 44 and the gate spacer 46 are protected and not etched. The top surface of the recessed semiconductor strip 26 may be lower than the top surface 24T of the STI region 24 according to some embodiments. Thus, a recess 50 is formed. The recess 50 includes portions on opposite sides of the dummy gate stack 44 and portions between the remaining portions of the protruding fin 36 . There may or may not be remaining fin spacers on the opposite side of the recess 50, which are not shown.

[0020] Next, as shown in FIG. 9C, epitaxial regions (source / drain regions) 54 are formed by selectively growing (via epitaxy) semiconductor material starting from the recess 50. The respective process diagrams are process 216 in the process flow 200 as shown in FIG. 22. FIG. 9A and FIG. 9B illustrate vertical cross-sections 9A-9A and 9B-9B, respectively, of the structure shown in FIG. 9C.

[0021] Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, different materials may be grown epitaxially. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), or the like may be grown. According to alternative embodiments, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof.

[0022] After the recess 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 may cause the epitaxial region 54 to expand horizontally and a facet may be formed. Further growth of the epitaxial region 54 may also cause adjacent epitaxial regions 54 to merge. A void (air gap) 56 may be generated. After the epitaxial step, the epitaxial region 54 may be further implanted with p-type or n-type impurities, the epitaxial region 54 also being designated using reference numeral 54. According to an alternative embodiment, the implantation step is skipped when the epitaxial region 54 is in-situ doped with p-type or n-type impurities during epitaxy.

[0023] Next, as shown in FIG. 10A and FIG. 10B, an inhibitor film 57 is selectively formed. The respective process diagram is process 218 in process flow 200 as shown in FIG. 22. According to some embodiments, the inhibitor film 57 is formed by a deposition process, in which the wafer 10 is exposed and immersed in a process gas (precursor) so that the inhibitor film 57 is deposited thereon. The deposition is performed without switching on the plasma. Depending on the process gas, the deposition temperature may be in the range between about 50° C. and about 300° C., or in the range between about 50° C. and about 200° C. The deposition time may be in the range between about 30 seconds and about 60 minutes. In the deposition, the flow rate of the process gas may be in the range between about 500 sccm and about 10,000 sccm.

[0024] The process gas may include silane-based materials, amine-based materials, phosphate-based materials, and / or thiol-based materials. Example process gases may include Si-Cl based process gases including octadecyltrichlorosilane (CH3(CH2)17SiCl3), trichloro(1H,1H,2H,2H-perfluorooctyl)silane (CF3(CF2)5(CH2)2SiCl3), dimethyldichlorosilane ((CH3)2SiCl2), (dimethylamino)trimethylsilane ((CH3)2NSi(CH3)3), 1-(trimethylsilyl)pyrrolidine ((CH3)3Si-NC4H8), hexamethyldisilane ([(CH3)3Si]2NH), bis(dimethylamino)dimethylsilane ([(CH3)2N]2Si(CH3)2), or the like, or combinations thereof.

[0025] According to an alternative embodiment, the inhibitor film 57 is formed by immersing the wafer 10 in a chemical solution, wherein one or more of the chemical substances or Si-N-based chemical substances discussed above are dissolved in a solvent. The solvent may include acetone or isopropyl alcohol (IPA). In some other embodiments, the solvent may include deionized water. The immersion time may be in the range of about 30 seconds to about 60 minutes.

[0026] According to some embodiments, the exposed dielectric material of the wafer 10 has OH bonds at its surface, which dielectric material may include silicon and / or oxide. The exposed material may be included in the gate spacer 46, the hard mask 42', and the STI region 24. In the formation of the inhibitor film 57, the OH bonds are broken, and the oxygen atoms on the surface of the exposed dielectric material are bonded to the molecules in the precursor to form the inhibitor film 57. The functional groups in the precursor are thus attached to the oxygen in the underlying dielectric layer such as in the gate spacer 46, the hard mask 42', and the STI region 24, thereby forming the inhibitor film 57.

[0027] However, on the source / drain region 54, no OH bonds exist, and such reactions do not occur on the source / drain region 54, although the source / drain region 54 is also exposed to the same precursor. Therefore, the inhibitor film 57 is selectively formed on the exposed semiconductor regions, such as the top surface and sidewalls of the gate spacer 46, the hard mask 42', and the STI region 24, but not on the source / drain region 54. The inhibitor film 57 may be formed as a self-assembled-monolayer (SAM). The respective processes may also be referred to as SAM processes in which the previously attached molecules terminate the dangling bonds of oxygen, and thus there may not be more layers of the inhibitor film 57 formed thereon. The formation of the inhibitor film 57 may thus be self-terminating. Depending on the size of the attached molecules, the inhibitor film 57 may have a thickness ranging from about 0.3 nm to about 2 nm.

[0028] The inhibitor film 57 is thus selectively formed / deposited. In addition, the inhibitor film 57 may be an organic film and may include functional groups CH 3, CH 2, CF 2 or a combination thereof. The inhibitor film 57 may also include a carbon chain (and a CH 3 chain) in which a plurality of carbon atoms are linked to form a chain.

[0029] FIGS. 11A and 11B illustrate the selective deposition of a contact etch stop layer (CESL) 58 according to some embodiments. The respective process diagrams are process 220 as depicted in process flow 200 in FIG. 22 . CESL 58 is also an etch stop layer used to stop etching in subsequent processes. According to some embodiments, the formation process may include a thermal deposition process such as a Chemical Vapor Deposition (CVD) process, an Atomic Vapor Deposition (CVD) process, or the like. The deposited CESL 58 may include silicon nitride, silicon carbonitride, silicon oxycarbonitride, or the like, wherein corresponding precursors are directed to produce a reaction.

[0030] Due to the presence of the inhibitor film 57, the CESL 58 is selectively grown where the inhibitor film 57 is not formed, and is thus formed on the source / drain region 54. According to some embodiments, as shown in FIG. 11B , the source / drain region 54 may include an upward surface, and may or may not include a downward surface. The downward surface may be a surface having a downward facet.

[0031] According to some embodiments, depending on the deposition method and process conditions, the formation of CESL 58 is conformal and thus both the upper and lower surfaces have CESL 58 grown thereon. According to alternative embodiments, the upper surfaces of source / drain regions 54 have CESL 58A grown thereon, while some or all portions of the lower surfaces of source / drain regions 54 do not have CESL thereon. Therefore, portions 58B of CESL 58 are marked in dashed form to indicate that these portions may or may not be formed.

[0032] Next, the inhibitor film 57 is removed. The respective process diagrams are process 222 in process flow 200 as depicted in FIG. 22. FIG. 12A, FIG. 12B, and FIG. 12C illustrate the resulting structure. Depending on the thickness of the inhibitor film 57, the CESL 58 may or may not extend into the region 59 previously occupied by the inhibitor film 57. In other words, the CESL 58 may be separated from the nearest dielectric feature by the space in the region 59. According to some embodiments, the removal of the inhibitor film 57 is performed via a thermal process. For example, the temperature may be above about 200° C. or above about 300° C. A process gas including O 2, H 2, N 2, or the like, or a combination thereof, may be used. Thus, the inhibitor film 57 is decomposed into a gas and removed. [ , , ]

[0033] FIG. 13 illustrates a perspective view of forming an inter-layer dielectric (ILD) 60. Individual process diagrams are process 224 in process flow 200 as shown in FIG. 22. ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another suitable deposition method. ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as silicon oxide, phospho-silicon glass (PSG), boro-silicon glass (BSG), boron-doped phospho-silicon glass (BPSG), or the like. A planarization process such as a CMP process or a mechanical polishing process may then be performed to make the top surfaces of ILD 60, dummy gate stack 44, and gate spacer 46 flush with each other. Due to the selective formation of CESL 58, ILD 60 may be in physical contact with the top surface of STI region 24. As shown in FIG. 13 , ILD 60 may be in physical contact with source / drain region 54 at the bottom of the downwardly facing facet of source / drain region 54.

[0034] The hard mask 42', the dummy gate electrode 40' and the dummy dielectric 38' are then removed, thereby forming a trench 62 between the gate spacers 46, as shown in FIG. 14. The respective process diagram is process 226 in the process flow 200 as shown in FIG. 22. According to some embodiments, similar to the patterning process as shown in FIG. 6, the removal of the dummy gate electrode 40' is performed using an anisotropic etching process. According to alternative embodiments, the removal of the dummy gate electrode 40' is performed using an isotropic etching process, which can be a wet etching process or a dry etching process. After removing the dummy gate electrode 40', the dummy gate dielectric 38' is exposed through the trench 62.

[0035] Next, the dummy gate dielectric 38' is removed. According to some embodiments, the etching process may be anisotropic, and the process gas may include a mixture of NF3 and NH3, or a mixture of HF and NH3. The etching process may include an isotropic effect and an anisotropic effect to ensure the removal of the sidewall portion of the dummy gate dielectric 38'. According to alternative embodiments, an isotropic etching process such as a wet etching process may be used. For example, an HF solution may be used. The top surface and sidewalls of the protruding semiconductor wafer 36 are thus exposed to the trench 62, as shown in FIG. 14.

[0036] Next, as shown in FIG. 15 , a replacement gate stack 68 is formed. A respective process diagram is shown as process 228 in process flow 200 as shown in FIG. 22 . According to some embodiments, the replacement gate stack 68 includes a gate dielectric 64 and a gate electrode 66. The gate dielectric 64 may further include an interfacial layer (IL) and a high-k dielectric on the IL. According to some embodiments, the formation of the IL is performed via an oxidation process. The IL may include silicon oxide (SiO 2). According to some embodiments, the IL is deposited. Next, a high-k dielectric layer is deposited over the IL. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like.

[0037] The gate electrode 66 is formed on and contacts the gate dielectric 64. The gate electrode 66 may include stacked layers, which may include a diffusion barrier layer (cap layer, not shown) and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of TiN, TiSiN, or the like.

[0038] The work function layer determines the work function of the gate electrode 66 and includes at least one layer, or a plurality of layers formed of different materials. The material of the work function layer can be selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminide (TiAl) layer on the TaN. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer and possibly a TiN layer.

[0039] After depositing the work function layer, a blocking layer (such as a TiN layer) and a metal filling region are deposited to fully fill the trench 62. Then, a planarization process such as a CMP process or a mechanical polishing process is performed so that the top surface of the gate stack 68 is coplanar with the top surface of the ILD 60. Thus, the FinFET 100 is formed.

[0040] According to some embodiments, as shown in FIG. 15 , the replacement gate stack 68 is etched back, resulting in a recess formed between the opposing gate spacers 46 . Next, a hard mask 70 is formed over the replacement gate stack 68 . The hard mask 70 is self-aligned with the underlying gate stack 68 . The respective process is illustrated as process 230 in the process flow 200 as illustrated in FIG. 22 . According to some embodiments, forming the hard mask 70 includes a deposition process to form a blanket dielectric material filling the recess; and a planarization process to remove excess dielectric material over the gate spacers 46 and the ILD 60 . The hard mask 70 may be formed of, for example, silicon nitride or other similar dielectric materials. According to an alternative embodiment, the replacement gate stack 68 is not recessed, and the hard mask 70 is not formed. Therefore, the hard mask 70 is illustrated as a dashed line to indicate that the hard mask 70 may or may not be formed.

[0041] In a subsequent process, the ILD 60 and CESL 58 are etched to form source / drain contact openings 71, as shown in FIGS. 16A and 16B. The respective process diagrams are process 232 in the process flow 200 as shown in FIG. 22. The location of the source / drain contact openings 71 is further shown in FIG. 15. In the formation process, an etching process is performed to etch the ILD 60 and form the source / drain contact openings 71 and the etching stops on the CESL 58. Next, the CESL 58 is etched to reveal the underlying source / drain regions 54.

[0042] In subsequent processes, as shown in FIGS. 16A and 16B, a source / drain silicide layer 72 is formed. The respective process diagrams are process 234 in the process flow 200 shown in FIG. 22. Forming the recess may include: depositing a metal layer extending into the opening 71 to contact the source / drain region 54, performing an annealing process to react the metal layer with the source / drain region 54 and form the source / drain silicide layer 72, and removing the metal layer.

[0043] FIGS. 17A and 17B illustrate (lower) the formation of source / drain contact plugs 74. The respective process diagrams are process 236 in process flow 200 as depicted in FIG. 22. According to some embodiments, the formation process may include: depositing a conductive material, which may include a metal material such as tungsten, cobalt, or the like; and performing a CMP process to remove excess portions of the metal material. A conductive barrier layer such as a TiN layer may (or may not) be formed after the deposition of the conductive material.

[0044] According to some embodiments, due to the selective formation of CESL 58, CESL 58 does not include vertical portions on the sidewalls of gate spacer 46 (FIG. 12A and FIG. 12C). This has two benefits. First, if CESL 58 has vertical portions on the sidewalls of gate spacer 46, the vertical portions will occupy space that could otherwise be used by source / drain contact plugs 74, resulting in an increase in the resistance of source / drain contact plugs 74. Therefore, by selectively forming CESL 58, source / drain contact plugs 74 are formed wider and therefore have a lower resistance.

[0045] In addition, CESL 58 has a higher dielectric constant (k value) than the dielectric constant of ILD 60. For example, ILD 60 may have a k value ranging between about 3.1 and about 3.9. On the other hand, CESL 58 may have a k value between about 4 and about 7. By not forming the vertical portion of CESL 58, the parasitic capacitance between source / drain contact plugs 74 and gate electrode 66 is reduced.

[0046] FIGS. 18A and 18B illustrate selectively forming an inhibitor film 80 on a dielectric material (which may have OH groups on the surface) according to some embodiments. The respective process diagram is process 238 in process flow 200 as shown in FIG. 22 . According to some embodiments, the precursor, material, and formation process of the inhibitor film 80 may be selected from the same group of candidate precursors, candidate materials, and candidate formation processes of the inhibitor film 57, respectively, and thus are not repeated. As shown in FIGS. 18A and 18B , the inhibitor film 80 is formed on the ILD 60. When the hard mask 70 is formed, the inhibitor film 80 may be formed on the hard mask 70. Depending on the material of the gate spacer 46, the inhibitor film 80 may or may not be formed on the top of the gate spacer 46. On the other hand, the inhibitor film 80 is not formed on the source / drain contact plug 74.

[0047] Next, as shown in FIGS. 18A and 18B , CESL 82 (which is also an etch stop layer, also labeled as 82SD) is selectively deposited. The respective processes are also illustrated as process 238 in process flow 200 as illustrated in FIG. 22 . Due to the presence of inhibitor film 80, CESL 82 is selectively deposited where inhibitor film 80 is not formed. Therefore, CESL 82 is selectively formed on source / drain contact plugs 74. According to some embodiments where inhibitor film 80 is not formed on the top surface of gate spacer 46, CESL 82 will also be formed on the top surface of gate spacer 46. Otherwise, CESL 82 is not formed on the top surface of gate spacer 46, as shown in FIG. 18A .

[0048] After forming the CESL 82, the inhibitor film 80 is removed, for example, in a thermal process using H2, N2 and / or O2 as a processing gas. The respective process diagram is shown as process 240 in the process flow 200 in FIG.

[0049] FIG. 19A-1 illustrates a cross section in forming ILD 86 and contact plugs 88 (including gate contact plug 88A and source / drain contact plug 88B) according to some embodiments. The respective process diagrams are process 242 in process flow 200 as depicted in FIG. 22. According to these embodiments of forming hard mask 70, inhibitor film 80 (FIG. 18A) will be formed over hard mask 70, and thus CESL 82 (also labeled 82SD) will not be formed on hard mask 70. ILD 86 is thus in physical contact with hard mask 70. The dashed portion of CESL 82 indicates that CESL 82 may or may not be formed on gate spacer 46.

[0050] In a subsequent process, contact plugs 88 (including gate contact plugs 88A and source / drain contact plugs 88B) are formed. The formation process may include: etching ILD 86, hard mask 70, and CESL 82SD to form openings; filling the openings with conductive materials (such as tungsten, cobalt, copper, TiN, and / or the like); and performing a planarization process to remove excess conductive materials.

[0051] In subsequent processes, an etch stop layer 92 may be selectively formed on contact plugs 88A and 88B. The formation may include selectively forming an inhibitor film 90 on ILD 86 but not on contact plugs 88, and selectively depositing the etch stop layer 92 where the inhibitor film 90 is not formed. The inhibitor film 90 may then be removed. An inter-metal dielectric (IMD) layer (not shown), which may be a low-k dielectric layer, may then be formed over CESL 82 and ILD 86. Metal vias (which may be part of a single damascene structure or a dual damascene structure) are then formed to penetrate the IMD layer and the etch stop layer 92.

[0052] FIG. 19A-2 illustrates an embodiment in which the replacement gate stack 68 is not recessed and the hard mask 70 is not formed. Thus, the inhibitor film (see FIG. 18A ) will not be formed on the replacement gate electrode 66, thereby allowing the CESL 82 (also labeled as CESL 82G, FIG. 19A-2 ) to be formed directly over and vertically aligned with the replacement gate electrode 66. The gate contact plug 88A and the source / drain contact plug 88B thus penetrate through the portions 82G and 82SD of the CESL 82, respectively, to contact the gate electrode 66 and / or the source / drain contact plug 74, respectively.

[0053] 19B shows a cross-sectional view in which the source / drain contact plug 74 is shown. An etch stop layer 92 is also selectively formed over the source / drain contact plug 88B and where the inhibitor film 90 is not formed.

[0054] FIG. 20 illustrates an embodiment in which CESL and an etch stop layer are selectively formed by using an inhibitor film and applied to a GAA transistor 100' according to some embodiments. The structure shown in FIG. 20 is obtained from a cross section through a replacement gate stack 68', which includes a gate dielectric 64' and a gate electrode 66'. A semiconductor nanostructure 69 is surrounded by the gate stack 68' to act as a channel. The structure of the source / drain region 54 of the GAA transistor 100' is substantially the same as that shown in FIGS. 16B, 17B, 18B, and 19B.

[0055] FIG. 21 shows a top view of transistor 100 according to some embodiments. The cross-sectional view of FIG. 19A-1 or FIG. 19A-2 can be obtained from cross-sectional view AA in FIG. 21 (also referred to as cross-sectional view AA in FIG. 15). Gate contact plug 88A is also shown in the cross-sectional view of FIG. 19A-1 or FIG. 19A-2, although it may be outside the cross-sectional view as shown in FIG. 21. The cross-sectional view in FIG. 19B can be obtained from cross-sectional view BB in FIG. 21 (also referred to as cross-sectional view BB in FIG. 15).

[0056] Embodiments of the present disclosure have several advantageous features. By forming an etch stop layer (which includes a contact etch stop layer and other etch stop layers) on the feature where the contact is to be made but not on the surrounding dielectric layer, the size of the etch stop layer is reduced. Since the etch stop layer can have a higher k value than the interlayer dielectric nearby, reducing the size of the etch stop layer results in a reduction in parasitic capacitance. In addition, the reduction in the size of the selectively formed etch stop layer creates some space for forming a contact plug and reduces the resistance of the contact plug. [ , , ]

[0057] According to some embodiments, a method includes: forming a gate stack above a semiconductor region; performing an epitaxial process to form a source / drain region next to the gate stack; forming a source / drain contact plug above the source / drain region and electrically coupled to the source / drain region; forming a gate contact plug above the gate stack and electrically coupled to the gate stack; selectively forming a first inhibitor film on a dielectric layer next to a conductive feature, wherein the conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited on the conductive feature; and removing the first inhibitor film.

[0058] In one embodiment, the conductive feature includes the source / drain region, and wherein the first inhibitor film includes a portion on a shallow trench isolation adjacent to the source / drain region. In one embodiment, the structure further includes: selectively forming a second inhibitor film on a second dielectric layer adjacent to the source / drain contact plug; selectively depositing a second etch stop layer on the source / drain contact plug; and removing the second inhibitor film. In one embodiment, the second etch stop layer further includes a portion directly above and in contact with the gate stack. In one embodiment, the structure further includes recessing the gate stack to form a recess; and forming a hard mask in the recess, wherein the first inhibitor film includes a portion directly above and in contact with the hard mask.

[0059] In one embodiment, the first etch stop layer is selectively deposited by immersing the conductive feature in a precursor. In one embodiment, the first etch stop layer is selectively deposited using a silane-containing precursor. In one embodiment, the first inhibitor film is removed via a thermal process. In one embodiment, the thermal process is performed using a precursor comprising hydrogen (H2). In one embodiment, the first inhibitor film comprises carbon.

[0060] According to some embodiments, a structure includes: a semiconductor region; a gate stack above the semiconductor region; a source / drain region next to the gate stack; a source / drain silicide region above and in contact with the source / drain region; a shallow trench isolation region next to the source / drain region; a first contact etch stop layer on the source / drain region; and an interlayer dielectric above the first contact etch stop layer, wherein the interlayer dielectric is in physical contact with both the first etch stop layer and the shallow trench isolation region. In one embodiment, the structure further includes a source / drain contact plug in the interlayer dielectric and the first contact etch stop layer, wherein the source / drain contact plug contacts the source / drain silicide region.

[0061] In one embodiment, the structure further comprises: a second contact etch stop layer contacting a top surface of the source / drain contact plug; and an additional interlayer dielectric over and contacting both the second contact etch stop layer and the interlayer dielectric. In one embodiment, the first contact etch stop layer comprises a first portion directly over a top surface of the source / drain region.

[0062] In one embodiment, the source / drain region includes a downward facing surface, and the interlayer dielectric is in physical contact with the downward facing surface. In one embodiment, the source / drain region includes a downward facing surface, and the first contact etch stop layer includes a second portion that is in physical contact with the downward facing surface. In one embodiment, an entirety of the first contact etch stop layer is physically separated from the shallow trench isolation region.

[0063] According to some embodiments, a structure includes: a semiconductor substrate; a dielectric isolation region in the semiconductor substrate; a semiconductor fin adjacent to and above a top surface of the dielectric isolation region; a gate stack on the semiconductor fin; a source / drain region bonded to the semiconductor fin and beside the gate stack; a source / drain silicide region on the source / drain region; a contact etch stop layer on the source / drain region and separated from the dielectric isolation region; an interlayer dielectric on the contact etch stop layer and in contact with the contact etch stop layer, wherein the interlayer dielectric further contacts the dielectric isolation region; and a source / drain contact plug above and in contact with the source / drain silicide region.

[0064] In one embodiment, the interlayer dielectric further physically contacts the source / drain region. In one embodiment, the interlayer dielectric physically contacts a downward structure of the source / drain region and is spaced from an upward surface of the source / drain region.

[0065] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously changed, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

[0066] 10: Wafer 20:Substrate 24: Quarantine 24T: Top surface 24B: Bottom surface 26: Semiconductor Strip 28: Pad oxide layer 30: Hard mask layer 36: Fins 38: Virtual dielectric layer 38': Virtual dielectric 40: dummy gate electrode layer 40': dummy gate electrode 40': dummy gate electrode 42: Hard mask layer 42': Hard cover 44: Dummy Gate Stack 46: Gate spacer 50: concave part 54: Epitaxial area 56: Porosity 57: Inhibitor membrane 58: Contact Etch Stop Layer (CESL) 58A: Contact Etch Stop Layer (CESL) 58B: Part 59: District 60: Interlayer Dielectric (ILD) 62: Groove 64: Gate dielectric 64': Gate dielectric 66: Gate electrode 66': Gate electrode 68: Replace the gate stack 68': Replace the gate stack 69:Semiconductor Nanostructures 70:Hard mask 71: Source / drain contact opening 72: Source / drain silicide layer 74: Source / drain contact plug 80: Inhibitor membrane 82: Contact Etch Stop Layer (CESL) 82G: Contact Etch Stop Layer (CESL) 82SD: Contact Etch Stop Layer (CESL) 86: Interlayer Dielectric (ILD) 88: Contact plug 88A: Gate contact plug 88B: Source / Drain Contact Plug 90: Inhibitor membrane 92: Etching stop layer 100':GAA transistor / FinFET 100: Transistor 200:Process flow 202: Process 204: Process 206: Process 208: Process 210: Process 212: Process 214: Process 216: Process 218: Process 220: Process 222: Process 224: Process 226: Process 228: Process 230: Process 232: Process 234: Process 236: Process 238: Process 240:Process 242: Process AA: Cross section BB: Cross section

[0067] Domestic storage information (please note the order of storage institution, date and number) none Overseas deposit information (please note the order of deposit country, institution, date and number) none

Claims

1. A method of forming a semiconductor structure, comprising the steps of: forming a gate stack over a semiconductor region; performing an epitaxial process to form a source / drain region adjacent to the gate stack; forming a source / drain contact plug over and electrically coupled to the source / drain region; forming a gate contact plug over and electrically coupled to the gate stack; selectively forming a first inhibitor film on a dielectric layer adjacent to a conductive feature, wherein the conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited on the conductive feature, the first etch stop layer being a dielectric comprising silicon nitride, silicon carbonitride, or silicon oxycarbonitride; and removing the first inhibitor film, wherein the first inhibitor film is removed by thermal decomposition.

2. The method as claimed in claim 1, wherein the conductive feature includes the source / drain region, and wherein the first inhibitor film includes a portion of a shallow trench isolation adjacent to the source / drain region.

3. The method as described in claim 2 further comprises the following steps: selectively forming a second inhibitor film on a second dielectric layer adjacent to the source / drain contact plug; selectively depositing a second etch stop layer on the source / drain contact plug; and removing the second inhibitor film.

4. The method as described in claim 3, wherein the second etch stop layer further comprises a portion directly above and in contact with the gate stack.

5. A semiconductor structure comprising: a semiconductor region; a gate stack above the semiconductor region; a source / drain region adjacent to the gate stack; a source / drain silicide region situated above and in contact with the source / drain region; a shallow trench isolation region adjacent to the source / drain region, the source / drain region including a downward surface, a region existing between the downward surface and the shallow trench isolation region; a first contact etch stop layer on the source / drain region, the first contact etch stop layer not extending into the region and substantially separated from the shallow trench isolation region; and an interlayer dielectric layer above the first contact etch stop layer, wherein the interlayer dielectric layer substantially contacts both the first contact etch stop layer and the shallow trench isolation region, the interlayer dielectric layer filling the region and substantially contacting the downward surface of the source / drain region.

6. The semiconductor structure as claimed in claim 5, further comprising: a source / drain contact plug in the interlayer dielectric and the first contact etch stop layer, wherein the source / drain contact plug contacts the source / drain silicate region.

7. The semiconductor structure as claimed in claim 6, further comprising: a second contact etch stop layer that contacts a top surface of the source / drain contact plug; and an additional interlayer dielectric that is above and contacts both the second contact etch stop layer and the interlayer dielectric.

8. The semiconductor structure as claimed in claim 5, wherein the first contact etch stop layer comprises a first portion directly above the top surface of one of the source / drain regions.

9. A semiconductor structure comprising: a semiconductor substrate; a dielectric isolation region in the semiconductor substrate; a semiconductor fin adjacent to and above a top surface of the dielectric isolation region; a gate stack on the semiconductor fin; a source / drain region bonded to the semiconductor fin and adjacent to the gate stack, the source / drain region including a downward surface, and a region existing between the downward surface and the dielectric isolation region; a source / drain silicide region on the source / drain region; and a contact etch stop layer on the source / drain region and physically separated from the dielectric isolation region without extending into the region. An interlayer dielectric layer is located on and in contact with the contact etch stop layer, wherein the interlayer dielectric layer further contacts the dielectric isolation region, the interlayer dielectric layer fills the region and substantially contacts the downward surface of the source / drain region; and a source / drain contact plug is located above and in contact with the source / drain silicate region.

10. The semiconductor structure as claimed in claim 9, wherein the interlayer dielectric is separated from an upward surface solid of the source / drain region.

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