Semiconductor device and fabricating method thereof

Abstract

This disclosure provides a method for manufacturing a semiconductor device, including forming alternating complex semiconductor channels and complex interposers on a substrate, and complex sacrificial structures between the complex interposers. Source / drain openings are formed, and strain within the channels is adjusted. Source / drain structures are formed within the openings, and dielectric layers are deposited. The resulting semiconductor device has a stacked nanostructure and also internal spacers of varying heights, thereby improving the performance of the electronic device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same capable of adjusting tensile strain and / or compressive strain. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in numerous generations of ICs, each featuring smaller and more complex circuits than the previous generation. In the development of ICs, functional density (i.e., the number of interconnects per unit wafer area) typically increases, while geometry (i.e., the smallest component (or line segment) that can be created using manufacturing processes) decreases. This miniaturization process usually benefits production efficiency and reduces associated costs. However, this miniaturization also increases the complexity of handling and manufacturing ICs. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor device. The method includes forming a stack on a substrate, the stack including alternating plurality of first semiconductor channels and plurality of second semiconductor interposers. The stack also includes a first sacrificial structure between adjacent pairs of the plurality of second semiconductor interposers, the first sacrificial structure including a third semiconductor layer having an etch selectivity different from that of the plurality of first semiconductor channels and the plurality of second semiconductor interposers. The formation of the stack includes forming source / drain openings. The method also includes replacing the third semiconductor layer with a first dielectric layer. The method also includes forming a first source / drain structure to a height below the first dielectric layer in a portion below the source / drain opening. The method also includes forming a second dielectric layer on the first source / drain structure. The method also includes increasing the tensile strain of one of the plurality of first semiconductor channels above the second dielectric layer. The method also includes forming a second source / drain structure after increasing the tensile strain, the second source / drain structure being formed in a portion above the source / drain opening above the lower portion and adjacent to one of the plurality of first semiconductor channels.

[0004] This disclosure provides a method for manufacturing a semiconductor device. The method includes forming a stack on a substrate, the stack including alternating complex nanostructure channels and complex interposers. The stack also includes a first sacrificial structure between adjacent pairs of the complex interposers, the first sacrificial structure including a third semiconductor layer having etch selectivity different from that of the complex nanostructure channels and the complex interposers. The formation of the stack includes forming source / drain openings. The method also includes reducing the tensile strain of one of the complex nanostructure channels after forming the source / drain openings. The method further includes forming a first source / drain in the source / drain openings after reducing the tensile strain, the first source / drain adjacent to one of the complex nanostructure channels. The method also includes forming a first dielectric layer on the first source / drain. The method also includes forming a second source / drain in the source / drain openings and on the first dielectric layer.

[0005] This disclosure provides a semiconductor device including a first nanostructure stack. The semiconductor device also includes a second nanostructure stack located above the first nanostructure stack and separated from it by a first dielectric layer. The semiconductor device also includes a first internal spacer vertically positioned between two adjacent nanostructures of the first nanostructure stack. The semiconductor device also includes a second internal spacer vertically positioned between two adjacent nanostructures of the second nanostructure stack, wherein the height of the second internal spacer exceeds the height of the first internal spacer. Simple Explanation of the Diagram

[0006] The present invention will be better understood from the subsequent embodiments and drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to make the explanation clearer. Figures 1A to 1D, 2A to 2D, 3A to 3D, 4A to 4D, 5A to 5H, 6A to 6F, 7A to 7F, 8A to 8F, 9A to 9D, 10A to 10D, 11A to 11D, 12A to 12D, 13A to 13D, 14A to 14D Figures 15A to 15D, 16A to 16D, 17A to 17D, 18A to 18D, 19A to 19D, 20A to 20D, 21A to 21D, 22A to 22D, 23A to 23D, and 24 are diagrams illustrating various embodiments of IC devices at various manufacturing stages according to various aspects of this disclosure. Figure 25 is a flowchart illustrating a method for forming an IC device according to various embodiments. Figure 26 is a flowchart illustrating a method for forming an IC device according to various embodiments. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these are merely examples and are not intended to limit this disclosure. For instance, if the description shows a first feature formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplification and clarity and does not inherently define the relationships between the various embodiments and / or configurations discussed.

[0008] Furthermore, this disclosure may use spatial relative terms such as "below," "below," "lower than," "above," "above," and similar words to describe the relationship between one element or feature and other elements or features in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are also intended to cover the different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0009] Terms used to indicate relative degree, such as “about” and “substantially”, should be interpreted by those with ordinary knowledge in the art in consideration of current technical standards.

[0010] The terms "first," "second," "third," etc., can be used in this text to describe the sequence of events or the sequential order of elements, but they can be interchanged or varied in some textual contexts. For example, the second layer can be (e.g., sequentially following) formed on the first layer, but in some textual contexts, the first layer can be referred to as "second layer," "third layer," "fourth layer," etc., and the second layer can be referred to as "first layer," "third layer," "fourth layer," etc.

[0011] The term "wrap" can be used in this document to describe how one structure completely or partially surrounds another element or structure in, for example, three dimensions. For instance, a first structure may "wrap" around a second structure on four lateral sides (e.g., left, right, front, and back) while not wrapping around it on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially wrap around a second structure, for example, wrapping around three sides (e.g., top, front, and back) while leaving the other sides exposed (e.g., left, right, and bottom).

[0012] The source / drain region can refer to the source or drain individually or together, depending on the context.

[0013] This disclosure relates to semiconductor devices, particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure FETs, including nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and gate-all-around FETs (GAAFETs). Complementary FETs, also known as "CFETs," are devices that include different types of vertically stacked FETs, such as n-type FETs (NFETs) stacked on top of p-type FETs (PFETs).

[0014] Tensile strain is beneficial to the performance of n-type field-effect transistors (NFETs), while compressive strain is beneficial to the performance of p-type field-effect transistors (PFETs). Nanostructures can exhibit tensile strain due to the SiGe interposer, which can improve the performance of NFET devices but may degrade the performance of PFET devices. In NFET devices, a Ge content exceeding 40% is generally unfavorable due to thickness considerations. For example, a Ge content exceeding 40% can introduce defects in the nanosheet lattice during epitaxial growth.

[0015] In this disclosed embodiment, the SiGe interposer in the NFET device can be replaced with substantially pure Ge (e.g., Ge% substantially 100%) after source / drain etching, which facilitates increasing tensile strain without reducing thickness. The top nanostructure (which may be the top nanosheet of the NFET device) has less tensile strain than the lower nanostructures (e.g., the second and third nanosheets) because the top nanostructure has only one-sided (e.g., bottom) stress, while the lower nanostructures have two-sided (e.g., top and bottom) stress. When a top SiGe layer is also included above the top nanostructure, the top nanostructure can also benefit from the two-sided stress through the replacement of the top SiGe layer.

[0016] In the PFET device region, the SiGe interposer can be replaced by a dielectric, which changes the tensile strain to neutral or compressive strain, which in turn facilitates enhanced compressive strain after source / drain epitaxy. It should be understood that the replacement of the SiGe interposer can be performed in NFET devices (e.g., with pure Ge), in PFET devices (e.g., with a dielectric), or in both NFET and PFET devices (e.g., with pure Ge in an NFET device and with a dielectric in a PFET device).

[0017] Nanostructured transistor structures can be patterned using any suitable method. For example, one or more lithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine lithography with a self-aligned process, allowing the created patterns to have smaller pitches, for example, smaller than those achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the structure of the nanostructure.

[0018] Figures 1A through 24 are diagrams illustrating intermediate stages in the fabrication of a FET (e.g., a nanostructure FET) according to some embodiments. Figures 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B Figures 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, and 23B are diagrams of a CFET comprising an NFET and a PFET, wherein the semiconductor interposer 24 in the NFET is replaced by a germanium layer 24G that is substantially pure Ge, and there is no internal spacer 74N on the upper surface of the topmost semiconductor channel 22B. Figures 1C, 1D, 2C, 2D, 3C, 3D, 4C, 4D, 5C, 5D, 6C, 6D, 7C, 7D, 8C, 8D, 9C, 9D, 10C, 10D, 11C, 11D, 12C, 12D, 13C, 13D, 14C, 14D, 15C, 15D, 16C Figures 16D, 17C, 17D, 18C, 18D, 19C, 19D, 20C, 20D, 21C, 21D, 22C, 22D, 23C, and 23D are diagrams for forming NFET and PFET, wherein the interposer 24 in the NFET is replaced by a germanium layer 24G that is essentially pure Ge, and an internal spacer 74N is present on the upper surface of the topmost semiconductor channel 22B. Figures 5E, 5F, 5G, 5H, 6E, 6F, 7E, 7F, 8E, and 8F are diagrams illustrating the formation of an NFET and a PFET, wherein the interposer 24 in the NFET is replaced by a germanium layer 24G that is substantially pure Ge, and the interposer 24 in the PFET is replaced by a dielectric interposer 24D, and an internal spacer 74N is present on the upper surface of the topmost semiconductor channel 22B. It should be noted that the embodiments described in Figures 1A to 24 can be combined to form additional embodiments, and in some embodiments, certain actions may be omitted to form additional embodiments.For example, in some embodiments, the action of replacing the dielectric interposer 24 with the dielectric interposer 24D can be performed without replacing it with a germanium layer 24G that is substantially pure Ge. In another example, in the embodiments described with reference to Figures 5E, 5F, 5G, 5H, 6E, 6F, 7E, 7F, 8E, and 8F, the top internal spacer 74N on the upper surface of the semiconductor channel 22B can be omitted. That is, the feature of replacing the dielectric interposer 24D as described in Figures 5E, 5F, 5G, 5H, 6E, 6F, 7E, 7F, 8E, and 8F can be used in conjunction with the features described in Figures 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B. The characteristics of unilateral strain formed on semiconductor channel 22B as described in Figures 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 23A, and 23B are combined.

[0019] Figures 25 and 26 are flowcharts illustrating one or more embodiments of this disclosure of a method 1000, 2000 for forming an IC device or a portion thereof from a workpiece. Methods 1000, 2000 are merely exemplary and are not intended to limit this disclosure to the content explicitly shown in methods 1000, 2000. Additional actions may be provided before, during, and after methods 1000, 2000, and for additional embodiments of the method, some of these actions may be replaced, eliminated, or moved. For simplicity, not all actions are described in detail herein. The following description will use partial perspective and / or cross-sectional views of different manufacturing stages according to embodiments of methods 1000, 2000, as shown in Figures 1A through 24. For the avoidance of ambiguity, throughout the figures of this disclosure, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X and Y directions. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device depending on the context.

[0020] Figures 1A through 1D are cross-sectional side views of a portion of a nanostructure device 10 (which may be referred to as CFET 10) according to various embodiments of the present disclosure. Figure 1A shows a diagram in the XZ plane. The nanostructure device 10 of Figures 1A and 1B will be described in detail below to provide background for understanding the technical features and benefits of the various embodiments depicted in Figures 1A through 24. The nanostructure device 10 may be included in an integrated circuit that includes a number of CFETs that are similar in most respects to the nanostructure device 10, and these CFETs are interconnected to form functional circuitry, such as logic circuitry, memory circuitry, etc.

[0021] Referring to Figures 1A through 1D, the nanostructure device 10 may be or may include one or more N-type FETs (NFETs) or P-type FETs (PFETs). In the diagrams depicted in Figures 1A and 1B, the nanostructure device 10 is in an intermediate manufacturing stage prior to the formation of source / drain features (including a second source / drain region 82N and a first source / drain region 82P), an active gate 200 (also referred to as gate structure 200), or both. The nanostructure device is formed on and / or within a substrate 110 and typically includes semiconductor channels 22A and 22B (or "nanostructures") located above semiconductor fins 32, which protrude from and are separated by isolation regions 36 (see Figure 1B). Semiconductor channels 22A and 22B may be collectively referred to as channel 22, nanostructure 22, or nanosheet 22.

[0022] Each of the illustrated nanostructure devices includes a channel. That is, the first nanostructure device may include semiconductor channel 22A, and the second nanostructure device stacked on the first nanostructure device may include semiconductor channel 22B. In subsequent operations, semiconductor channels 22A and 22B will be laterally adjacent to source / drain features (including the second source / drain region 82N and the first source / drain region 82P), respectively, and will be covered and surrounded by gate structure 200.

[0023] In the diagrams depicted in Figures 23A and 23B, the nanostructure device 10 includes source / drain features (including a second source / drain region 82N and a first source / drain region 82P) and a gate structure 200. Generally, the number of channels 22 (i.e., nanostructures 22) is two or more, such as four, six, or more. The gate structure 200 controls the flow of current through semiconductor channels 22A and 22B and from the source / drain features (including the second source / drain region 82N and the first source / drain region 82P) based on the voltage applied to the gate structure 200 and the source / drain features (including the second source / drain region 82N and the first source / drain region 82P).

[0024] Referring again to Figures 1A and 1B, in some embodiments, the semiconductor fin 32 comprises silicon. Source / drain openings 86 may be formed extending into the semiconductor fin 32, resulting in a fin platform (mesa) 32M located below the nanostructure 22 and between adjacent second source / drain regions 82N and / or first source / drain regions 82P.

[0025] Each of semiconductor channels 22A and 22B comprises a semiconductor material, such as silicon or germanium, or a semiconductor alloy, such as SiGe, GeSn, SiGeSn, etc. Semiconductor channels 22A and 22B are nanostructures (e.g., having dimensions in the range of several nanometers) and may each have an elongated shape and extend in the X direction. In some embodiments, each of semiconductor channels 22A and 22B has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shape. The cross-sectional profiles of semiconductor channels 22A and 22B may be rectangular, rounded, square, circular, elliptical, hexagonal, or combinations thereof.

[0026] In some embodiments, the lengths (e.g., measured in the X direction) of semiconductor channels 22A and 22B may differ from each other, for example, due to the tapering produced during the fin etching process. In some embodiments, the length of semiconductor channel 22B may be less than the length of semiconductor channel 22A. In some embodiments, when four or more channels 22 (nanostructures 22) are included in a vertical stack, the spacing between adjacent nanostructures 22 may be in the range of about 8 nanometers (nm) to about 12 nm, although ranges outside or below said range may also be beneficial, and are also conceived in this disclosure.

[0027] In Figures 1A through 1D, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped (e.g., doped with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may also be used.

[0028] Next, a multilayer stack or "lattice" is formed over the substrate 110. The multilayer stack includes alternating layers of first and second semiconductor layers that will form the nanostructure 22 and the interposer 24. When forming the nanostructure device 10, it is advantageous to vertically isolate the semiconductor channel 22B of the upper transistor from the semiconductor channel 22A of the lower transistor. In this way, in addition to the first and second semiconductor layers that form the nanostructure 22 and the interposer 24, the multilayer stack may also include additional first and third semiconductor layers, which will form a sacrificial isolation structure 126S including semiconductor layer 127 and sacrificial layer 129L. The thickness of the two additional first semiconductor layers forming semiconductor layer 127 can be less than the thickness of the first semiconductor layers forming semiconductor channels 22A and 22B. The thickness of the third semiconductor layer forming sacrificial layer 129L can be similar to or slightly less than the thickness of semiconductor channels 22A and 22B. The third semiconductor layer can be formed from a semiconductor material with different etching selectivity than the first and second semiconductor layers. In some embodiments, the third semiconductor layer is or includes a silicon-germanium layer having a germanium concentration (Ge%) of more than about 50%, or a substantially pure or pure germanium layer having a germanium concentration of more than about 99% (e.g., 100%).

[0029] The formation of the source / drain opening 86 can cause the formation of nanostructure 22 and semiconductor layer 127 from the first semiconductor layer and the additional first semiconductor layer, the formation of an interposer layer 24 from the second semiconductor layer, and the formation of a sacrificial layer 129L between the semiconductor layers 127. In some embodiments, the first semiconductor layer and the additional first semiconductor layer may be formed of a first semiconductor material such as silicon or silicon carbide, and the second semiconductor layer may be formed of a second semiconductor material such as silicon germanium. As described above, the third semiconductor layer forming the sacrificial layer 129L may have a high germanium concentration to increase its etch selectivity relative to the first and second semiconductor layers.

[0030] Each layer in the multilayer stack can be epitaxially grown, for example using chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the germanium concentration of the second semiconductor layer forming the interposer 24 is less than about 40%, which is advantageous during lattice formation and provides some tensile strain to the nanostructure 22 formed from the first semiconductor layer. A germanium concentration exceeding about 40% would cause germanium to diffuse into the nanostructure 22 during subsequent processes.

[0031] To increase the tensile strain in the semiconductor channel 22B of the n-type FET, one or more interposers 24 adjacent to the semiconductor channel 22B may be replaced by a germanium layer 24G in subsequent processes. The germanium layer 24G has a germanium concentration exceeding 40%, such as 50%, 60%, 70%, 80%, 90%, 95%, 98%, 99%, 99.9%, 99.99%, or any value between these values. In some embodiments, the germanium layer 24G is a pure germanium layer 24G having a germanium concentration of 100% or substantially 100%. Throughout the embodiments, the germanium concentration can refer to the atomic percentage of germanium in the germanium layer 24G. The germanium concentration can refer to a weight percentage, mole fraction, or other suitable measure. When the germanium layer 24G is a SiGe, SiGeSN, or GeSn layer with a high germanium concentration (e.g., greater than about 50%), the molar ratio of germanium to silicon or tin can be used instead of the absolute concentration. For example, according to various embodiments, a high-concentration germanium layer 24G can have a germanium-to-silicon molar ratio in the range of about 50:50 to about 99:1.

[0032] Figures 1A and 1B show two semiconductor channels 22A and 22B and three interposers 24. In some embodiments, the multilayer stack may include fewer or more pairs of nanostructures 22 and interposers 24. Although the multilayer stack is shown as including an interposer 24 as the bottom thin layer, in some embodiments, the bottom thin layer of the multilayer stack may be a first semiconductor layer. In some embodiments, the top thin layer of the multilayer stack is an interposer 24, rather than the semiconductor channel 22B depicted in Figures 1A and 1B. For example, as shown in Figures 1C and 1D, the top thin layer may be an interposer 24. Replacing the interposer 24 on the top and bottom sides of the semiconductor channel 22B, rather than just replacing the interposer 24 on the bottom side of the semiconductor channel 22B, including an interposer 24 located above the semiconductor channel 22B, is advantageous for increasing the strain on the semiconductor channel 22B.

[0033] In Figures 1A to 1D, corresponding to actions 1100 and 2100 in Figures 25 and 26 respectively, semiconductor fins 32 are formed in substrate 110, and nanostructures 22 and 24 (i.e., channels 22 and interposers 24) are formed in a multilayer stack. In some embodiments, nanostructures 22 and 24 and semiconductor fins 32 may be formed by etching trenches 84 in the multilayer stack and substrate 110 (see Figure 1B). The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching may be anisotropic. First nanostructures 22A and 22B (i.e., semiconductor channels 22A and 22B, hereinafter also referred to as "channel 22" or "nanostructure 22") are formed from a first semiconductor layer, and a second nanostructure or interposer 24 (hereinafter also referred to as "nanostructure 24") is formed from a second semiconductor layer. The distance CD1 between adjacent semiconductor fins 32 and nanostructures 22 and 24 can be from about 18 nm to about 100 nm, but narrower distances of less than about 18 nm are also considered herein. For the sake of simplicity, Figures 1A to 1D show a portion of the nanostructure device 10, which includes two semiconductor fins 32. The methods 1000 and 2000 shown in Figures 25 and 26 can be extended to any number of fins, and are not limited to the two semiconductor fins 32 shown in Figures 1A to 23D.

[0034] Semiconductor fins 32 and nanostructures 22, 24 can be patterned using any suitable method. For example, one or more lithography processes involving dual or multiple patterning can be used to form semiconductor fins 32 and nanostructures 22, 24. Generally, dual or multiple patterning processes combine lithography with self-alignment processes, allowing the created patterns to have smaller pitches, for example, smaller than those achievable using a single, direct lithography process. As an example of a multiple patterning process, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern semiconductor fins 32.

[0035] Figures 1B and 1D show semiconductor fins 32 with tapered sidewalls, such that the width of each of the fins 32 and / or nanostructures 22, 24 continuously increases in the direction toward the substrate 110. In these embodiments, each of the nanostructures 22, 24 may have different widths and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the semiconductor fins 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0036] In Figures 1A through 1D, an isolation region, feature, or structure 36 (which may be a shallow trench isolation (STI) region, feature, or structure) is formed adjacent to the semiconductor fin 32 (see Figure 1B). The isolation region 36 can be formed by depositing an insulating material over the substrate 110, the semiconductor fin 32, and the nanostructures 22, 24, and between adjacent semiconductor fins 32 and nanostructures 22, 24. The insulating material can be an oxide of silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 110, the semiconductor fin 32, and the nanostructures 22, 24. A core material, such as those previously discussed, can then be formed over the liner.

[0037] The insulating material undergoes removal processes, such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof, to remove excess insulating material above nanostructures 22 and 24. After the removal process is completed, the top surfaces of nanostructures 22 and 24 can be exposed and level with the insulating material.

[0038] The insulating material is then recessed to form the isolation region 36. After recessing, the upper portions of the nanostructures 22, 24 and the semiconductor fins 32 may protrude from between adjacent isolation regions 36. The top surface of the isolation region 36 may be flat (as shown), convex, concave, or a combination thereof. In some embodiments, the isolation region 36 is recessed by a suitable etching process, such as using an oxide such as dilute hydrofluoric acid (dHF) for removal, which is selective for the insulating material and leaves the semiconductor fins 32 and nanostructures 22, 24 substantially unchanged.

[0039] An embodiment of forming the semiconductor fins 32 and nanostructures 22, 24 has been described previously (e.g., post-etching). In some embodiments, the semiconductor fins 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., pre-etching). The epitaxial structures may include alternating semiconductor materials as previously discussed, such as a first semiconductor material and a second semiconductor material.

[0040] In Figures 1A to 1D, suitable wells (not shown separately) can be formed in the semiconductor fins 32, nanostructures 22, 24, and / or isolation region 36. By using a mask, n-type impurity implantation can be performed in the p-type region of the substrate 110, and p-type impurity implantation can be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. After implantation, annealing can be performed to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during the epitaxial growth of the semiconductor fins 32 and nanostructures 22, 24 can eliminate the need for separate implantation; however, in-situ doping and implantation doping can be used together.

[0041] In Figures 1A to 1D, a dummy or sacrificial gate structure 40 is formed over the semiconductor fins 32 and / or nanostructures 22, 24, corresponding to actions 1200 and 2200 in Figures 25 and 26, respectively. A dummy or sacrificial gate layer 45 is formed over the semiconductor fins 32 and / or nanostructures 22, 24. The dummy gate layer 45 may be or may include a material with high etch selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive, semi-conductive, or non-conductive material, and may be or may include amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material.

[0042] A masking layer 47 is formed over the virtual gate layer 45, and may, for example, include silicon nitride, silicon oxynitride, etc. In some embodiments, the masking layer 47 includes a first masking layer 47A in contact with the virtual gate layer 45, and a second masking layer 47B covering and in contact with the first masking layer 47A. The first masking layer 47A may be made of or may include the same or different material as the second masking layer 47B.

[0043] In some embodiments, before the virtual gate layer 45, a virtual gate dielectric 43 is first formed between the virtual gate layer 45 and the semiconductor fins 32 and / or nanostructures 22, 24.

[0044] Gate spacer 41 is formed above the sidewalls of mask layer 47 and dummy gate layer 45. According to some embodiments, gate spacer 41 is or includes an insulating material, such as SiOCN, SiOC, SiCN, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Gate spacer 41 may be formed by depositing a spacer material layer (not shown) over mask layer 47 and dummy gate layer 45. According to some embodiments, an isotropic etching process is used to remove portions of the spacer material layer between the dummy gate structures 40. In some embodiments, gate spacer 41 is a multilayer structure comprising at least a first spacer layer and a second spacer layer.

[0045] In Figures 1A to 1D, the portions of the protruding semiconductor fins 32 and / or nanostructures 22, 24 not covered by the dummy gate structure 40 are etched by performing an etching process to form source / drain openings 86, corresponding to action 1300 in Figure 25. The source / drain openings 86 extend through the stack of nanostructures 22, 24. The tunneling to form the source / drain openings 86 can be anisotropic, such that the portion of the semiconductor fin 32 directly below the dummy gate structure 40 and the gate spacer 41 is protected and substantially unetched. According to some embodiments, the top surface of the tunneled semiconductor fin 32 can be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, the top surface of the tunneled semiconductor fin 32 can be lower than the top surface of the isolation region 36. In these embodiments, a plurality of fin platforms 32M can be formed in the semiconductor fin 32. For simplicity, Figure 1A illustrates a vertical stack of three nanostructures 22, 24 formed after an etching process. Generally, an etching process can be used to form fewer or more vertical stacks of nanostructures 22, 24 over the semiconductor fin 32. In some embodiments, the second masking layer 47B is exposed after the etching process, for example, because the upper portion of the gate spacer 41 is removed during the etching process.

[0046] In Figures 1C and 1D, the optional top second semiconductor layer 24 (i.e., interposer 24 or nanostructure 24) is included between the virtual gate structure 40 and the uppermost semiconductor channel 22B. A source / drain opening 86 extends through the top nanostructure 24 and the stack of nanostructures 22, 24, and into the semiconductor fin 32, as described with reference to Figures 1A and 1B.

[0047] Although the source / drain opening 86 is a continuous opening in the vertical direction (e.g., the Z-axis direction), the source / drain opening 86 includes an upper portion 86U and a lower portion 86L that can be associated with an upper transistor and a lower transistor, respectively. The upper transistor may include an upper semiconductor channel 22B, and the lower transistor may include a lower semiconductor channel 22A. While not intended to be limiting herein, according to various embodiments, the dashed lines included in Figures 1A and 1C depict one possible interface between the upper portion 86U and the lower portion 86L. For example, the interface may be located near the vertical midpoint of the sacrificial fourth semiconductor layer (sacrificial layer 129L). Generally, the interface is located vertically at a height between the upper and lower boundaries of the sacrificial layer 129L.

[0048] In Figures 2A to 2D, the sacrificial layer 129L is removed to form an opening 129O between the semiconductor layers 127. The sacrificial layer 129L can be removed by a suitable etching operation that is selective for the material of the sacrificial layer 129L and does not damage the channel 22 (nanostructure 22), the semiconductor layer 127, and the interposer layer 24 (nanostructure 24). For example, the sacrificial layer 129L can be a thin layer with a high Ge% content, while the nanostructure 22, the semiconductor layer 127, and the nanostructure 24 can be thin layers with a low Ge% content, so that the sacrificial layer 129L is removed without substantially removing the material of the nanostructure 22, the semiconductor layer 127, and the nanostructure 24. In some embodiments, some material at the end portions of the nanostructure 24 (which can be low Ge% SiGe) is removed during the removal of the sacrificial layer 129L. However, since the sacrificial layer 129L is a thin layer with a high Ge content, the material of the sacrificial layer 129L is removed at a much higher rate than that of the nanostructure 24, so that when the sacrificial layer 129L is completely consumed, the nanostructure 24 is hardly changed by etching.

[0049] In some embodiments, as shown in Figures 2B and 2D, the surface of semiconductor layer 127 facing sacrificial layer 129L may have a thin layer 127G, which has a higher germanium concentration than other portions of semiconductor layer 127. This may be because the surface facing sacrificial layer 129L is in contact with the high-Ge% semiconductor material of sacrificial layer 129L, which may cause germanium to diffuse or mix into the semiconductor material near the surface of semiconductor layer 127, which has a relatively low Ge% concentration.

[0050] In Figures 3A to 3D, after forming the opening 129O, a first dielectric layer 129 is formed in the opening 129O. The first dielectric layer 129 can be, or may include, one or more materials such as SiO, SiN, SiON, SiC, SiOC, SiCN, and SiOCN. The formation of the first dielectric layer 129 may include a deposition operation and a subsequent etch-back operation. The deposition operation may be PVD, CVD, ALD, etc. The etch-back operation may be dry or wet etching.

[0051] Next, a sacrificial dielectric layer 82D can be formed in the portion 86L below the source / drain opening 86, covering the semiconductor channel 22A. The sacrificial dielectric layer 82D can be, or may include, one or more materials such as SiO, SiN, SiON, SiC, SiOC, SiCN, and SiOCN. The formation of the sacrificial dielectric layer 82D may include a deposition operation and a subsequent etch-back operation. The deposition operation may be PVD, CVD, ALD, etc. The etch-back operation may be dry or wet etching. The dielectric material of the sacrificial dielectric layer 82D is different from the dielectric material of the first dielectric layer 129. Therefore, the etch-back operation of etching the sacrificial dielectric layer 82D can remove excess material from the sacrificial dielectric layer 82D without substantially damaging the first dielectric layer 129.

[0052] In Figures 4A to 4D, after forming the sacrificial dielectric layer 82D, a sacrificial spacer layer 820 can be formed to cover and protect the semiconductor channel 22B and the adjacent interposer layer 24 (nanostructure 24). The sacrificial spacer layer 820 can be a conformal thin layer of dielectric material, which can be one or more of materials such as SiO, SiN, SiON, SiC, SiOC, SiCN, and SiOCN. The formation of the sacrificial spacer layer 820 can include a deposition operation and a subsequent etch-back operation. The deposition operation can be PVD, CVD, ALD, etc. The etch-back operation can be anisotropic etching, removing the horizontal portion of the sacrificial spacer layer 820 to expose the sacrificial dielectric layer 82D. The dielectric material of the sacrificial spacer layer 820 is different from the dielectric material of the sacrificial dielectric layer 82D. Therefore, the etch-back operation of etching the sacrificial spacer layer 820 can remove excess material from the sacrificial spacer layer 820 without substantially damaging the sacrificial dielectric layer 82D. Similarly, when the sacrificial dielectric layer 82D is removed in a subsequent operation, the sacrificial spacer layer 820 can protect the semiconductor channel 22B and the nanostructure 24 adjacent to the semiconductor channel 22B. Since the sacrificial dielectric layer 82D already occupies its position during the formation of the sacrificial spacer layer 820, the sacrificial spacer layer 820 does not extend to the portion 86L below the source / drain opening 86.

[0053] In Figures 5A to 5D, after forming the sacrificial spacer layer 820, an extended lower source / drain opening 82O is formed by removing the sacrificial dielectric layer 82D and the interposer layer 24 (nanostructure 24) embedded in the lower portion 86L of the source / drain opening 86. The lower source / drain opening 82O includes the lower portion 86L of the source / drain opening 86 and a first internal spacer groove 74R1, which corresponds to action 2300 in Figure 26. That is, the lower portion 86L of the source / drain opening 86 is reopened by removing the sacrificial dielectric layer 82D. Then, the first internal spacer groove 74R1 is formed by removing the end portion of the nanostructure 24 exposed in the lower portion 86L of the source / drain opening 86. The removal of the end portion of the nanostructure 24 can be performed by selective wet etching of the second semiconductor material (e.g., low Ge% SiGe) of the nanostructure 24. During the removal of the end portion of nanostructure 24, a small amount of material from semiconductor channel 22A and semiconductor fin 32 can be removed. The exposed portion of semiconductor layer 127 can also be removed, such that semiconductor layer 127 extends to be substantially coplanar with the side surface of nanostructure 24 exposed by the first internal spacer groove 74R1.

[0054] In some embodiments, instead of leaving the interposer 24 (nanostructure 24) on top of and below the semiconductor channel 22A, the nanostructure 24 can be removed to reduce the tensile strain of the semiconductor channel 22A to a neutral strain. Figures 5E to 5H are schematic cross-sectional views showing the process for forming the dielectric layer 24D, or "dielectric interposer 24D," which replaces the nanostructure 24 adjacent to the semiconductor channel 22A and reduces the tensile strain of the semiconductor channel 22A, corresponding to action 2400 in Figure 26. Compressive strain is advantageous for PFET performance. Source / drain epitaxy can create compressive strain in the semiconductor channel 22A in a PFET device. Before source / drain epitaxy, the semiconductor channel 22A has tensile strain due to the SiGe material nanostructure 24 in contact with it, which degrades the performance of the PFET. To reduce the tensile strain in the PFET device region before source / drain epitaxy, a dielectric interposer 24D can be used to replace the SiGe material interposer 24 (nanostructure 24), which reduces the tensile strain to a neutral or compressive strain. The dielectric interposer 24D can convert the tensile strain to a neutral strain and can further convert the tensile strain to compressive strain via heat treatment (e.g., annealing). Then, compared to an embodiment where the SiGe material nanostructure 24 is not replaced, the compressive strain increases after source / drain epitaxy.

[0055] In Figures 5E and 5F, prior to the formation of the opening 54, the gate spacer 41 and the sacrificial spacer layer 820 exist on the virtual gate structure 40, and on the surface above the nanostructure 24 and the semiconductor channel 22B in the portion 86U above the source / drain opening 86.

[0056] After forming the source / drain openings 86 and the sacrificial spacer layer 820, the nanostructure 24 exposed by the underlying source / drain openings 820 is removed by a suitable etching operation to form openings 54 above and below the semiconductor channel 22A. For example, the etching operation may be or may include one or more isotropic etching operations, such as wet etching, which removes the nanostructure 24 at a rate higher than that of the semiconductor channel 22A. In some embodiments, the semiconductor channel 22A is slightly thinned by the etching operation that removes the nanostructure 24. In some embodiments, the nanostructure 24 is completely removed by the etching operation. In some embodiments, the nanostructure 24 is partially (e.g., substantially) removed by the etching operation, such that some material of the nanostructure 24 (e.g., low concentration of SiGe) remains on the upper or lower surfaces of one or more semiconductor channels 22A.

[0057] In Figures 5G and 5H, while the dielectric interposer 24D is formed in the opening 54 adjacent to (e.g., above and / or below) the semiconductor channel 22A (i.e., where the nanostructure 24 was previously disposed), the upper portion 86U of the source / drain opening 86 associated with the NFET region remains protected. The dielectric interposer 24D can be formed by a suitable deposition operation, such as PVD, CVD, ALD, etc. In some embodiments, the dielectric interposer 24D is or includes a dielectric material, such as SiO, SiOC, SiC, SiN, SiON, SiOCN, combinations thereof (e.g., multiple layers thereof). Other dielectric materials such as HfO, Al₂O₃, etc., can also be included in the dielectric interposer 24D. First, one or more dielectric material layers containing one or more of the dielectric materials mentioned above can be formed in the opening 54, and optionally outside the opening 54. In some embodiments, the dielectric material layers can partially or completely fill the source / drain opening 86. That is, the dielectric material layer can exist on the side surface of the sacrificial spacer layer 820 exposed by the source / drain opening 86 and on the upper surface of the semiconductor fin 32.

[0058] After depositing the dielectric material layer, one or more etching operations can be performed to tunnel into the dielectric material layer to form a dielectric interposer 24D. In some embodiments, after tunneling, the dielectric interposer 24D has a width smaller than the width of the channel 22 (nanostructure 22) (e.g., in the X-axis direction plotted in Figure 5G). Internal spacer recesses 64, which will form internal spacers, may be present at the end portions of the dielectric interposer 24D. In some embodiments, the width of the internal spacer recesses 64 in the X-axis direction is in the range of about 0.5 nm to about 3 nm.

[0059] In Figures 6A to 6F, internal spacers 74 are formed. Following the formation of the dielectric interposer 24D as described in Figures 5E to 5H, Figures 6E to 5H show internal spacer recesses 64 formed (see Figure 5G). In Figures 6A to 6D, a selective etching process is performed to excavate the end portions of the nanostructure 24 exposed by the openings in the sacrificial spacer layer 820, without substantially damaging the nanostructure 22. After the selective etching process in Figures 6A to 6D, recesses similar to the internal spacer recesses 64 depicted in Figure 5G are formed in the nanostructure 24 at the locations where the removed end portions were previously located. Next, after forming the grooves in Figures 6A to 6D or the internal spacer groove 64 in Figure 5G, an internal spacer layer is formed to (partially or completely) fill the grooves or internal spacer grooves 64 formed in the nanostructure 24 by the previous selective etching process. The internal spacer layer can be a suitable dielectric material, such as SiN, SiCN, SiOCN, SiOC, etc., and is formed by a suitable deposition method such as PVD, CVD, ALD, etc. In the NFET device region, the internal spacer layer is deposited on the sacrificial spacer layer 820.

[0060] Then, after forming the internal spacer layer, an etching process, such as anisotropic etching, is performed to remove portions of the internal spacer layer disposed outside the recesses, such as portions disposed on the side surface of the semiconductor channel 22A and the upper surface of the semiconductor fin 32. The remaining portions of the internal spacer layer (e.g., portions disposed in the recesses within the nanostructure 24 or dielectric interposer 24D) form internal spacers 74. The etching process forming internal spacers 74 can remove the internal spacer layer in the NFET device region above the portion 86L below the source / drain opening 86.

[0061] Next, in Figures 7A to 7F, a first source / drain region 82P, or "first source / drain 82P", is formed according to various embodiments, corresponding to action 2500 in Figure 26. Figures 7A, 7C, and 7E depict the formation of the p-type first source / drain region 82P. The first source / drain region 82P can be epitaxially grown from an epitaxial material. In some embodiments, the first source / drain region 82P applies stress in the corresponding semiconductor channel 22A, thereby improving performance. The first source / drain region 82P is formed such that each virtual gate structure 40 is disposed between corresponding adjacent and paired first source / drain regions 82P. The first source / drain region 82P can be or may include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The first source / drain region 82P can apply compressive strain in the channel region.

[0062] As shown in Figure 7A, in some embodiments, the upper surface of the first source / drain region 82P is lower than the height of the bottom surface of the isolation structure 126. That is, the first source / drain region 82P can extend upward to a height between the upper and lower surfaces of the internal spacer 74, which is located between the semiconductor channel 22A and the isolation structure 126.

[0063] The lattice constant of the semiconductor channel 22A can be smaller than that of the fin platform 32M by a range of about 0.5% to about 2%, due to the compressive strain from the dielectric interlayer 24D and / or due to the high Ge% SiGe material (e.g., about 40% to about 80%).

[0064] In Figures 8A through 8F, after the formation of the first source / drain region 82P, the sacrificial spacer layer 820 is removed to expose the gate spacer 41, semiconductor channel 22B, and interposer layer 24 (nanostructure 24) above the isolation structure 126. Removal of the sacrificial spacer layer 820 may include wet or dry etching, such as using fluorine-based plasma in reactive ion etching (RIE).

[0065] Starting with Figures 9A through 9D, diagrams depicting dielectric interposer 24D are no longer provided. Instead, it should be understood that the interposer adjacent to the first source / drain region 82P may be the interposer 24 (nanostructure 24) shown or the dielectric interposer 24D described with reference to Figures 8E and 8F. For example, in Figures 9A through 9D, nanostructure 24 is depicted adjacent to the first source / drain region 82P, but in some embodiments, instead of nanostructure 24, the nanostructure device 10 depicted in Figures 9A through 9D may include dielectric interposer 24D, and the same is true in Figures 10A through 20D. Figures 21A through 21D depict the removal of interposer 24 and / or dielectric interposer 24D to release semiconductor channels 22A, 22B. That is, in Figures 21A to 23D, the interposer 24 and the optional dielectric interposer 24D no longer exist.

[0066] In Figures 9A to 9D, after forming the first source / drain region 82P and removing the sacrificial spacer layer 820, a third dielectric layer 910 is formed on the exposed surface of the first source / drain region 82P. The third dielectric layer 910 can be or may include one or more dielectric materials, such as SiN, SiCN, SiON, SiOCN, SiC, SiO, combinations thereof, etc., and can be deposited using suitable deposition processes such as PVD, CVD, ALD, etc. The third dielectric layer 910 helps protect the first source / drain region 82P in subsequent operations, where the interposer 24 (nanostructure 24) associated with the n-type FET is replaced with a high Ge% interposer (i.e., germanium layer 24G). For example, the first source / drain region 82P can be or may include SiGe, and therefore may be etched during the removal of the interposer 24, which may also include SiGe. The formation of the third dielectric layer 910 can physically isolate the first source / drain region 82P from etching chemicals (e.g., gases) that are introduced to remove the nanostructure 24 above the third dielectric layer 910.

[0067] Figures 10A to 17D are schematic cross-sectional views illustrating various embodiments, showing a process in which a high-Ge% germanium layer 24G replaces the nanostructure 24 in the NFET device region. The high-Ge% germanium layer 24G has an indented end portion from the outer surface of the channel 22 (nanostructure 22) to form a second internal spacer recess 74R2, in which an internal spacer 74N is formed. In Figures 10A to 13D, the high-Ge% germanium layer 24G is formed after the second internal spacer recess 74R2 is formed. In Figures 14A to 17D, the second internal spacer recess 74R2 is formed after the high-Ge% germanium layer 24G is formed. It should be understood that the embodiments described with reference to Figures 10A to 13D and Figures 14A to 17D can be combined with any of the embodiments described with reference to Figures 1A to 9D.

[0068] In Figures 10A to 13D, the SiGe nanostructure 24 is replaced by an interposer 24G (i.e., a germanium layer 24G), wherein the germanium layer 24G facilitates increasing the tensile strain of the channel 22 (nanostructure 22) in the NFET device region, corresponding to operation 1400 in Figure 25. In the description referring to Figures 10A to 13D, the replacement germanium layer 24G is described as a pure or substantially pure germanium interposer, a high-germanium-concentration interposer, or a germanium-based semiconductor or "germanium alloy" interposer with a germanium concentration exceeding approximately 50%. The replacement germanium layer 24G has the function of increasing the tensile strain of the nanostructure 22. Increasing the tensile strain can include through lattice mismatch and / or thermal expansion mismatch. In some embodiments, the material comprising the replacement germanium layer 24G may increase the tensile strain of the Si nanostructure 22, but this material is different from pure or substantially pure germanium, high-germanium-concentration semiconductors, or germanium-based semiconductors with a germanium concentration exceeding about 50%.

[0069] In Figures 10A to 10D, one or more operations can be performed to form oxide layers 22O and 24O on the outer surfaces of semiconductor channel 22B and nanostructure 24, respectively, which are associated with an n-type FET. The oxide layers 22O and 24O can be formed by one or more chemical oxidation processes, such as exposure to oxygen and / or a cleaning process. The oxide layer 22O is a SiO layer that protects the semiconductor channel 22B during subsequent growth of the germanium layer 24G, allowing the germanium layer 24G to grow selectively on the exposed upper and / or lower surfaces of the semiconductor channel 22B and semiconductor layer 127, and substantially not on the outer surfaces of the semiconductor channel 22B. The oxide layer 24O is a SiGeO porous layer following a chemical oxidation process. In some embodiments, the SiGeO layer is a thin layer comprising SiO and GeO. For example, the process allows silicon in a SiGe alloy to react with oxygen to form silicon dioxide (SiO₂). However, germanium oxidizes differently from silicon and may form the less stable germanium oxide (GeO₂x), which volatilizes at oxidation temperatures and affects the uniformity and quality of the oxide layer. The porosity of oxide layer 24O allows nanostructure 24 to be selectively removed through its pores, and allows germanium layer 24G to be selectively grown through its pores. The thicknesses of oxide layers 22O and 24O can be the same, substantially the same, or different. For example, during a chemical oxidation process, the thickness of SiGeO in oxide layer 24O can be increased at a faster, slower, or the same rate as the thickness of SiO in oxide layer 22O.

[0070] In Figures 11A through 11D, an etching operation is performed to completely, substantially completely, or partially remove the nanostructure 24. In some embodiments, the nanostructure 24 is removed by a selective etching process, where the etchant used is selective for the material of the nanostructure 24, such that the nanostructure 24 is removed without substantially damaging the semiconductor channel 22B. In some embodiments, the etching process is an isotropic etching process, using an etching gas and an optional carrier gas, wherein the etching gas includes F₂ and HF, and the carrier gas may be an inert gas, such as Ar, He, N₂, or combinations thereof. Due to the porosity of the oxide layer 24O, the etching gas can enter through the pores of the oxide layer 24O to erode the SiGe of the nanostructure 24, while being blocked by the oxide layer 22O, so that the Si of the semiconductor channel 22B located on the side surface of the semiconductor channel 22B is not substantially damaged. During the etching process that removes the nanostructure 24, some silicon of the semiconductor channel 22B can be removed, resulting in a reduced thickness of the semiconductor channel 22B. That is, the width of the semiconductor channel 22B in the X-axis direction is substantially unchanged (shortened) due to the protection of the oxide layer 22O. However, the height or thickness of the semiconductor channel 22B may be changed (reduced) due to the etching of the internal opening 24H left by the removal of the nanostructure 24. For subsequent operations forming the internal spacer 74N in the NFET device region, the reduced thickness of the semiconductor channel 22B may lead to an increase in the height or thickness of the internal spacer 74N in the NFET device region (e.g., in the Z-axis direction). The thickness loss in the semiconductor channel 22B can be in the range of about 0.5 nm to about 2 nm. It should be noted that in Figures 11C and 11D, since the nanostructures 24 on the top and bottom sides of the semiconductor channel 22B are removed, the semiconductor channel 22B may be thinned more than the semiconductor channel 22B shown in Figures 11A and 11B where only one nanostructure 24 on the bottom side is removed. For example, for semiconductor channel 22B shown in Figures 11C and 11D, the thickness loss can be in the range of approximately 1 nm to approximately 4 nm. Thus, the thickness of semiconductor channel 22B can be less than the thickness of semiconductor channel 22A, numerically less than approximately 0.5 nm to approximately 2 nm. The thickness difference between semiconductor channel 22A and semiconductor channel 22B described above can also occur between the internal spacers 74 and 74N or between the gate structures 200.

[0071] In some embodiments, nanostructure 24 is almost completely removed, but a thin layer of low-concentration SiGe can be retained on the upper and / or lower surfaces of channel 22 (nanostructure 24), which can reduce lattice mismatch during subsequent operations after the growth of germanium layer 24G.

[0072] In Figures 12A to 12D, after the removal of nanostructure 24, a germanium layer 24G may be formed in the internal opening 24H previously occupied by nanostructure 24, that is, vertically below and optionally above semiconductor channel 22B. In embodiments where the topmost nanostructure 24 is present on the topmost semiconductor channel 22B, the germanium layer 24G may be formed on the upper surface of the topmost semiconductor channel 22B. To improve tensile strain in the NFET, the nanostructure or interposer 24 is replaced by a substantially pure germanium layer 24G (or interposer 24G). The substantially pure high Ge% germanium layer 24G may have a germanium concentration of more than about 98%, more than about 99%, more than about 99.9%, more than about 99.99%, etc. In some embodiments, the germanium layer 24G is a high-concentration high Ge% germanium layer 24G, having a Ge concentration of more than about 80%, about 85%, about 90%, etc. In some embodiments, the germanium layer 24G is a Ge alloy germanium layer 24G (e.g., a SiGe layer) having a Ge concentration of more than about 50%, about 60%, about 70%, etc.

[0073] The interposer layer 24G (germanium layer 24G) can be formed by an epitaxial growth process including CVD (e.g., low-pressure CVD, ALD, etc.). A germanium precursor gas, such as germanane (GeH4), can be introduced into a heated chamber under reduced pressure. The precursor can decompose on exposed areas of the hot substrate, such as on the exposed upper and / or lower surfaces of the semiconductor channel 22B, so that pure or substantially pure germanium atoms are deposited layer by layer on the semiconductor channel 22B. In embodiments forming a pure or substantially pure high-Ge% germanium layer 24G, germanane can be the only precursor gas introduced into the chamber. In embodiments forming a high-concentration high-Ge% germanium layer 24G or a Ge alloy germanium layer 24G, germanane and silane (SiH4) can be introduced into the chamber simultaneously. Although the germanium layer 24G is described above as a germanium-containing semiconductor layer with a germanium concentration exceeding approximately 50% (e.g., approximately 99.99% or even 100%), it should be understood that other material layers can also be formed on channel 22 (nanostructure 22). These material layers possess the quality of beneficially increasing tensile strain, enabling the tensile strain to be increased beyond that achievable through nanostructure 24 (with a germanium concentration of less than approximately 40%). For example, instead of pure or high-concentration germanium, semiconductors such as ZnSe, AlInAs, or GaSb can be grown on nanostructure 22 to increase the tensile strain of nanostructure 22 through lattice mismatch, thermal expansion mismatch, or both. Pure or high-concentration germanium can have the advantage of easy integration, allowing for relatively easy integration into fabrication processes that already use silicon and germanium (e.g., for forming SiGe nanostructure 24).

[0074] Due to the germanium layer 24G, the lattice constant of semiconductor channel 22B can exceed that of semiconductor channel 22A, by approximately 0.5% to approximately 2%. Similarly, the lattice constant of semiconductor channel 22B can exceed that of fin platform 32M, by approximately 0.5% to approximately 2%. In embodiments where both the top and bottom surfaces of semiconductor channel 22B are adjacent to the germanium layer 24G, the two values ​​described above can be in the range of approximately 0.5% to approximately 4%.

[0075] In Figures 13A to 13D, after the formation of the replacement germanium layer 24G, oxide layers 22O and 24O are removed, and a second internal spacer recess 74R2 is formed, in which an internal spacer 74N is formed. The oxide layers 22O and 24O can be removed by a suitable etching process, such as wet etching, which removes the oxide layers 22O and 24O without substantially damaging other exposed thin layers (e.g., gate spacer 41). The formation of the second internal spacer recess 74R2 can, in most respects, be similar to that described with reference to Figures 5A to 5D. For example, a selective etching process is performed to drill into the end portion of the replacement germanium layer 24G without substantially damaging the nanostructure 22. In some embodiments, the etching process of the end portion of the replaced germanium layer 24G thins the end of the nanostructure 22, such that the thickness of the end portion of the nanostructure 22 is less than the thickness of the middle portion of the nanostructure 22 in contact with the replaced germanium layer 24G.

[0076] In Figures 10A to 13D, the second internal spacer groove 74R2 is formed after the replacement germanium layer 24G is formed. In Figures 14A to 17D, the second internal spacer groove 74R2 is formed before the replacement germanium layer 24G is formed.

[0077] In Figures 14A through 14D, a selective etching process is performed to form the second internal spacer groove 74R2. This selective etching process tunnels into the end portion of the nanostructure 24 without substantially damaging the semiconductor channel 22B. The end portion of the nanostructure 22 can be slightly thinned by the selective etching process, as shown in Figures 14A and 14C. The tunneling depicted in Figures 14A through 14D can be similar in most respects to that described with reference to Figures 5A through 5D.

[0078] In Figures 15A to 15D, oxide layers 22O and 24O are formed on the semiconductor channel 22B and nanostructure 24 via a process largely similar to that described with reference to Figures 10A to 10D. In Figures 15A to 15D, in addition to the side surface of the semiconductor channel 22B, oxide layer 22O extends to the upper and lower surfaces of the end portion of the semiconductor channel 22B, while oxide layer 24O is configured to extend slightly inward along the X-axis direction from the outer side surface of the semiconductor channel 22B.

[0079] In Figures 16A to 16D, nanostructure 24 is removed via a process similar to that described with reference to Figures 11A to 11D. In the embodiment described with reference to Figures 10A to 13D, the end portion of semiconductor channel 22B is etched twice: once during the removal of nanostructure 24 and again during the formation of the second internal spacer recess 74R2. In the embodiment described with reference to Figures 14A to 17D, the end portion of semiconductor channel 22B is etched once during the formation of the second internal spacer recess 74R2, and is not etched during the removal of nanostructure 24 due to the protection of oxide layer 22O. Thus, when performing the process described in Figures 10A to 13D, the thickness of the end portion of semiconductor channel 22B can be slightly less than the thickness of the middle portion of semiconductor channel 22B. When performing the process shown in Figures 14A to 17D, the end portion of semiconductor channel 22B can have a thickness that is uniform or substantially uniform with the middle portion of semiconductor channel 22B.

[0080] In Figures 17A to 17D, the replacement interposer layer 24G (germanium layer 24G) is formed via a process largely similar to that described with reference to Figures 12A to 12D. In the embodiments of Figures 14A to 17D, since the second internal spacer recess 74R2 has already been formed in the operations previously described with reference to Figures 14A to 14D, further etching of the replacement germanium layer 24G is not required. That is, once the formation operation (e.g., epitaxial growth of germanium) is completed, the replacement germanium layer 24G formed in Figures 17A to 17D is substantially complete. The replacement germanium layer 24G in Figures 17A to 17D can be formed with a width smaller than the width of the semiconductor channel 22B because the presence of the oxide layer 22O prevents the growth of the high Ge% semiconductor material at the end portion of the semiconductor channel 22B.

[0081] In Figures 18A to 18D, oxide layers 22O and 24O are removed via a process largely similar to that described with reference to Figures 13A to 13D. Next, an internal spacer layer is formed via a process largely similar to that described with reference to Figures 6A to 6D. In Figures 18A to 18D, an internal spacer layer is formed to fill a second internal spacer recess 74R2 in the NFET device region, while the PFET device region is protected by a third dielectric layer 910. Then, an internal spacer 74N in the N-type FET is formed via a process largely similar to that described with reference to Figures 6A to 6D. In Figures 18A to 18D, the internal spacer 74N is formed in the NFET device region. The internal spacer 74N is adjacent to the germanium layer 24G at either end. Because of the additional etching of the semiconductor channel 22B during the replacement of the interposer 24 (nanostructure 24) with the interposer 24G (germanium layer 24G), the thickness / height of the internal spacer 74N in the NFET device region in the Z-axis direction can exceed the thickness / height of the internal spacer 74 in the PFET device region. This may be more pronounced in embodiments where the nanostructure 24 in the PFET device region is not replaced, compared to embodiments where the nanostructure 24 in the PFET device region is replaced with a dielectric interposer 24D. In some embodiments, the thickness of the internal spacer 74N exceeds the thickness of the internal spacer 74 by approximately 0.5 nm to approximately 2 nm.

[0082] In Figures 19A to 19D, a second source / drain region or second source / drain region 82N is formed, corresponding to action 1500 in Figure 25. The second source / drain region 82N can be epitaxially grown from an epitaxial material. In some embodiments, the second source / drain region 82N applies stress in the corresponding semiconductor channel 22B, thereby improving performance. The second source / drain region 82N is formed such that each dummy gate structure 40 is disposed between corresponding adjacent and paired second source / drain regions 82N. In some embodiments, gate spacers 41 separate the second source / drain regions 82N from the dummy gate layer 45 at an appropriate lateral distance to prevent electrical bridging to the gate of the subsequently formed device. In some embodiments, the second source / drain region 82N can be or may include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, etc. The second source / drain region 82N can apply tensile strain in the channel region (semiconductor channel 22B).

[0083] In Figures 20A to 20D, after the formation of the second source / drain region 82N, an inter-layer dielectric (ILD) 130 is formed to cover the second source / drain region 82N and the first source / drain region 82P, and adjacent to the gate spacer 41. In some embodiments, an etch stop layer (ESL) 131 is formed prior to the formation of the inter-layer dielectric 130. The etch stop layer 131 may be formed by depositing compliant thin layers of dielectric materials that are different from the dielectric material of the inter-layer dielectric 130, and such as one or more of SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlOx, HfAlOx, HfSiOx, Al2O3, or other suitable materials. After depositing the etch stop layer 131, an interlayer dielectric 130 can be deposited using a suitable process, such as a blanket deposition process including PVD, CVD, and ALD. The material of the interlayer dielectric 130 may include silicon dioxide or a low-k dielectric material (e.g., a material with a dielectric constant (k-value) lower than that of silicon dioxide (approximately 3.9)). Low-k dielectric materials may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbonate (SiO₂xC₂y), spin-on-glass (SOG), or combinations thereof. The interlayer dielectric 130 can be deposited by spin-on coating, CVD, flow CVD (FCVD), plasma-enhanced CVD (PECVD), PVD or other deposition processes.

[0084] In Figures 21A to 21D, after forming the second source / drain region 82N, the first source / drain region 82P, the etch stop layer 131, and the interlayer dielectric 130, a gate structure 200 (also referred to as an active gate or alternative gate structure) can be formed. A planarization process, such as chemical mechanical polishing (CMP), is performed on the interlayer dielectric 130 and the etch stop layer 131. Parts of the first mask layer 47A, the second mask layer 47B, and the gate spacer 41 are also removed by the planarization process. After the planarization process, the dummy gate layer 45 is exposed. After the planarization process, the top surfaces of the interlayer dielectric 130 and the etch stop layer 131 can be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacer 41. Then, the dummy gate layer 45 is removed in the etching process, thus forming a gate opening 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the gate spacer 41. When a dummy gate dielectric 43 is present, it may be used as an etch stop layer during the etching of the dummy gate layer 45. After the dummy gate layer 45 is removed, the dummy gate dielectric 43 may then be removed.

[0085] Then, the replacement interposer 24G (germanium layer 24G) and nanostructure 24 or dielectric interposer 24D are removed to release nanostructure 22, corresponding to actions 1600 and 2600 in Figures 25 and 26, respectively. After removing the germanium layer 24G and nanostructure 24 or dielectric interposer 24D, nanostructure 22 forms a plurality of horizontally extending (e.g., parallel to the main upper surface of substrate 110) nanosheets. The removal of the replacement germanium layer 24G and nanostructure 24 or dielectric interposer 24D can be performed by one or more selective etching processes using etchants that are selective to the materials of nanostructure 24, germanium layer 24G, or dielectric interposer 24D, so that nanostructure 24, germanium layer 24G, or dielectric interposer 24D are removed without substantially damaging nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas, such as Ar, He, N2, or combinations thereof. In embodiments including a dielectric interposer 24D, the material of the dielectric interposer 24D may be selected to have etch selectivity different from the materials of the interlayer dielectric 130, the etch stop layer 131, the gate spacer 41, and the isolation region 36, and / or to have a different material from the materials of the interlayer dielectric 130, the etch stop layer 131, the gate spacer 41, and the isolation region 36. This is beneficial to avoid damage to the interlayer dielectric 130, the etch stop layer 131, the gate spacer 41, and the isolation region 36 when removing the dielectric interposer 24D.

[0086] In some embodiments, the nanostructure 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. Reshaping can be performed using a selective isotropic etching process on the nanostructure 22. After reshaping, the nanostructure 22 can exhibit a dog bone shape, wherein the central portion of the nanostructure 22 is thinner in the X direction than the peripheral portion.

[0087] In some embodiments, during the removal of germanium layer 24G, nanostructure 24 and / or dielectric interposer 24D, semiconductor layer 127 of isolation structure 126 is removed, such that isolation structure 126 includes only first dielectric layer 129.

[0088] In Figures 22A to 22D, following the release channel 22 (nanostructure 22) in Figures 21A to 21D, a replacement gate structure 200 is formed, corresponding to actions 1700 and 2700 in Figures 25 and 26, respectively. The gate structure 200 may be referred to as an active gate 200 or a replacement gate 200. The gate structure 200 can be formed by a series of deposition operations (e.g., ALD cycling), depositing various thin layers of the gate structure 200 in the opening, as described below with reference to Figure 24.

[0089] Figure 24 is a detailed diagram of a portion of the gate structure 200. The gate structure 200 typically includes an interfacial layer (IL, or "first interfacial layer" hereinafter) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290 (hereinafter referred to as the metal core layer 290). In some embodiments, the gate structure 200 further includes at least one of a second interfacial layer 240 or a work function barrier layer 700.

[0090] Referring to Figure 24, in some embodiments, the first interface layer 210 comprises an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first interface layer 210 may comprise other suitable types of dielectric materials. The thickness of the first interface layer 210 is in the range of about 5 angstroms to about 50 angstroms.

[0091] Referring again to Figure 24, a gate dielectric layer 600 is formed over the first interface layer 210. In some embodiments, an atomic layer deposition (ALD) process is used to form the gate dielectric layer 600 to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process uses deposition cycles between about 40 and 80 and is performed at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as precursors. This ALD process can form a gate dielectric layer 600 with a thickness ranging from about 10 angstroms to about 100 angstroms.

[0092] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which can be a dielectric material having a dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂, Ta₂O₅, or combinations thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to adjust the critical voltage of the nanostructure device.

[0093] Referring further to Figure 24, an optional second interface layer 240 is formed on the gate dielectric layer 600, and a work function barrier layer 700 is formed on the second interface layer 240. The second interface layer 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second interface layer 240 further provides improved thermal stability to the gate structure 200 and serves to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the second interface layer 240 is formed by first depositing a high-k capping layer (not illustrated for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO, or other suitable materials. In one embodiment, the high-k capping layer comprises titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by ALD, which uses approximately 40 to approximately 100 cycles and is performed at a temperature of approximately 400 to approximately 450 degrees Celsius. Next, thermal annealing is performed to form a second interface layer 240, which in some embodiments may be or may include TiSiNO. After the second interface layer 240 is formed by thermal annealing, artificial intelligence (AI)-controlled atomic layer etch (ALE) may be performed cyclically to remove the high-k capping layer without substantially removing the second interface layer 240. Each cycle may include a first pulse of WCl 5, followed by an Ar purge, then a second pulse of O 2, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further tuning of the complex threshold voltage through metal gate patterning.

[0094] Further in Figure 24, according to some embodiments, after forming the second interface layer 240 and removing the high-k capping layer, a work function barrier layer 700 may be optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a particular embodiment, the work function barrier layer 700 is TiN. The thickness of the work function barrier layer 700 can be in the range of about 5 angstroms to about 20 angstroms. Including the work function barrier layer 700 provides additional threshold voltage tuning flexibility. Generally, the work function barrier layer 700 increases the threshold voltage of an NFET transistor device and decreases the threshold voltage (magnitude) of a PFET transistor device.

[0095] In some embodiments, a work function metal layer 900 is formed on the work function barrier layer 700. The work function metal layer 900 may include at least one of an n-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. The n-type work function metal layer is or includes an n-type metallic material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The n-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, electroplating, and / or other suitable methods, and may have a thickness between about 10 angstroms and 20 angstroms. An in-situ capping layer is formed on the n-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or other suitable materials, and may have a thickness between about 10 angstroms and 20 angstroms. An oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen diffusion into the n-type work function metal layer, wherein oxygen diffusion would cause an undesirable shift in the critical voltage. The oxygen barrier layer is formed of a dielectric material capable of preventing oxygen from penetrating into the n-type work function metal layer and protecting the n-type work function metal layer from further oxidation. The oxygen barrier layer may include oxides of silicon, germanium, SiGe, or other suitable materials. In some embodiments, the oxygen barrier layer is formed using an ALD and has a thickness between about 10 angstroms and about 20 angstroms.

[0096] Figure 24 further illustrates the metal core layer 290. In some embodiments, an adhesive layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The adhesive layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the adhesive layer can be formed from a metal nitride using an ALD, such as TiN, TaN, MoN, WN, or other suitable materials. In some embodiments, the thickness of the adhesive layer is between about 10 angstroms and about 25 angstroms. The metal core layer 290 can be formed on the adhesive layer and can include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or combinations thereof. In some embodiments, the metal core layer 290 can be deposited using methods such as CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, a seam 510, which may be an air gap, is formed in the metal core layer 290, perpendicularly between adjacent nanostructures 22 or between semiconductor channels 22A and semiconductor fins 32. In some embodiments, a metal core layer 290 is compliantly deposited on a work function metal layer 900. The seam 510 may be formed due to the fusion of thin films deposited on the sidewalls during compliant deposition. In some embodiments, no seam 510 exists between adjacent nanostructures 22.

[0097] In some embodiments, the PFET device includes one or more metal layers comprising a metal core layer 290, a work function barrier layer 700, and a work function metal layer 900, which may include Ti, Al, Zn, W, Nb, Co, etc., and the total thickness of the combination of metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm. In some embodiments, the NFET device includes one or more metal layers comprising a metal core layer 290, a work function barrier layer 700, and a work function metal layer 900, which may include Ti and / or Al, and the total thickness of the combination of metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm.

[0098] In Figures 23A to 23D, after the gate structure 200 is formed, a source / drain opening can be formed in the interlayer dielectric 130, and a source / drain contact 120 can be formed in the source / drain opening. The first source / drain region 82P and the second source / drain region 82N can be collectively referred to as source / drain region 82. A silicate region 118 and the source / drain contact 120 are formed on the source / drain region 82. In the diagrams shown in Figures 23A to 23D, only the source / drain contact 120 formed on the second source / drain region 82N is shown. In some embodiments, additional source / drain contacts 120 may be formed on the first source / drain region 82P using a method largely similar to that described with reference to the second source / drain region 82N, except that the additional source / drain contacts 120 may be formed after thinning or removing the substrate 110, which exposes the backside of the first source / drain region 82P.

[0099] In some embodiments, the silicate layer 118 is formed before or during the formation of the source / drain contact 120. For example, an n-type or p-type metal layer may be formed as a compliant thin layer over the exposed portion of the source / drain region 82. The metal layer may be or may include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or may include one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or other suitable materials. After the metal layer is formed, the silicate layer 118 may be formed by annealing the nanostructure device 10. After annealing, the silica layer 118 may be, or may include, one or more of the following: NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi. The silica in the silica layer 118 may diffuse into the region below the etch stop layer 131. The thickness of the silica layer 118 may be in the range of approximately 1 nm to approximately 10 nm. Below approximately 1 nm, the contact resistance may be too high. Above approximately 10 nm, the silica layer 118 may short-circuit with the semiconductor channel 22B.

[0100] After or during the formation of the silicate layer 118, the opening above the source / drain region 82 is filled with a layer such as a padding layer and a filler layer to form the source / drain contact 120. In some embodiments, the source / drain contact 120 is formed by depositing a material that is or includes a conductive material, such as Co, W, Ru, or combinations thereof. In some embodiments, the source / drain contact 120 is or includes a Co-based, W-based, or Ru-based compound or alloy and contains one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, or combinations thereof. The source / drain contact 120 lands on the silicate layer 118 and contacts the etch stop layer 131.

[0101] Additional processes can be performed to complete the fabrication of the nanostructure device 10. For example, gate contacts (or gate vias) can be formed to electrically couple to the gate structure 200. Then, interconnect structures can be formed over the source / drain contacts 120 and the gate contacts. The interconnect structures may include multiple dielectric layers (e.g., including a second ILD) surrounding metallic features, including conductive traces and conductive vias, which form electrical interconnects between devices on the substrate 110 and to IC devices outside the nanostructure device 10.

[0102] The embodiments disclosed herein offer numerous advantages. Replacing the interposer 24 (nanostructure 24) in an NFET device, PFET device, or both can improve the strain of their channels 22 (nanostructure 22). In an NFET device, the interposer 24 is replaced by a high-Ge% interposer 24G (germanium layer 24G), which increases the tensile strain of the channels 22. The interposer 24G can be a pure or substantially pure germanium layer, or other suitable material layer. In a PFET device, the interposer 24 can be replaced by a dielectric interposer 24D, which can reduce tensile strain and / or increase compressive strain.

[0103] According to at least one embodiment, this disclosure provides a method for manufacturing a semiconductor device. The method includes forming a stack on a substrate, the stack including alternating plurality of first semiconductor channels and plurality of second semiconductor interposers, the stack further including a first sacrificial structure between adjacent pairs of the plurality of second semiconductor interposers, the first sacrificial structure including a third semiconductor layer having an etch selectivity different from that of the plurality of first semiconductor channels and the plurality of second semiconductor interposers, wherein forming the stack includes forming source / drain openings. The method also includes replacing the third semiconductor layer with a first dielectric layer. The method also includes forming a first source / drain structure to a height below the first dielectric layer in a portion below the source / drain opening. The method also includes forming a second dielectric layer on the first source / drain structure. The method also includes increasing the tensile strain of one of the plurality of first semiconductor channels above the second dielectric layer. The method also includes forming a second source / drain structure after increasing the tensile strain, the second source / drain structure being formed in a portion above the source / drain opening above the lower portion and adjacent to one of the plurality of first semiconductor channels.

[0104] In some embodiments, the increase in tensile strain includes replacing one of the plurality of second semiconductor interposers with a replacement interposer.

[0105] In some embodiments, the replacement of one of the plurality of second semiconductor interlayers includes replacing the silicon-germanium interlayer with a substantially pure germanium interlayer having a germanium concentration of more than 99%.

[0106] In some embodiments, the replacement of one of the plurality of second semiconductor interlayers includes replacing the silicon-germanium interlayer with a high-concentration germanium interlayer having a germanium concentration of more than 80%.

[0107] In some embodiments, the replacement of one of the aforementioned in a plurality of second semiconductor interlayers includes replacing a silicon-germanium interlayer having a germanium concentration of less than 40% with a plurality of silicon-germanium interlayers having a germanium concentration of more than 50%.

[0108] In some embodiments, replacing one of the plurality of second semiconductor interposers with a replacement interposer includes: forming a first oxide layer on a side surface of one of the plurality of first semiconductor channels and forming a second oxide layer on a side surface of one of the plurality of second semiconductor interposers, wherein the second oxide layer is porous; removing one of the plurality of second semiconductor interposers through the plurality of pores of the second oxide layer; and growing a replacement interposer through the plurality of pores of the second oxide layer.

[0109] In some embodiments, the method further includes: forming a second internal spacer adjacent to a replacement interposer in the upper portion of the source / drain opening; and forming a first internal spacer adjacent to another of the plurality of second semiconductor interposers in the lower portion of the source / drain opening before forming the second internal spacer, wherein the height of the first internal spacer exceeds the height of the second internal spacer.

[0110] According to at least one embodiment, this disclosure provides a method for manufacturing a semiconductor device. The method includes forming a stack on a substrate, the stack including alternating plurality of nanostructure channels and plurality of interposers, the stack further including a first sacrificial structure between adjacent pairs of the plurality of interposers, the first sacrificial structure including a third semiconductor layer having an etch selectivity different from that of the plurality of nanostructure channels and the plurality of interposers, wherein forming the stack includes forming source / drain openings. The method also includes reducing the tensile strain of one of the plurality of nanostructure channels after forming the source / drain openings. The method also includes forming a first source / drain in the source / drain openings after reducing the tensile strain, the first source / drain adjacent to one of the plurality of nanostructure channels. The method also includes forming a first dielectric layer on the first source / drain. The method also includes forming a second source / drain in the source / drain openings and on the first dielectric layer.

[0111] In some embodiments, reducing tensile strain includes replacing one of the plurality of interposers with a replacement interposer. In some embodiments, replacing one of the plurality of interposers includes replacing one of the plurality of interposers with a dielectric interposer.

[0112] In some embodiments, replacing one of the plurality of interposers with a dielectric interposer includes: forming a first opening by removing one of the plurality of interposers; forming a dielectric interposer in the first opening; and forming a groove by excavating the end portion of the dielectric interposer. In some embodiments, the method further includes forming internal spacers in the groove.

[0113] In some embodiments, the above method further includes: after forming the second source / drain, releasing multiple nanostructure channels by removing the dielectric interlayer, thereby forming a second opening; and forming an active gate in the second opening.

[0114] In some embodiments, the method further includes increasing the tensile strain of one of the complex nanostructure channels above the first dielectric layer after the formation of the first source / drain and before the formation of the second source / drain.

[0115] According to at least one embodiment, this disclosure provides a semiconductor device including a first nanostructure stack. The semiconductor device also includes a second nanostructure stack located above the first nanostructure stack and separated from it by a first dielectric layer. The semiconductor device also includes a first internal spacer vertically located between two adjacent nanostructures of the first nanostructure stack. The semiconductor device also includes a second internal spacer vertically located between two adjacent nanostructures of the second nanostructure stack, wherein the height of the second internal spacer exceeds the height of the first internal spacer.

[0116] In some embodiments, the semiconductor device further includes a third internal spacer, vertically positioned above the uppermost nanostructure of the second nanostructure stack. In some embodiments, the thickness of the nanostructure of the first nanostructure stack exceeds the thickness of the nanostructure of the second nanostructure stack.

[0117] In some embodiments, the semiconductor device further includes a fin platform located below the first nanostructure stack, wherein the lattice constant of the first nanostructure directly above the fin platform is greater than the lattice constant of the fin platform.

[0118] In some embodiments, the lattice constant of the second nanostructure stack exceeds that of the first nanostructure stack. In some embodiments, the height of the second internal spacer exceeds the height of the first internal spacer by about 0.5 nanometers to about 2 nanometers.

[0119] The foregoing disclosure outlines the features of various embodiments, thereby enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or attain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

[0120] 10: Nanostructure Devices 22: Channel / Nanostructure 22A: Semiconductor Channel 22B: Semiconductor Channel 22O: Oxide layer 24: Intermediate Layer / Nano Structure 24D: Dielectric Interchange 24G: Germanium layer 24H: Internal opening 24O: Oxide layer 32: Semiconductor fins 32M: Finned Platform 36: Isolation Area 40: Virtual gate structure 41: Gate spacer 43: Virtual gate dielectric 45: Virtual Gate Layer 47: Masking layer 47A: First masking layer 47B: Second masking layer 54: Opening 64: Internal spacer groove 74: Internal spacers 74N: Internal spacer 74R1: First internal spacer groove 74R2: Second internal spacer groove 82D: Sacrificial Dielectric Layer 82N: Second source / drain region 82O: Lower source / drain opening 82P: First source / drain region 84: Trench 86: Source / Drain Opening 86L: Lower part 86U: Top section 92: Gate opening 110:Substrate 118: Silicone region 120: Source / drain contact 126: Isolation Structure 126S: Sacrificial Isolation Structure 127: Semiconductor layer 127G: Thin film 129: First dielectric layer 129L: Sacrifice Layer 129O: Opening 130: Interlayer dielectric 131: Etching Stop Layer 200: Gate structure 210: First Interface Layer 240: Second Interface Layer 290: Metal Core Layer 510: Seam 600: Gate dielectric layer 700: Work Function Barrier Layer 820: Sacrificial spacer layer 900: Work function metal layer 910: Third dielectric layer 1000: Method 1100~1700: Actions 2000: Method 2100~2700: Actions CD1: Distance

Claims

1. A method for manufacturing a semiconductor device, comprising: A stack is formed on a substrate, the stack including alternating plurality of first semiconductor channels and plurality of second semiconductor interposers, the stack including a first sacrificial structure between adjacent pairs of one of the second semiconductor interposers, the first sacrificial structure including a third semiconductor layer having etch selectivity different from the first semiconductor channels and the second semiconductor interposers, the formation of the stack including forming a source / drain opening; replacing the third semiconductor layer with a first dielectric layer; forming a first source / drain structure to a height below the first dielectric layer in a portion below the source / drain opening; and forming a second dielectric layer on the first source / drain structure. Increase the tensile strain of the first semiconductor channel above the second dielectric layer, such that the lattice constant of the first semiconductor channel exceeds the lattice constant of the second semiconductor channel below the second dielectric layer; and after increasing the tensile strain, form a second source / drain structure in an upper portion above the lower portion of the source / drain opening, and adjacent to the first semiconductor channel.

2. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the increase in tensile strain includes replacing one of the second semiconductor interlayers with a replacement interlayer.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the replacement of the aforementioned second semiconductor interlayer includes replacing a silicon-germanium interlayer with a substantially pure germanium interlayer having a germanium concentration of more than 99% or a high-concentration germanium interlayer having a germanium concentration of more than 80%.

4. A method for manufacturing a semiconductor device as described in claim 2, wherein replacing one of the aforementioned second semiconductor interposers with the aforementioned replacement interposer comprises: A first oxide layer is formed on the side surface of the first of the first semiconductor channels, and a second oxide layer is formed on the side surface of the second semiconductor interposer, wherein the second oxide layer is porous; the first of the second semiconductor interposer is removed through the plurality of pores of the second oxide layer; and the replacement interposer is grown through the pores of the second oxide layer.

5. The method for manufacturing a semiconductor device as described in claim 2 further includes: In the above-mentioned upper portion of the aforementioned source / drain opening, a second internal spacer is formed adjacent to the aforementioned replacement interlayer; And prior to forming the second internal spacer, a first internal spacer is formed in the lower portion of the source / drain opening adjacent to the other of the second semiconductor interposer, wherein the height of the first internal spacer exceeds the height of the second internal spacer.

6. A method for manufacturing a semiconductor device, comprising: A stack is formed on a substrate, the stack comprising alternating plurality of nanostructure channels and plurality of interposers, the stack comprising a first sacrificial structure between adjacent pairs of one of the interposers, the first sacrificial structure comprising a third semiconductor layer having an etch selectivity different from that of the nanostructure channels and the interposers, the formation of the stack comprising forming a source / drain opening; after forming the source / drain opening, reducing the tensile strain of one of the nanostructure channels such that the lattice constant of the first nanostructure channel is less than that of a second nanostructure channel; after reducing the tensile strain, forming a first source / drain in the source / drain opening, the first source / drain adjacent to the first nanostructure channel; A first dielectric layer is formed on the first source / drain, wherein the first of the nanostructure channels is lower than the first dielectric layer, and the second of the nanostructure channels is higher than the first dielectric layer; and a second source / drain is formed in the source / drain opening and on the first dielectric layer.

7. A method for manufacturing a semiconductor device as claimed in claim 6, wherein the reduction of the tensile strain includes replacing the intermediate layer with a replacement intermediate layer.

8. A method for manufacturing a semiconductor device as claimed in claim 7, wherein replacing one of the aforementioned interposers includes replacing one of the aforementioned interposers with a dielectric interposer, wherein replacing one of the aforementioned interposers with the dielectric interposer includes: A first opening is formed by removing one of the aforementioned interposers; the aforementioned dielectric interposer is formed in the aforementioned first opening; And by drilling into one end portion of the aforementioned dielectric interlayer to form a groove.

9. The method of manufacturing a semiconductor device as claimed in claim 6 further includes increasing the tensile strain of the nanostructure channel above the first source / drain layer after forming the first source / drain and before forming the second source / drain.

10. A semiconductor device, comprising: A stack of first nanostructures; A second nanostructure stack is located above the first nanostructure stack and separated from the first nanostructure stack by a first dielectric layer, wherein the lattice constant of one nanostructure in the second nanostructure stack exceeds the lattice constant of one nanostructure in the first nanostructure stack; a first internal spacer is vertically located between two adjacent nanostructures of the first nanostructure stack; and a second internal spacer is vertically located between two adjacent nanostructures of the second nanostructure stack, wherein the height of the second internal spacer exceeds the height of the first internal spacer.

11. The semiconductor device as claimed in claim 10 further includes a third internal spacer, which is vertically located on the uppermost nanostructure of one of the second nanostructure stacks.

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