Package structure and method for forming the same
Patent Information
- Application Number
- TW113131732
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2024-05-09
- Filing Date
- 2024-08-23
- Publication Date
- 2026-08-11
- Estimated Expiration
- 2044-08-22
AI Technical Summary
Existing semiconductor packaging technologies face challenges in achieving high integration density and efficient heat dissipation while minimizing package warpage and coplanarity issues, which affect the performance and reliability of miniaturized electronic devices.
The implementation of a contour ring on a substrate with an opening that exposes the package, followed by a top cover extending into the opening, enhances structural support and improves heat dissipation by evenly distributing thermal interface material, reducing substrate warpage and coplanarity problems.
This configuration mitigates package warpage, enhances coplanarity, and improves heat dissipation efficiency by ensuring uniform distribution of thermal interface material, thereby improving the performance and reliability of semiconductor packaging structures.
Smart Images

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Abstract
Description
[Technical Field]
[0001] None. [Previous Technology]
[0002] The semiconductor industry has experienced rapid development due to the continuous increase in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integrated density comes from the continuous shrinking of the minimum feature size, which allows more components to be integrated in a given area.
[0003] With the increasing demand for miniaturized electronic devices, there is a need for smaller, more innovative semiconductor wafer packaging technologies. One example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to achieve high integration and component density. Another example is Chip-On-Wafer-On-Substrate (CoWoS) structures, in which a semiconductor wafer is attached to a wafer (e.g., an interposer) to form a Chip-On-Wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form the CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and smaller coverage areas. [Summary of the Invention]
[0004] None.
Implementation Method
[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where additional features can be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.
[0007] Furthermore, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" are used herein to describe the relationship between an element or feature and another element or feature illustrated in the figures. In addition to the orientations described in the figures, spatial relative terms are also intended to include different orientations of the device during use or operation. The device may also be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. As used herein, "around," "about," "approximately," or "substantially" generally mean within 20%, 10%, or 5% of a given value or range. The figures given herein are approximate values, meaning that "about," "approximately," "approximately," or "substantially" can be inferred unless explicitly stated otherwise. However, those familiar with this technique should realize that the values or ranges described throughout the description are merely examples and may be reduced or changed as the integrated circuit is scaled.
[0008] Figures 1A to 5B illustrate methods for forming a package structure at different stages according to some embodiments of the present disclosure. Figures 1A, 2A, 3A, 4A, and 5A are top views of the package structure, and Figures 1B, 2B, 3B, 4B, and 5B are cross-sectional views of the package structure. More specifically, Figures 1B, 2B, 3B, 4B, and 5B are cross-sectional views along line BB of Figures 1A, 2A, 3A, 4A, and 5A, respectively.
[0009] See Figures 1A and 1B. Package structure 100 is shown here. In some embodiments, package structure 100 may be a three-dimensional integrated circuit (3DIC) package. In some embodiments, the 3DIC package may include a chip-on-wafer-on-substrate (CoWoS) package structure. In other embodiments, package structure 100 may include a chip stack, such as logic-on-logic (LoL), memory-on-logic (MoL), or the like.
[0010] The package structure 100 includes a package 110 and a substrate 120 that are bonded to each other. More specifically, the package 110 is disposed on the top surface of the substrate 120. In some embodiments, the package 110 may be a chip-on-wafer (CoW) package.
[0011] Package 110 may include a plurality of wafers 112. A wafer 112 may also be referred to as a die. Five wafers 112 are illustrated in the top view of Figure 1A, but this disclosure is not limited thereto. In other embodiments, more or fewer wafers 112 may be used. In some embodiments, wafer 112 may include high-power wafers and / or low-power wafers. For example, a high-power wafer may consume relatively more power and thus generate relatively more heat compared to a low-power wafer. A high-power wafer may be a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or the like. A low-power wafer may be a memory wafer, such as high bandwidth memory (HBM), a memory block, a memory stack, or the like.
[0012] The chip 112 is bonded to the top surface of the package assembly 114. The chip 112 may be electrically and mechanically coupled to the package assembly 114 via a plurality of first connectors 142. In some embodiments, the first connectors 142 may be conductive bumps, microbumps, metal pillars, or the like.
[0013] The wafer 112 may be surrounded by an encapsulating adhesive 130, which includes a molding compound. The wafer 112 and the encapsulating adhesive 130 may be planarized such that the top surfaces of the wafer 112 and the encapsulating adhesive 130 are substantially flush with each other. In some embodiments, the encapsulating adhesive 130 may also surround the first connector 142. In some embodiments, the encapsulating adhesive 130 may also extend to the sidewalls of the package assembly 114. In other embodiments, the encapsulating adhesive 130 may surround the wafer 112, while the first connector 142 and the package assembly 114 may not be covered by the encapsulating adhesive 130.
[0014] The package assembly 114 may be an interposer, which may be a semiconductor substrate. For example, the package assembly 114 may be a silicon substrate. The package assembly 114 may also be formed of other semiconductor materials, such as silicon germanium, silicon carbon, or the like. According to some embodiments, active devices (such as transistors) (not described separately) are formed on the surface of the package assembly 114. Passive devices (such as resistors and / or capacitors) (not described separately) may also be formed in the package assembly 114. According to alternative embodiments of this disclosure, the package assembly 114 may be a semiconductor substrate or a dielectric substrate, and individual package assemblies 114 may not include active devices. According to these embodiments, the package assembly 114 may or may not include passive devices formed therein.
[0015] Although not shown in the cross-sectional view of Figure 1B, vias may be formed extending from the top surface of the package assembly 114 into the package assembly 114. In embodiments where the package assembly 114 is a silicon substrate, the vias may be referred to as through-substrate vias or through-silicon vias. In some embodiments, the package assembly 114 may include interconnect structures for electrically connecting integrated circuit devices in the package 110. The interconnect structures may include a plurality of dielectric layers, metal lines formed in the dielectric layers, and vias formed and interconnected between the overlying metal lines and the underlying metal lines. According to some embodiments, the dielectric layers may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or multiple layers thereof. Alternatively, the dielectric layers may include one or more low-k dielectric layers having a low dielectric constant (k value). For example, the k value of the low-k dielectric material in the dielectric layer may be less than about 3.0 or less than about 2.5.
[0016] The encapsulation component 114 of the package 110 is bonded to the top surface of the substrate 120. The encapsulation component 114 may be electrically and mechanically coupled to the substrate 120 via a plurality of second connectors 144. In some embodiments, the second connectors 144 may be conductive bumps, microbumps, metal pillars, or the like. An underfill material 135 may be formed between the encapsulation component 114 and the substrate 120, surrounding the second connectors 144. In embodiments where the first connector 142 is not covered by encapsulant 130, the underfill material 135 may also extend between the wafer 112 and the encapsulation component 114, surrounding the first connector 142.
[0017] The substrate 120 may be a packaging substrate, which may be a printed circuit board (PCB) or the like. The substrate 120 may include one or more dielectric layers and conductive features, such as conductive lines and vias. In some embodiments, the substrate 120 may include vias, active devices, passive devices, and the like. The substrate 120 may further include conductive pads formed on the upper and lower surfaces of the substrate 120. The second connector 144 may be coupled to the conductive pad on the top surface of the substrate 120. A plurality of third connectors 146 may be coupled to the conductive pad on the bottom surface of the substrate 120. In some embodiments, the third connectors 146 may be conductive bumps, microbumps, metal pillars, or the like.
[0018] Refer to Figures 2A and 2B. Adhesive materials 152 and 154 are coated on substrate 120. In some embodiments, adhesive materials 152 and 154 may be epoxy-based materials (e.g., epoxy resin), silicone-based materials (e.g., silicone resin), adhesives, or the like. In the top view of Figure 2A, the top outlines of both adhesive materials 152 and 154 are rectangular rings. More specifically, adhesive material 152 surrounds adhesive material 154. Furthermore, adhesive material 154 may surround wafer 112 and may also surround encapsulating adhesive 130.
[0019] In the cross-sectional view of Figure 2B, the adhesive material 152 is in contact with the top surface of the substrate 120. On the other hand, the adhesive material 154 can extend from the top surface of the encapsulant 130, pass through the sidewalls of the encapsulant 130 and the sidewalls of the underfill material 135, and reach the top surface of the substrate 120. That is, the adhesive material 154 can contact the top surface of the encapsulant 130, the sidewalls of the encapsulant 130, the sidewalls of the underfill material 135, and the top surface of the substrate 120. Therefore, the top surface of the adhesive material 154 may be higher than the top surface of the adhesive material 152, and the bottom surface of the adhesive material 154 may be substantially flush with the bottom surface of the adhesive material 152.
[0020] In the cross-sectional view of Figure 2B, one or more surface mount devices 160 may be disposed on the substrate 120. It should be noted that, for simplicity, the surface mount devices 160 are not shown in Figure 2A. The surface mount devices 160 may be used to provide additional functionality or programming for the package 110 or package structure 100. In some embodiments, the surface mount device 160 may include a surface mount device (SMD) or an integrated passive device (IPD), which includes passive devices such as resistors, inductors, capacitors, antennas, jumpers, combinations of these devices, or the like, which are intended to be connected and used in conjunction with other parts of the package 110 or package structure 100. The surface mount device 160 may be disposed on the top surface of the substrate 120. In other embodiments, one or more surface mount devices 160 may also be disposed on the bottom surface of the substrate 120.
[0021] Refer to Figures 3A and 3B. A contour ring 172 is disposed on the substrate 120 and surrounds the package 110. As shown in the top view of Figure 3A, the top contour of the contour ring 172 is rectangular and includes an opening O1. On the other hand, as shown in the cross-sectional view of Figure 3B, the contour ring 172 is connected to the substrate 120 by adhesive materials 152 and 154. In some embodiments, the contour ring 172 may include an L-shaped cross-sectional view. For example, the contour ring 172 may include a horizontal portion 172A and a vertical portion 172B extending downward from one end of the horizontal portion 172A. The horizontal portion 172A of the contour ring 172 contacts the adhesive material 154, and the vertical portion 172B of the contour ring 172 contacts the adhesive material 152. In some embodiments, the bottom surface of the horizontal portion 172A of the contour ring 172 is higher than the top surface of the wafer 112 and the encapsulant 130. The bottom surface of the horizontal portion 172A of the contour ring 172 may also be higher than the top surface of the adhesive material 154.
[0022] As described above, the contour ring 172 includes an opening O1. In some embodiments, the opening O1 exposes all of the wafers 112 of the package 110. That is, in the cross-sectional view of Figure 3B, the contour ring 172 may not overlap with the wafers 112 in the vertical direction. In some embodiments, the contour ring 172 may not overlap with the encapsulating adhesive 130 surrounding the wafers 112. In the top view of Figure 3A, the adhesive material 154 may be exposed at least partially through the opening O1 of the contour ring 172.
[0023] In some embodiments, the profile ring 172 may be a metal, a metal alloy, or the like. For example, the profile ring 172 may include metals and / or metal alloys such as Al, Cu, Ni, Co, combinations thereof, and the like. The profile ring 172 may also be formed of composite materials such as silicon carbide, aluminum nitride, graphite, or the like. In some embodiments, the profile ring 172 may be a metal coated with another metal (e.g., gold). In some embodiments, the profile ring 172 may be made of stainless steel. The profile ring 172 may be formed of a material with a thermal conductivity of about 100 W / m·K to about 400 W / m·K, for example, about 400 W / m·K. In some embodiments, the profile ring 172 is a single continuous material. That is, the horizontal portion 172A of the profile ring 172 may be in direct contact with the vertical portion 172B of the profile ring 172, which may increase the robustness of the profile ring 172. In other embodiments, the profile ring 172 may include multiple components, which may be made of the same material or different materials. For example, the horizontal portion 172A and the vertical portion 172B of the contour ring 172 can be separate portions and can be connected to each other by an adhesive material.
[0024] Refer to Figures 4A and 4B. Adhesive material 182 and thermal interface material (TIM) 184 are respectively coated on the contour ring 172 and the package 110. More specifically, adhesive material 182 is coated on and in contact with the horizontal portion 172A of the contour ring 172. Thermal interface material 184 is coated on and in contact with the top surfaces of the wafer 112 and the encapsulant 130. In some embodiments, the bottom surface of thermal interface material 184 may be lower than the bottom surface of adhesive material 182. Thermal interface material 184 may be spaced apart from the contour ring 172 and adhesive material 182.
[0025] The adhesive material 182 may be epoxy resin, silicone resin, glue, or the like. The adhesive strength of the adhesive material 182 may be greater than that of the thermal interface material 184, while the thermal conductivity of the thermal interface material 184 may be greater than that of the adhesive material 182. The thermal conductivity of the adhesive material 182 may be from about 1 W / m·K to about 3 W / m·K, below about 0.5 W / m·K or the like. The position of the adhesive material 182 allows a subsequently formed top cover (e.g., top cover 174 in Figures 5A and 5B) to be attached to the contour ring 172. Thus, in some embodiments, the adhesive material 182 may be disposed along the top surface of the contour ring 172, and its top contour may also be rectangular. In some embodiments, the adhesive materials 152, 154, and 182 may be made of the same material, which is different from the material of the thermal interface material 184.
[0026] The thermal interface material 184 may be a polymer with good thermal conductivity, ranging from about 3 W / m·K to about 5 W / m·K. In some embodiments, the thermal interface material 184 may include a polymer with thermally conductive filler. The thermally conductive filler may increase the effective thermal conductivity of the thermal interface material 184 to about 10 W / m·K to about 50 W / m·K or higher. Suitable thermally conductive filler materials may include alumina, boron nitride, aluminum nitride, aluminum, copper, silver, indium, combinations thereof, or the like. In other embodiments, the thermal interface material 184 may contain other materials, such as metal-based materials or solder-based materials composed of silver, indium paste, or the like thereof. In further embodiments, the thermal interface material 184 may contain thin film or sheet materials, such as sheet materials comprising synthetic carbon nanotubes (CNTs) or thermally conductive sheets with vertically oriented graphite fillers. Although thermal interface material 184 is described as a continuous material extending onto wafer 112, in other embodiments, thermal interface material 184 may include several separate portions. In some embodiments, thermal interface material 184 may be applied after adhesive material 182; however, thermal interface material 184 may also be applied before adhesive material 182.
[0027] Refer to Figures 5A and 5B. A top cover 174 is disposed on the contour ring 172 and the package 110. In the cross-sectional view of Figure 5B, the top cover 174 includes an upper portion 174A and a lower portion 174B extending downward from the upper portion 174A, wherein the lower portion 174B is narrower than the upper portion 174A. The lower portion 174B of the top cover 174 extends into the opening O1 of the contour ring 172, such that the lower portion 174B of the top cover 174 can be at least partially laterally aligned with the horizontal portion 172A of the contour ring 172. The upper portion 174A of the top cover 174 can cover the package 110 and the contour ring 172. That is, the upper portion 174A of the top cover 174 can overlap the contour ring 172 in the vertical direction. More specifically, the upper portion 174A of the top cover 174 can overlap with the vertical portion 172B of the contour ring 172. In some embodiments, the bottom surface of the lower portion 174B of the upper cover 174 may be higher than the wafer 112.
[0028] During the placement of the top cover 174 on the contour ring 172 and the package 110, the top cover 174 is placed on the contour ring 172, with the lower portion 174B of the top cover 174 extending into the opening O1 of the contour ring 172, such that the upper portion 174A of the top cover 174 contacts the adhesive material 182, and the lower portion of the top cover 174 contacts the thermal interface material 184. Next, the top cover 174 is pressed onto the adhesive material 182 and the thermal interface material 184 to engage the top cover 174 with the contour ring 172 and the package 110. In some embodiments, the thermal interface material 184 may be pressed so that the thermal interface material 184 can extend laterally and fill the space formed within the top cover 174, the contour ring 172, and the package 110. Therefore, after the top cover 174 is placed, the thermal interface material 184 can contact the sidewall of the horizontal portion 172A of the contour ring 172. In some embodiments, the thermal interface material 184 may also extend to the top surface of the horizontal portion 172A of the contour ring 172 and contact the adhesive material 182. Alternatively, the thermal interface material 184 may contact the bottom surface and sidewalls of the lower portion 174B of the top cover 174 and the bottom surface of the upper portion 174A of the top cover 174. In some embodiments, the thermal interface material 184 may also contact the adhesive material 154 and the bottom surface of the horizontal portion 172A of the contour ring 172. This can improve the adhesion between the top cover 174 and the underlying structure and improve the heat dissipation of the package structure 100.
[0029] In some embodiments, the cover 174 may be a metal, a metal alloy, or the like. For example, the cover 174 may comprise a metal and / or a metal alloy, such as Al, Cu, Ni, Co, combinations thereof, or the like. The cover 174 may also be formed of a composite material, such as silicon carbide, aluminum nitride, graphite, or the like. In some embodiments, the cover 174 may be a metal coated with another metal (e.g., gold). In some embodiments, the cover 174 may be made of stainless steel. The cover 174 may be formed of a material with a thermal conductivity of about 100 W / m·K to about 400 W / m·K, for example, about 400 W / m·K. In some embodiments, the cover 174 is a single continuous material. That is, the upper portion 174A of the cover 174 may be in direct contact with the lower portion 174B of the cover 174, which may increase the robustness of the cover 174. In some embodiments, the contour ring 172 and the cover 174 may be made of the same material to simplify manufacturing. In some embodiments, the contour ring 172 may be made of a more robust material than the material of the top cover 174. Alternatively, the top cover 174 may be made of a more robust material than the material of the contour ring 172. In some embodiments, the top cover 174 may be made of a material with higher thermal conductivity than the material of the contour ring 172, thereby creating a larger heat dissipation path for the chip 112 and improving the heat dissipation capability of the package structure.
[0030] Figure 6 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. In particular, Figure 6 is an enlarged view of Figure 3B. It should be noted that some elements of Figure 6 have been described above with reference to Figures 1A to 5B. The reference numerals for such elements are the same, and for the sake of brevity, the relevant details will not be repeated.
[0031] The vertical distance between the top surface of the substrate 120 and the top surface of the package 110 (or the top surface of the wafer 112) is called the height H1. The vertical distance between the top surface of the substrate 120 and the bottom surface of the horizontal portion 172A of the contour ring 172 is called the height H2. The horizontal portion 172A of the contour ring 172 has a vertical thickness D1, and the vertical portion 172B of the contour ring 172 has a lateral thickness D2. The interface length between the adhesive material 154 and the top surface of the package 110 (or the top surface of the encapsulant 130) is called the width W1. The distance between the outer sidewall of the encapsulant 130 and the nearest wafer 112 is called the width W2. The distance between the outer sidewall of the substrate 120 and the sidewall of the package 110 (or the sidewall of the encapsulant 130) is called the length L1. The distance between the outer sidewall of the contour ring 172 and the inner sidewall of the contour ring 172 is called the length L2 (ring length).
[0032] In some embodiments, the height H2 may be greater than the height H1. The thickness D1 may be equal to or greater than the height H1. For example, the thickness D1 may be 1 to 1.5 times H1. The length L2 is less than the length L1. The thickness D2 is less than the length L1. For example, the thickness D2 is 0.3 to 0.6 times L1. These ensure that the contour ring 172 has sufficient space to be disposed on the substrate 120. The width W1 is less than the width W2. This ensures that the adhesive material 154 does not cover the top surface of the wafer 112, thereby improving the packaging quality.
[0033] The embodiments disclosed herein provide a packaging structure by providing a contour ring 172 on a substrate 120 and then providing a top cover 174 on the contour ring 172. The contour ring 172 has an opening that exposes the package 110 disposed on the substrate 120, and the top cover 174 has a portion extending into the opening of the contour ring 172 (e.g., a lower portion 174B). The robustness of the contour ring 172 and the downward force applied when the contour ring 172 is disposed can mitigate package warpage of the substrate 120, which in turn reduces coplanarity (COP) problems after the contour ring 172 is disposed on the substrate 120. For example, when the substrate 120 warps (e.g., the substrate 120 bends), the contour ring 172 with the opening is first disposed on the substrate 120 without contacting the package 110. Therefore, the downward force can only be applied to the edge portion of the substrate 120, and the substrate 120 is pressed over the contour ring 172 to reduce warpage. It should be noted that during the application of downward force, the profile ring 172 can be secured to the substrate 120 at more than one location (e.g., by adhesive materials 152 and 154) using adhesives, thereby increasing the robustness and structural support of the profile ring 172. Since the warpage of the substrate 120 has been reduced, the thermal interface material 184 can be evenly distributed on the portion extending to the opening of the profile ring 172, which in turn improves heat dissipation efficiency. The thermal interface material 184 can also contact the profile ring 172 and the top cover 174 after the top cover 174 is attached, thereby further improving heat dissipation efficiency. However, if the profile ring is disposed on the substrate 120 and contacts the package 110 (by adhesive material), the package 110 may press against the profile ring 172 during placement, and the downward force may not be able to restore the bent substrate 120. In such cases, warpage may still exist, and the COP problem may not be reduced, which may lead to unsatisfactory heat dissipation performance.
[0034] Figures 7A to 9B illustrate methods for forming a package structure at different stages according to some embodiments of the present disclosure. Figures 7A, 8A, and 9A are top views of the package structure, and Figures 7B, 8B, and 9B are cross-sectional views of the package structure. More specifically, Figures 7B, 8B, and 9B are cross-sectional views along line BB of Figures 7A, 8A, and 9A, respectively. It should be noted that some elements of Figures 7A to 9B have been described above with reference to Figures 1A to 5B. These elements are labeled identically, and for the sake of brevity, related details will not be repeated.
[0035] Refer to Figures 7A and 7B. A contour ring 272 is disposed on the substrate 120 and surrounds the package 110. The shape of the contour ring 272 in Figures 7A and 7B differs from the contour ring 172 discussed in Figures 1A to 5B. In some embodiments, the contour ring 272 may also include an L-shaped cross-sectional view. For example, the contour ring 272 may include a horizontal portion 272A and a vertical portion 272B extending downward from one end of the horizontal portion 272A. In the lateral direction, the vertical portion 272B is narrower than the horizontal portion 272A. The horizontal portion 272A of the contour ring 272 is in contact with the adhesive material 154, and the vertical portion 272B of the contour ring 272 is in contact with the adhesive material 252. The adhesive material 154 may contact the sidewalls and bottom surface of the horizontal portion 272A of the contour ring 272. In some embodiments, the bottom surface of the horizontal portion 272A of the contour ring 272 is lower than the top surface of the wafer 112 and the encapsulant 130, while the top surface of the horizontal portion 272A of the contour ring 272 is higher than the top surface of the wafer 112 and the encapsulant 130.
[0036] The contour ring 272 includes an opening O2. In some embodiments, the opening O2 may expose all of the wafer 112 of the package 110. That is, in the cross-sectional view of Figure 7B, the contour ring 272 may not overlap with the wafer 112 in the vertical direction. In some embodiments, the contour ring 172 may not overlap with the encapsulating adhesive 130 surrounding the wafer 112.
[0037] Refer to Figures 8A and 8B. Adhesive material 182 and thermal interface material (TIM) 184 are respectively coated on the contour ring 272 and the package 110. More specifically, adhesive material 182 is coated on and in contact with the horizontal portion 272A of the contour ring 272. Thermal interface material 184 is coated on and in contact with the top surfaces of the wafer 112 and the encapsulant 130. In some embodiments, the bottom surface of thermal interface material 184 may be lower than the bottom surface of adhesive material 182. Thermal interface material 184 may be spaced apart from the contour ring 172 and the adhesive material 182.
[0038] See Figures 9A and 9B. A top cover 174 is disposed on the contour ring 272 and the package 110. The lower portion 174B of the top cover 174 extends into the opening O2 of the contour ring 272, such that the lower portion 174B of the top cover 174 can be at least partially laterally aligned with the horizontal portion 272A of the contour ring 272. The upper portion 174A of the top cover 174 can cover the package 110 and the contour ring 272. That is, the upper portion 174A of the top cover 174 can overlap with the contour ring 272 in the vertical direction. More specifically, the upper portion 174A of the top cover 174 can overlap with the vertical portion 272B of the contour ring 272.
[0039] Therefore, after the top cover 174 is disposed on the contour ring 272 and the package 110, the thermal interface material 184 can contact the sidewall of the horizontal portion 272A of the contour ring 272. In some embodiments, the thermal interface material 184 can also extend to the top surface of the horizontal portion 272A of the contour ring 272 and contact the adhesive material 182. On the other hand, the thermal interface material 184 can contact the bottom surface and sidewall of the lower portion 174B of the top cover 174 and the bottom surface of the upper portion 174A of the top cover 174. In some embodiments, the thermal interface material 184 can extend to a position below the top surface of the wafer 112 and the encapsulant 130.
[0040] Figure 10 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. In particular, Figure 10 is an enlarged view of Figure 7B. It should be noted that some elements of Figure 10 have been described above with reference to Figures 7A to 9B. The reference numerals for such elements are the same, and for the sake of brevity, the relevant details will not be repeated.
[0041] The vertical distance between the top surface of the substrate 120 and the top surface of the surface device 160 is called the height H3. The vertical distance between the top surface of the substrate 120 and the bottom surface of the horizontal portion 272A of the contour ring 272 is called the height H4. The horizontal portion 272A of the contour ring 272 has a vertical thickness D3, and the vertical portion 272B of the contour ring 272 has a lateral thickness D4. The interface length between the adhesive material 154 and the top surface of the package 110 (or the top surface of the encapsulant 130) is called the width W1. The distance between the outer sidewall of the encapsulant 130 and the nearest wafer 112 is called the width W2. The distance between the outer sidewall of the substrate 120 and the sidewall of the package 110 (or the sidewall of the encapsulant 130) is called the length L1. The distance between the outer sidewall of the contour ring 172 and the inner sidewall of the contour ring 172 is called the length L3 (ring length).
[0042] Height H4 may be greater than height H3. Thickness D3 may be equal to or greater than height H3. For example, thickness D3 may be 2 to 2.5 times H3. Length L3 is less than length L1. Thickness D4 is less than length L1. For example, thickness D4 is 0.3 to 0.6 times L1. This ensures that the contour ring 172 has sufficient space to be disposed on the substrate 120. Width W1 is less than width W2. This ensures that the adhesive material 154 does not cover the top surface of the wafer 112, thereby improving packaging quality.
[0043] Figures 11A to 14B illustrate methods for forming a package structure at different stages according to some embodiments of the present disclosure. Figures 11A, 12A, 13A, and 14A are top views of the package structure, and Figures 11B, 12B, 13B, and 14B are cross-sectional views of the package structure. More specifically, Figures 11B, 12B, 13B, and 14B are cross-sectional views along line BB of Figures 11A, 12A, 13A, and 14A, respectively. It should be noted that some elements in Figures 11A to 14B have been described above with reference to Figures 1A to 5B. These elements are labeled identically, and for the sake of brevity, related details will not be repeated.
[0044] Refer to Figures 11A and 11B. Adhesive materials 152 and 155 are applied to substrate 120. In the top view of Figure 11A, the top outlines of both adhesive materials 152 and 155 are rectangular rings. More specifically, adhesive material 152 surrounds adhesive material 155. Furthermore, adhesive material 155 may surround wafer 112 and may also surround encapsulant 130. In the cross-sectional view of Figure 11B, adhesive material 155 is spaced apart from package 110. Each surface device 160 is located between adhesive material 152 and adhesive material 155.
[0045] Refer to Figures 12A and 12B. A contour ring 372 is disposed on the substrate 120 and surrounds the package 110. As shown in the top view of Figure 12A, the top contour of the contour ring 372 is a rectangular ring shape, including an opening O3. On the other hand, as shown in the cross-sectional view of Figure 12B, the contour ring 372 is connected to the substrate 120 by adhesive materials 152 and 155. The contour ring 372 may include a horizontal portion 372A and vertical portions 372B and 372C extending downward from opposite ends of the horizontal portion 372A. The vertical portions 372B and 372C are in contact with the adhesive materials 152 and 155, respectively. In some embodiments, the bottom surface of the horizontal portion 372A of the contour ring 372 is lower than the top surface of the wafer 112 and the encapsulant 130, while the top surface of the horizontal portion 372A of the contour ring 372 is higher than the top surface of the wafer 112 and the encapsulant 130.
[0046] As described above, the contour ring 372 includes an opening O3. In some embodiments, the opening O3 may expose all wafers 112 of the package 110. That is, in the cross-sectional view of Figure 3B, the contour ring 372 may not overlap with the wafer 112 in the vertical direction. In some embodiments, the contour ring 372 may not overlap with the encapsulant 130 and the underfill material 135.
[0047] Refer to Figures 13A and 13B. Adhesive material 182 and thermal interface material (TIM) 184 are respectively coated on the contour ring 372 and the package 110. More specifically, adhesive material 182 is coated on and in contact with the horizontal portion 372A of the contour ring 372. Thermal interface material 184 is coated on and in contact with the top surfaces of the wafer 112 and the encapsulant 130. In some embodiments, the bottom surface of thermal interface material 184 may be lower than the bottom surface of adhesive material 182. Thermal interface material 184 may be spaced apart from the contour ring 372 and adhesive material 182.
[0048] Refer to Figures 14A and 14B. A top cover 174 is disposed on the contour ring 272 and the package 110. The lower portion 174B of the top cover 174 extends into the opening O3 of the contour ring 372, such that the lower portion 174B of the top cover 174 can be at least partially laterally aligned with the horizontal portion 372A of the contour ring 372. The upper portion 174A of the top cover 174 can cover the package 110 and the contour ring 372. That is, the upper portion 174A of the top cover 174 can overlap the contour ring 372 in the vertical direction.
[0049] Figure 15 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. In particular, Figure 15 is an enlarged view of Figure 12B. It should be noted that some elements of Figure 15 have been described above with reference to Figures 11A to 14B. The reference numerals for such elements are the same, and for the sake of brevity, the relevant details will not be repeated.
[0050] The vertical distance between the top surface of the substrate 120 and the top surface of the surface mount 160 is called height H8. The vertical distance between the top surface of the substrate 120 and the top surface of the horizontal portion 372A of the contour ring 372 is called height H5. The vertical distance between the top surface of the substrate 120 and the top surface of the package 110 is called height H6. The vertical distance between the top surface of the substrate 120 and the bottom surface of the horizontal portion 372A of the contour ring 372 is called height H7. The vertical portion 372B of the contour ring 372 has a lateral thickness D5, and the vertical portion 372C of the contour ring 372 has a lateral thickness D6. The vertical thickness of the horizontal portion 372A is D7. The distance between the surface mount 160 and the underfill material 135 is called width W3. The distance between the outer sidewall of the encapsulant 130 and the nearest wafer 112 is called W2. The distance between the outer sidewall of the substrate 120 and the underfill material 135 is called length L4. The distance between the outer wall of the contour ring 372 and the inner wall of the contour ring 372 is called the length L5 (ring length).
[0051] Height H7 may be greater than height H8. Height H5 may be greater than height H6. For example, height H5 may be 3 to 3.5 times the height H6. Length L5 is less than length L4. Thickness D5 is less than width W3. This ensures that the vertical portion 372B is located between the surface device 160 and the bottom filler material 135. The sum of thicknesses D5 and D6 may be less than length L4. For example, the sum of thicknesses D5 and D6 (e.g., D5 + D6) may be 0.5 to 0.8 times L4. In some embodiments, thickness D6 is different from thickness D5 to better reduce COP. For example, thickness D6 may be greater than thickness D5 to prevent COP problems. In other embodiments, thickness D6 is substantially the same as thickness D5 to simplify manufacturing. In some embodiments, thickness D7 is greater than thicknesses D5 and D6. That is, horizontal portion 372A is thicker than vertical portions 372B and 372C.
[0052] An additional portion (e.g., vertical portion 372B) of the contour ring 372 between the surface device 160 and the underfill material 135 provides better adhesion between the ring and the substrate 120. The better ring adhesion, the robustness of the contour ring 372, and the downward force when the contour ring 372 is attached reduce package warpage of the substrate 120, which in turn reduces coplanarity (COP) issues after the contour ring 372 is attached to the substrate 120. Since the warpage of the substrate 120 is reduced, the thermal interface material 184 can be uniformly distributed on the portion extending to the opening of the contour ring 172, which in turn improves heat dissipation efficiency.
[0053] Figures 16A and 16B are cross-sectional views of a package structure according to some embodiments of the present disclosure. More specifically, Figure 16B is an enlarged view of Figure 16A. Figure 16A is similar to Figure 14B, and Figure 16B is similar to Figure 15, except that in Figures 16A and 16B, the thickness D7 of the horizontal portion 372A of the contour ring 372 is less than the thicknesses D5 and D6 of the vertical portions 372B and 372C. That is, the horizontal portion 372A is thinner than the vertical portions 372B and 372C. Furthermore, the height H7 may be greater than the height H6. That is, the bottom surface of the horizontal portion 372A of the contour ring 372 may be higher than the top surface of the package 110. This configuration allows for more space for surface devices 160 of different thicknesses, which is beneficial for improving manufacturing flexibility.
[0054] Figure 17 is a cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Figure 17 is similar to Figure 5B, wherein a heat sink 194 is additionally provided on the top cover 174 by means of a thermal interface material 192. The thermal interface material 192 may include a material similar to the thermal interface material 184. In some embodiments, the heat sink 194 may include a heat sink and / or a cooling device. For example, the heat sink may include a planar bottom surface to which the thermal interface material 192 is attached. The heat sink may also include a plurality of heat sink fins, with a plurality of grooves separating the plurality of heat sink fins. The cooling device may be a fan or other fan-driven device. It should be noted that the heat sink 194 may also be applied to the structures of Figures 9B, 14B, and 16A. That is, the heat sink 194 may be provided on the top cover 174 of the structures of Figures 9B, 14B, and 16A by means of a thermal interface material 192.
[0055] Based on the above embodiments, it can be seen that the present disclosure has advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no particular advantage is necessary for all embodiments. Embodiments of the present disclosure provide a package structure by providing a contour ring on a substrate and then providing a top cover on the contour ring, wherein the contour ring has an opening that exposes the package disposed on the substrate, and a portion of the top cover extends into the opening of the contour ring. The robustness of the contour ring and the downward force when the contour ring is disposed can mitigate package warpage on the substrate, which in turn reduces coplanarity (COP) problems after the contour ring is attached to the substrate. For example, when the substrate warps (e.g., the substrate bends), the contour ring with the opening is first disposed on the substrate without contacting the package on the substrate. Therefore, the downward force can only be applied to the edge portion of the substrate, and the substrate is pressed over the contour ring to reduce warpage. It should be noted that during the application of downward force, the profile ring can be secured to the substrate at more than one location using adhesive, thereby increasing the profile ring's rigidity and structural support. Since the substrate warpage has been reduced, the thermal interface material can be evenly distributed across the portion extending to the profile ring opening, which in turn improves heat dissipation efficiency. The thermal interface material can also contact the profile ring and the top cover after the top cover is attached, further enhancing heat dissipation efficiency.
[0056] In some embodiments of this disclosure, a package structure includes a substrate. A package is located on the substrate. A contour ring is disposed on the substrate, wherein the contour ring surrounds the package and has an opening. A top cover is disposed on the contour ring, wherein the top cover has a portion extending into the opening of the contour ring.
[0057] In some embodiments, the packaging structure further includes an adhesive material along one surface of the package, wherein the contour ring is disposed on the substrate by means of the adhesive material.
[0058] In some embodiments, the packaging structure further includes a thermal interface material located between the packaging and the portion of the top cover.
[0059] In some embodiments, the thermal interface material is in contact with the contour ring.
[0060] In some embodiments, in a cross-sectional view, the contour ring includes a horizontal portion and a first vertical portion extending downward from one end of the horizontal portion, and the first vertical portion is narrower than the horizontal portion in a lateral direction.
[0061] In some embodiments, in the cross-sectional view, the contour ring further includes a second vertical portion extending downward from the other end of the horizontal portion, and the second vertical portion is narrower than the horizontal portion in the lateral direction.
[0062] In some embodiments, the packaging structure further includes a surface device disposed on the substrate and laterally located between the first vertical portion and the second vertical portion of the contour ring.
[0063] In some embodiments, the second vertical portion is closer to the package than the first vertical portion, and the second vertical portion is narrower than the first vertical portion in the lateral direction.
[0064] In some embodiments of this disclosure, a package structure includes a substrate. A package is located on the substrate and includes a plurality of wafers. A contour ring is on the substrate, wherein the contour ring includes a horizontal portion and a vertical portion extending downward from one end of the horizontal portion. A top cover is disposed on the contour ring, wherein, in a top view, the top cover includes a first portion overlapping the horizontal portion of the contour ring and a second portion overlapping the wafers of the package.
[0065] In some embodiments, one of the lowermost surfaces of the cover is lower than a top surface of the horizontal portion of the contour ring.
[0066] In some embodiments, the packaging structure further includes an adhesive material extending from one top surface of the package to one top surface of the substrate, wherein the adhesive material contacts the horizontal portion of the contour ring.
[0067] In some embodiments, the wafers of the package are not covered by the contour ring.
[0068] In some embodiments, a bottom surface of the horizontal portion of the contour ring is higher than a top surface of the package.
[0069] In some embodiments, a bottom surface of the horizontal portion of the contour ring is lower than a top surface of the package.
[0070] In some embodiments, the cover includes an upper portion and a lower portion located below the upper portion, the upper portion of the cover being wider than the lower portion of the cover, and the upper portion of the cover being perpendicularly coincident with the vertical portion of the contour ring.
[0071] In some embodiments of this disclosure, a method includes: packaging one of a plurality of wafers on a substrate; applying a first adhesive material and a second adhesive material to the substrate and surrounding the package, wherein the first adhesive material surrounds the second adhesive material; disposing a contour ring on the substrate and contacting the first adhesive material and the second adhesive material; and disposing a top cover on the contour ring.
[0072] In some embodiments, the cover has an upper portion and a lower portion extending downward from the upper portion, the lower portion of the cover extending into an opening of the contour ring, and the upper portion of the cover being located above a top surface of the contour ring.
[0073] In some embodiments, the contour ring includes a horizontal portion and one or more vertical portions extending downward from the horizontal portion.
[0074] In some embodiments, the method further includes applying a third adhesive material to the contour ring and disposing a thermal interface material on the package before placing the top cover on the contour ring, wherein the top cover is in contact with the thermal interface material and the third adhesive material.
[0075] In some embodiments, the thermal interface material is spaced apart from the third adhesive material and the contour ring before the top cover is disposed on the contour ring, and the thermal interface material comes into contact with the third adhesive material and the contour ring after the top cover is disposed on the contour ring.
[0076] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]
[0005] The various aspects of this disclosure can be better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of various features may be arbitrarily increased or decreased. Figures 1A to 5B illustrate methods at different stages of forming a package structure according to some embodiments of this disclosure. Figure 6 is a cross-sectional view of a package structure according to some embodiments of this disclosure. Figures 7A to 9B illustrate methods at different stages of forming a package structure according to some embodiments of this disclosure. Figure 10 is a cross-sectional view of a package structure according to some embodiments of this disclosure. Figures 11A to 14B illustrate methods at different stages of forming a package structure according to some embodiments of this disclosure. Figure 15 is a cross-sectional view of a package structure according to some embodiments of this disclosure. Figures 16A and 16B are cross-sectional views of a package structure according to some embodiments of this disclosure. Figure 17 is a cross-sectional view of a package structure according to some embodiments of this disclosure. [Biomaterial Storage]
[0078] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.
Claims
1. A packaging structure comprising: a substrate; a package disposed on the substrate, wherein the package includes a wafer and an encapsulating adhesive covering the wafer; an adhesive material surrounding the package and contacting the encapsulating adhesive; a contour ring disposed on the substrate and contacting the adhesive material, wherein the contour ring surrounds the package and has an opening; a top cover disposed on the contour ring, wherein the top cover has a portion extending into the opening of the contour ring; and a thermal interface material disposed between the portion of the package and the top cover, the thermal interface material filling a space formed within the top cover, the contour ring, and the package.
2. The packaging structure as claimed in claim 1, wherein, in a cross-sectional view, the contour ring includes a horizontal portion and a first vertical portion extending downward from one end of the horizontal portion, and the first vertical portion is narrower than the horizontal portion in a lateral direction.
3. The packaging structure as claimed in claim 2, wherein, in the cross-sectional view, the contour ring further includes a second vertical portion extending downward from the other end of the horizontal portion, and the second vertical portion is narrower than the horizontal portion in the lateral direction.
4. The packaging structure as described in claim 3 further includes a surface device disposed on the substrate and laterally located between the first vertical portion and the second vertical portion of the contour ring.
5. A packaging structure comprising: a substrate; a package located on the substrate and including a plurality of wafers and an encapsulating adhesive covering the wafers; an adhesive material surrounding the package and contacting the encapsulating adhesive of the package; a contour ring located on the substrate and contacting the encapsulating adhesive of the package, wherein the contour ring includes a horizontal portion and a vertical portion extending downward from one end of the horizontal portion; a top cover disposed on the contour ring, wherein, in a top view, the top cover includes a first portion overlapping the horizontal portion of the contour ring and a second portion overlapping the wafers of the package; and a thermal interface material disposed between the package and the second portion of the top cover, the thermal interface material filling the space formed within the top cover, the contour ring, and the package.
6. The packaging structure as described in claim 5, wherein one of the lowest surfaces of the top cover is lower than a top surface of the horizontal portion of the contour ring.
7. The encapsulation structure as described in claim 5, wherein the adhesive material contacts the thermal interface material.
8. The packaging structure as described in claim 5, wherein the wafers of the package are not covered by the contour ring.
9. A method of forming a package structure, comprising: disposing a package on a substrate, wherein the package includes a plurality of wafers and an encapsulating adhesive covering the wafers; applying a first adhesive material and a second adhesive material to the substrate and surrounding the package, wherein the first adhesive material surrounds the second adhesive material and the second adhesive material contacts the encapsulating adhesive of the package; disposing a contour ring on the substrate and contacting the first adhesive material and the second adhesive material; applying a third adhesive material to the contour ring and disposing a thermal interface material on the package, wherein the thermal interface material is spaced apart from the third adhesive material and the contour ring; and disposing a top cover on the contour ring and pressing the thermal interface material to fill the space formed in the top cover, the contour ring, and the package.
10. The method of claim 9, wherein the cover has an upper portion and a lower portion extending downward from the upper portion, the lower portion of the cover extending into an opening of the contour ring, and the upper portion of the cover being located above a top surface of the contour ring.
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