Data access apparatus for SRAM array, system, method, device, chip and medium

Abstract

Data access apparatus, system, method, electronic device, system-on-a-chip, and computer-readable storage medium for SRAM arrays. The apparatus includes: M arbitration modules, each coupled to one of the M SRAM groups; and a parsing module, coupled to the M arbitration modules, configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command, pointing to an SRAM group, and sending the access command to the arbitration module coupled to the pointed-to SRAM group; wherein each arbitration module, when determining that the received access command pointing to the corresponding SRAM group is a single command, sends the access command pointing to the corresponding SRAM group to the corresponding SRAM group for execution of the access command by the corresponding SRAM group.

Description

Data Access Device, System, Data Access Method, Electronic Device, System-on-Chip, and Computer-Readable Storage Medium for SRAM Array The present invention relates to the field of data storage, and in particular to a data access device, system, data access method, electronic device, system-on-chip, and computer-readable storage medium for a static random-access memory (SRAM) array. SRAM is a commonly used storage device in chip design. Limited by the SRAM manufacturing process, the capacity of a single SRAM is usually limited. A system-on-chip (SOC) has a large demand for SRAM space and usually uses an SRAM array containing multiple SRAM groups to achieve large-space storage. Currently, for an SRAM array containing multiple SRAM groups, when accessing one SRAM group in the SRAM array, other SRAM groups are in an idle state and cannot be accessed (unreadable and unwritable), resulting in low access efficiency. Embodiments of the present invention provide a data access device, system, data access method, electronic device, system-on-chip, and computer-readable storage medium for an SRAM array. The technical solutions of the embodiments of the present invention are as follows: A data access device for an SRAM array, the SRAM array includes M SRAM groups, and the device includes: M arbitration modules, each arbitration module is coupled to one of the M SRAM groups; A parsing module, coupled to the M arbitration modules, for receiving N data access requests in parallel, parsing at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and sending the access command to the arbitration module coupled to the pointed SRAM group; Wherein, each arbitration module is configured to, when it is determined that the received access command pointing to the corresponding SRAM group is a single one, send the access command pointing to the corresponding SRAM group to the corresponding SRAM group for the corresponding SRAM group to execute the access command; Wherein, M is a positive integer greater than or equal to 2, and N is a positive integer. A data access system for an SRAM array, including: An SRAM array, the SRAM array includes multiple SRAM groups, and each SRAM group includes multiple SRAMs; M arbitration modules, each arbitration module is coupled to one of the M SRAM groups; A parsing module, coupled to the M arbitration modules, is configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and pointing to a corresponding SRAM bank, and send the access command to the arbitration module coupled to the pointed SRAM bank; Wherein, each of the arbitration modules is configured to, when determining that a single access command is received, send the received access command to the corresponding SRAM bank for the corresponding SRAM bank to execute the received access command; Wherein, M is a positive integer greater than or equal to 2, and N is a positive integer. A system-on-chip includes a data access device of the SRAM array as described above or a data access system of the SRAM array as described above. A method for accessing data of an SRAM array, the SRAM array including M SRAM banks, the method comprising: Receiving N data access requests; Parsing at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM bank; Performing arbitration processing for the access commands pointing to each SRAM bank, including: when determining that the access command pointing to the corresponding SRAM bank is single, sending the access command pointing to the corresponding SRAM bank to the corresponding SRAM bank for the corresponding SRAM bank to execute the access command; wherein, M is a positive integer greater than or equal to 2, and N is a positive integer. An electronic device includes: A memory; A processor; Wherein, an application program executable by the processor is stored in the memory, for causing the processor to execute the method for accessing data of the SRAM array as described above. A computer-readable storage medium stores computer-readable instructions thereon, and when the computer-readable instructions are executed by a processor, the processor is caused to execute the method for accessing data of the SRAM array as described above. It can be seen from the above technical solutions that in the embodiments of the present invention, multiple data access requests are received in parallel, each data access request is parsed to send the access commands to the arbitration modules coupled to their respective pointed SRAM banks respectively, realizing parallel processing for multiple data access requests, enabling parallel access to multiple SRAM banks, improving the access efficiency of the SRAM array, and also solving the conflict problem of read commands and write commands accessing the same SRAM bank simultaneously based on the arbitration modules. To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings. For the sake of brevity and intuitiveness in description, the solutions of the present invention will be elaborated below by describing several representative embodiments. A large number of details in the embodiments are only used to help understand the solutions of the present invention. However, it is obvious that the technical solutions of the present invention can be implemented without being limited to these details. In order to avoid unnecessarily obscuring the solutions of the present invention, some embodiments are not described in detail, but only the framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the quantity of a component is not specifically indicated hereinafter, it means that the component can be one or more, or can be understood as at least one. FIG. 1 is a schematic diagram of accessing an SRAM array in the related art. The SRAM array usually includes multiple SRAM groups, and each SRAM group includes multiple SRAMs. The SRAM array shown in FIG. 1 includes M SRAM groups, namely SRAM group 1, SRAM group 2, SRAM group 3... SRAM group M. Each SRAM group respectively includes p SRAMs. Therefore, the SRAM array totally includes M*p SRAMs. Among them, M is a positive integer greater than or equal to 2. p is a positive integer. In some embodiments, the SRAM group is an access object for data access requests in technical practice. At the same moment, the SRAM array can only process one data access request (the data access request includes a read command or a write command, and cannot include both a read command and a write command at the same time), and based on this data access request, only one SRAM group in the SRAM array is accessed, and other SRAM groups cannot be accessed simultaneously. For example, assume that the data access party (such as a host) needs to read data from SRAM group 1 in the SRAM array. The data access party sends a read command with SRAM group 1 as the destination address to the SRAM array. The SRAM array responds to this read command and returns the data in SRAM group 1 to the data access party. However, when it is necessary to simultaneously (i.e., in parallel) access at least two SRAM groups in the SRAM array (for example, request to read data from SRAM group 1 and write data to SRAM group 2 in parallel), the related art cannot access multiple SRAM groups in parallel. To solve the above problems, the applicant considered sending a read command with SRAM group 1 as the destination address and a write command with SRAM group 2 as the destination address to the SRAM array in parallel. However, the applicant further found that: since there is no corresponding mechanism in the SRAM array to cooperate in processing multiple parallel data access requests, this simple solution of sending multiple data access requests to the SRAM array in parallel cannot achieve parallel access to multiple SRAM groups. The embodiments of the present invention propose a data access technical solution for an SRAM array, which receives multiple data access requests, parses each data access request to send access commands to arbitration modules coupled to the SRAM groups pointed to respectively, realizes parallel processing of multiple data access requests, accesses multiple SRAM groups in parallel, and improves the access efficiency of the SRAM array. FIG. 2 is an exemplary structural diagram of a data access device for an SRAM array according to an embodiment of the present invention. The SRAM array shown in FIG. 2 includes M SRAM groups, namely SRAM group 1, SRAM group 2, SRAM group 3... SRAM group M. Each SRAM group includes p SRAMs respectively. Therefore, the SRAM array includes a total of M * p SRAMs. The data access device includes: M arbitration modules, corresponding to the M SRAM groups, where each arbitration module is coupled to one of the M SRAM groups; A parsing module coupled to the M arbitration modules, configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and send the access command to the arbitration module coupled to the pointed SRAM group. Each of the M arbitration modules is configured to, when it is determined that the received access command pointing to the corresponding SRAM group is a single one, send the access command pointing to the corresponding SRAM group to the corresponding SRAM group for the corresponding SRAM group to execute the access command; where M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1. In an alternative embodiment, the M arbitration modules can be integrated into an overall arbitration unit, and the overall arbitration unit corresponds to the M SRAM groups to perform access arbitration processing for the M SRAM groups as a whole. In another alternative embodiment, a part of the M arbitration modules can be integrated into one or more (the specific number can depend on the specific integration strategy) arbitration units, and the remaining arbitration modules remain functionally independent. At this time, the one or more integrated arbitration units perform access arbitration processing for the SRAM groups corresponding to the one or more arbitration units as a whole, and the remaining arbitration modules continue to independently perform access arbitration processing for the SRAM groups corresponding to the remaining arbitration modules. It can be seen that parallel processing of multiple data access requests is realized, multiple SRAM groups can be accessed in parallel, and the access efficiency of the SRAM array is improved. In one embodiment, the parsing module can receive N data access requests in parallel from a full-duplex data transfer bus; where the full-duplex data transfer bus includes at least one of the following: AXI-Lite; AXI-Full; AXI-Stream. Among them: both AXI-Lite and AXI-Full implement data transfer in the form of memory mapping (i.e., including an address bus), while AXI-Stream implements transfer in the form of a data stream without an address bus. AXI-Lite is a simplified version of AXI-Full, suitable for small-batch data transfer and commonly used for command transfer; AXI-Full is suitable for large-batch, high-performance data transfer. The above exemplary description shows typical examples of the full-duplex data transfer bus. Those of ordinary skill in the art can realize that such a description is only exemplary and is not used to limit the embodiments of the present invention. In one embodiment, each data access request may include at least one access command. For example, a data access request may simultaneously include a write command and a read command, where the destination SRAM bank of the write command and the destination SRAM bank of the read command may be the same or different. Example 1: The data access request 1 in Figure 2 may simultaneously include a write command and a read command. The destination SRAM bank of the write command is SRAM bank 1, that is, the write command points to SRAM bank 1. The destination SRAM bank of the read command is SRAM bank 2, that is, the read command points to SRAM bank 2. That is, the data access request 1 indicates to initiate a write operation for SRAM bank 1 and a read operation for SRAM bank 2. Example 2: The data access request 1 in Figure 2 simultaneously includes a write command and a read command. The destination SRAM bank of the write command is SRAM bank 1, that is, the write command points to SRAM bank 1. The destination SRAM bank of the read command is SRAM bank 1, that is, the read command points to SRAM bank 1. That is, the data access request 1 indicates to initiate a write operation for SRAM bank 1 and a read operation for SRAM bank 1. In this case, there are both a read command and a write command for the same SRAM bank, which usually causes a conflict problem. This conflict problem can be solved by the arbitration mechanism of the arbitration module described in detail later. In one embodiment, a data access request may only include one of a write command and a read command. Example 1: The data access request 2 in Figure 2 only includes a write command, and the destination SRAM bank of the write command is SRAM bank 1. That is, the data access request 2 indicates to initiate a write operation for SRAM bank 1. Example 2: The data access request 2 in Figure 2 only contains a read command, and the target SRAM bank of the read command is SRAM bank 2. That is, the data access request 2 indicates to initiate a read operation for SRAM bank 2. The parsing module respectively parses at least one access command in each of the N data access requests. Each access command is a read command or a write command, and then sends the access command to an arbitration module coupled to the SRAM bank pointed to by the access command. Example: Assume that there are 4 data access requests received by the parsing module, which are data access request 1, data access request 2, data access request 3, and data access request 4 respectively. Data access request 1 includes: (1) a write command 1 with SRAM bank 1 as the target SRAM bank; (2) a read command 1 with SRAM bank 2 as the target SRAM bank. Data access request 2 includes: (1) a write command 2 with SRAM bank 3 as the target SRAM bank. Data access request 3 includes: (1) a write command 3 with SRAM bank 4 as the target SRAM bank; (2) a read command 2 with SRAM bank 5 as the target SRAM bank. Data access request 4 includes: (1) a write command 4 with SRAM bank 6 as the target SRAM bank; (2) a read command 3 with SRAM bank 7 as the target SRAM bank. The parsing module sends the write command 1 (with SRAM bank 1 as the target SRAM bank) to the arbitration module 1 corresponding to SRAM bank 1; sends the read command 1 (with SRAM bank 2 as the target SRAM bank) to the arbitration module 2 corresponding to SRAM bank 2; sends the write command 2 (with SRAM bank 3 as the target SRAM bank) to the arbitration module 3 corresponding to SRAM bank 3; sends the write command 3 (with SRAM bank 4 as the target SRAM bank) to the arbitration module 4 corresponding to SRAM bank 4; sends the read command 2 (with SRAM bank 5 as the target SRAM bank) to the arbitration module 5 corresponding to SRAM bank 5; sends the write command 4 (with SRAM bank 6 as the target SRAM bank) to the arbitration module 6 corresponding to SRAM bank 6; sends the read command 3 (with SRAM bank 7 as the target SRAM bank) to the arbitration module 7 corresponding to SRAM bank 7. Each arbitration module from arbitration module 1 to arbitration module 7 determines that the received access command directed to the corresponding SRAM bank is single, for example, it determines that there are no write command and read command existing simultaneously. Therefore, the respective write command or read command can be sent to their respective corresponding SRAM banks respectively, so that multiple SRAM banks can execute multiple commands concurrently. Specifically: SRAM bank 1 executes write command 1; SRAM bank 2 executes read command 1; SRAM bank 3 executes write command 2; SRAM bank 4 executes write command 3; SRAM bank 5 executes read command 2; SRAM bank 6 executes write command 4; SRAM bank 7 executes read command 3, thereby achieving parallel access to the 7 SRAM banks in the SRAM array. The above describes an exemplary example where the arbitration module does not receive a read command and a write command from the parsing module simultaneously. In fact, based on the specific configuration of the data access request, the arbitration module may also receive a read command and a write command from the parsing module simultaneously, that is, there is a read-write conflict problem. In one embodiment, each arbitration module is used to, when determining that the received access command directed to the corresponding SRAM bank is at least two commands, determine the execution order of the received at least two access commands based on a predetermined arbitration strategy, and send the at least two access commands to the corresponding SRAM bank in sequence according to the execution order, so that the corresponding SRAM bank executes the at least two access commands in sequence. For example, when it is determined that there are a read command and a write command both targeting the corresponding SRAM bank simultaneously, arbitration is performed on the read command and the write command both targeting the corresponding SRAM bank based on a predetermined arbitration strategy to obtain an arbitration result representing the execution order. Based on the arbitration result, an access command (for example, a read command or a write command both targeting the corresponding SRAM bank) is first sent to the corresponding SRAM bank, so that the corresponding SRAM bank executes the read command or the write command both targeting the corresponding SRAM bank. Then, after an access command is executed, the arbitration module will send another access command to the corresponding SRAM bank. When the arbitration module receives two access commands from the parsing module simultaneously, for example, receives a read command and a write command simultaneously, it can determine the execution order based on a predetermined arbitration strategy, such as selecting a specific command to be executed first. It can be seen that the embodiment of the present invention can solve the conflict problem of the read command and the write command accessing the same SRAM bank simultaneously based on the arbitration performed by the arbitration module. Under normal circumstances, in order to ensure logical consistency, the arbitration strategies adopted in each arbitration module are the same. However, the arbitration strategies adopted in each arbitration module can also be different. Preferably, the arbitration strategy includes: (1) Polling execution strategy; (2) Read command priority strategy; (3) Write command priority strategy; (4) Time-sharing strategy. In the polling execution strategy, the read command and the write command are polled for execution, that is, the read command and the write command are alternately executed. For example, when the read command and the write command are received simultaneously for the first time, the execution order is: first execute the write command, and then execute the read command; when the read command and the write command are received simultaneously for the second time, the execution order is: first execute the read command, and then execute the write command; when the read command and the write command are received simultaneously for the third time, the execution order is: first execute the write command, and then execute the read command; when the read command and the write command are received simultaneously for the fourth time, the execution order is: first execute the read command, and then execute the write command. Another example, when the arbitration module receives two access commands (including: read command and write command) from the parsing module at the same time, if the corresponding SRAM bank has executed a read command most recently (that is, the last time a read command was executed), then for the two access commands received this time, the execution order is: first execute the write command, and then execute the read command. If the corresponding SRAM bank has executed a write command most recently (that is, the last time a write command was executed), then for the two access commands received this time, the execution order is: first execute the read command, and then execute the write command. In the read command priority strategy, the read command is preferentially executed. In the write command priority strategy, the write command is preferentially executed. In the time-sharing strategy, the corresponding commands are processed based on time segments. For example: only read commands are processed in the starting time segment, and write commands are processed in the next time segment; or, only write commands are processed in the starting time segment, and read commands are processed in the next time segment, and so on. The above exemplary description shows typical examples of the arbitration strategy. Those of ordinary skill in the art can realize that such a description is only exemplary and is not used to limit the protection scope of the embodiments of the present invention. Example: Assume that there are a total of 4 data access requests received by the parsing module, namely data access request 1, data access request 2, data access request 3, and data access request 4. Data access request 1 includes: (1) write command 1 with SRAM bank 1 as the target SRAM bank; (2) read command 1 with SRAM bank 2 as the target SRAM bank. Data access request 2 includes: (1) read command 2 with SRAM bank 1 as the target SRAM bank. Data access request 3 includes: (1) write command 2 with SRAM bank 4 as the target SRAM bank; (2) read command 3 with SRAM bank 5 as the target SRAM bank. The data access request 4 includes: (1) a write command 3 for the SRAM bank 6 targeting the SRAM bank; (2) a read command 4 for the SRAM bank 7 targeting the SRAM bank. The parsing module sends the write command 1 and the read command 2 (both targeting the SRAM bank 1) to the arbitration module 1 corresponding to the SRAM bank 1; sends the read command 1 (targeting the SRAM bank 2) to the arbitration module 2 corresponding to the SRAM bank 2; sends the write command 2 (targeting the SRAM bank 4) to the arbitration module 4 corresponding to the SRAM bank 4; sends the read command 3 (targeting the SRAM bank 5) to the arbitration module 5 corresponding to the SRAM bank 5; sends the write command 3 (targeting the SRAM bank 6) to the arbitration module 6 corresponding to the SRAM bank 6; sends the read command 4 (targeting the SRAM bank 7) to the arbitration module 7 corresponding to the SRAM bank 7. The arbitration modules 2, 4, 5, 6, and 7 all determine that there are no write and read commands existing simultaneously in themselves (that is, they do not receive a write command and a read command simultaneously, but only receive one access command), so they can execute their respective write or read commands, thereby performing parallel access to the 5 corresponding SRAM banks in the SRAM array respectively. The arbitration module 1 determines that there are a write command and a read command existing simultaneously in itself (the write command 1 and the read command 2), and performs arbitration based on a pre-determined arbitration strategy (assumed to be a read command priority strategy). The arbitration result is: first execute the read command 2 to read data from the SRAM bank 1, and after the read command 2 is executed, then execute the write command 1 to write data to the SRAM bank 1. Therefore, the arbitration module 1 first sends the read command 2 to the SRAM bank 1 to read data from the SRAM bank 1, and then the arbitration module 1 sends the write command 1 to the SRAM bank 1 to write data to the SRAM bank 1. In one embodiment, the read command includes a first set of selection signals and a read control instruction. The first set of selection signals is used to select the corresponding SRAM bank during the read operation, and the read control instruction is used to read data in the corresponding SRAM bank. For example, the read control instruction may include: (1) an SRAM chip select enable signal in the SRAM bank, used to select the SRAM from the SRAM bank; (2) an SRAM read enable signal, used to enable the read operation of the SRAM; (3) a read address in the SRAM. In one embodiment, the write command includes a second set of select signals and a write control instruction. The second set of select signals is used to select the corresponding SRAM bank during a write operation, and the write control instruction is used to write data into the corresponding SRAM bank. For example, the write control instruction may include: (1) an SRAM chip select enable signal in the SRAM bank, which is used to select an SRAM from the SRAM bank; (2) an SRAM write enable signal, which is used to enable the write operation of the SRAM; (3) a write address in the SRAM. Based on the above specific command types, an input / output port structure of an arbitration module is further proposed in an embodiment of the present invention. FIG. 3 is an exemplary structural diagram of an input / output port of an arbitration module according to an embodiment of the present invention. As shown in FIG. 3, the input / output port of the arbitration module includes: a read command bank select signal input terminal, which is used to receive the first set of select signals; a read control instruction input terminal, which is used to receive a read control instruction; an arbitration policy input terminal, which is used to receive an arbitration policy selection signal; a write command bank select signal input terminal, which is used to receive the second set of select signals; a write control instruction input terminal, which is used to receive a write control instruction; a command output terminal, which is used to send a read control instruction or a write control instruction to the corresponding SRAM bank; a read status indication signal output terminal, which is used to output a read status indication signal to the corresponding SRAM bank; and a write status indication signal output terminal, which is used to output a write status indication signal to the corresponding SRAM bank. Among them: the read status indication signal is used to indicate whether the SRAM bank is in a readable state. For example, when the read status indication signal is at a high level, it means that the SRAM bank is in a readable state; the write status indication signal is used to indicate whether the SRAM bank is in a writable state. For example, when the write status indication signal is at a high level, it means that the SRAM bank is in a writable state. The data access device and the data access system of the above SRAM array can be applied to a system-on-chip. An embodiment of the present invention further proposes a system-on-chip, which includes the data access system as described above or the data access device of the SRAM array as described above. It should be noted that the embodiments of the present application can use a hardware description language to implement the business logic executed by the data access device as a specific hardware circuit. For example, the embodiments of the present application can use the code of the business logic described at the register transfer level (RTL) to implement the data access chip (i.e., the hardware circuit structure of the data access device) in a field-programmable gate array (FPGA). Another example is that the embodiments of the present application can implement the code of the business logic described by RTL as an application specific integrated circuit (ASIC) chip (i.e., the hardware circuit structure of the data access device). It can be seen that based on the business logic of the data access device described in the embodiments of FIGS. 2 and 3, those of ordinary skill in the art can undoubtedly implement the specific circuit structure of the data access device through a hardware description language. Therefore, the specific structure of the data access device in the embodiments of the present application can be implemented as an FPGA or an ASIC chip. Correspondingly, the arbitration module and the parsing module can be implemented as corresponding circuit structures in the FPGA or ASIC. FIG. 4 is an exemplary structural diagram of a data access method for an SRAM array according to an embodiment of the present invention. As shown in FIG. 4, the method includes: Step 401: Receive N data access requests. Step 402: Parse at least one access command from each data access request. Each access command is a read command or a write command and points to an SRAM bank. Step 403: Perform arbitration processing for the access commands pointing to each SRAM bank, including: when it is determined that the access command pointing to the corresponding SRAM bank is a single one, send the access command pointing to the corresponding SRAM bank to the corresponding SRAM bank for the corresponding SRAM bank to execute the access command; where M is a positive integer greater than or equal to 2, and N is a positive integer. In one embodiment, the data access method of the present application can be executed in an FPGA, an ASIC, or an electronic device. In one implementation, performing the arbitration processing includes: When it is determined that the access commands pointing to the corresponding SRAM bank are at least two access commands, determine the execution order of the at least two access commands based on a predetermined arbitration strategy; Send the at least two access commands to the corresponding SRAM bank in the execution order for the corresponding SRAM bank to execute the at least two access commands in sequence. FIG. 5 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. The electronic device includes: a processor 501 and a memory 502. The processor 501 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 501 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 501 may also include a main processor and an auxiliary processor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the auxiliary processor is a low-power processor for processing data in the standby state. In some embodiments, the processor 501 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 501 may further include an AI processor, and the AI processor is used to process computational operations related to machine learning. For example, the AI processor may be implemented as a neural network processor. The memory 502 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 502 may also include high-speed random access memory and non-volatile memory, such as one or more magnetic disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 502 is used to store at least one instruction, and the at least one instruction is used to be executed by the processor 501 to implement the data access method of the SRAM array provided in various embodiments of the present disclosure. The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. 401: Step 402: Step 403: Step 501: Processor 502: Memory [Figure 1] is a schematic diagram of accessing an SRAM array in the related art. [Figure 2] is an exemplary structural diagram of a data access device for an SRAM array according to an embodiment of the present invention. [Figure 3] is an exemplary structural diagram of an input / output port of an arbitration module according to an embodiment of the present invention. [Figure 4] is an exemplary structural diagram of a data access method for an SRAM array according to an embodiment of the present invention. [Figure 5] is an exemplary structural diagram of an electronic device according to an embodiment of the present invention.

Claims

1. A data access device for an SRAM array, the SRAM array comprising M SRAM groups, wherein, The device includes: M arbitration modules, each coupled to one of the M SRAM groups; and a parsing module, coupled to the M arbitration modules, configured to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group, and send the access command to the arbitration module coupled to the pointed SRAM group; wherein each arbitration module is configured to, when determining that the received access command pointing to the corresponding SRAM group is a single command, send the access command pointing to the corresponding SRAM group to the corresponding SRAM group for execution by the corresponding SRAM group; wherein M is a positive integer greater than or equal to 2, and N is a positive integer; wherein the parsing module is further configured to receive the N data access requests in parallel from a full-duplex data transport bus; wherein the full-duplex data transport bus includes at least one of the following: Advanced Scalable Interface Protocol (AAPI) - Simplified; AAPI - Full; AAPI - Data Flow.

2. The data access device as described in claim 1, wherein, Each arbitration module is further configured to, when it is determined that the received access command to the corresponding SRAM group consists of at least two commands, determine the execution order of the received at least two access commands based on a predetermined arbitration strategy, and send the at least two access commands to the corresponding SRAM group in sequence according to the execution order, so that the corresponding SRAM group executes the at least two access commands in sequence.

3. The data access device as described in claim 2, wherein, The arbitration strategy includes at least one of the following: polling execution strategy; read command priority strategy; write command priority strategy; time-sharing strategy.

4. The data access device as described in any one of claims 1 to 3, wherein, The read command includes a first set of selection signals and a read control instruction. The first set of selection signals is used to select a corresponding SRAM group in the read operation, and the read control instruction is used to read data from the corresponding SRAM group. The write command includes a second set of selection signals and a write control instruction. The second set of selection signals is used to select a corresponding SRAM group in the write operation, and the write control instruction is used to write data to the corresponding SRAM group. The arbitration module includes: a read command group selection signal input terminal for receiving a first group selection signal; a read control instruction input terminal for receiving a read control instruction; an arbitration strategy input terminal for receiving an arbitration strategy selection signal; a write command group selection signal input terminal for receiving a second group selection signal; a write control instruction input terminal for receiving a write control instruction; a command output terminal for sending a read control instruction or a write control instruction to the corresponding SRAM group; a read status indication signal output terminal for outputting a read status indication signal to the corresponding SRAM group; and a write status indication signal output terminal for outputting a write status indication signal to the corresponding SRAM group.

5. A data access system for an SRAM array, comprising: An SRAM array, wherein the SRAM array comprises M SRAM groups, and each SRAM group contains multiple SRAMs; M arbitration modules, each coupled to one of the M SRAM groups; a parsing module, coupled to the M arbitration modules, is used to receive N data access requests in parallel, parse at least one access command from each data access request, each access command being a read command or a write command, pointing to an SRAM group, and sending the access command to the arbitration module coupled to the pointed SRAM group; wherein, each arbitration module is used to send the access command pointing to the corresponding SRAM group to the corresponding SRAM group when it determines that the received access command pointing to the corresponding SRAM group is a single command, so that the corresponding SRAM group executes the access command; wherein M is a positive integer greater than or equal to 2, and N is a positive integer; wherein, the parsing module is also used to receive the N data access requests in parallel from a full-duplex data transport bus; wherein, the full-duplex data transport bus includes at least one of the following: Advanced Scalable Interface Protocol (AAPI) - Simplified Version; AAPI - Full Version; AAPI - Data Flow Version.

6. The data access system as described in claim 5, wherein, Each arbitration module is further configured to, when it is determined that the received access command to the corresponding SRAM group consists of at least two commands, determine the execution order of the received at least two access commands based on a predetermined arbitration strategy, and send the at least two access commands to the corresponding SRAM group in sequence according to the execution order, so that the corresponding SRAM group executes the at least two access commands in sequence.

7. A system-on-a-chip, wherein, Includes a data access device for an SRAM array as described in any one of claims 1 to 4, or a data access system for an SRAM array as described in claim 5 or 6.

8. A data access method for an SRAM array, wherein the SRAM array comprises M SRAM groups, wherein, The method includes: receiving N data access requests in parallel from a full-duplex data transport bus; wherein the full-duplex data transport bus includes at least one of the following: Advanced Scalable Interface Protocol (AAPI) Simplified Version; AAPI Full Version; AAPI Dataflow Version; parsing at least one access command from each data access request, each access command being a read command or a write command and pointing to an SRAM group; and performing arbitration processing for each access command pointing to an SRAM group, including: when it is determined that the access command pointing to the corresponding SRAM group is a single command, sending the access command pointing to the corresponding SRAM group to the corresponding SRAM group for execution by the corresponding SRAM group; wherein M is a positive integer greater than or equal to 2, and N is a positive integer.

9. The data access method as described in request item 8, wherein, The arbitration process further includes: when it is determined that there are at least two access commands pointing to the corresponding SRAM group, determining the execution order of the at least two access commands based on a predetermined arbitration strategy; and sending the at least two access commands to the corresponding SRAM group in the order of execution so that the corresponding SRAM group can execute the at least two access commands in sequence.

10. An electronic device, wherein, include: Memory; A processor; wherein the memory stores an application program executable by the processor, which causes the processor to perform a data access method for the SRAM array as described in claim 8 or 9.

11. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer-readable instructions that, when executed by a processor, cause the processor to perform a data access method for an SRAM array as described in claim 8 or 9.

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