Packet sending system

Abstract

A packet transmission system includes multiple transmission queues, each used to temporarily store a string of data; a media access controller for processing received data to be transmitted into packets for transmission through the physical layer. Transmission logic circuitry, electrically connected to both the transmission queues and the media access controller, records the characteristics of each transmission queue and is configured to perform the following method: data is retrieved from a first transmission queue as data to be transmitted and sent to the media access controller. When a second characteristic flag of a transmittable second transmission queue indicates "fast" and a first characteristic flag of the first transmission queue indicates "preemptible," a packet switching procedure is selectively executed.

Description

[Technical Field]

[0001] This invention relates to a packet delivery system, and more particularly to a packet delivery system applied to the IEEE 802.3br standard. [Previous Technology]

[0002] Signal transmission channels are limited and fixed, while the number of signal packets to be transmitted varies over time. This can sometimes lead to the signal transmission channel being clogged with packets waiting to be transmitted, causing delays. To address this issue, the Institute of Electrical and Electronics Engineers (IEEE) proposed the 802.3br standard, which classifies packets into express packets and preemptible packets. The architecture of the media access layer was also modified to separate express and preemptible packets. This standard classifies delay-sensitive packets, packets that affect system performance, or packets that affect user experience as express packets, allowing them to interrupt the transmission of other preemptible packets and prioritize the signal transmission channel, thereby improving system performance and / or user experience.

[0003] However, in the current architecture, parallel fast MAC and preemptible MAC are usually designed in the media access control (MAC) layer, and the front-end packet queues are directly electrically connected to the fast MAC or preemptible MAC in hardware. This not only wastes hardware resources, but also makes it impossible for the hardware to freely change the characteristics of each packet queue, thus limiting its scalability. [Summary of the Invention]

[0004] The present invention provides a packet transmission system that adjusts the process of preempting packets and / or fast packets in the system's transmission queue configuration, thereby reducing the impact of the number of sender memory / transmission queues on the user experience.

[0005] A packet transmission system according to an embodiment of the present invention includes: a transmission queue having a plurality of transmission queues, each transmission queue being used to temporarily store a string of data; a media access controller being used to process the received data to be transmitted into packets for transmission through a physical layer; and a transmission logic circuit electrically connected to the transmission queue and the media access controller, the transmission logic circuit being used to record the characteristics of each transmission queue, and the transmission logic circuit being configured to perform the following method:

[0006] Data is retrieved from the first transmission queue among the aforementioned plurality of transmission queues as data to be transmitted and transmitted to the media access controller; and in response to the state of the second transmission queue among the aforementioned plurality of transmission queues being transmittable and the second characteristic flag of the second transmission queue indicating fast, and the first characteristic flag of the first transmission queue indicating preemptible, a packet switching procedure is selectively executed, the packet switching procedure including:

[0007] A transmission switching instruction is given to the media access controller; data retrieval from the first transmission queue is stopped; and data retrieval from the second transmission queue is started and sent to the media access controller as data to be transmitted.

[0008] According to another embodiment of the packet transmission system of the present invention, the media access controller includes: a first register, a second register, and a controller electrically connected to the transmission logic circuit, the first register, the second register, and the physical layer, respectively. The controller obtains data to be transmitted from the transmission logic circuit and transmits it to the physical layer, and calculates the cyclic redundancy check (CRC) code corresponding to the data to be transmitted and updates it to the first register. When a switching instruction is received, the controller writes the CRC code in the first register to the second register, performs bitwise inversion on the CRC code, and then transmits it to the physical layer.

[0009] According to another embodiment of the packet transmission system of the present invention, each transmission column of the transmission column has a data end flag (EOF) for the data temporarily stored therein, and the transmission column determines the remaining data length of each transmission column based on the position of the data end flag in each transmission column.

[0010] According to another embodiment of the present invention, in a packet transmission system, when the state of the second transmission queue is transmittable and the second characteristic flag of the second transmission queue indicates fast, and the first characteristic flag of the first transmission queue indicates preemptible, the transmission logic circuit reads the remaining data length of the first transmission queue from the transmission queuer to selectively execute the packet switching procedure.

[0011] According to another embodiment of the packet transmission system of the present invention, when the remaining data length is not greater than a preset value, the transmission logic circuit selects to retrieve data from the first transmission queue and completes the transmission, and then continues to retrieve data from the second transmission queue.

[0012] According to another embodiment of the packet transmission system of the present invention, when the transmission logic circuit completes the acquisition of data from the second transmission queue, the transmission logic circuit further determines whether there is a transmission queue with the characteristic of being fast in the transmission queue, so as to decide whether to continue transmitting the data of the first transmission queue.

[0013] According to another embodiment of the packet transmission system of the present invention, when the state of each transmission queue that is indicated as fast by the corresponding characteristic flag in the transmission queue is not transmittable, the transmission logic circuit transmits the data continuation flag to the media access controller, and continues to retrieve data from the first transmission queue as data to be transmitted to the media access controller.

[0014] According to another embodiment of the packet transmission system of the present invention, when the second transmission queue completes transmission, the transmission logic circuit continues to transmit the data of the transmission queue in the transmission queue according to the fast transmission order and the preemptible transmission order.

[0015] According to the present invention, by using an additional register and a set transmission logic circuit in the media access controller, a packet transmission system can be realized with only one MAC channel.

[0016] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

Implementation Method

[0018] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0019] Please refer to Figure 1, which is an architecture diagram of a packet transmission system according to an embodiment of the present invention. The packet transmission system 100 in this embodiment includes at least a transmission queue 110, a transmission logic circuit 120, and a media access control (MAC) 130. The transmission queue 110 is electrically connected to the transmission logic circuit 120, and the transmission logic circuit 120 is electrically connected to the media access control 130.

[0020] The transmission queue 110 has multiple transmission queues Q0 to Q3. Transmission queues Q0 and Q1 are used, for example, to store preemptible packet data. Each transmission queue has a queue length K, for example, 16384 bytes. Transmission queues Q0 to Q3 are all first-in first-out (FIFO) architectures. In one embodiment, each piece of data temporarily stored in transmission queues Q0 to Q3 has an end-of-file (EOF) flag.

[0021] Transmission logic circuit 120 is electrically connected to transmission queue 110. Transmission logic circuit 120 records the characteristics of each transmission queue Q0 to Q3. In the following example, transmission queues Q0 and Q1 are preemptible, while transmission queues Q2 and Q3 are express. However, in the 802.13 standard, whenever data collection in a transmission queue with express characteristics is completed (the end-of-data flag EOF is detected), the preemptible packet being transmitted is temporarily interrupted and the transmission is switched to data in the transmission queue with express characteristics.

[0022] Specifically, please refer to Figure 2, which is a flowchart of the preemption judgment process of the transmission logic circuit according to an embodiment of the present invention. The transmission logic circuit 120 is configured to perform the following steps: as shown in step S210, data is retrieved from the first transmission queue Q0 to Q3 as data to be transmitted to the media access controller 130, and a first characteristic flag regarding the first transmission queue is transmitted to the media access controller 130. The first transmission queue can be transmission queue Q0 or Q1 (preemptible packet) or transmission queue Q2 or Q3 (fast packet).

[0023] As shown in step S220, monitor whether any transmission queue other than the current first transmission queue has the data end flag EOF. If no other transmission queue with the data end flag EOF is detected, return to step S210. Otherwise, proceed to step S230 to determine the characteristics of the second transmission queue that has newly obtained the data end flag EOF and the characteristics of the current first transmission queue. There will be four judgment results, described in the following table: Table 1 First teleportation queue Second teleportation queue Procedure to be executed Quick Quick Quick sort (step S240) Quick Can be preempted Preemptive sorting (step S260) Can be preempted Can be preempted Preemptive sorting Can be preempted Quick Preemption (Step S240 - Packet Switching)

[0024] Quick sorting means that the transmission order of the transmission queue with the EOF flag at the end of the newly acquired data is appended to the existing quick transmission order. In other words, if the first transmission queue is transmission queue Q2 and the second transmission queue is transmission queue Q3, then the data in transmission queue Q3 will be transmitted first after the data in transmission queue Q2 has been transmitted.

[0025] Preemptible sorting sorts the transmission orders of all preemptible transmission queues into a single preemptible transmission order. However, data transmission in the preemptible transmission queues only begins when all fast transmission queues have completed their transmissions (all fast transmission queues do not have the data end flag EOF). In other words, when the first transmission queue (e.g., transmission queue Q2) is halfway through its transmission, and the second transmission queue (e.g., transmission queue Q0) acquires the data end flag EOF, preemptible sorting determines whether there is another preemptible transmission queue (i.e., transmission queue Q1) that already has the data end flag EOF, thus determining the position of the second transmission queue in the preemptible transmission order.

[0026] In summary, in response to the second transmission queue being transmittable (with the data end flag EOF) and the second characteristic flag of the second transmission queue indicating fast, if the first characteristic flag of the first transmission queue is preemptible at this time, the transmission logic circuit 120 will selectively execute step S250: packet switching procedure. The packet switching procedure includes: step S253, sending a switching instruction to the media access controller 130. Step S255, stopping data retrieval from the first transmission queue. Step S257, starting data retrieval from the second transmission queue as data to be transmitted and sending it to the media access controller 130. Step S259, inserting the interrupted first transmission queue (e.g., transmission queue Q0) into the first position in the preemptible transmission sequence, in other words, giving it the first priority to be transmitted among all preemptible transmission queues.

[0027] In one embodiment, the transmission logic circuit 120 may perform an exception handling in step S250, as shown in step S251 (optionally), by determining whether the remaining data length in the first transmission queue is greater than a threshold. The remaining data length can be calculated based on the position of the end flag in the first transmission queue, which will not be elaborated here. The aforementioned threshold may be, for example, 60 bytes, 124 bytes, 188 bytes, or even 252 bytes. If the remaining data length is greater than this threshold, the transmission logic circuit 120 executes step S253; otherwise, the transmission logic circuit 120 executes step S252 to complete the transmission of the remaining data in the first transmission queue.

[0028] Next, please refer to Figure 3, which is a flowchart of the transmission logic circuit performing a sequential transmission judgment according to an embodiment of the present invention. When a transmission queue has been completed, that is, when even the data end flag EOF has been retrieved by the transmission logic circuit 120, the transmission logic circuit 120 executes step S310 to determine whether there is a transmission queue with data to be transmitted that is fast. If so, then as in step S320, the corresponding transmission queue is started to be transmitted according to the fast transmission order. If not, then as in step S330, the corresponding transmission queue is started to be transmitted according to the preemptible transmission order.

[0029] The media access controller 130 is used to process the received data to be transmitted into packets for transmission through the physical layer. Specifically, the media access controller 130 has a controller 131 front end electrically connected to the transmission logic circuit 120, and the controller 131 also has an electrical physical layer PHY, a first register 135 and a second register 137.

[0030] The general task of controller 131 is to sequentially receive the data to be transmitted from transmission logic circuit 120, and calculate the cyclic redundancy check (CRC) code based on the current CRC code and the received data to be transmitted. The calculated CRC code is continuously updated to the first register 135, and the portion of the data to be transmitted after the CRC code has been calculated is transmitted to the physical layer PHY for transmission to the other end of the network. Furthermore, when transmission logic circuit 120 sends the End of Data Flag (EOF), the last calculated CRC code is also transmitted to the physical layer PHY.

[0031] In addition, the controller 131 also has an additional first receiver (PIN_SW) to receive a switching signal SW from the transmission logic circuit 120. In one embodiment, if the logic value of the switching signal SW jumps from a low level (FALSE) to a high level (TRUE), it indicates that a switching instruction has been received. At this time, it indicates that the aforementioned step S240 is being executed, and the first characteristic flag must be preemptible. In response to this switching instruction, the controller 131 records the cyclic redundancy check code currently stored in the first register 135 to the second register 137, and transmits the cyclic redundancy check code bits bitwise inverted to the physical layer PHY.

[0032] To better understand this part of the operation, please refer to Figure 4, which is a signal timing diagram according to an embodiment of the present invention. From time point T1 to time point T2, the controller 131 receives the Start of Data Flag (SOF) from the transmission logic circuit 120. Then, from time point T2 to time point T3, the controller 131 receives the data to be transmitted, DATA_IN_1, from the transmission logic circuit 120, and outputs it as packet data, DATA_OUT_1, to the physical layer PHY from time point T2' to time point T3' as described above, and continuously updates the Cyclic Redundancy Check (CRC) code in the first register 135. At time point T3, the controller 131 receives the switching signal SW from the transmission logic circuit 120, and the logic value jumps from a low level to a high level (and then drops back to a low level), indicating that a switching is required. At this time, controller 131 writes the Cyclic Redundancy Check (CRC) code in the first register 135 into the second register 137, and then inverts the bits of this CRC code before appending it to the packet data DATA_OUT_1 as the preemptive CRC code mCRC, which is output to the physical layer PHY between time point T3' and time point T4. Then, starting from time point T5, controller 131 will receive the Start of Data Flag (SOF) of the fast packet from the transmission logic circuit 120.

[0033] In one embodiment, after the fast packet is received at time T6 (the data end flag EOF is received), and the controller 131 sends the cyclic redundancy check (CRC) code of this fast packet at time T6', from time T7 to time T8, the controller 131 receives not another data start flag SOF from the transmission logic circuit 120, but the data continuation flag COF of the previously preempted packet. Therefore, the controller 131 writes the CRC code temporarily stored in the second register 137 back to the first register 135, and continues to receive subsequent data and continuously calculate the CRC code starting from time T8. Then, at time T9, the data end flag EOF is received, and at time T9', the CRC code of this preemptible packet is sent out.

[0034] In summary, by not pre-setting the number of transmission strings stored in each transmission queue, this invention can support the coexistence of one fast packet and three preemptible packets, two fast packets and two preemptible packets, and three fast packets and one preemptible packet when four transmission queues exist. Furthermore, those skilled in the art will understand after reading this invention that when eight transmission queues exist, the number of fast packets and preemptible packets and the transmission queues they occupy can be arbitrarily allocated. Moreover, as long as the queue capacity is large enough, the supported packet characteristic combinations can be increased without being limited by hardware definitions, providing greater resource configuration flexibility.

[0035] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0017] Figure 1 is a schematic diagram of a packet transmission system according to an embodiment of the present invention. Figure 2 is a flowchart of the preemption judgment process of the transmission logic circuit according to an embodiment of the present invention. Figure 3 is a flowchart of the continuation transmission judgment process of the transmission logic circuit according to an embodiment of the present invention. Figure 4 is a signal timing diagram according to an embodiment of the present invention.

Claims

1. A packet transmission system, comprising: A transmission queue has multiple transmission queues, each of which is used to temporarily store a string of data; A media access controller is configured to process received data to be transmitted into a packet for transmission through a physical layer; and a transmission logic circuit electrically connected to the transmission queue and the media access controller, the transmission logic circuit being configured to record the characteristics of each transmission queue, the transmission logic circuit being configured to perform the following methods: extracting data from a first transmission queue as data to be transmitted to the media access controller, and transmitting a first characteristic flag of the first transmission queue to the media access controller; and in response to a second transmission queue being in a transmittable state and a second characteristic flag of the second transmission queue indicating fast, and the first characteristic flag of the first transmission queue indicating preemptible, selectively executing a packet switching procedure, the packet switching procedure including: transmitting a switching instruction to the media access controller; stopping data extraction from the first transmission queue; and starting data extraction from the second transmission queue as data to be transmitted to the media access controller; Each of the transmission queues in the transmission queue has a data end flag (EOF) temporarily stored in the data string, and the transmission queue determines the remaining data length of each transmission queue based on the position of the data end flag in each transmission queue; when the state of the second transmission queue is transmittable and the second characteristic flag of the second transmission queue indicates fast, and the first characteristic flag of the first transmission queue indicates preemptible, the transmission logic circuit reads the remaining data length of the first transmission queue from the transmission queue to selectively execute the packet switching procedure.

2. The packet transmission system of claim 1, wherein the media access controller includes: First temporary register; A second temporary register; The system includes a controller electrically connected to the transmission logic circuit, the first register, the second register, and the physical layer. The controller retrieves the data to be transmitted from the transmission logic circuit and transmits it to the physical layer. It also calculates the cyclic redundancy check (CRC) code corresponding to the data to be transmitted and updates it to the first register. When the system receives the switching instruction, the controller writes the CRC code from the first register into the second register and performs bitwise inversion on the CRC code before transmitting it to the physical layer.

3. In the packet transmission system of request item 1, when the remaining data length is not greater than a preset value, the transmission logic circuit selects to retrieve data from the first transmission queue to complete the transmission, and then continues to retrieve data from the second transmission queue.

4. In the packet transmission system of request item 1 or 2, when the transmission logic circuit completes the acquisition of data from the second transmission queue, the transmission logic circuit further determines whether there is a transmission queue with fast characteristics in the transmission queue, so as to decide whether to continue transmitting the data of the first transmission queue.

5. The packet transmission system of claim 4, wherein when the state of each transmission queue, which is indicated by the corresponding characteristic flag in the transmission queue as fast, is not transmittable, the transmission logic circuit transmits a data continuation flag to the media access controller and continues to retrieve data from the first transmission queue as data to be transmitted to the media access controller.

6. The packet transmission system of claim 4, wherein when the second transmission queue completes transmission, the transmission logic circuit continues to transmit data of at least one transmission queue in the transmission queue according to a fast transmission sequence and a preemptible transmission sequence.

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