Method of forming semiconductor structure

Abstract

The method includes forming a shallow trench isolation region near a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. The method further includes forming a hard mask on the shallow trench isolation region; forming a dummy gate stack on the protruding fin; removing a sacrificial layer in the protruding fin to retain space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interposer in the space; removing the dummy gate stack; removing the disposable interposer with an etch chemical, wherein the hard mask is exposed to the etch chemical when the disposable interposer is removed; and forming a gate stack, wherein a portion of the gate stack fills the space.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to a method for forming a semiconductor structure, and more particularly to a semiconductor structure employing a one-time oxide interposer. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form electronic components and electronic units on the semiconductor substrate.

[0003] The semiconductor industry continues to shrink minimum structural dimensions to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to incorporate more components into a given area. However, as the minimum structural dimensions shrink, additional problems need to be addressed. [Summary of the Invention]

[0004] In some embodiments of the present invention, a method for forming a semiconductor structure includes: forming a shallow trench isolation region near a protruding fin; forming a hard mask on the shallow trench isolation region; forming a dummy gate stack on the protruding fin; removing a sacrificial layer in the protruding fin to retain space between a first semiconductor nanostructure and a second semiconductor nanostructure, wherein the first semiconductor nanostructure and the second semiconductor nanostructure are contained in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; removing the disposable interposer using an etch chemical, wherein the hard mask is exposed to the etch chemical when the disposable interposer is removed; and forming a gate stack, wherein a portion of the gate stack fills the space.

[0005] In some embodiments of the present invention, the method of forming a semiconductor structure includes forming a shallow trench isolation region in a semiconductor substrate, wherein a portion of the semiconductor substrate near the shallow trench isolation region forms a semiconductor protrusion; forming a first semiconductor nanostructure, wherein the first semiconductor nanostructure is separate from and overlaps with the semiconductor protrusion; forming a hard mask on the shallow trench isolation region; and forming a gate stack, the gate stack including a first portion and a second portion, wherein the first portion of the gate stack is located between the first semiconductor nanostructure and the semiconductor protrusion, and the hard mask is located between the shallow trench isolation region and the second portion of the gate stack.

[0006] In some embodiments of the present invention, the method of forming a semiconductor structure includes forming a shallow trench isolation region in a semiconductor substrate, wherein a portion of the semiconductor substrate located near and in contact with the shallow trench isolation region serves as a semiconductor strip; forming a dielectric pad on the shallow trench isolation region to contact the shallow trench isolation region; forming a dielectric hard mask on the dielectric pad, wherein the sidewall portion of the dielectric pad includes sidewalls on both sides to contact the dielectric hard mask and the semiconductor strip; and forming a gate stack on the dielectric hard mask to contact the dielectric hard mask.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or that the two are separated by other additional components rather than in direct contact. Furthermore, various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Furthermore, spatial relative terms such as "below," "below," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another element in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0011] A fully wound gate transistor and a method thereof are provided. In some embodiments of the present invention, the method for forming the fully wound gate transistor employs a disposable oxide interposing (DOI) process, which includes forming a sacrificial layer containing oxide. Because the sacrificial layer has insufficient etch selectivity relative to the shallow trench isolation region, unwanted depressions may occur in the shallow trench isolation region, resulting in an unwanted increase in effective capacitance between conductive structures and an unwanted increase in edge capacitance. Therefore, a protective layer (which can also be considered a hard mask) is formed on the shallow trench isolation region to prevent depressions in the shallow trench isolation region when the sacrificial layer is removed.

[0012] The embodiments described herein provide examples of implementing or employing the subject matter of the embodiments of the present invention, and those skilled in the art will readily understand feasible adjustments and maintain within the scope of different embodiments. In various drawings and illustrative embodiments, similar reference numerals may be used to designate similar elements. While embodiments of some methods are described with steps performed in a particular order, embodiments of other methods may have these steps performed in any logical order.

[0013] Figures 1 to 18A and 18B are diagrams of intermediate stages in forming a fully wound gate transistor in some embodiments of the present invention. The corresponding process is also schematically reflected in the process flow 200 shown in Figure 19.

[0014] FIG1 is a perspective view of wafer 10. Wafer 10 includes a multilayer structure containing multiple layers stacked 22 on substrate 20. In some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or the like, or other substrates and / or structures such as semiconductor-on-insulator, strained semiconductor-on-insulator, silicon-germanium-on-insulator, or the like. Substrate 20 may be doped with p-type semiconductor, but in other embodiments, substrate 20 may be doped with n-type semiconductor.

[0015] In some embodiments, materials are deposited in an alternating series of deposition processes to form a multilayer stack 22. Individual processes are processes 202 in the process flow 200 shown in FIG19. In some embodiments, the multilayer stack includes a first layer 22A and a second layer 22B. The first layer 22A is composed of a first semiconductor material, and the second layer 22B is composed of a second semiconductor material, and the second semiconductor material is different from the first semiconductor material.

[0016] In some embodiments, the composition of the first semiconductor material of the first layer 22A may be or include silicon germanium, silicon, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or the like. In some embodiments, the first layer 22A (such as silicon germanium) is deposited by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy, molecular beam epitaxy, chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, ultra-high vacuum chemical vapor deposition, distal plasma chemical vapor deposition, distal plasma chemical vapor deposition, or similar processes. In some embodiments, the first thickness of the first layer 22A is between about 30 Å and about 300 Å. However, any suitable thickness may be used, which is still within the scope of the embodiments of the present invention.

[0017] Once the first layer 22A is deposited on the substrate 20, the second layer 22B can be deposited on the first layer 22A. In some embodiments, the composition of the second semiconductor material of the second layer 22B may be silicon, silicon germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like, and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, in some embodiments, the first layer 22A is silicon germanium, while the composition of the second layer 22B may be silicon, and vice versa. It should be understood that the first layer 22A and the second layer 22B may use any suitable combination of materials.

[0018] In some embodiments, the deposition technique used to epitaxially grow the second layer 22B on the first layer 22A may be similar to the deposition technique used to form the first layer 22A. In some embodiments, the thickness of the second layer 22B is similar to the thickness of the first layer 22A. The thickness of the second layer 22B may also be different from the thickness of the first layer 22A. In some embodiments, the thickness of the first layer 22A is between about 4 nm and 7 nm, while the thickness of the second layer 22B is between about 8 nm and 12 nm.

[0019] Once the second layer 22B is formed on the first layer 22A, the deposition process can be repeated to form the remaining layers in the multilayer stack 22 until the top layer required to form the multilayer stack 22 is formed. In some embodiments, the thicknesses of the first layers 22A may be the same or similar to each other, and the thicknesses of the second layers 22B may be the same or similar to each other. The thickness of the first layer 22A may be the same as or different from the thickness of the second layer 22B. In some embodiments, the first layer 22A is removed in a subsequent process, so the first layer 22A can be considered a sacrificial layer. In other embodiments, the second layer 22B is a sacrificial layer and will be removed in a subsequent process.

[0020] In some embodiments, pad oxide layers and hard masks (not shown) may be formed on the multilayer stack 22. These layers are patterned for subsequent patterning processes of the multilayer stack 22.

[0021] As shown in FIG2, a portion of the multilayer stack 22 and the underlying substrate 20 is patterned using an etching process to form a trench 23. The individual process is process 204 in process flow 200 shown in FIG19. The trench 23 extends into the substrate 20. The retained portion of the multilayer stack can be considered as the multilayer stack 22'. Some portions of the substrate 20 remain beneath the multilayer stack 22' and can be considered as semiconductor strips 20'. The multilayer stack 22' includes semiconductor layers such as a sacrificial layer (first layer 22A) and a nanostructure (second layer 22B). The portion of the multilayer stack 22' and the underlying semiconductor strip 20' can be considered together as semiconductor strip 24.

[0022] In the above embodiments, the patterning method for the fully wound gate transistor structure can be any suitable method. For example, one or more photolithography processes can be used to pattern the structure, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the sacrificial layer. The sacrificial layer is then removed, and the thickness of the remaining spacers can be used to pattern the fully wound gate structure.

[0023] As shown in FIG3A, an isolation region, such as a shallow trench isolation region 26, is formed. A specific process is process 206 of process flow 200 shown in FIG19. The shallow trench isolation region 26 may include a dielectric pad (see FIG3B), which may be a thermal oxide formed on the surface layer of the thermally oxidized substrate 20. The dielectric pad may also be a deposited silicon oxide layer, formed by atomic layer deposition, high-density plasma chemical vapor deposition, chemical vapor deposition, or similar processes. The shallow trench isolation region 26 may also include a dielectric material on the dielectric pad, wherein the dielectric material is formed by flowable chemical vapor deposition, spin coating, high-density plasma chemical vapor deposition, or similar methods. A planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, may then be performed to make the upper surface of the dielectric material flush, and the remaining portion of the dielectric material constitutes the shallow trench isolation region 26.

[0024] Next, the shallow trench isolation region 26 is recessed, so that the top of the semiconductor strip 24 protrudes above the upper surface 26T of the retained portion of the shallow trench isolation region 26, to form a protruding fin 28. The protruding fin 28 includes the top of the multilayer stack 22' and the semiconductor strip 20'. The process for recessing the shallow trench isolation region 26 can be a dry etching process, such as using nitrogen trifluoride and ammonia as etching gases. Plasma can be generated during the etching process. The process may also include argon. In some other embodiments of the invention, the shallow trench isolation region 26 can be recessed by a wet etching process. For example, the etching chemical may include hydrofluoric acid.

[0025] Figure 3B corresponds to section A1-A1 in Figure 3A. As shown in Figure 3B, the shallow trench isolation region 26 may include a dielectric pad 26A and a dielectric region 26B located on the dielectric pad 26A. The dielectric pad 26A and the dielectric region 26B may be composed of different dielectric materials or the same dielectric material. For example, the dielectric pad 26A may be composed of silicon nitride or silicon oxide, while the dielectric region 26B may be composed of silicon oxide or silicon nitride. The dielectric pad 26A and the dielectric region 26B may also be composed of the same dielectric material, such as silicon oxide, but with different characteristics. For example, the dielectric region 26B may have a lower density and a higher etching rate compared to the dielectric pad 26A. In other embodiments, all shallow trench isolation regions 26 are composed of a homogeneous material such as silicon oxide. In subsequent diagrams, dielectric pad 26A and dielectric region 26B are not shown separately.

[0026] In some embodiments, the space S1 between adjacent protruding fins 28 is between about 20 nm and about 200 nm. The height H1 of the protruding fins 28 may be between about 50 nm and about 70 nm.

[0027] As shown in FIG. 4, a dielectric layer 120 is formed. Individual processes include process 208 of process flow 200 as shown in FIG. 19. In some embodiments, the dielectric layer 120 comprises silicon oxide. The formation method may include a deposition process, which may be a compliant deposition process such as atomic layer deposition, chemical vapor deposition, or a similar process. The thickness T3 of the dielectric layer 120 must not be too small, otherwise the protruding fins 28 cannot be effectively protected in subsequent etching processes. The thickness T3 of the dielectric layer 120 must not be too large, otherwise edge sagging may occur, as illustrated in conjunction with FIG. 16A. In some embodiments, the thickness T3 of the dielectric layer 120 may be between about 1 nm and about 8 nm, and may be between about 1 nm and about 4 nm.

[0028] As shown in FIG5, a hard mask layer 122 (which can also be considered as a protective layer) is deposited. A specific process is process 210 in process flow 200 shown in FIG19. In some embodiments, the hard mask layer 122 is a non-compliant layer having a sidewall portion with a thickness T4, a top portion with a thickness T5, and a bottom portion with a thickness T6. Thicknesses T5 and T6 are greater than thickness T4. For example, the ratios T5 / T4 and T6 / T4 can be between about 3 and about 20.

[0029] The hard mask layer 122 is composed of a dielectric material that differs from the dielectric material of the underlying shallow trench isolation region 26, and the dielectric material of the hard mask layer 122 has high etch selectivity. The material of the hard mask layer 122 also differs from the material of the subsequently formed one-time oxide interposer layer 29 (Figures 13A and 13B), and the material of the hard mask layer 122 has high etch selectivity. For example, the etch selectivity is higher than about 10 and can be between about 10 and 100.

[0030] In some embodiments, the hard masking layer may be composed of or include dielectric materials containing silicon and nitrogen and / or dielectric materials containing silicon and carbon, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, silicon carbide, silicon carbide, or the like. The hard masking layer 122 may also include dielectric materials with high dielectric constants such as alumina, hafnium oxide, hafnium silicon oxide, zirconium oxide, lanthanum oxide, yttrium oxide, the like, or combinations thereof. The hard masking layer 122 may also include inorganic or organic low dielectric constant materials such as fluorosilicates, porous carbon-doped oxides such as porous silicon carbide, degels, aerogels, amorphous fluorinated carbon, parylene, benzocyclobutene, polyimide, or the like.

[0031] In some embodiments, the method of forming the non-compliant hard mask layer 122 may include multiple cycles. Each cycle may include depositing a silicon layer, followed by converting the silicon layer into a silicon nitride layer using a nitriding process. The deposition process may also include atomic layer deposition, chemical vapor deposition, physical vapor deposition, distal plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, flowable chemical vapor deposition, high aspect ratio processes, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, organometallic chemical vapor deposition, similar processes, or combinations thereof. In some embodiments, the method of depositing the silicon layer employs plasma deposition with an applied bias voltage. In summary, the horizontal portion of the silicon layer at the top of the protruding fin 28 and the bottom of the space (such as between the protruding fin 28) has more suspension bonds due to plasma, while the vertical portion of the silicon layer on the sidewall of the protruding fin 28 has fewer suspension bonds.

[0032] In the nitriding process, the horizontal portion of the silicon layer has a higher conversion rate (converted into silicon nitride), while the sidewall portion of the silicon layer has a lower conversion rate because the horizontal portion has more dangling bonds. During the conversion process, the unconverted portion of the silicon layer on the sidewall can be extracted from individual process chambers. In summary, the final silicon nitride layer is non-compliant. Through multiple cycles, the thickness of the silicon nitride layer can be increased to the desired thickness in each cycle.

[0033] In other embodiments, the hard mask layer 122 is a compliant layer. In these embodiments, silicon nitride can be deposited via plasma deposition using an applied bias voltage (e.g., via atomic layer deposition, chemical vapor deposition, or similar methods). The top and bottom of the hard mask layer 122 may contain silicon nitride, which is harder and denser than the sidewall portions. This allows for a higher etching rate on the sidewall portions during the subsequent etching processes shown in Figures 7 and 8, enabling complete removal of the sidewall portions while retaining some portions of the bottom. In summary, the bottom may have an appropriate thickness to serve as a protective layer in the subsequent sheet formation process shown in Figure 16A.

[0034] As shown in FIG. 6, a sacrificial layer 124 is formed as an etch mask. A specific process is process 212 in process flow 200 as shown in FIG. 19. In some embodiments, the material comprising the sacrificial layer 124 may serve as a base antireflective coating and may include cross-linked photoresist, silicon carbide, or the like. The method of forming the sacrificial layer 124 may include a deposition (or delivery) process, followed by a planarization process, and then an etch-back process. This exposes the top of the hard mask layer 122.

[0035] As shown in FIG. 7, an etching process is performed to remove some of the top portion of the hard mask layer 122. An etching chemical may be selected to result in a low etching rate for the dielectric layer 120. Etching may be performed via a dry etching process, a wet etching process, or a similar process. In some embodiments, the etching gas may include fluorine-containing gases such as carbon tetrafluoride, nitrogen trifluoride, sulfur hexafluoride, fluoroform, chlorine trifluoride, the like, or combinations thereof. Other gases such as nitrogen, hydrogen, argon, nitric oxide, or the like may also be added. In other embodiments, a wet etching process may use phosphoric acid. After the etching process, the top portion of the hard mask layer 122 may be completely removed to expose the dielectric layer 120, or a thin top portion may be retained.

[0036] Next, the sacrificial layer 124 is removed, followed by an etching process to remove the top (if retained) and sidewall portions of the hard mask layer 122. Individual processes include process 214 in process flow 200 as shown in FIG19. The final structure is shown in FIG8. The retained portion of the hard mask layer 122 can also be considered as a hard mask. The etching process can be isotropic and can be a dry etching process or a wet etching process, which can use the aforementioned chemical agent used to remove the top of the hard mask layer 122. The dielectric layer 120 serves as an etching stop layer.

[0037] In some embodiments, the sidewall portions (vertical portions) of the hard mask layer 122 are thinner than the bottom portion. When etching the sacrificial layer 124, the etching process needs to be controlled to completely remove the top and sidewall portions of the hard mask layer 122, while retaining at least some portions of the bottom portion of the hard mask layer 122. In embodiments where the sidewall portions and the bottom portion have the same thickness but the density of the sidewall portions is less than the density of the bottom portion, the etching rate of the sidewall portions is greater than the etching rate of the bottom portion. When completely removing the sidewall portions, at least some portions of the bottom portion can be retained.

[0038] In some embodiments shown in FIG8, due to the etching process, the hard mask layer 122 may have an arcuate upper surface, and the middle portion of the arcuate upper surface between adjacent semiconductor strips 20' is lower than the portion near the semiconductor strip 20'. Although the upper surface of the hard mask layer 122 in the following figures is not arcuate, the upper surface of the hard mask layer 122 may also be arcuate, as shown in the final structures of FIG18A and 18B.

[0039] In some embodiments, the hard mask layer 122 retained when the etching process is stopped is neither too thick nor too thin. An excessively thin hard mask layer 122 may challenge process control; non-uniformity across the wafer may cause the hard mask layer 122 in some portions of the wafer to be completely etched or etched too thin to protect the underlying shallow trench isolation region during subsequent wafer formation processes. An excessively thick hard mask layer 122 may result in excessively high capacitance between the subsequently formed gate and the semiconductor strip 20' (which can also be considered a semiconductor protrusion) due to the high dielectric constant of the hard mask layer 122. In some embodiments, the thickness of the retained hard mask layer 122 is between about 0.5 nm and about 10 nm.

[0040] Next, the dielectric layer 120 is etched to expose the protruding fins 28. The final structure is shown in Figure 9. Some portions of the dielectric layer 120 on the sidewalls of the hard mask layer 122 and beneath the hard mask layer 122 may be retained as dielectric pads (or regarded as dielectric pads). In the specification, the hard mask layer 122 and individual dielectric pads such as the dielectric layer 120 may be regarded together as hard mask layer 122 / 120 or composite hard mask layer 122 / 120.

[0041] As shown in the perspective view of FIG10, the dummy gate stack 30 and the gate spacer 38 are formed on the upper surface and sidewalls of the protruding fin 28. The individual process is process 216 in process flow 200 shown in FIG19. The dummy gate stack 30 may include a dummy gate dielectric layer 32 and a dummy gate 34 located on the dummy gate dielectric layer 32. The dummy gate dielectric layer 32 may be formed by oxidizing the surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, the dummy gate 34 may be composed of polycrystalline silicon or amorphous silicon, and may also use other materials such as amorphous carbon.

[0042] The dummy gate stack 30 may also each include one or more hard masks 36 on the dummy gate 34. The hard masks 36 may be composed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxide, or multiple layers of the above. The dummy gate stack 30 may extend beyond one or more protruding fins 28 and the shallow trench isolation region 26 between the protruding fins 28. The length direction of the dummy gate stack 30 is perpendicular to the length direction of the protruding fins 28. The method of forming the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate layer on the dummy gate dielectric layer, depositing one or more hard masks, and then patterning the above-mentioned layers via a patterning process.

[0043] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. In some embodiments of the present invention, the gate spacer 38 is composed of a dielectric material such as silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbonitride, or the like, and the gate spacer 38 may be a single-layer structure or a multilayer structure containing multiple dielectric layers. The formation process of the gate spacer 38 may include depositing one or more dielectric layers, followed by an anisotropic etching process on the dielectric layers. The retained portion of the dielectric layer is the gate spacer 38.

[0044] Figure 11 shows the source / drain recess process. Individual process 218 is shown in process flow 200 as shown in Figure 19. Protruding fins 28 that are not directly located below the dummy gate stack 30 and the gate spacer 38 are etched using an isotropic etching process. This forms the source / drain recess 42, as shown in Figure 11. Figure 11 corresponds to the cross-section BB shown in Figure 10.

[0045] As shown in Figures 12A, 12B, 13A, and 13B, the sacrificial layer, such as the first layer 22A, is replaced with a one-time oxide interposer layer 29. Figures 12A and 12B correspond to cross sections A2-A2 and BB in Figure 10, respectively. The sacrificial layer, such as the first layer 22A, is removed first, and then openings 27 are formed between the nanostructures, such as the second layer 22B. Individual processes are shown in process flow 200 in Figure 19, specifically process 220.

[0046] As shown in Figures 13A and 13B, a disposable oxide interposer 29 is formed between nanostructures such as the second layer 22B. A specific process is process 222 in process flow 200 as shown in Figure 19. In some embodiments, the disposable oxide interposer 29 comprises an oxide such as silicon oxide, and is therefore considered as a disposable oxide interposer 29. In some other embodiments, other types of oxides may be used.

[0047] A method for forming a disposable oxide interposer 29 may include depositing a dielectric layer using a conformal deposition process, such that some portions of the dielectric layer fill the opening 27, while other portions of the dielectric layer remain outside the opening 27. A finishing process, such as an isotropic etching process, is then performed to etch and remove the portions of the dielectric layer outside the opening 27. The remaining portions of the dielectric layer thus form the disposable oxide interposer 29.

[0048] Next, the primary oxide interposer 29 is laterally recessed to form the inner spacer 44 (FIG. 13A). The primary oxide interposer 29 can be laterally recessed by a wet etching process or a dry etching process. The wet etching process can be an immersion process, a spray process, a spin coating process, or a similar method. This process does not etch nanostructures such as the second layer 22B.

[0049] Next, the inner spacer 44 is formed. Individual processes include process 224 in process flow 200 as shown in FIG19. In some embodiments, the method of forming the inner spacer 44 includes depositing a compliant dielectric layer extending into the lateral recess. An etching process (which can also be considered a spacer trimming process) is then performed to trim portions of the dielectric layer outside the lateral recess, leaving portions of the dielectric layer within the lateral recess. The retained portions of the dielectric layer can be considered as the inner spacer 44.

[0050] Figures 14A and 14B show cross-sections A1-A1 and BB from Figure 10, respectively. Selective epitaxy forms epitaxial source / drain regions 48 in source / drain recesses 42. Individual processes include process 226 in process flow 200 as shown in Figure 19. P-type or n-type impurities can be doped in situ during epitaxy, depending on whether the final transistor is a p-type or n-type transistor. For example, when the final transistor is a p-type transistor, silicon germanium boride, silicon boride, or similar materials can be grown. Conversely, when the final transistor is an n-type transistor, silicon phosphide, silicon carbide, or similar materials can be grown.

[0051] Figures 15A and 15B are cross-sectional views of the structure after the formation of the contact etch stop layer 50 and the interlayer dielectric layer 52. Figures 15A and 15B show sections A2-A2 and BB in Figure 10, respectively. The contact etch stop layer 50 may be composed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed by chemical vapor deposition, atomic layer deposition, or similar methods. The interlayer dielectric layer 52 includes a dielectric material, and may be formed by flowable chemical vapor deposition, spin coating, chemical vapor deposition, or any other suitable deposition method. The interlayer dielectric layer 52 may be composed of an oxygen-containing dielectric material, which may include silicon oxide, phosphosilicate, borosilicate, borophosphosilicate, undoped silicate, or the like.

[0052] The contact etching stop layer 50 and the interlayer dielectric layer 52 can be planarized by a planarization process such as chemical mechanical polishing or mechanical polishing. In some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate 34, as shown in Figures 15A and 15B. In some other embodiments, the planarization process may expose and stop at the hard mask 36. In some embodiments, the dummy gate 34 (or hard mask 36), gate spacer 38, and the upper surface of the interlayer dielectric layer 52 after the planarization process are flush (within process variations).

[0053] Next, the dummy gate 34 and the dummy gate dielectric layer 32 (and the hard mask 36, if the hard mask 36 was retained in the previous step) are removed by one or more etching processes to form a recess 58, as shown in Figures 16A and 16B. Individual processes are process 228 in process flow 200 as shown in Figure 19. In some embodiments, the dummy gate 34 and the dummy gate dielectric layer 32 are removed by an isotropic dry etching process. For example, the etching process uses a reactive gas that selectively etches the dummy gate 34 and the dummy gate dielectric layer 32 at a rate greater than the rate at which the interlayer dielectric layer 52 is etched. The recesses 58 each expose a portion of the multilayer stack 22' and / or are located on a portion of the multilayer stack 22', which includes other channel regions in the subsequently completed transistor.

[0054] Next, the primary oxide interposer 29 is removed to extend the recess 58 between the nanostructures such as the second layer 22B. Individual processes include process 230 in process flow 200 as shown in FIG19. An isotropic etching process, such as a wet etching process, can be performed to remove the primary oxide interposer 29, wherein the etchant used in the wet etching process is selective for the material of the primary oxide interposer 29. The nanostructures such as the second layer 22B remain relatively unetched relative to the primary oxide interposer 29 and the substrate 20. In some embodiments, the primary oxide interposer 29 comprises silicon oxide, and the primary oxide interposer 29 can be removed using a mixture of nitrogen trifluoride and ammonia, a mixture of hydrofluoric acid and ammonia, or hydrofluoric acid.

[0055] When etching the one-time oxide interposer 29, the shallow trench isolation region 26 can be protected from the effects of etching chemicals by the hard masking layer 122 due to high etching selectivity (e.g., the ratio of the etching rate of the one-time oxide interposer 29 to the etching rate of the hard masking layer 122). It should be understood that when removing the one-time oxide interposer 29, the remaining portion of the dielectric layer 120 may be recessed. For example, a portion of the dielectric layer 120 within the dashed circle 59 in FIG. 16A may be removed, and the upper surface of the sidewall portion of the dielectric layer 120 may be recessed below the upper surface of the hard masking layer 122. However, the selected thickness of the dielectric layer 120 is small, so the recess of the dielectric layer 120 can be controlled, and the bottom of the dielectric layer 120 can be maintained. The upper surface of the hard masking layer 122 can also be dished, i.e., the middle portion of the upper surface is lower than the individual side portions.

[0056] Examples of some dimensions will be illustrated with reference to Figure 16A. The height A of the nanostructure, such as the second layer 22B, can be between about 50 nm and about 70 nm. The height A measured from the upper surface of the nanostructure to the upper surface of the fin / protrusion, such as the semiconductor strip 20', can also be considered as the thickness. The height of the nanostructure, such as the second layer 22B, can be between about 6 nm and about 10 nm. The space between the nanostructures, such as the second layer 22B, can be between about 8 nm and about 10 nm. The width B of the nanostructure, such as the second layer 22B, can be between about 20 nm and about 30 nm, and the space S1 can be between about 20 nm and about 200 nm. The thickness C of the hard mask layer 122 can be between about 0.5 nm and about 20 nm, between about 0.5 nm and about 10 nm, or between about 10 nm and about 20 nm. The thickness D of the dielectric layer 120 may be between about 1 nm and about 8 nm, between about 1 nm and about 4 nm, or between about 4 nm and about 8 nm.

[0057] The distance E from the top of the semiconductor strip 20' to the bottom of the hard masking layer 122 can be between about 5 nm and about 20 nm. The distance F from the top of the semiconductor strip 20' to the top of the hard masking layer 122 (located at the edge of the hard masking layer 122) can be between about 2 nm and about 5 nm. The distance G from the top of the semiconductor strip 20' to the top of the hard masking layer 122 (located at the center of the hard masking layer 122) can be between about 2 nm and about 8 nm.

[0058] As shown in Figures 17A and 17B, gate dielectric layers 62 and gates 68 are formed, thus forming a displacement gate stack 70. Individual processes are described in process 232 of process flow 200 as shown in Figure 19. In some embodiments, each gate dielectric layer 62 includes an interface layer and a high-dielectric-constant dielectric layer on the interface layer. The interface layer may be composed of or include silicon oxide, which may be formed by compliant deposition processes such as atomic layer deposition or chemical vapor deposition, or by an oxidation process. In some embodiments, the interface layer may be formed on a nanostructure such as a second layer 22B and a semiconductor strip 20'. In some embodiments, the high-dielectric-constant dielectric layer includes one or more layers of high-dielectric-constant dielectric layers. For example, the high-dielectric-constant dielectric layer may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0059] A gate 68 may also be formed. When forming the gate 68, a conductive layer may first be formed on a high-dielectric-constant dielectric layer, and then filled into the remaining portion of the recess 58. The gate 68 may include metallic materials such as titanium nitride, tantalum nitride, titanium aluminum, titanium aluminum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, the gate 68 may include any number of layers, any number of work function layers, and may be a filling material. The gate dielectric layer 62 and the gate 68 may also fill the space between the underlying nanostructure such as the second layer 22B, and fill the space between the bottom nanostructure such as the second layer 22B and the underlying semiconductor strip 20'.

[0060] After filling the depression 58, a planarization process such as chemical mechanical polishing or mechanical polishing can be performed to remove excess portions of the gate dielectric layer 62 and gate 68 above the upper surface of the interlayer dielectric layer 52. The gate 68 and the gate dielectric layer 62 can be considered together as the replacement gate stack 70 of the final transistor.

[0061] In the process shown in Figures 18A and 18B, the replacement gate stack 70 is recessed, so that the recess is formed directly on the replacement gate stack 70 and between portions of the gate spacers 38 on both sides. A gate mask 74 containing one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into each recess. Then, excess portions of the dielectric material extending on the interlayer dielectric layer 52 are removed by a planarization process.

[0062] As shown in Figures 18A and 18B, an interlayer dielectric layer 76 is deposited on the interlayer dielectric layer 52 and the gate mask 74. An etch stop layer (not shown) may or may not be deposited before the formation of the interlayer dielectric layer 76. In some embodiments, the interlayer dielectric layer 76 is formed by flowable chemical vapor deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods. The interlayer dielectric layer 76 is composed of a dielectric material, which may be silicate, phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like.

[0063] Subsequently, the interlayer dielectric layer 76, interlayer dielectric layer 52, contact etch stop layer 50, and gate mask 74 are etched to form a recess (occupied by contact plugs 80A and 80B), which may expose the source / drain region 48 and / or the surface of the replacement gate stack 70. Although the contact plugs 80A and 80B shown in FIG18B are formed in the same cross section, the contact plugs 80A and 80B in different embodiments may be formed in different cross sections to reduce the risk of shorting to each other.

[0064] After the recess is formed, a silicate region 78 may be formed on the source / drain region 48. A contact plug 80B is then formed on the silicate region 78. A contact plug 80A (which can also be considered as a gate contact plug) may also be formed in the recess and on the gate 68 and in contact with the gate 68. The corresponding structure is also shown in Figure 18A. Thus, a transistor 82 is formed.

[0065] Embodiments of the present invention have several advantages. By forming a hard mask on top of the shallow trench isolation region, the hard mask can protect the shallow trench isolation region from denting when the disposable interposer is removed. The unwanted increase in parasitic capacitance between the gate and the semiconductor strip can therefore be reduced.

[0066] In some embodiments of the present invention, a method for forming a semiconductor structure includes: forming a shallow trench isolation region near a protruding fin; forming a hard mask on the shallow trench isolation region; forming a dummy gate stack on the protruding fin; removing a sacrificial layer in the protruding fin to retain space between a first semiconductor nanostructure and a second semiconductor nanostructure, wherein the first semiconductor nanostructure and the second semiconductor nanostructure are contained in the protruding fin; forming a disposable interposer in the space; removing the dummy gate stack; removing the disposable interposer using an etch chemical, wherein the hard mask is exposed to the etch chemical when the disposable interposer is removed; and forming a gate stack, wherein a portion of the gate stack fills the space.

[0067] In one embodiment, after removing the disposable intermediary layer, the bottom of the hard mask is retained.

[0068] In one embodiment, the deposited hard mask includes a top portion overlapping the protruding fin and having a first thickness; and a sidewall portion located on the sidewall of the protruding fin and having a second thickness, the second thickness being less than the first thickness. In one embodiment, the method further includes removing the top and sidewall portions of the hard mask and retaining the bottom portion of the hard mask before forming a dummy gate stack. In one embodiment, the step of forming the hard mask includes forming a silicon nitride layer. In one embodiment, the step of forming the silicon nitride layer includes multiple cycles, each cycle including depositing a silicon layer; and performing a nitriding process on the silicon layer.

[0069] In one embodiment, the step of depositing the silicon layer applies a bias voltage, and the bottom thickness of the hard mask is greater than the sidewall thickness of the hard mask. In one embodiment, the method further includes depositing a dielectric layer on the protruding fins before forming the hard mask.

[0070] In one embodiment, the dielectric layer and the shallow trench isolation region comprise the same dielectric material. In one embodiment, during etching of the one-time dielectric layer, the shallow trench isolation region is separated from the etch chemical by a bottom of a hard mask. In one embodiment, the gate stack contacts the bottom of the hard mask.

[0071] In some embodiments of the present invention, the method of forming a semiconductor structure includes forming a shallow trench isolation region in a semiconductor substrate, wherein a portion of the semiconductor substrate near the shallow trench isolation region forms a semiconductor protrusion; forming a first semiconductor nanostructure, wherein the first semiconductor nanostructure is separate from and overlaps with the semiconductor protrusion; forming a hard mask on the shallow trench isolation region; and forming a gate stack, the gate stack including a first portion and a second portion, wherein the first portion of the gate stack is located between the first semiconductor nanostructure and the semiconductor protrusion, and the hard mask is located between the shallow trench isolation region and the second portion of the gate stack.

[0072] In one embodiment, the hard mask and the shallow trench isolation region comprise different dielectric materials.

[0073] In one embodiment, the step of forming a hard mask includes a deposition process and an etching process following the deposition process.

[0074] In one embodiment, the method further includes forming a dielectric pad between the hard mask and the semiconductor protrusion, wherein the dielectric pad contacts the hard mask and the semiconductor protrusion.

[0075] In one embodiment, the method further includes forming a second semiconductor nanostructure to overlap with and separate from the first semiconductor nanostructure, wherein the gate stack further includes a third portion between the first nanostructure and the second nanostructure.

[0076] In one embodiment, the top of the hard mask is lower than the top of the semiconductor protrusion.

[0077] In some embodiments of the present invention, the method of forming a semiconductor structure includes forming a shallow trench isolation region in a semiconductor substrate, wherein a portion of the semiconductor substrate located near and in contact with the shallow trench isolation region is a semiconductor strip; forming a dielectric pad on the shallow trench isolation region to contact the shallow trench isolation region; forming a dielectric hard mask on the dielectric pad, wherein the sidewall portion of the dielectric pad includes sidewalls on both sides to contact the dielectric hard mask and the semiconductor strip; and forming a gate stack on the dielectric hard mask to contact the dielectric hard mask.

[0078] In one embodiment, the dielectric hard shield and the shallow trench isolation region are composed of different materials.

[0079] In one embodiment, when forming a gate stack, the dielectric hard shield includes an arcuate upper surface, and the middle portion of the arcuate upper surface is lower than the portions of the arcuate upper surface on both sides of the middle portion.

[0080] In one embodiment, the step of forming a dielectric hard mask includes a deposition process and an etching process following the deposition process.

[0081] In some embodiments of the present invention, the semiconductor structure includes a semiconductor strip; a first semiconductor nanostructure overlapping and separated from the semiconductor strip; a shallow trench isolation region contacting the edge of the semiconductor strip; a gate stack including a first portion located between the first semiconductor nanostructure and the semiconductor strip; and a hard mask located between the shallow trench isolation region and the gate stack. In one embodiment, the hard mask and the shallow trench isolation region comprise different dielectric materials.

[0082] In one embodiment, the hard mask comprises silicon nitride, and the shallow trench isolation region comprises silicon oxide. In one embodiment, the semiconductor structure further includes a dielectric pad located between the hard mask and the semiconductor strip, and contacting the hard mask and the semiconductor strip. In one embodiment, the semiconductor structure further includes a second semiconductor nanostructure that overlaps with and is separated from the first semiconductor nanostructure. The gate stack further includes a third portion located between the first semiconductor nanostructure and the second semiconductor nanostructure. In one embodiment, the top edge of the hard mask is lower than the top edge of the semiconductor strip.

[0083] In some embodiments of the present invention, the semiconductor structure includes a semiconductor substrate; a shallow trench isolation region located in the semiconductor substrate, wherein a portion of the semiconductor substrate is located near and in contact with the shallow trench isolation region to serve as a semiconductor strip; a dielectric pad located on and in contact with the shallow trench isolation region; a dielectric hard mask located on the dielectric pad, wherein a sidewall portion of the dielectric pad includes sidewalls on both sides to contact the dielectric hard mask and the semiconductor strip; and a gate stack located on and in contact with the dielectric hard mask.

[0084] In one embodiment, the dielectric hard mask and the shallow trench isolation region are made of different materials. In one embodiment, the dielectric hard mask includes an arcuate upper surface, wherein the middle portion of the arcuate upper surface is lower than the portions of the arcuate upper surface on both sides of the middle portion. In one embodiment, the semiconductor structure further includes a plurality of semiconductor nanostructures, wherein the upper semiconductor nanostructure overlaps with the lower semiconductor nanostructure, and the gate stack portion is located between adjacent semiconductor nanostructures.

[0085] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figures 1, 2, 3A, 3B, 4 to 11, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, and 18B are diagrams of intermediate stages in the formation of a transistor in some embodiments. Figure 19 is a process flow diagram for forming a transistor in some embodiments.

Claims

1. A method for forming a semiconductor structure, comprising: A shallow trench isolation region is formed near a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; a hard mask is formed on the shallow trench isolation region; a dummy gate is formed on the protruding fin; a sacrificial layer in the protruding fin is removed to retain a space between the first semiconductor nanostructure and the second semiconductor nanostructure; a disposable interposer is formed in the space; Remove the dummy gate stack; remove the disposable interposer layer using an etch chemical, wherein the hard mask is exposed to the etch chemical when the disposable interposer layer is removed; and form a gate stack, wherein a portion of the gate stack fills the space.

2. The method for forming a semiconductor structure as described in claim 1, wherein the deposited hard mask comprises: A top portion, overlapping the protruding fin and having a first thickness; and a sidewall portion, located on the sidewall of the protruding fin and having a second thickness, the second thickness being less than the first thickness.

3. The method for forming a semiconductor structure as described in claim 2 further includes: Before forming the dummy gate stack, the top and sidewall portions of the hard shield are removed, while the bottom portion of the hard shield is retained.

4. The method of forming a semiconductor structure as described in claim 1, wherein after removing the disposable interposer, a bottom of the hard mask is retained.

5. A method for forming a semiconductor structure, comprising: A shallow trench isolation region is formed in a semiconductor substrate, wherein a semiconductor protrusion is formed on a portion of the semiconductor substrate near the shallow trench isolation region; A first semiconductor nanostructure is formed, wherein the first semiconductor nanostructure is separate from and overlaps with the semiconductor protrusion; a hard mask is formed on the shallow trench isolation region; a dummy gate stack is formed on the first semiconductor nanostructure and the hard mask; and a gate stack is formed to replace the dummy gate stack, the gate stack including a first portion and a second portion, the first portion of the gate stack being located between the first semiconductor nanostructure and the semiconductor protrusion, and the hard mask being located between the shallow trench isolation region and the second portion of the gate stack.

6. The method of forming a semiconductor structure as described in claim 5, wherein the hard mask and the shallow trench isolation region comprise different dielectric materials.

7. A method for forming a semiconductor structure as described in claim 6, wherein the step of forming the hard mask includes a deposition process and an etching process following the deposition process.

8. A method for forming a semiconductor structure, comprising: A shallow trench isolation region is formed in a semiconductor substrate, wherein a portion of the semiconductor substrate located near and in contact with the shallow trench isolation region serves as a semiconductor strip; a dielectric pad is formed on the shallow trench isolation region to contact the shallow trench isolation region; a dielectric hard mask is formed on the dielectric pad, wherein the sidewall portion of the dielectric pad includes sidewalls on both sides to contact the dielectric hard mask and the semiconductor strip; a dummy gate stack is formed on the dielectric hard mask; and a gate stack is formed in place of the dummy gate stack on the dielectric hard mask to contact the dielectric hard mask.

9. A method for forming a semiconductor structure as described in claim 8, wherein the dielectric hard mask and the shallow trench isolation region are composed of different materials.

10. A method of forming a semiconductor structure as claimed in claim 8 or 9, wherein when forming the gate stack, the dielectric hard mask includes an arcuate upper surface, and the middle portion of the arcuate upper surface is lower than portions of the arcuate upper surface on both sides of the middle portion.

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