Semiconductor structure and method for forming the same

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region. Each of the first active region and the second active region includes alternatingly stacked plurality of first semiconductor layers and plurality of second semiconductor layers. The method also includes replacing the first semiconductor layers of the second active region with plurality of dielectric layers, removing the dielectric layers to form a plurality of first gaps, removing the first semiconductor layers of the first active region to form a plurality of second gaps, and forming a first gate stack to fill the first gaps and second gaps.

Description

Technical Field

[0001] This invention relates to a method for forming semiconductor structures, and more particularly to a method for forming semiconductor structures of static random access memory. Prior Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support increasingly complex and sophisticated functionality. Therefore, there has been a persistent trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by miniaturizing semiconductor IC dimensions (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of semiconductor manufacturing processes. Therefore, continued progress in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such introduced multi-gate device is the gate-all-around transistor (GAA). The name "GAA" comes from its gate structure, which completely surrounds the channel region, providing access to both sides or all four sides of the channel. GAAs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for radical miniaturization while maintaining gate control and mitigating SCEs. In conventional processes, GAAs provide the channel within silicon nanowires. However, integrating the fabrication of nanowires around the GAA component can be challenging. For example, while current methods are satisfactory in many respects, further improvements are needed. Summary of the Invention

[0004] This invention provides a method for forming a semiconductor structure, comprising forming a first active region and a second active region, wherein each of the first active region and the second active region comprises a plurality of alternately stacked first semiconductor layers and a plurality of second semiconductor layers; replacing the first semiconductor layers of the second active region with a plurality of dielectric layers; removing the dielectric layers to form a plurality of first gaps; removing the first semiconductor layers of the first active region to form a plurality of second gaps; and forming a first gate stack to fill the first gaps and the second gaps.

[0005] This invention provides a method for forming a semiconductor structure, comprising forming a first active region and a second active region, wherein the first active region includes a plurality of alternately stacked first semiconductor layers and a plurality of alternately stacked second semiconductor layers, and the second active region includes a plurality of alternately stacked dielectric layers and second semiconductor layers; removing the dielectric layers of the second active region and simultaneously etching the second semiconductor layers of the second active region with a first etch amount; removing the first semiconductor layers of the first active region and simultaneously etching the second semiconductor layers of the first active region with a second etch amount, wherein the second etch amount is greater than the first etch amount; and forming a gate stack to surround the second semiconductor layers of the first active region and the second semiconductor layers of the second active region.

[0006] This invention provides a semiconductor structure comprising a first transistor in a cell region and including a plurality of first nanostructures and a first gate stack; a second transistor in the cell region and including a plurality of second nanostructures and a first gate stack; and a gate spacer layer along the first gate stack, wherein: the first gate stack extends in a first horizontal direction; each of the first nanostructures includes a plurality of central portions surrounded by the first gate stack and having a first width in the first horizontal direction, and each of the first nanostructures includes a plurality of edge portions surrounded by the gate spacer layer and having a second width in the first horizontal direction; each of the second nanostructures includes a plurality of central portions surrounded by the first gate stack and having a third width in the first horizontal direction, and each of the second nanostructures includes a plurality of edge portions surrounded by the gate spacer layer and having a fourth width in the first horizontal direction; and the first ratio of the second width to the first width is less than the second ratio of the fourth width to the third width. Simple Explanation of the Diagram

[0007] The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention. Figure 1 is a perspective schematic diagram illustrating a semiconductor structure according to some embodiments disclosed herein. Figure 2 is a simplified schematic diagram illustrating a static random access memory according to some embodiments disclosed herein. Figure 3A is a schematic diagram illustrating a single-port static random access memory unit according to some embodiments of the present disclosure. Figure 3B is an alternative schematic diagram illustrating the static random access memory unit of Figure 3A according to some embodiments of the present disclosure. Figure 4 is a schematic diagram illustrating the layout of two static random access memory units in Figure 2, according to some embodiments disclosed herein. Figures 5A-1, 5A-2, and 5A-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5B-1, 5B-2, and 5B-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5C-1, 5C-2, and 5C-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 5D is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the section line X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 5E is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the section line X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 5F is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the section line X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5G-1, 5G-2, and 5G-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments disclosed herein. Figure 5H is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the section line X1-X1 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 5I is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the cross-section X1-X1 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5J-1 and 5J-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5K-1, 5K-2, and 5K-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 5L-1, 5L-2, and 5L-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments disclosed herein. Figures 5M-1, 5M-2, and 5M-3 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1, X2-X2, and YY corresponding to Figure 4, according to some embodiments disclosed herein. Figure 5M-4 is a planar schematic diagram of plane AA corresponding to Figure 5M-1, based on some embodiments of the present disclosure. Figure 5M-5 is a plan view of plane BB corresponding to Figure 5M-1, according to some embodiments of the present disclosure. Figure 5N is a schematic diagram illustrating experimental results demonstrating the germanium distribution of a pull-up crystal, based on some embodiments of this disclosure. Figure 50 is a schematic cross-sectional view of the nanostructures of a pull-up crystal and a pull-down crystal, according to some embodiments. Figures 6A-1 and 6A-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 6B is a schematic cross-sectional view illustrating the formation of a semiconductor structure of a static random access memory cell at one intermediate stage of the section line X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 6C-1 and 6C-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 6D-1 and 6D-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 6E-1 and 6E-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 6F-1 and 6F-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 6F-3 is a planar schematic diagram of plane AA corresponding to Figure 6F-1, according to some embodiments of the present disclosure. Figures 7A-1 and 7A-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 7B-1 and 7B-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 7C-1 and 7C-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of the cross-sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figures 7D-1 and 7D-2 are schematic cross-sectional views illustrating the formation of a semiconductor structure of a static random access memory cell at one of the intermediate stages of sections X1-X1 and X2-X2 corresponding to Figure 4, according to some embodiments of the present disclosure. Figure 7D-3 is a planar schematic diagram of plane AA corresponding to Figure 7D-1, according to some embodiments of the present disclosure. Implementation

[0008] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0009] Variations of the embodiments are described. In the various schematic diagrams and illustrative embodiments, similar reference numerals are used to identify similar elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0010] The nanostructured transistors described below (e.g., sheet transistors, wire transistors, multi-bridge channels, field-effect transistors (FETs), and fully wound gate (GAA) transistor structures) can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes (including dual-patterning or multi-patterning processes). Generally, dual-patterning or multi-patterning processes combine lithography with self-alignment processes to create patterns with, for example, smaller pitches than those obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fully wound gate structure.

[0011] As component sizes continue to shrink, static random-access memory (SRAM) devices are increasingly employing nanostructured transistors (e.g., fully wound gate field-effect transistors) to improve cell performance, such as cell current, operating voltage (e.g., Vmax, Vmin, etc.), SRAM margins (e.g., write margin and / or read margin), and / or operating speed. This disclosure relates to the semiconductor structure of a SRAM device incorporating nanostructured transistors. This method includes a disposable oxide interposer (DOI) process, in which the SiGe layer of the active region is replaced by a dielectric layer. Due to the relatively high etch selectivity between the dielectric layer (e.g., SiO) and the Si layer in the active region, the resulting transistor can have a larger effective channel width. For example, the formation of the n-channel transistors PD and PG of the static random access memory cell can include a disposable oxide intermediate process, and thus can enhance the performance (e.g., operating speed) of the resulting static random access memory device.

[0012] Figure 1 is a perspective view illustrating a semiconductor structure 100 according to some embodiments of the present disclosure. According to some embodiments, the semiconductor structure 100 includes a substrate 102 and a fin structure (e.g., active region 104) (including active region 104N and active region 104P) located above the substrate 102, as illustrated in Figure 1. In some embodiments, the semiconductor structure 100 is used to form a static random access memory (SRAM) cell array. According to some embodiments, the substrate 102 includes a p-type well PW and an n-type well NW adjacent to the p-type well PW. According to some embodiments, the active region 104N is formed in the p-type well PW of the substrate 102, while the active region 104P is formed in the n-type well NW of the substrate 102. According to some embodiments, the active regions 104N and 104P are the active regions of the semiconductor structure 100.

[0013] To better understand the semiconductor structure 100, XYZ coordinate references are provided in the accompanying drawings of this disclosure. Directions (axis) X and Y are generally oriented in a lateral (or horizontal) direction, parallel to the main surface of substrate 102. Direction Y is lateral to (e.g., substantially perpendicular to) direction X. Direction Z is generally oriented in a vertical direction, perpendicular to the main surface (or XY plane) of substrate 102.

[0014] According to some embodiments, active region 104N includes a lower fin element 103P formed of a p-type well PW, while active region 104P includes a lower fin element 103N formed of an n-type well NW. According to some embodiments, both lower fin elements 103P and 103N are surrounded by an isolation structure 110. According to some embodiments, each of active regions 104N and 104P further includes an upper fin element formed of an epitaxial stack comprising alternating first semiconductor layers 106 and second semiconductor layers 108. According to some embodiments, the second semiconductor layer 108 will form a nanostructure (e.g., a nanowire or nanosheet), and the second semiconductor layer 108 serves as a channel for the resulting semiconductor device.

[0015] According to some embodiments, active regions 104N and 104P extend in direction X. That is, according to some embodiments, active regions 104N and 104P have a longitudinal axis parallel to direction X. Direction X can also be referred to as the channel direction. The current in the resulting semiconductor device (i.e., nanostructured transistor) flows through the channel along direction X. According to some embodiments, each fin structure (e.g., active region 104) is defined as several channel regions and several source / drain regions, wherein the channel regions and source / drain regions are arranged alternately. It is worth noting that in this disclosure, source / drain regions or source / drain components may refer to the source or drain individually or collectively depending on the context.

[0016] According to some embodiments, the dummy gate structure 124 is formed having a longitudinal axis parallel to the direction Y and extending across and / or around the channel region of active region 104N and active region 104P. According to some embodiments, the source / drain regions of active region 104N and active region 104P are exposed from the dummy gate structure 124. The direction Y may also be referred to as the gate wiring direction. Although two fin structures (e.g., active region 104) are shown in Figure 1, the semiconductor structure 100 may include more than two fin structures (e.g., active region 104). Furthermore, Figure 1 shows two dummy gate structures 124 (or channel regions) for illustrative purposes and is not intended to be limiting. The number of fin structures and gate structures may depend on the design requirements of the integrated circuit and / or the performance considerations of the semiconductor device.

[0017] Figure 2 is a simplified schematic diagram illustrating a static random access memory (SRAM) 30 according to some embodiments of this disclosure. The SRAM 30 can be a standalone device or implemented in an integrated circuit (e.g., a system-on-a-chip (SOC)). The SRAM 30 comprises a cell array formed by a plurality of SRAM cells (or bit cells) 10, arranged in multiple rows and columns within the cell array. In the fabrication of the SRAM cells, the cell array may be surrounded by a plurality of strap cells 20A and a plurality of edge cells 20B, where the strap cells 20A and edge cells 20B are dummy cells of the cell array. In some embodiments, the strap cells 20A are arranged horizontally around the cell array, while the edge cells 20B are arranged vertically around the cell array. The shape and size of the strap cells 20A and edge cells 20B are determined according to the specific application.

[0018] In some embodiments, the connection unit 20A and the edge unit 20B have the same shape and size as the static random access memory (SRAM) unit 10. In some embodiments, the connection unit 20A, the edge unit 20B, and the SRAM unit 10 have different shapes and sizes. Furthermore, in the SRAM 30, each SRAM unit 10 has the same rectangular shape / area; for example, the width and height of the SRAM unit 10 are the same. In the cell array of the SRAM 30, although only one group GP is shown in Figure 2, the SRAM units 10 can be divided into multiple groups GP, and each group GP contains four adjacent SRAM units 10.

[0019] Figure 3A illustrates a single-port static random access memory (SRAM) cell 10 according to some embodiments of this disclosure. The SRAM cell 10 includes a pair of cross-coupled inverters, Inverter-1 and Inverter-2, and two pass-gate transistors, PG-1 and PG-2. Inverter-1 and Inverter-2 are cross-coupled between storage nodes SN1 and SN2, forming a latch. Storage nodes SN1 and SN2 are complementary nodes, typically at opposite logic levels (logic high or logic low). Pass-gate transistor PG-1 is coupled between bit line BL and storage node SN1, while pass-gate transistor PG-2 is coupled between complementary bit line BLB and storage node SN2, and complementary bit line BLB is complementary to bit line BL. The gates of gate transistors PG-1 and PG-2 are coupled to the same word line WL. Both gate transistors PG-1 and PG-2 are n-type metal-oxide-semiconductor (NMOS) transistors.

[0020] Figure 3B is an alternative schematic diagram of the static random access memory cell of Figure 3A according to some embodiments of the present disclosure. The inverter-1 in Figure 3A includes a pull-up transistor PU-1 and a pull-down transistor PD-1, as illustrated in Figure 3B. The pull-up transistor PU-1 is a p-type metal-oxide-semiconductor (PMOS) transistor, and the pull-down transistor PD-1 is an n-type metal-oxide-semiconductor transistor. The drains of both the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled to a storage node SN1 connected to a gate transistor PG-1. The gates of both the pull-up transistor PU-1 and the pull-down transistor PD-1 are coupled to a storage node SN2 connected to a gate transistor PG-2. Furthermore, the source of the pull-up transistor PU-1 is coupled to a power supply node VDD, while the source of the pull-down transistor PD-1 is coupled to ground VSS.

[0021] Approximately, the inverter-2 in Figure 3A includes a pull-up transistor PU-2 and a pull-down transistor PD-2, as illustrated in Figure 3B. The pull-up transistor PU-2 is a p-type metal-oxide-semiconductor (MOS) transistor, while the pull-down transistor PD-2 is an n-type MOS transistor. The drains of both the pull-up transistor PU-2 and the pull-down transistor PD-2 are coupled to a storage node SN2 connected to a gate transistor PG-2. The gates of both the pull-up transistor PU-2 and the pull-down transistor PD-2 are coupled to a storage node SN1 connected to a gate transistor PG-1. Furthermore, the source of the pull-up transistor PU-2 is coupled to the power supply node VDD, while the source of the pull-down transistor PD-2 is coupled to ground VSS. In some embodiments, the transistors of the static random access memory unit 10 (including the through gate transistor PG-1, the through gate transistor PG-2, the pull-up transistor PU-1, the pull-up transistor PU-2, the pull-down transistor PD-1, and the pull-down transistor PD-2) are nanostructured transistors (e.g., fully wound gate transistors).

[0022] Figure 4 is a schematic diagram illustrating the layout of two static random access memory (SRAM) cells 10 shown in Figure 2, according to some embodiments of this disclosure. According to some embodiments, SRAM cells 10_1 and 10_2 in Figure 4 are arranged adjacent to each other and constitute half of group GP in Figure 2. SRAM cells 10_1 and 10_2 are formed by active regions 104 (including active regions 104N_1, 104P_1, 104P_2, and 104N_2) and gate stacks 172 (including gate stacks 172_1 to 172_4). According to some embodiments, active region 104N_1 is formed in a p-type well PW, active regions 104P_1 and 104P_2 are formed in an n-type well NW, and active region 104N_2 is formed in another p-type well PW. According to some embodiments, an n-type well (NW) is arranged between two p-type wells (PW).

[0023] Active region 104 may be the fin structure illustrated in Figure 1. According to some embodiments, each active region 104 includes a lower fin element and a group of nanostructures located above the lower fin element. As used in this disclosure, "a group of nanostructures" refers to an active region comprising a semiconductor structure having multiple semiconductor layers in cylindrical, elongated, and / or sheet-like shapes. According to some embodiments, the lower fin element of active region 104 extends in the X-direction (row direction). According to some embodiments, each of active regions 104P_1 and active regions 104P_2 includes several segments that are physically isolated from each other.

[0024] According to some embodiments, the gate stack 172 spans the lower fin element and wraps around the nanostructure in the Y direction (column direction). In some embodiments, each gate stack 172 may include several segments that are electrically and physically isolated from each other. In some embodiments, each static random access memory cell 10 includes six functional transistors (a gate transistor PG, a pull-down transistor PD, and a pull-up transistor PU) as nanostructured transistors. In some embodiments, the gate transistors PG-1 and PG-2, as well as the pull-down transistors PD-1 and PD-2, are n-channel nanostructured transistors, while the pull-up transistors PU-1 and PU-2 are p-channel nanostructured transistors.

[0025] In static random access memory (SRAM) cell 10_1, a gate transistor PG-1 is formed at the intersection of active region 104N_1 and gate stack 172_1. A pull-down transistor PD-1 is formed at the intersection of active region 104N_1 and gate stack 172_2. A gate transistor PG-2 is formed at the intersection of active region 104N_2 and gate stack 172_2. A pull-down transistor PD-2 is formed at the intersection of active region 104N_2 and gate stack 172_1. In SRAM cell 10_1, a pull-up transistor PU-1 is formed at the intersection of active region 104P_1 and gate stack 172_2. A pull-up transistor PU-2 is formed at the intersection of active region 104P_2 and gate stack 172_1. Furthermore, no functional transistors are formed at the intersection of the active region 104P_1 and the gate stack 172_1, or at the intersection of the active region 104P_2 and the gate stack 172_1.

[0026] Various contact plugs and their corresponding interconnect vias can be used to electrically connect the components in each static random access memory (SRAM) cell 10. For example, in SRAM cell 10_1, the bit line (BL) (not shown) can be electrically connected to the source terminal of gate transistor PG-1 via contact plug 186_1, while the complementary bit line (BLB) (not shown) can be electrically connected to the source terminal of gate transistor PG-2 via contact plug 186_2. The power supply node VDD (not shown) can be electrically connected to the source terminal of pull-up transistor PU-1 via contact plug 186_3, and to the source terminal of pull-up transistor PU-2 via contact plug 186_4. The ground VSS (not shown) can be electrically connected to the source terminal of pull-down transistor PD-1 via contact plug 186_5, and to the source terminal of pull-down transistor PD-2 via contact plug 186_6.

[0027] In static random access memory (SRAM) cell 10_1, the drain terminals of pull-up transistor PU-1 and pull-down transistor PD-1 can be electrically connected to each other through contact plug 186_7, and the drain terminals of pull-up transistor PU-2 and pull-down transistor PD-2 can be electrically connected to each other through contact plug 186_8. In some embodiments, SRAM cell 10_2 is a copy of SRAM cell 10_1, but is flipped in the Y direction (axis).

[0028] According to some embodiments, Figure 4 further illustrates the reference cross-sections used in the following figures. Section line X1-X1 lies in a plane parallel to the longitudinal axis (direction X) of the active region 104 and passing through the active region 104P_1. Section line X2-X2 lies in a plane parallel to the longitudinal axis (direction X) of the active region 104 and passing through the active region 104N_2. Section line YY lies in a plane parallel to the longitudinal axis (direction Y) of the gate stack 172 and passing through the gate stack 172_1 of the pull-down transistor PD-2 and the pull-up transistor PU-2.

[0029] Figures 5A-1 to 5M-3 are schematic cross-sectional views illustrating the formation of the semiconductor structure 100_1 of the static random access memory cell at various intermediate stages according to some embodiments. According to some embodiments, Figures 5A-1, 5B-1, 5C-1, 5G-1, 5H, 5I, 5J-1, 5K-1, 5L-1 and Figure 5M-1 correspond to cross-sections X1-X1, Figures 5A-2, 5B-2, 5C-2, 5D, 5E, 5F, 5G-2, 5J-2, 5K-2, 5L-2 and Figure 5M-2 correspond to cross-sections X2-X2, and Figures 5A-3, 5B-3, 5C-3, 5G-3, 5K-3, 5L-3 and Figure 5M-3 correspond to cross-section YY.

[0030] Figures 5A-1, 5A-2, and 5A-3 are schematic diagrams illustrating a semiconductor structure 100_1 after the formation of the active region 104 and the isolation structure 110, according to some embodiments of the present disclosure. According to some embodiments, a substrate 102 is provided, as illustrated in Figures 5A-1, 5A-2, and 5A-3. The substrate 102 may be a portion of a semiconductor wafer, a semiconductor wafer (or die), and the like. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the substrate 102 comprises elemental semiconductors such as germanium; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In addition, the substrate 102 may optionally include an epi-layer, which may be strained to enhance performance, and may include a silicon-on-insulator (SOI) structure, and / or have other suitable reinforcing components.

[0031] According to some embodiments, an n-type well (NW) and a p-type well (PW) are formed in a substrate 102, as illustrated in Figures 5A-1 to 5A-3. In some embodiments, the n-type well (NW) and the p-type well (PW) are formed by an ion implantation process. In some embodiments, the n-type well (NW) and the p-type well (PW) have different conductivity types. For example, according to some embodiments, a patterned masking layer (such as a photoresist layer and / or a hard masking layer) is formed to cover a predetermined area of ​​the substrate 102 where a p-type well region is to be formed, and then an n-type dopant (such as phosphorus or arsenic) is implanted into the substrate 102 to form an n-type well (NW). Similarly, according to some embodiments, a patterned masking layer (such as a photoresist layer and / or a hard masking layer) is formed to cover a predetermined area of ​​the substrate 102 where an n-type well region is to be formed, and then a p-type dopant (such as boron or BF2) is implanted into the substrate 102 to form a p-type well (PW).

[0032] According to some embodiments, active regions 104 (including active regions 104N and 104P) are formed over substrate 102, as illustrated in Figures 5A-1 to 5A-3. According to some embodiments, active region 104N is formed over a p-type well PW, and active region 104P is formed over an n-type well NW. In some embodiments, active regions 104N and 104P extend in the X direction. That is, according to some embodiments, active regions 104N and 104P have a longitudinal axis parallel to the X direction. According to some embodiments, the formation of active regions 104N and 104P includes forming an epitaxial stack over substrate 102 using an epitaxial growth process. According to some embodiments, the epitaxial stack includes alternating first semiconductor layers 106 and second semiconductor layers 108. Epitaxial growth processes can include molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or other suitable techniques.

[0033] In some embodiments, the first semiconductor layer 106 is formed of a first semiconductor material, and the second semiconductor layer 108 is formed of a second semiconductor material. According to some embodiments, the first semiconductor material used for the first semiconductor layer 106 has a different lattice constant than the second semiconductor material used for the second semiconductor layer 108. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etch selectivity. In some embodiments, the first semiconductor layer 106 is formed of SiGe, wherein the percentage of germanium (Ge) in SiGe ranges from about 20 atomic percent to about 50 atomic percent, and the second semiconductor layer 108 is formed of pure silicon or is substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si 1-xGe x, where x is greater than about 0.3, or Ge (x = 1.0), and the second semiconductor layer 108 is Si or Si 1-yGe y, where y is less than about 0.4, and x > y.

[0034] According to some embodiments, a first semiconductor layer 106 is configured as a sacrificial layer and will be removed to form gaps to accommodate gate material, while a second semiconductor layer 108 will form a nanostructure (e.g., nanowires or nanosheets) that extends laterally between source / drain components and serves as a channel for the resulting semiconductor device (such as a nanostructured transistor). In some embodiments, the thickness of each first semiconductor layer 106 ranges from about 3 nm to about 20 nm, such as from about 4 nm to about 12 nm. In some embodiments, the thickness of each second semiconductor layer 108 ranges from about 2 nm to about 20 nm, such as from about 2 nm to about 10 nm. Although three first semiconductor layers 106 and three second semiconductor layers 108 are depicted in Figures 5A-1 to 5A-3, the number is not limited to three and can be one, two, more than three, or less than ten.

[0035] In some embodiments, the active region 104N has a width W1 ranging from about 15 nm to about 50 nm. In some embodiments, the active region 104P has a width W2 ranging from about 15 nm to about 50 nm. In some embodiments where the semiconductor structure 100_1 is used to form a high-current static random access memory device, the width of the active region 104N is greater than the width of the active region 104P, for example, the ratio (W1 / W2) ranges from about 1.5 to about 4. In some other embodiments where the semiconductor structure 100_1 is used to form a high-density static random access memory device, the width W1 of the active region 104N is equal to the width W2 of the active region 104P.

[0036] According to some embodiments, an epitaxial stack comprising a first semiconductor layer 106 and a second semiconductor layer 108 and an underlying n-well NW and p-well PW is patterned to form active regions 104N and 104P. In some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) over the epitaxial stack using an optical lithography process. According to some embodiments, an etching process is then performed to remove portions of the epitaxial stack and the n-well NW and p-well PW that are not covered by the patterned hard mask layer, thereby forming trenches and active regions 104N and 104P protruding from between the trenches. The etching process can be anisotropic etching, such as dry plasma etching.

[0037] According to some embodiments, the portion of a p-type well PW protruding from between the trenches forms the lower fin element 103P of the active region 104N. According to some embodiments, the portion of an n-type well NW protruding from between the trenches forms the lower fin element 103N of the active region 104P. According to some embodiments, the remaining portion of the epitaxial stack (including the first semiconductor layer 106 and the second semiconductor layer 108) forms the upper fin elements of the active region 104N and the active region 104P above the respective lower fin elements 103P and lower fin elements 103N.

[0038] According to some embodiments, a dicing process can be performed to dice the active region 104P (e.g., active region 104P_1), as illustrated in Figure 5A-1. Although only one segment of the active region 104P_1 is illustrated, the active region 104P can be diced into several segments. The dicing process can include optical lithography and etching processes. According to some embodiments, during the dicing process, the upper fin element of the active region 104P is removed, and the lower fin element 103N of the active region 104P can also be etched.

[0039] According to some embodiments, an isolation structure 110 is formed to surround the lower fin elements 103N and 103P of the active regions 104N and 104P, as illustrated in Figures 5A-1 and 5A-3. According to some embodiments, the isolation structure 110 is configured to electrically isolate the active regions 104N and 104P, and is also referred to as a shallow trench isolation (STI) component. In some embodiments, the isolation structure 110 includes a first liner 112, a second liner 114, a third liner 116, a first bulk layer 118, a fourth liner 120, and a second bulk layer 122. In some other embodiments, the isolation structure 110 may be formed of a single layer or a double layer of dielectric material.

[0040] In some embodiments, a first liner 112 extends conformally along active regions 104N and 104P and substrate 102; a second liner 114 is located above the first liner 112; a third liner 116 is located above the second liner 114; a first bulk layer 118 is nested within the third liner 116; a fourth liner 120 is located above the first liner 112, the second liner 114, the third liner 116, and the first bulk layer 118; and a second bulk layer 122 is nested within the fourth liner 120.

[0041] In some embodiments, the first substrate 112, the second substrate 114, the third substrate 116, and the fourth substrate 120, as well as the first bulk layer 118 and the second bulk layer 122, are formed of silicon-containing dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). In one embodiment, the first substrate 112 and the fourth substrate 120 are formed of silicon oxide (SiO), while the second substrate 114 and the third substrate 116 are formed of low dielectric constant dielectric materials (e.g., having a k value less than 7.9), such as silicon carbonitride (SiOCN). In another embodiment, the first bulk layer 118 and the second bulk layer 122 are formed of different materials and have significant differences in etching selectivity. For example, the first bulk layer 118 is formed of silicon oxide (SiO), while the second bulk layer 122 is formed of silicon nitride (SiN).

[0042] The formation of the isolation structure 110 includes depositing a first substrate 112, a second substrate 114, and a third substrate 116 to partially fill the trench, depositing a first bulk layer 118 to overfill the remaining portion of the trench, and planarizing and etching back the dielectric materials (first substrate 112, second substrate 114, third substrate 116, and first bulk layer 118) to re-form the trench. According to some embodiments, the formation of the isolation structure 110 further includes depositing a fourth substrate 120 to partially fill the trench, depositing a second bulk layer 122 to overfill the remaining portion of the trench, and planarizing and etching back the dielectric materials (fourth substrate 120 and second bulk layer 122) until the upper fin elements of the active regions 104N and 104P are exposed. In some embodiments, the deposition process includes in-situ steam generation (ISSG), thermal oxidation, chemical vapor deposition (CVD) (such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), high aspect ratio process (HARP), or flowable CVD (FCVD)), atomic layer deposition (ALD), other suitable techniques, and / or combinations thereof. The planarization process may be chemical mechanical polishing (CMP). The etch-back process may include dry plasma etching and / or wet chemical etching.

[0043] Figures 5B-1, 5B-2, and 5B-3 are schematic diagrams illustrating, according to some embodiments, the semiconductor structure 100_1 after the formation of the dummy gate structure 124, the gate spacer layer 130, and the source / drain recesses 136N and 136P. According to some embodiments, the dummy gate structure 124 (including dummy gate structures 124_1 to 124_4) is formed above the semiconductor structure 100_1, as illustrated in Figures 5B-1 to 5B-3. According to some embodiments, the dummy gate structure 124 extends in the Y direction across the channel region of the active region 104N and the active region 104P, and the isolation structure 110. According to some embodiments, the dummy gate structure 124 has a longitudinal axis parallel to the Y direction. According to some embodiments, the dummy gate structure 124 is configured as a sacrificial structure and is replaced by the gate stacks (gate stacks 172_1 to 172_4 illustrated in Figure 4). According to some embodiments, the active region 104 and the dummy gate structure 124 together define the locations of the pull-down transistor PD, the gate transistor PG, and the pull-up transistor PU to form the static random access memory cell.

[0044] According to some embodiments, each dummy gate structure 124 includes a dummy gate dielectric layer 126 and a dummy gate electrode layer 128 formed above the dummy gate dielectric layer 126, as illustrated in Figures 5B-1 and 5B-3. In some embodiments, the dummy gate dielectric layer 126 is formed of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO₂, HfZrO, HfSiO, HfTiO, HfAlO, and / or combinations thereof. In some embodiments, the dielectric material is formed using atomic layer deposition, chemical vapor deposition, thermal oxidation, physical vapor deposition (PVD), other suitable techniques, and / or combinations thereof.

[0045] In some embodiments, the dummy gate electrode layer 128 is formed of a semiconductor material, such as polycrystalline silicon or polycrystalline silicon-germanium. In some embodiments, the dummy gate electrode layer 128 is formed of a conductive material, such as a metal nitride, a metal silicate, a metal, and / or a combination thereof. In some embodiments, the material of the dummy gate electrode layer 128 is formed using chemical vapor deposition, other suitable techniques, and / or a combination thereof.

[0046] In some embodiments, the formation of the dummy gate structure 124 includes globally and compliantly depositing a dielectric material for the dummy gate dielectric layer 126 over the semiconductor structure 100_1, depositing a material for the dummy gate electrode layer 128 over the dielectric material, planarizing the material of the dummy gate electrode layer 128, and patterning the dielectric material and the material of the dummy gate electrode layer 128 into the dummy gate structure 124. According to some embodiments, the patterning process includes forming a patterned hard mask layer (not shown) using an optical lithography process to cover the channel regions of the active regions 104N and 104P, and etching away the material of the dummy gate electrode layer 128 and the dielectric material until the source / drain regions of the active regions 104N and 104P are exposed.

[0047] According to some embodiments, a gate spacer layer 130 is formed on both sides of the dummy gate structure 124, as illustrated in Figures 5B-1 and 5B-2. According to some embodiments, the gate spacer layer 130 extends in the Y direction and spans the active regions 104N and 104P and the isolation structure 110. The gate spacer layer 130 serves to offset and separate subsequently formed source / drain components. In some embodiments, the formation of the gate spacer layer 130 includes globally and compliantly depositing spacer layers 132 and 134 using atomic layer deposition, chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition, or combinations thereof), followed by an isotropic etching process.

[0048] In some embodiments, spacer layers 132 and 134 are formed of dielectric materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbide (Si(O)CN), silicon carbide (SiC), or other suitable dielectric materials. In some embodiments, spacer layers 132 and 134 are formed of different materials and have different dielectric constants. For example, spacer layers 132 and 134 are formed of SiOCN with different compositions (e.g., different carbon concentrations) and different dielectric constants. In some other embodiments, spacer layers 132 and 134 are made of the same material. According to some embodiments, after an isotropic etching process, the vertical portions of spacer layers 132 and 134 remaining on both sides of the dummy gate structure 124 are formed as gate spacer layers 130. Although not shown, the vertical portions of spacer layer 132 and spacer layer 134 may remain on both sides of active region 104N and active region 104P and form fin spacer layers.

[0049] According to some embodiments, an etching process is performed to etch the source / drain regions of the active regions 104N and 104P, thereby forming source / drain recesses 136N and 136P, as illustrated in Figures 5B-1 and 5B-2. The etching process can be anisotropic etching, such as dry plasma etching, or isotropic etching, such as dry chemical etching, far-end plasma etching, or wet chemical etching, and / or combinations thereof. According to some embodiments, the gate spacer layer 130 and the dummy gate structure 124 can be used as an etching mask, such that the source / drain recesses 136N and 136P are self-aligned and formed on both sides of the dummy gate structure 124. According to some embodiments, the bottoms of the source / drain recesses 136N and 136P extend into the lower fin elements 103N and 103P. According to some embodiments, the isolation structure 110 may also be etched during the etching process to expose the first bulk layer 118, as illustrated in Figure 5B-1. In some other embodiments, the isolation structure 110 may not be etched, or may be only slightly etched.

[0050] Figures 5C-1 to 5C-3 illustrate a replacement process for the first semiconductor layer 106 according to some embodiments. This replacement process may also be referred to as a disposable oxide interposer (DOI) process. Figures 5C-1, 5C-2, and 5C-3 illustrate a semiconductor structure 100_1 after the removal of the first semiconductor layer 106, according to some embodiments. According to some embodiments, a patterned masking layer 138 is formed to cover the active region 104P (or n-type well NW) and expose the active region 104N (or p-type well PW), as illustrated in Figures 5C-1 to 5C-3. The patterned masking layer 138 may be a patterned masking layer and / or a patterned photoresist layer.

[0051] For example, a hard mask layer can be globally and compliantly deposited over the semiconductor structure 100_1 using atomic layer deposition or chemical vapor deposition. The hard mask layer is formed of silicon-containing dielectric materials, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon carbide (SiC), or oxygen-doped nitrogen-doped silicon carbide (Si(O)CN); metal oxide dielectrics, such as Al2O3, LaO, HfO2, Ta2O5, TiO2, ZrO2, or Y2O3; other suitable masking materials; or combinations thereof. Next, a bottom anti-reflection coating (BARC) material (such as an inorganic or organic material (e.g., a polymer, oligomer, or monomer)) is formed on top of the hard mask layer using a spin-on coating process or a chemical vapor deposition process. Then, a patterned photoresist layer is formed on the bottom anti-reflection coating material using an optical lithography process, corresponding to or overlapping an n-type well (NW). The optical lithography process may include forming the photoresist material, performing a pre-exposure baking process, performing an exposure process using a photomask (or mask), performing a post-exposure baking process, and performing a development process.

[0052] Subsequently, according to some embodiments, a patterned photoresist layer is used to etch the bottom antireflective coating material and the hard mask layer, thereby forming a patterned mask layer 138. In some embodiments, the etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, or a combination thereof. The photoresist layer and / or the bottom antireflective coating material may be removed during the etching process or by means of an additional process (e.g., etching or ashing).

[0053] According to some embodiments, an etching process is performed using a patterned mask layer 138 to remove the first semiconductor layer 106 of the active region 104N, thereby forming a gap 140, as illustrated in Figures 5C-2 and 5C-3. According to some embodiments, the first semiconductor layer 106 of the active region 104P is protected by the patterned mask layer 138 and is retained after the etching process. The etching process includes isotropic etching processes, such as dry chemical etching, distal plasma etching, or wet chemical etching, or combinations thereof.

[0054] Figure 5D illustrates a semiconductor structure 100_1 after the deposition of dielectric material 142, according to some embodiments. According to some embodiments, dielectric material 142 is deposited over semiconductor structure 100_1 to overfill gaps 140, as illustrated in Figure 5D. In some embodiments, source / drain recesses 136N are partially filled by dielectric material 142. Dielectric material 142 is silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide nitride oxynitride (SiOCN), and / or oxygen-doped silicon carbide nitride (Si(O)CN). In some embodiments, the deposition process includes atomic layer deposition, chemical vapor deposition (such as plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or high aspect ratio processes), other suitable techniques, or combinations thereof.

[0055] Figure 5E illustrates a semiconductor structure 100_1 after an etching process, according to some embodiments. According to some embodiments, an etching process is performed to etch away the dielectric material 142 outside the gap 140, as illustrated in Figure 5E. The dielectric material 142 retained in the gap 140 is referred to as dielectric layer 142I. According to some embodiments, the etching process further etches the dielectric layer 142I laterally from the source / drain groove 136N to form a notch 144. In some embodiments, the etching process includes anisotropic etching processes, such as dry plasma etching, isotropic etching processes, such as dry chemical etching, distal plasma etching, or wet chemical etching, or combinations thereof.

[0056] Therefore, according to some embodiments, the first semiconductor layer 106 of the active region 104N is replaced by a dielectric layer 142I. In embodiments, the dielectric material 142 is formed of silicon oxide, and the dielectric layer 142I may also be referred to as a disposable oxide dielectric (DOI) component. According to some embodiments, the etch selectivity (e.g., greater than 10,000) between the dielectric layer 142I (e.g., SiO) and the second semiconductor layer 108 (e.g., Si) is much greater than the etch selectivity (e.g., about 170) between the first semiconductor layer 106 (e.g., SiGe) and the second semiconductor layer 108 (e.g., Si). According to some embodiments, the dielectric layer 142I is configured to reduce channel layer loss in subsequent channel release processes. According to some embodiments, a notch 144 is located directly below the gate spacer layer 130. According to some embodiments, the notch 144 is formed between adjacent second semiconductor layers 108 and between the lowermost second semiconductor layer 108 and the lower fin element 103P.

[0057] Figure 5F illustrates the semiconductor structure 100_1 after the formation of the inner spacer layer 146A, according to some embodiments. According to some embodiments, the inner spacer layer 146A is formed in a notch 144, as illustrated in Figure 5F. According to some embodiments, the inner spacer layer 146A is formed to abut against the concave side surface of the dielectric layer 142I. In some embodiments, the inner spacer layer 146A is located directly below the gate spacer layer 130. According to some theories, the inner spacer layer can prevent direct contact between the source / drain components and the gate stack, and is configured to reduce the parasitic capacitance (i.e., Cgs and Cgd) between the gate stack and the source / drain components.

[0058] In some embodiments, the inner spacer layer 146A is formed of a dielectric material, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide nitride oxynitride (SiOCN), and / or oxygen-doped silicon carbide nitride (Si(O)CN). In some embodiments, the inner spacer layer 146A is formed by depositing a dielectric material over the semiconductor structure 100_1 to overfill the gap 144, followed by etching back the dielectric material to remove the dielectric material outside the gap 144. According to some embodiments, dielectric material remains in multiple portions of the gap 144 as the inner spacer layer 146A. In some embodiments, the deposition process includes atomic layer deposition, chemical vapor deposition (such as plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or high aspect ratio processes), other suitable techniques, or combinations thereof. In some embodiments, the etch-back process includes anisotropic etching processes, such as dry plasma etching, isotropic etching processes, such as dry chemical etching, remote plasma etching, or wet chemical etching, or combinations thereof.

[0059] Due to the relatively high etch selectivity between dielectric layer 142I and second semiconductor layer 108, second semiconductor layer 108 can be substantially unetched during the etching process used to form notch 144. Therefore, the junctions between the top surface 146A1 and bottom surface 146A2 of inner spacer layer 146A and second semiconductor layer 108 are substantially horizontal and flat surfaces. After forming inner spacer layer 146A, patterned mask layer 138 (Figures 5C-1 and 5C-3) is removed, for example, using etching, ashing, and / or wet stripping processes.

[0060] Figures 5G-1, 5G-2, and 5G-3 illustrate the semiconductor structure 100_1 after the formation of the patterned mask layer 148, according to some embodiments. According to some embodiments, the patterned mask layer 148 is formed to cover the active region 104N (or p-type well PW) and expose the active region 104P (or n-type well NW), as illustrated in Figures 5G-1 to 5G-3. The patterned mask layer 148 may be a patterned mask layer and / or a patterned photoresist layer. The method for forming the patterned mask layer 148 may be similar to the previously described method.

[0061] Figure 5H illustrates the semiconductor structure 100_1 after the formation of notch 150, according to some embodiments. According to some embodiments, an etching process laterally etches the first semiconductor layer 106 from the source / drain recess 136P to form the notch 150. In some embodiments, the etching process includes anisotropic etching processes, such as dry plasma etching, isotropic etching processes, such as dry chemical etching, distal plasma etching, or wet chemical etching, or combinations thereof. According to some embodiments, the notch 150 is located directly below the gate spacer layer 130. According to some embodiments, the notch 150 is formed between adjacent second semiconductor layers 108 and between the lowermost second semiconductor layer 108 and the lower fin element 103N.

[0062] Figure 5I illustrates a semiconductor structure 100_1 after the formation of the inner spacer layer 146B, according to some embodiments. According to some embodiments, the inner spacer layer 146B is formed in a notch 150, as illustrated in Figure 5I. According to some embodiments, the inner spacer layer 146B is formed abutting against the concave side surface of the first semiconductor layer 106. In some embodiments, the inner spacer layer 146B is located directly below the gate spacer layer 130. In some embodiments, the inner spacer layer 146B is formed of a dielectric material, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide nitride oxynitride (SiOCN), and / or oxygen-doped silicon carbide nitride (Si(O)CN). The inner spacer layer 146B and the inner spacer layer 146A may be formed of the same dielectric material.

[0063] In some embodiments, the inner spacer layer 146B is formed by depositing dielectric material over the semiconductor structure 100_1 to overfill the gap 150, and then etching back the dielectric material to remove the dielectric material outside the gap 150. According to some embodiments, dielectric material remaining in multiple portions of the gap 150 serves as the inner spacer layer 146B. After forming the inner spacer layer 146B, the patterned mask layer 148 is removed, for example, using an etching process, an ashing process, and / or a wet stripping process.

[0064] Due to the relatively low etch selectivity between the first semiconductor layer 106 and the second semiconductor layer 108, the second semiconductor layer 108 can be etched recessed during the etching process used to form the notch 150. The junctions of the top surface 146B1 and the bottom surface 146B2 of the inner spacer layer 146B with the second semiconductor layer 108 taper toward the channel region. In some embodiments, the top surface 146B1 and the bottom surface 146B2 are curved surfaces. In some embodiments, the top surface 146B1 and the bottom surface 146B2 are linear surfaces inclined relative to a horizontal surface. In some embodiments, in the Z direction, the dimension D1 (Figure 5F) of the inner spacer layer 146A is smaller than the dimension D2 of the inner spacer layer 146B.

[0065] According to some embodiments, since the etch selectivity (e.g., greater than 10000) between dielectric layer 142I (e.g., SiO) and second semiconductor layer 108 (e.g., Si) is much greater than the etch selectivity (e.g., about 170) between first semiconductor layer 106 (e.g., SiGe) and second semiconductor layer 108 (e.g., Si), the loss (i.e., etch amount) of the second semiconductor layer 108 in active region 104N is less than the loss (i.e., etch amount) of the second semiconductor layer 108 in active region 104P.

[0066] Although Figures 5C-1 through 5I illustrate the performance of a disposable oxide medium process and the formation of the inner spacer layer 146A prior to its formation, embodiments of the method are not limited thereto. In some other embodiments, the disposable oxide medium process and the formation of the inner spacer layer 146A may be performed after the formation of the inner spacer layer 146B.

[0067] Figures 5J-1 and 5J-2 illustrate, according to some embodiments, the semiconductor structure 100_1 after the formation of semiconductor isolation component 154, dielectric isolation component 156, source / drain component 158N and source / drain component 158P, contact etching stop layer (CESL) 160, and first interlayer dielectric layer (ILD) 162. According to some embodiments, semiconductor isolation component 154 is formed in source / drain recesses 136N and 136P on lower fin element 103P and lower fin element 103N, as illustrated in Figures 5J-1 and 5J-2. In some embodiments, semiconductor isolation component 154 is formed from an epitaxial semiconductor material such as undoped silicon, and is formed by molecular beam epitaxy, metal-organic chemical vapor deposition, or vapor phase epitaxy, other suitable techniques, or combinations thereof.

[0068] According to some embodiments, a source / drain component 158P is formed above a semiconductor isolation component 154 in a source / drain recess 136P, as illustrated in Figure 5J-1. The epitaxial growth process can be molecular beam epitaxy, metal-organic chemical vapor deposition, or vapor phase epitaxy, other suitable techniques, or combinations thereof. In some embodiments, the source / drain component 158P is in-situ doped during the epitaxial process. In some embodiments, the source / drain component 158P is doped with a p-type dopant during the epitaxial growth process. For example, the p-type dopant can be boron (B) or BF₂.

[0069] For example, the p-type source / drain component 158P can be epitaxially grown silicon germanium (SiGe), silicon germanium carbon (SiGeC), germanium (Ge), silicon (Si), or a combination of the above-mentioned boron-doped materials (B). In some embodiments, the concentration of the dopant (e.g., B) in the source / drain component 158P ranges from about 1 × 10¹⁹ cm⁻³ to about 6 × 10²⁰ cm⁻³. In some embodiments, the p-type source / drain component 158P can be a multi-layer structure, such as comprising sequentially formed layers P1, P2, and P3. In some embodiments, the dopant concentration in layer P3 is greater than the dopant concentration in layer P2, for example, by one to two orders of magnitude. In an embodiment, layer P1 is a boron-doped silicon layer.

[0070] Furthermore, in some embodiments, an epitaxial proximity push (EPI) process is selectively performed on the second semiconductor layer 108 of the active region 104P prior to the formation of the p-type source / drain component 158P. In some embodiments, the sidewalls of the second semiconductor layer 108 of the active region 104P are indented from the sidewalls of the inner spacer layer 146B, as illustrated in Figure 5J-1. In some embodiments, the epitaxial proximity push process includes an isotropic etching process.

[0071] According to some embodiments, a dielectric isolation member 156 is formed over a semiconductor isolation member 154 in a source / drain recess 136N, as illustrated in Figure 5J-2. The dielectric isolation member 156 is configured to reduce the parasitic capacitance of the resulting n-channel transistor. In some other embodiments, the dielectric isolation member 156 may also be formed on the semiconductor isolation member 154 in a source / drain recess 136P. In some embodiments, the dielectric isolation component 156 is formed of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon carbide nitride nitride (SiOCN), and / or oxygen-doped silicon carbide nitride (Si(O)CN), or a high dielectric constant dielectric material (e.g., dielectric constant greater than about 7.9), such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or combinations thereof. In some embodiments, the dielectric isolation component 156 is deposited using techniques such as atomic layer deposition, chemical vapor deposition (such as high-density plasma chemical vapor deposition, low-pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition), other suitable techniques, or combinations thereof, followed by an etch-back process.

[0072] According to some embodiments, a source / drain component 158N is formed above a dielectric isolation component 156 in a source / drain recess 136N, as illustrated in Figure 5J-2. The epitaxial growth process can be molecular beam epitaxy, metal-organic chemical vapor deposition, or vapor phase epitaxy, other suitable techniques, or combinations thereof. In some embodiments, the source / drain component 158N is in-situ doped during the epitaxial process. In some embodiments, the source / drain component 158N is doped with an n-type dopant during the epitaxial growth process. For example, the n-type dopant can be phosphorus (P) or arsenic (As).

[0073] For example, the n-type source / drain component 158N can be epitaxially grown silicon-phosphorus (SiP), silicon-carbon (SiC), silicon-phosphorus-carbon (SiPC), silicon-phosphorus-arsenic (SiPAs), silicon-arsenic (SiAs), silicon (Si), or combinations of the above-mentioned doped phosphorus and / or arsenic. In some embodiments, the concentration of dopant (e.g., P) in the source / drain component 158N ranges from about 2 × 10¹⁹ cm⁻³ to about 3 × 10²¹ cm⁻³. In some embodiments, the n-type source / drain component 158N can be a multi-layer structure, for example, comprising sequentially formed film layers N1 and N2. In some embodiments, the dopant concentration in film layer N2 is greater than the dopant concentration in film layer N2, for example, on the order of 1-2.

[0074] In some embodiments, the n-type source / drain component 158N and the p-type source / drain component 158P are formed of different epitaxial materials. For example, the n-type source / drain component 158N is formed of SiP, and the p-type source / drain component 158P is formed of SiGe. According to some embodiments, the source / drain component 158N and the source / drain component 158P are formed on both sides of the dummy gate structure 124. In some embodiments, the source / drain component 158N has a different conductivity type than the source / drain component 158P.

[0075] In some embodiments, the source / drain components 158N and 158P can be formed separately. For example, a patterned masking layer (e.g., a photoresist layer and / or a hard masking layer) can be formed to cover the semiconductor structure 100_1 above the n-type well NW, and then the source / drain component 158N is grown. The patterned masking layer can then be removed. Similarly, a patterned masking layer (e.g., a photoresist layer and / or a hard masking layer) is formed to cover the semiconductor structure 100_1 above the p-type well PW, and then the source / drain component 158P is grown. The patterned masking layer can then be removed. According to some embodiments, once the source / drain component 158N and the source / drain component 158P are formed, an annealing process can be performed to activate the dopants in the source / drain component 158N and the source / drain component 158P.

[0076] According to some embodiments, a contact etch stop layer 160 is formed on the semiconductor structure 100_1 to cover the source / drain components 158N and 158P, as illustrated in Figures 5J-1 and 5J-2. In some embodiments, the contact etch stop layer 160 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped nitrogen-doped silicon carbide (Si(O)CN), or combinations thereof. In some embodiments, the dielectric material for the contact etch stop layer 160 is globally and compliantly deposited over the semiconductor structure 100_1 using chemical vapor deposition (such as low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, or high aspect ratio processes), atomic layer deposition, other suitable methods, or combinations thereof.

[0077] Subsequently, according to some embodiments, a first interlayer dielectric layer 162 is formed above the contact etch stop layer 160 to fill the space between the dummy gate structures 124, as illustrated in Figures 5J-1 and 5J-2. In some embodiments, the first interlayer dielectric layer 162 is formed of a dielectric material, such as un-doped silicate glass (USG), doped silica such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials.

[0078] In some embodiments, the first interlayer dielectric layer 162 and the contact etch stop layer 160 are formed of different materials and have significantly different etch selectivity. In some embodiments, the dielectric material for the first interlayer dielectric layer 162 is deposited using techniques such as chemical vapor deposition (e.g., high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), other suitable techniques, and / or combinations thereof. According to some embodiments, techniques such as chemical mechanical polishing are used to remove the dielectric material of the contact etch stop layer 160 and the first interlayer dielectric layer 162 located above the dummy gate electrode layer 128 until the top surface of the dummy gate electrode layer 128 is exposed.

[0079] Figures 5K-1, 5K-2, and 5K-3 illustrate, according to some embodiments, the semiconductor structure 100_1 after the formation of the patterned mask layer 164 and the first channel release process. According to some embodiments, the patterned mask layer 164 is formed to cover the active region 104P (or n-type well NW) and expose the active region 104N (or p-type well PW), as illustrated in Figures 5K-1 to 5K-3. The patterned mask layer 164 may be a patterned mask layer and / or a patterned photoresist layer. The method for forming the patterned mask layer 164 may be similar to the previously described method.

[0080] According to some embodiments, one or more etching processes are used to remove portions of the dummy gate structure 124 not covered by the patterned masking layer 164 to form a gate trench 166, as illustrated in Figure 5K-2. According to some embodiments, the gate trench 166 exposes the channel region of the active region 104N. In some embodiments, the gate trench 166 also exposes the sidewall of the gate spacer layer 130 facing the channel region. The etching process for removing the dummy gate structure 124 can be anisotropic etching processes, such as dry plasma etching, isotropic etching processes, such as dry chemical etching, distal plasma etching, or wet chemical etching, and / or combinations thereof.

[0081] According to some embodiments, an etching process is used to remove the dielectric layer 142I of the active region 104N to form a gap 168N. The inner spacer layer can serve as an etch stop layer in the etching process, protecting the source / drain components from damage. In some embodiments, the gap 168N also exposes the sidewall of the inner spacer layer 146A facing the channel region. The etching process used to remove the dielectric layer 142I can be an isotropic etching process, such as dry chemical etching, distal plasma etching, or wet chemical etching, and / or a combination thereof. In some embodiments, the etching process includes a diluted hydrogen fluoride (HF) solution. Subsequently, for example, an etching process, an ashing process, and / or a wet stripping process are used to remove the patterned mask layer 164.

[0082] In some embodiments, during the etching process that removes the dummy gate structure 124 and the dielectric layer 142I, the second bulk layer 122 and the isolation structure 110 are also etched. The fourth liner 120 and the second bulk layer 122 can reduce the loss of the isolation structure 110 during the etching process. In some other embodiments, the isolation structure 110 may be substantially unetched.

[0083] Figures 5L-1, 5L-2, and 5L-3 illustrate, according to some embodiments, the semiconductor structure 100_1 after the formation of the patterned mask layer 170 and the second channel release process. According to some embodiments, the patterned mask layer 170 is formed to cover the p-type well PW and expose the active region 104P (or the n-type well NW), as illustrated in Figures 5L-1 to 5L-3. The patterned mask layer 170 may be a patterned mask layer and / or a patterned photoresist layer. The method for forming the patterned mask layer 170 may be similar to the previously described method.

[0084] According to some embodiments, one or more etching processes are used to remove portions of the dummy gate structure 124 not covered by the patterned masking layer 170 to form a gate trench 166. According to some embodiments, the gate trench 166 exposes the channel region of the active region 104P. The etching process used to remove the dummy gate structure 124 can be anisotropic etching processes, such as dry plasma etching, isotropic etching processes, such as dry chemical etching, far-end plasma etching, or wet chemical etching, and / or combinations thereof.

[0085] According to some embodiments, an etching process is used to remove the first semiconductor layer 106 of the active region 104P to form a gap 168P. In some embodiments, the gap 168P also exposes the sidewall of the inner spacer layer 146B facing the channel region. The etching process for removing the first semiconductor layer 106 can be an isotropic etching process, such as dry chemical etching, distal plasma etching, or wet chemical etching, and / or a combination thereof. In some embodiments, the etching process includes an ammonium hydroxide-hydrogen peroxide-water mixture (APM) etching process. In some embodiments, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution. Subsequently, for example, an etching process, an ashing process, and / or a wet stripping process are used to remove the patterned mask layer 170.

[0086] According to some embodiments, after performing the first channel release process and the second channel release process, the main surface of the second semiconductor layer 108 is exposed. According to some embodiments, the exposed second semiconductor layer 108 of the active region 104N and the active region 104P is formed as multiple sets of nanostructures (second semiconductor layer 108), which serve as channel layers for the resulting semiconductor device (e.g., a nanostructured transistor such as a fully wound gate field-effect transistor).

[0087] According to some embodiments, since the etch selectivity between dielectric layer 142I (e.g., SiO) and second semiconductor layer 108 (e.g., Si) is much greater than the etch selectivity between first semiconductor layer 106 (e.g., SiGe) and second semiconductor layer 108 (Si), the loss (i.e., etch amount) of the second semiconductor layer 108 in the active region 104N in the first channel release process is less than the loss (i.e., etch amount) of the second semiconductor layer 108 in the active region 104P in the second channel release process.

[0088] Although Figures 5K-1 through 5L-3 illustrate that the first channel release process is performed before the second channel release process, embodiments of the method are not limited thereto. In some other embodiments, the first channel release process may be performed after the second channel release process. Furthermore, in some other embodiments, all dummy gate structures 124 may be completely removed in an etching process prior to the channel release process.

[0089] Figures 5M-1, 5M-2, and 5M-3 illustrate, according to some embodiments, the semiconductor structure 100_1 after forming the gate stack 172, etch stop layer 180, second interlayer dielectric layer 182, and contact plug 186. Figure 5M-4 is a planar schematic diagram corresponding to plane AA in Figure 5M-1. Plane AA cuts through the nanostructure (second semiconductor layer 108). Figure 5M-5 is a planar schematic diagram corresponding to plane BB in Figure 5M-1. Plane BB cuts through the lower fin element 103N and lower fin element 103P.

[0090] According to some embodiments, a final gate stack 172 (comprising gate stacks 172_1 to 172_4) is formed to fill the gate trench 166 and gaps 168N and 168P, thereby enclosing the nanostructure (second semiconductor layer 108), as illustrated in Figures 5M-1 to 5M-4. In some embodiments, the final gate stack 172 extends in the Y direction. That is, according to some embodiments, the final gate stack 172 has a longitudinal axis parallel to the Y direction. The final gate stack 172 engages the channel region, allowing current to flow between the source / drain regions during operation. In some embodiments, each of the final gate stack 172 includes an interface layer 174, a gate dielectric layer 176, and a metal gate electrode layer (including an n-type work function layer 178N, a p-type work function layer 178P, a metal capping layer 178C, and a metal filler layer 178F), as illustrated in Figures 5M-1 to 5M-4.

[0091] In some embodiments, the interface layer 174 is formed of chemically formed silicon oxide. In some embodiments, the interface layer 174 is formed using one or more cleaning processes, such as those comprising ozone (O3), a mixture of ammonium hydroxide-hydrogen peroxide-water, and / or a mixture of hydrochloric acid-hydrogen peroxide-water. According to some embodiments, semiconductor materials from the nanostructure (second semiconductor layer 108) and the lower fin elements 103N and 103P are oxidized to form the interface layer 174.

[0092] According to some embodiments, the gate dielectric layer 176 is compliantly formed along the interface layer 174, the upper surface of the isolation structure 110, the sidewalls of the gate spacer layer 130, and the sidewalls of the inner spacer layers 146A and 146B. The gate dielectric layer 176 is formed of a high dielectric constant dielectric layer. In some embodiments, the high dielectric constant dielectric layer is a dielectric material having a high dielectric constant (k value), such as greater than 7.9, like greater than 13. In some embodiments, the high dielectric constant dielectric layer comprises hafnium oxide (HfO 2), TiO 2, HfZrO, Ta 2O 3, HfSiO 4, ZrO 2, ZrSiO 2, LaO, Al 2O 3, ZrO, TiO, Ta 2O 5, Y 2O 3, SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Si 3N 4, oxides of nitride (SiON), combinations thereof, or other suitable materials. The high dielectric constant dielectric layer can be deposited using atomic layer deposition, physical vapor deposition, chemical vapor deposition, and / or other suitable techniques.

[0093] According to some embodiments, a metal gate electrode layer is formed to overfill the remaining portions of the gate trench 166 and gaps 168N and 168P. In some embodiments, the metal gate electrode layer is formed of more than one conductive material, such as a p-type work function layer 178P, an n-type work function layer 178N, a metal capping layer 178C, and a metal filler layer 178F, as illustrated in Figures 5M-1 to 5M-4. In some embodiments, the p-type work function layer 178P is formed on the gate dielectric layer 176 in an n-type well NW. In some embodiments, the n-type work function layer 178N is formed on the gate dielectric layer 176 in a p-type well PW and on the p-type work function layer 178P in an n-type well NW. In some embodiments, the p-type work function layer 178P and the n-type work function layer 178N have selected work functions to enhance the device performance (e.g., threshold voltage) of the n-channel or p-channel field-effect transistor. For example, the p-type work function layer 178P is formed of TiN, WN, WCN, TaN, Ru, Co, W, or other suitable p-type work function metals, and the n-type work function layer 178N is formed of Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaAl, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, or other suitable n-type work function metals.

[0094] According to some embodiments, a metal capping layer 178C is formed on an n-type work function layer 178N, and a metal filler layer 178F is formed on the metal capping layer 178C. The metal capping layer 178C protects the n-type work function layer 178N from oxidation and can be formed of silicon, titanium, or metal nitrides such as TiN or TSN (silicon-doped titanium nitride). The metal filler layer 178F can be formed of W, Co, or Ru. These gate electrode materials can be deposited using atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable techniques.

[0095] According to some embodiments, a planarization process such as chemical mechanical polishing can be performed on the semiconductor structure 100_1 to remove material from the gate dielectric layer 176 and the metal gate electrode layer formed above the first interlayer dielectric layer 162. The final gate stack 172 surrounding the nanostructure (second semiconductor layer 108) is combined with adjacent source / drain components 158N or source / drain components 158P to form a nanostructure transistor.

[0096] According to some embodiments, the transistors formed on the nanostructure (second semiconductor layer 108) in the p-type well PW (active region 104N) are n-channel nanostructure transistors, such as pull-down transistors PD-1 and PD-2, and gate transistors PG-1 and PG-2. According to some embodiments, the transistors formed on the nanostructure (second semiconductor layer 108) in the n-type well NW (active region 104P) are p-channel nanostructure transistors, such as pull-up transistors PU-1 and PU-2.

[0097] According to some embodiments, a gate dicing member 179 is formed in and / or through the final gate stack 172, gate spacer layer 130, first interlayer dielectric layer 162, and contact etch stop layer 160, as illustrated in Figure 5M-4. According to some embodiments, the gate stack 172 is diced by the gate dicing member 179 into several segments that are physically and electrically isolated from each other. The gate dicing member 179 may also be referred to as a cut metal gate (CMG) pattern. The gate dicing component 179 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), silicon oxycarbide (SiOCN), oxygen-doped silicon carbide (Si(O)CN), silicon oxide (SiO2), or a high-dielectric-constant dielectric material, such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or combinations thereof. The formation of the gate dicing component 179 includes patterning the semiconductor structure 100_1 using optical lithography and etching processes to form a gate dicing opening, depositing dielectric material to overfill the gate dicing opening, and planarizing the dielectric material using chemical mechanical polishing or etch-back processes.

[0098] According to some embodiments, an etch stop layer 180 and a second interlayer dielectric layer 182 are sequentially formed above a semiconductor structure 100_1, as illustrated in Figures 5M-1 to 5M-3. In some embodiments, the etch stop layer 180 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped nitrogen-doped silicon carbide (Si(O)CN), or combinations thereof. In some embodiments, the second interlayer dielectric layer 182 is formed of a dielectric material, such as undoped silicate glass (USG), borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. In some embodiments, the etch stop layer 180 and the second interlayer dielectric layer 182 are deposited using chemical vapor deposition (e.g., high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, high aspect ratio process, or flowable chemical vapor deposition), other suitable techniques, or a combination thereof.

[0099] According to some embodiments, a contact plug 186 is formed through a second interlayer dielectric layer 182, an etch stop layer 180, a first interlayer dielectric layer 162, and a contact etch stop layer 160, as illustrated in Figures 5M-1, 5M-2, and 5M-4. According to some embodiments, the contact plug 186 rests on a source / drain component 158N / source / drain component 158P. In some embodiments, the formation of the contact plug 186 includes patterning the semiconductor structure 100_1 using optical lithography and etching processes to form a contact opening until the source / drain component 158N / source / drain component 158P is exposed. Etching processes can include dry etching, such as reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, capacitively coupled plasma (CCP) etching, other suitable methods, or combinations thereof.

[0100] According to some embodiments, a silicon layer 188 is formed on the exposed surfaces of the source / drain components 158N and 158P. In some embodiments, the silicon layer 188 is formed of WSi, NiSi, TiSi, and / or CoSi. In some embodiments, the formation of the silicon layer 188 includes depositing a metal material, followed by one or more annealing processes. According to some embodiments, a semiconductor material (e.g., Si) from the source / drain components 158N and 158P reacts with a metal material to form the silicon layer 188. Unreacted metal material is then removed, for example, using wet etching.

[0101] According to some embodiments, the contact liner 190 is formed along the sidewall of the contact opening using a deposition process and an etch-back process. In some embodiments, the contact liner 190 is formed of an insulating material, such as a dielectric material (e.g., SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, SiN, HfSi, or SiO); or undoped silicon (Si). Then, according to some embodiments, one or more conductive materials for the contact plug 186 are deposited to overfill the contact opening. In some embodiments, chemical vapor deposition, physical vapor deposition, electron beam evaporation, atomic layer deposition, electrochemical plating (ECP), electroless deposition (ELD), other suitable methods, or combinations thereof are used to deposit one or more conductive materials to overfill the contact opening. One or more conductive materials above the second interlayer dielectric layer 182 are planarized using, for example, chemical mechanical polishing.

[0102] The contact plug 186 may have a multi-layer structure. For example, a barrier / adhesive layer (not shown) may optionally be deposited along the sidewalls and bottom surface of the contact opening. The barrier / adhesive layer may be formed of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt-tungsten (CoW), other suitable materials, or combinations thereof. A bulk metal layer is then deposited on the barrier / adhesive layer (if formed) to fill the remaining portion of the contact opening. In some embodiments, the bulk metal layer is formed of one or more conductive materials with low resistance and good gap-filling ability, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), other suitable metallic materials, or combinations thereof.

[0103] According to some embodiments, each nanostructure (second semiconductor layer 108) of gate transistor PG-1 and gate transistor PG-2, and pull-down transistors PD-1 and PD-2 includes a central portion 108C1 surrounded by gate stack 172 and an edge portion 108E1 surrounded by gate spacer layer 130, as illustrated in Figure 5M-4. In some embodiments, the central portion 108C1 has a width W1', and the edge portion 108E1 has a width W1. In some embodiments, the width W1 is greater than the width W1', for example, greater than the dimension D3 of about 0-2.5 nm, because the nanostructure (second semiconductor layer 108) is damaged during the first channel release process and during the formation of interface layer 174. In some other embodiments, the width W1 is equal to the width W1'. In some embodiments, the ratio of width W1 to width W1' (W1 / W1') ranges from about 1 to 1.05.

[0104] According to some embodiments, each nanostructure (second semiconductor layer 108) of pull-up crystal PU-1 and pull-up crystal PU-2 includes a central portion 108C2 surrounded by gate stack 172 and an edge portion 108E2 surrounded by gate spacer layer 130, as illustrated in Figure 5M-4. In some embodiments, the central portion 108C2 has a width W2', and the edge portion 108E2 has a width W2. In some embodiments, the width W2 is greater than the width W2', for example, greater than the dimension D4 of about 2-5 nm, because the nanostructure (second semiconductor layer 108) is damaged during the second channel release process and during the formation of interface layer 174. In some embodiments, the dimension D4 is greater than the dimension D3 because the etch selectivity between dielectric layer 142I and second semiconductor layer 108 is greater than the etch selectivity between first semiconductor layer 106 and second semiconductor layer 108. In some embodiments, the ratio of width W2 to width W2' (W2 / W2') ranges from about 1.05 to 1.5 and is greater than the ratio (W1 / W1'). In some embodiments, width W1' is greater than W2', for example, the ratio (W1' / W2') ranges from about 1.5 to about 10. In some embodiments, each nanostructure (second semiconductor layer 108) of pull-up crystal PU-1 and pull-up crystal PU-2 has a biconcave profile, as illustrated in Figure 5M-4.

[0105] According to embodiments disclosed herein, an n-channel nanostructure transistor (i.e., through a gate transistor and a pull-down transistor) is formed using a disposable oxide dielectric process prior to the formation of the source / drain components. Without increasing the cell height of the static random access memory (SRAM) cell, the n-channel nanostructure transistor can have a larger effective channel width (i.e., W1'), while preventing an increase in the risk of source / drain merging, and thus the saturation current ("Idsat") through the gate transistor and the pull-down transistor can be increased, for example, by 3-5%. Therefore, the performance (e.g., operating speed) of the resulting SRAM device can be enhanced by a 3-5% improvement in read current.

[0106] Figure 5N is a schematic diagram illustrating experimental results demonstrating the germanium distribution of the pull-up transistor PU according to some embodiments of this disclosure. The experimental results are analyzed and detected using energy-dispersive X-ray spectroscopy (EDX). When the semiconductor structure undergoes several thermal processes (e.g., source / source annealing and / or deposition processes), mixing of the first semiconductor layer 106 (e.g., SiGe) and the second semiconductor layer 108 (e.g., Si) may occur at the interface between them. Therefore, according to some embodiments of this disclosure, Ge residue may accumulate on the surface of the inner spacer layer 146B of the pull-up transistor PU, as illustrated in Figure 5N.

[0107] Because a disposable oxide dielectric process is used to fabricate the n-channel nanostructure transistor (i.e., through the gate transistor and pull-down transistor), the first semiconductor layer 106 is removed before the source / drain components are formed, resulting in less Ge residue buildup on the surfaces of the pull-up transistor PU and the inner spacer layer 146A through the gate transistor PG. Therefore, in some embodiments, the germanium concentration in the pull-down transistor PD and the inner spacer layer 146A through the gate transistor PG is less than the germanium concentration in the inner spacer layer 146B of the pull-up transistor PU.

[0108] Figure 50 is a schematic cross-sectional view of the nanostructure (second semiconductor layer 108) of the pull-up transistor PU and the pull-down transistor PD according to some embodiments of the present disclosure. According to some embodiments, since the etch selectivity between the dielectric layer 142I and the second semiconductor layer 108 is much greater than the etch selectivity between the first semiconductor layer 106 and the second semiconductor layer 108, the roughness of the main surface of the nanostructure (second semiconductor layer 108) of the pull-up transistor PU can be greater than the roughness of the main surface of the nanostructure (second semiconductor layer 108) of the pull-down transistor PD. For example, the distance R1 between the vertex and the bottom point of the top surface of the nanostructure (second semiconductor layer 108) of the pull-up transistor PU is greater than the distance R2 between the vertex and the bottom point of the top surface of the nanostructure (second semiconductor layer 108) of the pull-down transistor PD. Furthermore, in some embodiments, the nanostructure (second semiconductor layer 108) of the pull-up transistor PU has rounded corners C1 between adjacent main surfaces, while the nanostructure (second semiconductor layer 108) of the pull-down transistor PD has sharp corners C2 between adjacent main surfaces. Although not shown, the nanostructure (second semiconductor layer 108) of the gate transistor PG can have low roughness and sharp-cornered main surfaces.

[0109] The semiconductor structure 100_1 may undergo further back end of line (BEOL) processes to form various interconnect conductive components (not shown) on the semiconductor structure 100_1, such as metal layers and vias between two adjacent metal layers.

[0110] Figures 6A-1 to 6F-2 are schematic cross-sectional views illustrating the formation of the semiconductor structure 100_2 of the static random access memory cell at various intermediate stages, according to some embodiments. The embodiments in Figures 6A-1 to 6F-2 are similar to those in Figures 5A-1 to 5M-3, but differ in that the formation of the gate transistor PG does not involve a disposable oxide intermediate process. According to some embodiments, Figures 6A-1, 6C-1, 6D-1, 6E-1, and 6F-1 correspond to cross-sections X1-X1, and Figures 6A-2, 6B, 6C-2, 6D-2, 6E-2, and 6F-2 correspond to cross-sections X2-X2.

[0111] Figures 6A-1 and 6A-2 illustrate, according to some embodiments, the semiconductor structure 100_2 after the removal of the first semiconductor layer 106. According to some embodiments, continuing from Figures 5B-1 to 5B-3, forming a patterned masking layer 138 to cover the active region 104P (or n-type well NW) and the active region 104N (or p-type well PW) will form a first portion through the gate transistor PG, as illustrated in Figures 6A-1 and 6A-2. According to some embodiments, exposing the active region 104N (or p-type well PW) with the patterned masking layer 138 will form a second portion of the pull-down transistor PD. According to some embodiments, an etching process is performed using the patterned masking layer 138 to remove the first semiconductor layer 106 of the second portion of the active region 104N, thereby forming a gap 140.

[0112] Figure 6B illustrates, according to some embodiments, the semiconductor structure 100_2 after the first semiconductor layer 106 is replaced with a dielectric layer 142I and an inner spacer layer 146A is formed. According to some embodiments, the steps described above in Figures 5D to 5F are performed to form the dielectric layer 142I in the gap 140 and to form the inner spacer layer 146A, as illustrated in Figure 6B. According to some embodiments, the patterned mask layer 138 is then removed.

[0113] Figures 6C-1 and 6C-2 illustrate, according to some embodiments, the semiconductor structure 100_2 after the formation of the inner spacer layer 146B. According to some embodiments, a patterned masking layer (not shown) is formed to cover the second portion of the active region 104N (or p-well PW) to which the pull-down transistor PD will be formed. According to some embodiments, the patterned masking layer exposes the active region 104P (or n-well NW) and the first portion of the active region 104N (or p-well PW) to which the gate transistor PG will be formed. According to some embodiments, the steps described above in Figures 5H to 5I are performed to form the inner spacer layer 146B, as illustrated in Figures 6C-1 and 6C-2. According to some embodiments, the patterned masking layer is then removed.

[0114] Figures 6D-1 and 6D-2 illustrate, according to some embodiments, the semiconductor structure 100_2 after the first channel release process. According to some embodiments, the steps described above in Figures 5J-1 and 5J-2 are performed to form source / drain components 158N and source / drain components 158P, a contact etch stop layer 160, and a first interlayer dielectric layer 162, as illustrated in Figures 6D-1 and 6D-2.

[0115] According to some embodiments, a patterned masking layer 164 is formed to cover the active region 104P (or n-well NW) and the active region 104N (or p-well PW) to form a first portion of the gate transistor PG, as illustrated in Figures 6D-1 and 6D-2. According to some embodiments, the patterned masking layer 164 exposes the active region 104N (or p-well PW) to form a second portion of the pull-down transistor PD.

[0116] According to some embodiments, one or more etching processes are used to remove portions of the dummy gate structure 124 not covered by the patterned masking layer 164 to form a gate trench 166. According to some embodiments, an etching process is used to remove the dielectric layer 142I of the second portion of the active region 104N to form a gap 168N. Then, according to some embodiments, the patterned masking layer 164 is removed.

[0117] Figures 6F-1 and 6F-2 illustrate, according to some embodiments, the semiconductor structure 100_2 after the second channel release process. According to some embodiments, a patterned mask layer (not shown) is formed to cover a second portion of the active region 104N. According to some embodiments, the patterned mask layer exposes a first portion of the active region 104P (or n-type well NW) and the active region 104N (or p-type well PW).

[0118] According to some embodiments, one or more etching processes are used to remove portions of the dummy gate structure 124 not covered by the patterned masking layer to form a gate trench 166. According to some embodiments, an etching process is used to remove the first semiconductor layer 106 of the active region 104P and a first portion of the first semiconductor layer 106 of the active region 104N to form gaps 168P and 168N. Subsequently, according to some embodiments, the patterned masking layer is removed.

[0119] Figures 6F-1 and 6F-2 illustrate, according to some embodiments, the semiconductor structure 100_2 after forming the gate stack 172, etch stop layer 180, second interlayer dielectric layer 182, and contact plug 186. Figure 6F-3 is a planar schematic diagram corresponding to plane AA of Figure 6F-1. According to some embodiments, the steps described above in Figures 5M-1 to 5M-3 are performed to form the final gate stack 172 (comprising gate stacks 172_1 to 172_4), gate dicing member 179, etch stop layer 180, second interlayer dielectric layer 182, and contact plug 186, as illustrated in Figures 6F-1 and 6F-2.

[0120] According to some embodiments, each nanostructure (second semiconductor layer 108) of gate transistor PG-1 and gate transistor PG-2 includes a central portion 108C3 surrounded by gate stack 172 and an edge portion 108E3 surrounded by gate spacer layer 130, as illustrated in Figures 6F-3. In some embodiments, the central portion 108C3 has a width W1'', and the edge portion 108E3 has a width W1. In some embodiments, the width W1 is greater than the width W1'', for example, greater than the dimension D5 of about 2-5 nm, because the nanostructure (second semiconductor layer 108) is damaged during the second channel release process and during the formation of interface layer 174. In some embodiments, the dimension D5 is greater than the dimension D3. In some embodiments, the width W1' is greater than the width W1''. In some embodiments, the ratio of width W1 to width W1'' (W1 / W1'') ranges from about 1.05 to 1.5, and is greater than the ratio (W1 / W1'). In some embodiments, each nanostructure (second semiconductor layer 108) of the gate transistor PG-1 and the gate transistor PG-2 has a biconcave profile.

[0121] According to embodiments disclosed herein, a disposable oxide dielectric process is used to form the pull-down transistor before forming the source / drain components. Without increasing the cell height of the static random access memory (SRAM) cell, the pull-down transistor can have a larger effective channel width (i.e., W1') while preventing an increase in the risk of source / drain merging. Therefore, the performance (e.g., operating speed) of the resulting SRAM device can be enhanced by a 3-5% improvement in read current. Furthermore, the formation of the gate transistor PG does not involve a disposable oxide dielectric process. The effective channel width (W1') of the pull-down transistor PD is greater than the effective channel width (W1'') of the gate transistor PG, and therefore the "beta ratio" of the saturation current ("Idsat"), i.e., the ratio of Idsat of the pull-down transistor PD to Idsat of the gate transistor PG, can be increased to, for example, greater than 1. This can enhance the cell performance of the resulting static random access memory (SRAM) cell, for example, improving the operating voltage (e.g., Vmax) by about 50-80 mV. Furthermore, the gate transistor PG can have lower parasitic capacitance, which can prevent AC performance degradation. Therefore, the speed of the resulting SRAM cell can be further enhanced.

[0122] Figures 7A-1 to 7D-2 are schematic cross-sectional views illustrating the formation of the semiconductor structure 100_3 of the static random access memory cell at various intermediate stages, according to some embodiments. The embodiments in Figures 7A-1 to 7D-2 are similar to the embodiments in Figures 5A-1 to 5M-3, but differ in that a polishable oxide intermediate process is also applied to form the pull-up transistor PU. According to some embodiments, Figures 7A-1, 7B-1, 7C-1, and 7D-1 correspond to section lines X1-X1, and Figures 7A-2, 7B-2, 7C-2, and 7D-2 correspond to section lines X2-X2.

[0123] Figures 7A-1 and 7A-2 illustrate, according to some embodiments, the semiconductor structure 100_3 after the removal of the first semiconductor layer 106. According to some embodiments, following Figures 5B-1 to 5B-3, an etching process is performed to remove the first semiconductor layer 106 of the active regions 104N and 104P, thereby forming a gap 140, as illustrated in Figures 7A-1 and 7A-2.

[0124] Figures 7B-1 and 7B-2 illustrate, according to some embodiments, a semiconductor structure 100_3 after the first semiconductor layer 106 is replaced with a dielectric layer 142I and an inner spacer layer 146A is formed. According to some embodiments, the steps described above in Figures 5D to 5F are performed to form a dielectric layer 142I in the gap 140 and to form an inner spacer layer 146A, as illustrated in Figures 7B-1 and 7B-2.

[0125] Figures 7C-1 and 7C-2 illustrate, according to some embodiments, the semiconductor structure 100_3 after the first channel release process. According to some embodiments, the steps described above in Figures 5J-1 and 5J-2 are performed to form source / drain components 158N and 158P, a contact etch stop layer 160, and a first interlayer dielectric layer 162, as illustrated in Figures 7C-1 and 7C-2. According to some embodiments, a dummy gate structure 124 is removed using one or more etch processes to form a gate trench 166. According to some embodiments, an etch process is used to remove the dielectric layer 142I of the active regions 104N and 104P to form gaps 168N and 168P.

[0126] Figures 7D-1 and 7D-2 illustrate, according to some embodiments, the semiconductor structure 100_3 after the formation of gate stack 172, etch stop layer 180, second interlayer dielectric layer 182, and contact plug 186. Figure 7D-3 is a planar schematic diagram corresponding to plane AA of Figure 7D-1. According to some embodiments, after the first channel release process, the steps described above in Figures 5M-1 to 5M-3 are performed to form the final gate stack 172 (comprising gate stacks 172_1 to 172_4), gate dicing member 179, etch stop layer 180, second interlayer dielectric layer 182, and contact plug 186, as illustrated in Figures 7D-1 and 7D-2.

[0127] According to some embodiments, each nanostructure (second semiconductor layer 108) of pull-up crystal PU-1 and pull-up crystal PU-2 includes a central portion 108C2 surrounded by gate stack 172 and an edge portion 108E2 surrounded by gate spacer layer 130, as illustrated in Figures 7D-3. In some embodiments, the central portion 108C2 has a width W2'', and the edge portion 108E2 has a width W2. In some embodiments, the width W2 is greater than the width W2'', for example, greater than the dimension D6 of about 0-2.5 nm, because the nanostructure (second semiconductor layer 108) is damaged during the first channel release process and during the formation of interface layer 174. In some other embodiments, the width W2 is equal to the width W2''. In some embodiments, the ratio of width W2 to width W2'' (W2 / W2'') ranges from about 1 to 1.05. In some embodiments, the ratio (W2 / W2'') may be substantially equal to the ratio (W1 / W1').

[0128] According to embodiments disclosed herein, a disposable oxide dielectric process is applied to the formation of n-channel nanostructured transistors (i.e., through-gate transistors and pull-down transistors) and p-channel nanostructured transistors (i.e., pull-down transistors) before forming the source / drain components. Without increasing the cell height of the static random access memory (SRAM) cells, both the n-channel and p-channel nanostructured transistors can have larger effective channel widths (i.e., W1' and W2''), while preventing an increase in the risk of source / drain coalescence. Therefore, the saturation current of the through-gate transistor and pull-down transistor can be increased, for example, by 3-5%, and the saturation current of the pull-up transistor can be increased, for example, by 15-25%. Thus, the performance (e.g., operating speed) of the resulting SRAM device can be enhanced. Furthermore, because the patterning process of the selectively disposable oxide dielectric process is omitted, the manufacturing cost of the resulting SRAM device can be reduced.

[0129] As described above, this disclosure relates to the semiconductor structure of a static random access memory (SRAM) device comprising a nanostructured transistor. The method includes a disposable oxide dielectric process, wherein the first semiconductor layer 106 of the active region is replaced with a dielectric layer 142I. Due to the relatively high etch selectivity between the dielectric layer 142I and the second semiconductor layer 108, the resulting transistor can have a larger effective channel width. In some embodiments, the formation of the n-channel transistor (pull-down transistor PD and through-gate transistor PG) includes a disposable oxide dielectric process, thus enhancing the performance (e.g., operating speed) of the resulting SRAM device.

[0130] In other embodiments, the formation of the pull-down transistor PD includes a disposable oxide dielectric process, but the through-gate transistor PG does not, and therefore the beta ratio of the saturation current can be increased, which can enhance the performance (e.g., Vmax) of the resulting static random access memory device. In still other embodiments, the formation of both the n-channel and p-channel transistors (pull-down transistor PD, pull-up transistor PU, and through-gate transistor PG) includes a disposable oxide dielectric process, thus enhancing the performance (e.g., operating speed) of the resulting static random access memory device.

[0131] Embodiments of semiconductor structures and methods for forming them can be provided. The method for forming the semiconductor structure may include forming an active region in a static random access memory (SRAM) cell region, replacing the first semiconductor layer of the active region with a dielectric layer, removing the dielectric layer to form a channel layer, and forming a gate stack around the channel layer. Replacing the first semiconductor layer with a dielectric layer can reduce the loss of the channel layer. Therefore, the performance of the resulting SRAM device can be enhanced.

[0132] In some embodiments, a method for forming a semiconductor structure is provided, including forming a first active region and a second active region, wherein each of the first active region and the second active region includes a plurality of alternately stacked first semiconductor layers and a plurality of second semiconductor layers. The method includes replacing the first semiconductor layers of the second active region with a plurality of dielectric layers, removing the dielectric layers to form a plurality of first gaps, removing the first semiconductor layers of the first active region to form a plurality of second gaps, and forming a first gate stack to fill the first gaps and second gaps.

[0133] In some embodiments, a first gate stack surrounds a second semiconductor layer of a first active region to form a pull-up transistor, and a first gate stack surrounds a second semiconductor layer of a second active region to form a pull-down transistor. In some embodiments, the step of replacing the first semiconductor layer of the second active region with a dielectric layer further includes forming a patterned mask layer to cover the first active region, removing the first semiconductor layer of the second active region to form a plurality of third gaps, depositing dielectric material to fill the third gaps, removing the dielectric material outside the third gaps, and removing the patterned mask layer. In some embodiments, the patterned mask layer further covers a first portion of the second active region while exposing a second portion of the second active region, and removes the first semiconductor layer of the second portion of the second active region to form the third gaps while retaining the first semiconductor layer of the first portion of the second active region. In some embodiments, the method further includes removing the first semiconductor layer of the first portion of the second active region to form a plurality of fourth gaps, and forming a second gate stack to fill the fourth gaps. In some embodiments, the method further includes forming a dummy gate structure above the first and second active regions, forming a gate spacer layer beside the dummy gate structure, and removing the dummy gate structure after replacing the first semiconductor layer of the second active region with the dielectric layer. In some embodiments, the first and second active regions are formed in a static random access memory cell region. In some embodiments, the method further includes forming an isolation structure around the first and second active regions, wherein the isolation structure includes a liner along the first and second active regions, a first bulk layer nested within the liner, and a second bulk layer located above the first bulk layer and the liner, the second bulk layer being formed of a material different from the first bulk layer.

[0134] In some embodiments, a method for forming a semiconductor structure is provided, comprising forming a first active region and a second active region, wherein the first active region comprises a plurality of alternately stacked first semiconductor layers and a plurality of alternately stacked second semiconductor layers, and the second active region comprises a plurality of alternately stacked dielectric layers and second semiconductor layers. The method further comprises removing the dielectric layers of the second active region while etching the second semiconductor layers of the second active region with a first etch amount. The method further comprises removing the first semiconductor layers of the first active region while etching the second semiconductor layers of the first active region with a second etch amount, wherein the second etch amount is greater than the first etch amount. The method further comprises forming a gate stack to surround the second semiconductor layers of the first active region and the second semiconductor layers of the second active region.

[0135] In some embodiments, the method further includes laterally etching the dielectric layer of the second active region to form a plurality of first notches, forming a plurality of first inner spacer layers in the first notches, laterally etching the first semiconductor layer of the first active region to form a plurality of second notches, and forming a plurality of second inner spacer layers in the second notches. In some embodiments, the germanium concentration of the first inner spacer layers is less than the germanium concentration of the second inner spacer layers. In some embodiments, in the vertical direction, the size of the second inner spacer layers is larger than the size of the first inner spacer layers. In some embodiments, the first active region is formed in an n-type well of the substrate, and the second active region is formed in a p-type well of the substrate.

[0136] In some embodiments, a semiconductor structure is provided, comprising a first transistor in a cell region and including a plurality of first nanostructures and a first gate stack; a second transistor in the cell region and including a plurality of second nanostructures and a first gate stack; and a gate spacer layer along the first gate stack. The first gate stack extends in a first horizontal direction. Each of the first nanostructures includes a plurality of central portions surrounded by the first gate stack and having a first width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the gate spacer layer and having a second width in the first horizontal direction. Each of the second nanostructures includes a plurality of central portions surrounded by the first gate stack and having a third width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the gate spacer layer and having a fourth width in the first horizontal direction. A first ratio of the second width to the first width is less than a second ratio of the fourth width to the third width.

[0137] In some embodiments, the semiconductor structure further includes a third transistor, a plurality of third nanostructures and a second gate stack, and a second gate spacer layer, located in the cell region and extending along the second gate stack, wherein the second gate stack extends in a first horizontal direction, each of the third nanostructures includes a plurality of central portions surrounded by the second gate stack and having a fifth width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the second gate spacer layer and having a sixth width in the first horizontal direction, wherein the third ratio of the sixth width to the fifth width is less than a second ratio. In some embodiments, the semiconductor structure further includes a first lower fin element extending in a second horizontal direction below the first transistor and the third transistor, wherein the second horizontal direction is perpendicular to the first horizontal direction, and a second lower fin element extending in the second horizontal direction below the second transistor. In some embodiments, the first transistor is a pull-down transistor, and the second transistor is a pull-up transistor. In some embodiments, the semiconductor structure further includes a third transistor, a plurality of third nanostructures and a second gate stack within a cell region, and a second gate spacer layer along the second gate stack, wherein the second gate stack extends in a first horizontal direction, each of the third nanostructures includes a plurality of central portions surrounded by the second gate stack and having a fifth width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the second gate spacer layer and having a sixth width in the first horizontal direction, wherein a third ratio of the sixth width to the fifth width is greater than a first ratio. In some embodiments, the semiconductor structure further includes a plurality of first inner spacer layers between the first nanostructures and directly below the gate spacer layers, and a plurality of second inner spacer layers between the second nanostructures and directly below the gate spacer layers, wherein a first germanium concentration of the first inner spacer layers is less than a second germanium concentration of the second inner spacer layers. In some embodiments, in the vertical direction, a first dimension of the first inner spacer layer is smaller than a second dimension of the second inner spacer layer.

[0138] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0139] 10: Static Random Access Memory (SRAM) units 10_1: Static Random Access Memory (SRAM) unit 10_2: Static Random Access Memory (SRAM) unit 20A: Connection Unit 20B: Edge Unit 30: Static Random Access Memory 100: Semiconductor Structure 100_1: Semiconductor Structure 100_2: Semiconductor Structure 100_3: Semiconductor Structure 102: Substrate 103N: Lower fin element 103P: Lower fin element 104: Active Zone 104N: Active region 104N_1, 104N_2: Active region 104P: Active Zone 104P_1, 104P_2: Active region 106: First semiconductor layer 108: Second semiconductor layer 108C1, 108C2, 108C3: Central part 108E1, 108E2, 108E3: Edge regions 110: Isolation Structure 112: First Liner 114: Second Liner 116: Third Liner 118: First body layer 120: Fourth Liner 122: Second body layer 124: Virtual Gate Structure 124_1, 124_2, 124_3, 124_4: Virtual gate structure 126: Dummy gate dielectric layer 128: Dummy gate electrode layer 130: Gate spacer layer 132: Spacer layer 134: Spacer layer 136N: Source / Drain Groove 136P: Source / Drain Groove 138: Patterned mask layer 140: Gap 142: Dielectric Materials 142I: Dielectric layer 144: Gap 146A: Inner spacer layer 146A1: Top surface 146A2: Bottom surface 146B: Inner spacer layer 146B1: Top surface 146B2: Bottom surface 148: Patterned mask layer 150: Gap 154: Semiconductor isolation components 156: Dielectric isolation components 158N: Source / Drain Components 158P: Source / Drain Components 160: Contact Etching Stop Layer 162: First interlayer dielectric layer 164: Patterned Mask Layer 166: Gate trench 168N: Clearance 168P: Gap 170: Patterned mask layer 172: Gate Stacking 172_1, 172_2, 172_3, 172_4: Gate Stacking 174: Interface Layer 176: Gate Dielectric Layer 178C: Metal capping layer 178F: Metal filler layer 178N: n-type work function layer 178P: p-type work function layer 179: Gate cutting component 180: Etching stop layer 182: Second interlayer dielectric layer 186: Contact plug 186_1, 186_2, 186_3, 186_4: Contact plugs 186_5, 186_6, 186_7, 186_8: Contact plugs 188: Silicon layer 190: Contact element liner AA: Plane BB: Plane BL: Bitline BLB: Complementary Bit Line C1: Rounded corners C2: Sharp corner D1: Dimensions D2: Size D3: Size D4: Dimensions D5: Size D6: Size GP: Group Inverter-1: Inverter Inverter-2: Inverter N1: Membrane layer N2: membrane layer NW: n-type well P1: Membrane layer P2: Membrane layer P3: Membrane PW: p-type well PD: Pull-down transistor PD-1: Pull-down transistor PD-2: Pull-down transistor PU: Pull-up transistor PU-1: Pull-up transistor PU-2: Pull-up transistor PG: Through gate transistor PG-1: Through gate transistor PG-2: Through gate transistor R1: Distance R2: Distance SN1: Storage Node SN2: Storage Node VDD: Power supply node VSS: Grounding W1, W1', W1'': Width W2, W2', W2'': Width WL: Character Line X: Direction X1-X1: Section X2-X2: Section Y: direction YY: Cross-section Z: Direction

Claims

1. A method for forming a semiconductor structure, comprising: Forming a first active region and a second active region, each of the first active region and the second active region comprising alternating stacked plurality of first semiconductor layers and plurality of second semiconductor layers; replacing the first semiconductor layers of the second active region with plurality of dielectric layers; removing the dielectric layers to form plurality of first gaps; removing the first semiconductor layers of the first active region to form plurality of second gaps; and forming a first gate stack to fill the first gaps and the second gaps, wherein the width of a plurality of edge portions of the second semiconductor layers in the second active region is a first ratio to the width of a plurality of center portions, and the width of a plurality of edge portions of the second semiconductor layers in the first active region is a second ratio to the width of a plurality of center portions, and the first ratio is less than the second ratio.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein the first gate stack surrounds the second semiconductor layers of the first active region to form a pull-up transistor, and the first gate stack surrounds the second semiconductor layers of the second active region to form a pull-down transistor.

3. The method of forming a semiconductor structure as described in claim 1 or claim 2, wherein the step of replacing the first semiconductor layers of the second active region with the dielectric layers further comprises: A patterned mask layer is formed to cover the first active area; Remove the first semiconductor layers of the second active region to form a plurality of third gaps; Deposit a dielectric material to fill the third gaps; remove the dielectric material outside the third gaps; And remove the patterned mask layer.

4. The method for forming a semiconductor structure as described in claim 3 further includes: Remove the first semiconductor layers of the first portion of the second active region to form a plurality of fourth gaps; And forming a second gate stack to fill the fourth gaps, wherein: the patterned mask layer further covers a first portion of the second active region while exposing a second portion of the second active region, and the first semiconductor layers of the second portion of the second active region are removed to form the third gaps, while retaining the first semiconductor layers of the first portion of the second active region, wherein the first active region and the second active region are formed in a static random access memory (SRAM) cell area.

5. The method for forming a semiconductor structure as described in claim 1 further includes: Before replacing the first semiconductor layers of the second active region with the dielectric layers, a dummy gate structure is formed above the first active region and the second active region; a gate spacer layer is formed next to the dummy gate structure; and after replacing the first semiconductor layers of the second active region with the dielectric layers, the dummy gate structure is removed.

6. The method for forming a semiconductor structure as described in claim 1 further includes: An isolation structure is formed to surround the first active region and the second active region, wherein the isolation structure includes a liner along the first active region and the second active region, a first bulk layer nested within the liner, and a second bulk layer located above the first bulk layer and the liner, the second bulk layer being formed of a material different from the first bulk layer.

7. A method for forming a semiconductor structure, comprising: Forming a first active region and a second active region, wherein the first active region includes a plurality of alternately stacked first semiconductor layers and a plurality of alternately stacked second semiconductor layers, and the second active region includes a plurality of alternately stacked dielectric layers and the second semiconductor layers; removing the dielectric layers of the second active region while etching the second semiconductor layers of the second active region with a first etch amount; removing the first semiconductor layers of the first active region while etching the second semiconductor layers of the first active region with a second etch amount, wherein the second etch amount is greater than the first etch amount; and forming a gate stack to surround the second semiconductor layers of the first active region and the second semiconductor layers of the second active region, wherein the width of a plurality of edge portions of the second semiconductor layers in the second active region is in a first ratio to the width of a plurality of center portions, wherein the width of a plurality of edge portions of the second semiconductor layers in the first active region is in a second ratio to the width of a plurality of center portions, and the first ratio is less than the second ratio.

8. The method for forming a semiconductor structure as described in claim 7 further includes: The dielectric layers of the second active region are etched laterally to form a plurality of first notches. A plurality of first inner spacer layers are formed in the first gaps; the first semiconductor layers of the first active region are laterally etched to form a plurality of second gaps; and a plurality of second inner spacer layers are formed in the second gaps.

9. A method for forming a semiconductor structure as described in claim 8, wherein the germanium concentration of the first inner spacer layers is less than the germanium concentration of the second inner spacer layers.

10. A method of forming a semiconductor structure as claimed in claim 8, wherein, in a vertical direction, the dimensions of the second inner spacer layers are larger than the dimensions of the first inner spacer layers.

11. A semiconductor structure, comprising: A first transistor, located in a unit region and including multiple first nanostructures and a first gate stack; A second transistor, located in the cell region and including a plurality of second nanostructures and the first gate stack; and a gate spacer layer, along the first gate stack, wherein: the first gate stack extends in a first horizontal direction; each of the first nanostructures includes a plurality of central portions surrounded by the first gate stack and having a first width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the gate spacer layer and having a second width in the first horizontal direction; each of the second nanostructures includes a plurality of central portions surrounded by the first gate stack and having a third width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the gate spacer layer and having a fourth width in the first horizontal direction, and the second width is in a first proportion to the first width less than the fourth width is in a second proportion to the third width.

12. The semiconductor structure as described in claim 11, further comprising: A third transistor is located in the cell region and includes multiple third nanostructures and a second gate stack; a second gate spacer layer is stacked along the second gate; a first lower fin element extends below the first transistor and the third transistor in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction; And a second lower fin element extending below the second transistor in the second horizontal direction, wherein: the second gate stack extends in the first horizontal direction, each of the third nanostructures includes a plurality of central portions surrounded by the second gate stack and having a fifth width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the second gate spacer layer and having a sixth width in the first horizontal direction, and the sixth width is a third ratio of the fifth width to the second ratio.

13. The semiconductor structure as claimed in claim 11, wherein the first transistor is a pull-down transistor and the second transistor is a pull-up transistor.

14. The semiconductor structure as described in claim 11, further comprising: A third transistor, located in the unit region, includes multiple third nanostructures and a second gate stack; And a second gate spacer layer, stacked along the second gate, wherein: the second gate stack extends in the first horizontal direction, each of the third nanostructures includes a plurality of central portions surrounded by the second gate stack and having a fifth width in the first horizontal direction, and each includes a plurality of edge portions surrounded by the second gate spacer layer and having a sixth width in the first horizontal direction, and the sixth width is in a third proportion to the fifth width that is greater than the first proportion.

15. The semiconductor structure as described in claim 11, further comprising: Multiple first inner spacer layers are located between the first nanostructures and directly below the gate spacer layer; And a plurality of second inner spacer layers, between the second nanostructures and directly below the gate spacer layer, wherein a first germanium concentration of the first inner spacer layers is less than a second germanium concentration of the second inner spacer layers, wherein in a vertical direction a first dimension of the first inner spacer layers is less than a second dimension of the second inner spacer layers.

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