Methods for making semiconductor transistor devices with recessed superlattice over well regions

Abstract

A method for manufacturing a semiconductor device may include forming spaced shallow trench isolation (STI) regions in a semiconductor layer, etching a first portion of the semiconductor layer between adjacent STI regions to an etch depth, and performing a well implantation in the first portions of the semiconductor layer. The method may further include forming corresponding superlattices on the first portions of the semiconductor layer between adjacent STI regions, such that their height is no greater than the etch depth. The method may also include forming corresponding spaced source and drain regions for each superlattice; and forming a corresponding gate above each superlattice.

Description

Method for manufacturing a semiconductor transistor device having a recessed superlattice above a well region The present disclosure relates generally to semiconductor devices, and more particularly to methods for fabricating semiconductor devices using enhanced semiconductor materials. Many structures and techniques have been proposed to improve semiconductor device performance by, for example, enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon, which also include impurity-free zones that would otherwise degrade performance. The biaxial strain created by these strained material layers in the upper silicon layer alters carrier mobility, thereby enabling the fabrication of higher-speed and / or lower-power devices. U.S. Patent Application Publication No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on similar strained silicon technology. U.S. Patent No. 6,472,685 B2 issued to Takagi discloses a semiconductor device comprising a silicon and carbon layer sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. This allows electrons with a smaller effective mass, induced by an electric field applied to the gate, to be confined within the second silicon layer, resulting in an N-type channel MOSFET having higher mobility. U.S. Patent No. 4,937,204 issued to Ishibashi et al. discloses a superlattice comprising a plurality of layers, each comprising fewer than eight monolayers and containing fractional or binary semiconductor layers or a binary compound semiconductor layer, grown alternately by epitaxial growth, wherein the primary current flow direction is perpendicular to the layers of the superlattice. U.S. Patent No. 5,357,119 issued to Wang et al. discloses a silicon-germanium short-period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on similar principles, U.S. Patent No. 5,683,934 issued to Candelaria discloses a MOSFET with improved mobility, which includes a channel layer comprising an alloy of silicon and a second material, the second material being present in the silicon lattice at a percentage that places the channel layer under tensile stress. U.S. Patent No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions sandwiched by an epitaxially grown semiconductor layer. Each barrier region is composed of alternating SiO2 / Si monolayers with a thickness ranging from two to six. A much thicker silicon segment is sandwiched between the barrier regions. In an article titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in Applied Physics and Materials Science & Processing, pp. 391–402, Tsu describes a semiconductor-atomic superlattice (SAS) of silicon and oxygen. This silicon / oxygen superlattice structure is described as useful for silicon quantum dot and light-emitting devices. Specifically, the article describes how to fabricate and test a green electroluminescence diode structure. The current flow in the diode structure is perpendicular to the SAS layer. The SAS described in the article can include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. Silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One SAS structure contained a 1.1 nm thick silicon portion, equivalent to about eight atomic layers of silicon, while the other structure had a silicon portion twice as thick. Luo et al. further discussed Tsu's light-emitting SAS structure in an article titled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002). U.S. Patent No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen that can reduce the vertical current flowing through the lattice by more than four orders of magnitude. The insulating / barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer. Published UK patent application No. 2,347,520 by Mears et al. discloses that aperiodic photonic band-gap (APBG) structures can be used in electronic bandgap engineering. Specifically, the application discloses that material parameters, such as the position of the band minimum and effective mass, can be tuned to produce new aperiodic materials with desired band structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric permittivity or magnetic permeability, are also potentially engineered into the material. Additionally, U.S. Patent No. 6,376,337 issued to Wang et al. discloses a method for forming an insulating or barrier layer for a semiconductor device. The method comprises depositing a layer of silicon and at least one other element on a silicon substrate, such that the deposited layer is substantially defect-free, thereby enabling the deposition of substantially defect-free epitaxial silicon on the deposited layer. Alternatively, a single layer of one or more elements, preferably including oxygen, is absorbed on the silicon substrate. Multiple insulating layers are sandwiched between the epitaxial silicon to form a barrier composite. Although the above methods exist, it is desirable to further enhance the use of advanced semiconductor materials and processing technologies in order to achieve improved performance of semiconductor devices. A method for fabricating a semiconductor device may include forming separated shallow trench isolation (STI) regions in a semiconductor layer, etching a first portion of the semiconductor layer between adjacent STI regions to an etch depth, and performing a well implant in the first portions of the semiconductor layer. The method may further include forming corresponding superlattices on the first portions of the semiconductor layer between adjacent STI regions, with a height no greater than the etch depth. Each superlattice may include a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent base semiconductor portion. The method may also include forming corresponding separated source and drain regions for each superlattice, and forming a corresponding gate above each superlattice. In one exemplary embodiment, each superlattice may define a channel region between its source and drain regions. In some embodiments, the method may further include forming a mask over at least some of the STI regions and the second portion of the semiconductor layer prior to etching. The method may also include forming corresponding first oxide portions over the superlattices and forming corresponding second oxide portions over the second portions of the semiconductor layer, the second oxide portions being thicker than the first oxide portions. For example, the etching depth may be 60 nm or less. In some embodiments, the method may also include growing a corresponding semiconductor buffer layer in each etched portion of the semiconductor layer after performing the well implantation. The method may additionally include performing another well implantation in the semiconductor buffer layers before forming the superlattices. In some embodiments, the method may include performing a post-etch clean after etching. For example, the etching may include reactive ion etching. For another example, the base semiconductor monolayers may include silicon, and the at least one non-semiconductor monolayer may include oxygen. Example embodiments are described in detail with reference to the accompanying drawings, which illustrate exemplary embodiments. However, the embodiments may be implemented in many different forms and should not be construed as limited to the specific examples provided herein. Rather, these examples are provided solely to provide a more complete and comprehensive overview of the present invention. Throughout this specification and the drawings, like reference numerals refer to like elements, and a prime symbol (') is used to denote similar elements in different embodiments. Generally speaking, the present disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide improved performance. In the present disclosure, the enhanced semiconductor superlattice may also be referred to as an MST layer or "MST technology." Specifically, MST technology involves advanced semiconductor materials, such as superlattices 25, which are described further below. In prior literature, applicants have theorized that the superlattice structures described herein can reduce the effective mass of charge carriers, thereby increasing charge carrier mobility. For example, see U.S. Patent No. 6,897,472, the entire contents of which are incorporated herein by reference. Further developments by the applicant have shown that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials, for example in the case of silicon and insulators such as SiO 2 or HfO 2) The interface between the two layers. The applicant theorizes (but the applicant does not wish to be bound by this theory) that this may occur due to various mechanisms. One mechanism is to reduce the concentration of charged impurities near the interface, reduce the diffusion of these impurities and / or capture impurities so that they cannot reach the interface. Charged impurities will cause Coulomb scattering, thereby reducing mobility. Another mechanism is to improve the interface quality. For example, oxygen released from the MST film can be transferred to the Si-SiO 2 The interface provides oxygen, thereby reducing the sub-stoichiometric SiO x Alternatively, the capture of interstitials by the MST layer can reduce the Si-SiO 2. The interstitial silicon concentration near the interface reduces the formation of substoichiometric SiO x It is known that in Si-SiO 2 Substoichiometric SiO at the interface x Relative to stoichiometric SiO 2 exhibits poor insulation properties. Reduce the substoichiometric SiO at the interface x The amount of scattering can more effectively confine free carriers (electrons or holes) in silicon, thereby increasing their mobility under the action of an electric field parallel to the interface. This is a standard practice in field-effect-transistor (FET) structures. Scattering due to the direct influence of the interface is called "surface-roughness scattering", which can be advantageously reduced by the adjacent MST layer after tempering or during thermal oxidation. In addition to having better mobility characteristics, these MST structures can be formed or used in a manner that allows them to provide piezoelectric, pyroelectric and / or ferroelectric properties that are beneficial for various device types, as will be discussed further below. 1 and 2 , the material or structure is in the form of a superlattice 25, whose structure is controlled at the atomic or molecular level and can be formed using conventional techniques of atomic or molecular layer deposition. Superlattice 25 comprises a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of FIG1 . As shown, each layer group 45a-45n of the superlattice 25 includes a plurality of stacked base semiconductor layers 46 (which define respective base semiconductor portions 46a-46n) and a non-semiconductor layer 50 thereon. For clarity of presentation, the non-semiconductor layer 50 is represented by dots in FIG. As shown, the non-semiconductor monolayer 50 comprises a non-semiconductor monolayer that is confined within a crystal lattice of adjacent base semiconductor portions. The term "confined within a crystal lattice of adjacent base semiconductor portions" refers to the fact that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bonded together through the non-semiconductor monolayer 50 between the opposing base semiconductor portions, as shown in FIG2 . Generally, this configuration is achieved by controlling the amount of non-semiconductor material deposited onto the semiconductor portions 46a-46n using atomic layer deposition techniques so that the available semiconductor bonding sites are not completely occupied (i.e., not completely or less than 100% covered) by bonds to non-semiconductor atoms, as discussed further below. Therefore, as more semiconductor material monolayers 46 are deposited onto or above a non-semiconductor monolayer 50, the newly deposited semiconductor atoms can fill in the remaining unoccupied semiconductor atomic bonding sites beneath the non-semiconductor monolayer. In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it refers to a monolayer made of a material that would be a non-semiconductor or semiconductor if formed into a bulk form. That is, the properties exhibited by a single monolayer of a material (e.g., silicon) do not necessarily correspond to the properties exhibited when formed into a bulk form or a relatively thick layer, as will be understood by those skilled in the art. The applicant theorizes (though the applicant does not wish to be bound by this theory) that the non-semiconductor monolayer 50 and the adjacent base semiconductor portions 46a-46n impart to the superlattice 25 a lower effective mass for suitable charge carrier conductivity than would otherwise be possible in a direction parallel to the layers. Alternatively, this parallel direction is perpendicular to the stacking direction. The non-semiconductor monolayer 50 also imparts a conventional band structure to the superlattice 25 while advantageously acting as an insulator between layers or regions perpendicularly above and below the superlattice. Furthermore, the superlattice structure can also advantageously serve as a barrier to dopant and / or material diffusion between multiple layers vertically above and below the superlattice 25. Therefore, these properties can advantageously allow the superlattice 25 to provide an interface for the high-K dielectric, which not only reduces the diffusion of high-K materials into the channel region, but also advantageously reduces unwanted scattering effects and improves device mobility, as will be understood by those skilled in the art to which the present invention relates. The present invention also proposes that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility due to their lower effective mass for conductivity. In certain embodiments, due to the band engineering achieved by these embodiments, superlattice 25 can further have a substantially direct band gap, which is particularly advantageous for applications such as optoelectronic devices. As shown, the superlattice 25 may also include a cap layer 52 above an upper layer group 45n. The cap layer 52 may include a plurality of base semiconductor monolayers 46. The cap layer 52 may include between 2 and 100 monolayers of the base semiconductor, preferably between 10 and 50 monolayers. Each base semiconductor portion 46a-46n may include a base semiconductor selected from the group consisting of a Group IV semiconductor, a Group III-V semiconductor, and a Group II-VI semiconductor. Of course, Group IV semiconductors also include Group IV-IV semiconductors, as will be understood by those skilled in the art. More specifically, the base semiconductor may include, for example, at least one of silicon and germanium. Each non-semiconductor single layer 50 may comprise a non-semiconductor selected from the group consisting of, for example, oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor also preferably remains thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art. More specifically, the base semiconductor may comprise, for example, at least one of silicon and germanium. It should be noted that the term "monolayer" herein refers to a single atomic layer, as well as a single molecular layer. It should also be noted that the non-semiconductor monolayer 50 provided by a single monolayer also includes a monolayer in which all possible positions in the layer are not completely occupied (i.e., not completely or less than 100% coverage). For example, referring to the atomic diagram in FIG2 , a 4 / 1 repeating structure is shown with silicon as the base semiconductor material and oxygen as the band-modifying material. Only half of the possible oxygen atom positions are occupied. In other embodiments and / or when using different materials, a one-half occupancy situation is not necessarily true, as will be understood by those skilled in the art to which the present invention relates. In fact, those skilled in the art of atomic deposition will understand that, even in this schematic diagram, individual oxygen atoms in a given monolayer are not arranged precisely along a flat plane. For example, a preferred occupancy range is one-eighth to one-half of the possible oxygen positions being filled, but other occupancy ranges may be used in certain embodiments. Because silicon and oxygen are currently widely used in general semiconductor manufacturing processes, manufacturers will be able to immediately utilize the materials described in this specification. Atomic deposition or monolayer deposition is also a widely used technique. Therefore, semiconductor devices incorporating the superlattice 25 of the embodiments described herein can be readily adopted and implemented, as will be readily understood by those skilled in the art. Referring now to FIG. 3 , another embodiment of a superlattice 25′ according to the present invention having different characteristics is described. In this embodiment, the repeating pattern is 3 / 1 / 5 / 1. More specifically, the bottommost base semiconductor portion 46a′ has three monolayers, and the second bottom base semiconductor portion 46b′ has five monolayers. This pattern repeats throughout the superlattice 25′. Each non-semiconductor monolayer 50′ may comprise a single monolayer. For this superlattice 25′ comprising silicon / oxygen, the charge carrier mobility enhancement is independent of the orientation of the planes of the layers. Other elements not mentioned in FIG. 3 are similar to those discussed above with reference to FIG. 1 and will not be discussed again. In some device embodiments, each base semiconductor portion of the superlattice may be the same number of monolayers thick. In other embodiments, at least some base semiconductor portions of the superlattice may be different numbers of monolayers thick. In yet another embodiment, each base semiconductor portion of the superlattice may be different numbers of monolayers thick. Referring to Figures 4A to 4E , a method for fabricating an MST thin film 125 in the channel region of a semiconductor transistor 100 between adjacent shallow trench isolation (STI) regions 102 will now be described. In this regard, after forming STI regions 102 in a semiconductor (e.g., silicon) substrate or layer 101, the upper surface of the silicon between the STI regions may be uneven. In this case, forming an MST layer 125 on this surface may cause the upper surface of the STI region 102 to be lower than the bottom of the adjacent MST layer 125, which may result in leakage, for example. However, in some manufacturing processes, it may not be possible to change the STI step height to be formed. To overcome these technical challenges, the method of the present invention advantageously provides a variation of the well implant step after the silicon recess etch. In some embodiments, this method can be used to fabricate FINFETs saddled within DRAM cell transistors, as well as other device configurations, as will be appreciated by those skilled in the art. In the method of the present invention, after forming the isolated STI regions 102, the thick oxide regions 103 above the STI regions are removed at the desired locations to expose the selected local silicon regions 104. A dry clean may be performed as needed to remove any native oxide from the silicon regions 104. The silicon regions 104 are then etched (e.g., using Cl 2) to the desired recess depth (FIG. 4B), which in this example is 60 nm or less, but different etching depths may be used in different embodiments. The wells may then be formed using one of several variations. In the examples of FIG. 4C-4D, a mask 105 is formed over the thick oxide region 103, and the well 106 implantation and annealing are performed together. Subsequently, an MST film 125 and a silicon cap 152 may be formed in the local region 104 at the silicon recess by semiconductor epitaxial growth (SEG), with or without post-growth annealing (PGA). Thus, each MST film 125 may be positioned flush with or below the top of the adjacent STI region 102, as shown. Afterwards, gate oxide 107 may be pre-cleaned and grown ( FIG4E ), followed by formation of gate electrode 108 and source / drain regions 109 and 110. The resulting device 100 is shown in FIG5A and FIG5B ( FIG5B is an orthogonal view of FIG5A ). The MST film 125 may be positioned below the top surface of the STI region 102 (i.e., P1>P2 in FIG4E ). Another variation of the steps shown in Figures 4C to 4D is shown in Figures 6A to 6C. After the recess is etched, a shield oxide 112' (Figure 6A) is formed, and then the well 106' is formed. For example, the shield oxide 112' (e.g., SiO 2) It can have a thickness of 10 nm or less. After the well 106' implant and anneal are completed, the screen oxide 112' is removed and a silicon buffer layer 111' is formed, followed by another well implant and anneal ( FIG6B ). For example, the silicon recess buffer can have a thickness of 10 nm or less, though different thicknesses may be used in different embodiments. The resulting MST layer segment 125' is again processed ( FIG6C ) to be flush with or below the upper surface of the adjacent STI region 102'. In yet another variation shown in Figures 7A-7B, the well 106" is grown in situ. Specifically, this can be accomplished in the same process chamber where the MST film 125" growth occurs, which can advantageously reduce processing time / cost. A second exemplary fabrication flow is now described with reference to Figures 8A to 8F . After removing the thick oxide (not shown) from the silicon wafer or layer 201, a silicon recess etch (e.g., reactive ion etching, RIE) (e.g., HBR, ion etching, or a combination thereof) may be performed, as shown in Figure 8B , to define a localized region 204. Again, the etch depth may be similar to that described above for the first fabrication flow. Thereafter, one of the well 206 implant variations described above is performed (e.g., implant (well) + anneal, Si buffer / implant (well) + anneal, or in-situ well formation (same chamber as MST growth). The growth of the MST film 225 and cap layer 252 may be performed, and as described above, in some embodiments, this may be performed in-situ in the same chamber as the well formation. Similarly, the formation of the MST film 125 may be performed with or without PGA. Thereafter, a thick oxide 213 may be deposited ( FIG. 8E ), followed by removal of the thick oxide from the location where the gate is to be formed, pre-cleaning, and growth of a thin gate oxide 207 ( FIG. 8F ), and formation of the gate electrode and source / drain (similar to FIGs. 5A and 5B ). Those skilled in the art will benefit from the disclosure of this specification and the accompanying drawings to devise various modifications and other embodiments. Therefore, it should be understood that the disclosure is not limited to the specific embodiments described in this specification, and that related modifications and embodiments also fall within the scope of the appended patent applications. 21, 21': Substrate 25, 25': Superlattice / MST layer 45a-45n, 45a'-45n-1', 45n': Layer group 46, 46': Base semiconductor single layer 46a-46n, 46a'-46n-1', 46n': Base semiconductor portion 50, 50': Band-modifying layer / non-semiconductor single layer 52, 52', 252: Cap layer 100: Semiconductor transistor 101: Semiconductor substrate or layer 102, 102', 202: STI region 103: Thick oxide region 104: Silicon region 105: Mask 106, 106', 106'', 206: Well 107, 207: Gate oxide 108: Gate electrode 109: Source region 110: Drain region 111': Silicon buffer layer 112': Screen oxide 125, 125', 125", 225: MST film / MST layer 152: Silicon cap 201: Silicon wafer or layer 204: Local region 213: Thick oxide FIG1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an exemplary embodiment. FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1 . FIG3 is an enlarged schematic cross-sectional view of a superlattice according to another exemplary embodiment. 4A to 4E are a series of schematic cross-sectional views of a method for fabricating a semiconductor device according to an exemplary embodiment, wherein superlattice epitaxial growth is performed after recess etching and well implantation. 5A and 5B are schematic cross-sectional views of an exemplary semiconductor device manufactured using the method of FIG. 4A to 4E . 6A-6C are a series of cross-sectional views of an alternative method to the steps shown in FIG. 4D . 7A-7B are a series of cross-sectional views of another alternative method to the step shown in FIG. 4D . 8A-8F are a series of schematic cross-sectional views of an alternative embodiment of the method shown in FIGs. 4A-4E. 201:Silicon wafer or layer 202:STI area 206: Well 207: Gate oxide 213: Thick oxide 225:MST film 252: Top cover

Claims

1. A method for manufacturing a semiconductor device, comprising: A shallow trench isolation (STI) region is formed in a semiconductor layer; a first portion of the semiconductor layer between adjacent STI regions is etched to an etch depth; a well implantation is performed in the first portions of the semiconductor layer; a corresponding superlattice is formed on the etched first portions of the semiconductor layer between adjacent STI regions, such that its height is not greater than the etch depth, each superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion; a corresponding separated source region and drain region are formed in each superlattice; and a corresponding gate is formed above each superlattice.

2. The method of claim 1, wherein each superlattice defines a channel region between its source and drain regions.

3. The method of claim 1, which includes forming a photomask over at least some STI regions and a second portion of the semiconductor layer prior to etching.

4. The method of claim 3, comprising forming a corresponding first oxide portion over the superlattices; and forming a corresponding second oxide portion over the second portions of the semiconductor layer, the second oxide portions being thicker than the first oxide portions.

5. The method of claim 1, wherein the etching depth is 60 nm or shallower.

6. The method of claim 1, further comprising growing a corresponding semiconductor buffer layer on each first portion of the semiconductor layer after the well implantation is performed.

7. The method of claim 6, which includes performing another well implantation in the semiconductor buffer layers prior to the formation of the superlattices.

8. The method of claim 1, wherein etching includes reactive ion etching.

9. The method of claim 1, which includes performing a post-etch cleaning after etching.

10. The method of claim 1, wherein the substrate semiconductor monolayer comprises silicon.

11. The method of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

12. A method for manufacturing a semiconductor device, comprising: A shallow trench isolation (STI) region is formed in a semiconductor layer; a first portion of the semiconductor layer between adjacent STI regions is etched to an etch depth; a well implantation is performed in the first portions of the semiconductor layer; a corresponding semiconductor buffer layer is grown in each etched portion of the semiconductor layer; a corresponding superlattice is formed on each semiconductor buffer layer between adjacent STI regions, such that its height is not greater than the etch depth, each superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate semiconductor monolayers defining a substrate semiconductor portion, and at least one non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion; a corresponding separated source region and drain region are formed in each superlattice, each superlattice defining a channel region between its source region and drain region; and a corresponding gate is formed above each superlattice.

13. The method of claim 12, comprising forming a photomask over at least some STI regions and a second portion of the semiconductor layer prior to etching.

14. The method of claim 13, comprising forming a corresponding first oxide portion over the superlattices; and forming a corresponding second oxide portion over the second portions of the semiconductor layer, the second oxide portions being thicker than the first oxide portions.

15. The method of claim 12, which includes performing another well implantation in the semiconductor buffer layers prior to the formation of the superlattices.

16. A method for manufacturing a semiconductor device, comprising: A shallow trench isolation (STI) region is formed in a semiconductor layer; a first portion of the semiconductor layer between adjacent STI regions is etched to an etch depth; a well implantation is performed in the first portions of the semiconductor layer; a corresponding superlattice is formed on the etched first portions of the semiconductor layer between adjacent STI regions, such that its height is not greater than the etch depth, each superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked substrate silicon monolayers defining a substrate silicon portion, and at least one oxygen monolayer confined within a lattice of an adjacent substrate silicon portion; a corresponding separated source region and drain region are formed for each superlattice; and a corresponding gate is formed above each superlattice.

17. The method of claim 16, wherein each superlattice defines a channel region between its source and drain regions.

18. The method of claim 16, comprising forming a photomask over at least some STI regions and a second portion of the semiconductor layer prior to etching.

19. The method of claim 18, comprising: The corresponding first oxide portions are formed above these superlattices; And a corresponding second oxide portion is formed above the second portions of the semiconductor layer, the second oxide portion being thicker than the first oxide portion.

20. The method of claim 16 further includes, after the well implantation, growing a corresponding semiconductor buffer layer on each first portion of the semiconductor layer; and before forming the superlattices, performing another well implantation on the semiconductor buffer layers.

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