Semiconductor device and method of forming the same

Abstract

A method includes forming a fin above a substrate; forming a first isolation region above the substrate; forming a hard shield above the first isolation region, wherein the fin protrudes from the hard shield; forming a dummy nanostructure above the fin; removing the dummy nanostructure; removing a portion of the fin to form an opening extending through the hard shield and the first isolation region; forming a second isolation region above the hard shield and in the opening; and forming a gate structure along the sidewall of the second isolation region.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to semiconductor manufacturing technology, and particularly to semiconductor devices and methods for forming the same. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the size of the smallest components, which allows more components to be integrated into a given area. However, as the size of the smallest components shrinks, other problems arise that need to be addressed. [Summary of the Invention]

[0004] A method for forming a semiconductor device is provided according to some embodiments. This method includes forming a fin over a substrate; forming a first isolation region over the substrate; forming a hard mask over the first isolation region, wherein the fin protrudes from the hard mask; forming a dummy nanostructure over the fin; removing the dummy nanostructure; removing a portion of the fin to form an opening extending through the hard mask and the first isolation region; forming a second isolation region over the hard mask and in the opening; and forming a gate structure along the sidewall of the second isolation region.

[0005] A method for forming a semiconductor device is provided according to some other embodiments. This method includes forming a first fin over a substrate; forming a first nanostructure and a second nanostructure over the first fin; forming an isolation region surrounding the first fin; forming a protective layer over the isolation region; forming a dummy gate over the protective layer, the first fin, the first nanostructure, and the second nanostructure; performing a first selective etching process to form an opening in the dummy gate over the first fin; performing a second selective etching process in the opening to remove the second nanostructure; performing a third selective etching process in the opening to remove the first nanostructure and the first fin; and filling the opening with an insulating material.

[0006] A semiconductor device is provided according to some other embodiments. The semiconductor device includes a first fin and a second fin above a substrate; an isolation region surrounding the first fin and the second fin; a hard mask above the isolation region and surrounding the first fin and the second fin; a nanostructure above the first fin; an isolation structure extending over the hard mask and through the second fin to the substrate; and a gate structure on a first sidewall of the hard mask, the first fin, the nanostructure, and the isolation structure.

Implementation Method

[0008] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and not intended to limit. For example, the description mentioning that a first component is formed on or above a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of the embodiments of the present invention. This repetition is for simplification and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0009] Additionally, this document may use spatial relative terms, such as “below,” “under,” “below,” “above,” “above,” and similar terms, to describe the relationship between one or more elements or components as shown in the figures and another element or component(s). Besides the orientations depicted in the figures, these spatial relative terms are also used to cover different orientations of the device in use or operation. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatial relative adjectives used herein will also be interpreted according to the orientation after the turn.

[0010] Several embodiments are described below in a specific context, wherein the die comprises a nanostructured field-effect transistor (e.g., "nanostructure-FETs" or "nano-FETs"). However, various embodiments may be applied to dies comprising other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, stacked transistors, or similar transistors) that replace or are combined with nanostructured field-effect transistors.

[0011] According to various embodiments, oxide dummy regions are used to fill the regions between channel regions of a nanostructured field-effect transistor, where a gate structure is subsequently formed. The use of oxide dummy regions allows for more selective etching when removing the oxide dummy regions, which can reduce the risk of etch damage to the channel regions or source / drain regions. A hard mask is formed over the isolation region surrounding the channel region to protect the isolation region from unwanted etching. For example, the hard mask can protect the isolation region from etching when the oxide dummy region is removed during the formation of the transistor isolation structure. The use of various selective etching methods can also reduce unwanted etching of the isolation region.

[0012] According to some embodiments, Figure 1 illustrates an example of a nanostructured field-effect transistor (e.g., a nanowire field-effect transistor, a nanosheet field-effect transistor, a nano-field-effect transistor, or a similar device), a gate-all-around (GAA) field-effect transistor, or a similar device in a three-dimensional view. For clarity, some components of the nanostructured field-effect transistor may be simplified and / or omitted in Figure 1. The nanostructured field-effect transistor includes a nanostructure 66 (e.g., a nanosheet, nanowire, or similar structure) located above fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 is a semiconductor component serving as a channel region of the nanostructured field-effect transistor. The nanostructure 66 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. For example, an isolation region 70 of a shallow trench isolation (STI) region is disposed between adjacent fins 62, and the fins 62 may protrude from and above the adjacent isolation regions 70. Nanostructure 66 is disposed above and between adjacent isolation regions 70. Some portions of isolation regions 70 may be covered by a protective layer, hard mask, or similar component (not shown in Figure 1). Although isolation regions 70 are described / illustrated as separate from substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom of fin 62 is illustrated as being a single, continuous material with substrate 50, the bottom portion of fin 62 and / or substrate 50 may comprise a single material or multiple materials. In this document, fin 62 refers to the portion extending between adjacent isolation regions 70.

[0013] A gate dielectric layer 120 is located above the top surface of the fin 62 and along the top, sidewalls, and bottom surfaces of the nanostructure 66. A gate electrode 122 is located above the gate dielectric layer 120. The gate dielectric layer 120 and the gate electrode 122 may be collectively referred to as a "gate structure" or a "gate stack". Source / drain regions 100 (e.g., epitaxial source / drain regions 100) are disposed on the fins 62 on both sides of the gate dielectric layer 120 and the gate electrode 122. Depending on the context, source or drain region 100 may refer to either a single source or drain region. An inter-layer dielectric (ILD) 104 is formed above the source / drain regions 100. Contacts (described later) will be formed to the source / drain regions 100 via the inter-layer dielectric 104. The source / drain regions 100 may be shared among various nanostructures 66. For example, adjacent source / drain regions 100 can be electrically connected, for example, by joining or merging source / drain regions 100 via epitaxial growth, or by coupling source / drain regions 100 with the same contacts.

[0014] Figure 1 further illustrates the reference cross-sections used in the following figures. Cross-section A-A' extends along the longitudinal axis of the gate electrode 122. Cross-section B-B' is perpendicular to cross-section A-A' and extends along the longitudinal axis of the fins 62 of the nanostructured field-effect transistor and in the direction of current flow, for example, between the source / drain regions 100 of the nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section B-B' (e.g., perpendicular to cross-section A-A') and extends between adjacent fins 62 of the nanostructured field-effect transistor and between corresponding adjacent source / drain regions 100 of the nanostructured field-effect transistor. Cross-section D-D' is parallel to cross-section A-A' and extends through the source / drain regions 100 of the nanostructured field-effect transistor. For clarity, the following figures refer to these reference cross-sections.

[0015] Some embodiments discussed herein are discussed in the context of nanostructured field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate the use of planar devices (e.g., planar field-effect transistors) or fin field-effect transistors (FinFETs) as alternatives to or in combination with nanostructured field-effect transistors. For example, a fin field-effect transistor may comprise semiconductor fins on a substrate, wherein the semiconductor fins are semiconductor components serving as channel regions of the fin field-effect transistor. Similarly, a planar field-effect transistor may comprise a substrate, wherein planar portions of the substrate are semiconductor components serving as channel regions of the planar field-effect transistor. Other field-effect transistors or configurations of field-effect transistors are also possible.

[0016] Figures 2 to 31C are views of intermediate stages in the fabrication of nanostructured field-effect transistors according to some embodiments. Figures 2, 3, 4, 5, 6, 7, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, and 31A illustrate cross-sectional views along a section similar to the reference section A-A' in Figure 1. Figures 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16A, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30, and 31B depict cross-sectional views along a section similar to the reference section B-B' in Figure 1. Figures 8C, 9C, 10C, 11C, 17C, 18C, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, 27C, 28C, 29C, and 31C depict cross-sectional views along a section similar to the reference section C-C' in Figure 1. Figures 11D, 17D, 17E, 18D, 19D and 31D depict cross-sectional views along a section similar to the reference section D-D' in Figure 1.

[0017] According to some embodiments, in Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar layer. An insulating layer is provided on the substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium arsenide phosphide; or combinations thereof.

[0018] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an N-type metal-oxide-semiconductor field-effect transistor (NMOS) transistor, such as an n-type nanostructure field-effect transistor, and the p-type region 50P can be used to form a p-type device, such as a P-type metal-oxide-semiconductor field-effect transistor (PMOS) transistor, such as a p-type nanostructure field-effect transistor. The n-type region 50N may (or may not) be physically separated from the p-type region 50P (not shown separately), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise stated, the following figures describe processing steps that can be performed in either the n-type region 50N or the p-type region 50P.

[0019] Further in Figure 2, according to some embodiments, a multilayer stack 55 is formed over a substrate 50. The multilayer stack 55 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layer 54 is formed of a first semiconductor material, and the second semiconductor layer 56 is formed of a second semiconductor material. Both semiconductor materials can be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form channel regions for nanostructured field-effect transistors in both the n-type region 50N and the p-type region 50P. In such an embodiment, the channel regions in both the n-type region 50N and the p-type region 50P can have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity for etching the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0020] In another embodiment (not shown separately), a first semiconductor layer 54 is patterned to form a channel region for a nanostructured field-effect transistor in one region (e.g., p-type region 50P), and a second semiconductor layer 56 is patterned to form a channel region for a nanostructured field-effect transistor in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for a p-type device, such as silicon germanium (e.g., Si xGe 1-x, where x can be in the range of 0 to 1), pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or similar materials. The second semiconductor material of the second semiconductor layer 56 may be a material suitable for an n-type device, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, or similar materials. The first semiconductor material and the second semiconductor material can have high etch selectivity relative to each other, such that the first semiconductor layer 54 can be removed in the n-type region 50N under the second semiconductor layer 56 without significant removal, and the second semiconductor layer 56 can be removed in the p-type region 50P under the first semiconductor layer 54 without significant removal.

[0021] The multilayer stack 55 is illustrated as comprising three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 55 may comprise any number of first semiconductor layers 54 and second semiconductor layers 56. Each layer of the multilayer stack 55 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or a similar process. In some embodiments, some layers of the multilayer stack 55 are formed to be thinner than other layers of the multilayer stack 55. For example, in other embodiments, the bottommost second semiconductor layer 56 (the second semiconductor layer 56 closest to the substrate 50) may be thinner than the upper second semiconductor layer 56 to improve short-channel control in the resulting nanostructured field-effect transistor. Other combinations or variations of layer thickness are possible.

[0022] According to some embodiments, in Figure 3, fins 62 are formed in the substrate 50, and first nanostructures 64 and second nanostructures 66 are formed in the multilayer stack 55. The first nanostructure 64 and second nanostructure 66 may be collectively referred to herein as nanostructures 64 / 66. In some cases, the nanostructures 64 / 66 above the fins 62 may be considered as a stack of nanostructures or a similar structure. Unless specifically discussed, Figure 3 may be located in either the n-type region 50N or the p-type region 50P of the substrate 50.

[0023] In some embodiments, nanostructures 64 / 66 and fins 62 can be formed in the multilayer stack 55 and the substrate 50, respectively, by etching trenches in the multilayer stack 55 and the substrate 50. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. The etching can be anisotropic. Forming nanostructures 64 / 66 by etching the multilayer stack 55 can further define the first nanostructure 64 from the first semiconductor layer 54 and the second nanostructure 66 from the second semiconductor layer 56.

[0024] Any suitable method can be used to pattern the fins 62 and the nanostructures 64 / 66. For example, one or more photolithography processes (including dual patterning or multiple patterning processes) can be used to pattern the fins 62 and the nanostructures 64 / 66. Generally, dual patterning or multiple patterning processes combine photolithography with a self-aligned process, which allows for patterns with, for example, a pitch smaller than that of patterns obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 62 and the nanostructures 64 / 66. Other patterning techniques are also possible.

[0025] The fin 62 is depicted as having approximately equal widths in both the n-type region 50N and the p-type region 50P. In other embodiments, the width of the fin 62 in the n-type region 50N may be greater than or less than the width of the fin 62 in the p-type region 50P. Furthermore, while each of the fins 62 and nanostructures 64 / 66 is depicted as always having a constant width, in other embodiments, the fins 62 and / or nanostructures 64 / 66 may have tapered sidewalls such that the width of each of the fins 62 and / or nanostructures 64 / 66 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 64 / 66 may have a different width and may be trapezoidal.

[0026] In Figure 4, an insulating material 68 is formed over the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 may be an oxide, such as silicon oxide, a nitride, a similar material, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), a similar process, or a combination thereof. Other insulating materials formed by any suitable process may be used. In some embodiments, the insulating material 68 comprises silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material 68 is formed, an annealing process may be performed. Although the insulating material 68 is depicted as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64 / 66. Subsequently, a filler material, such as one of the aforementioned insulating materials, may be formed over the liner.

[0027] An insulating material 68 may be deposited over the fins 62 and the nanostructures 64 / 66, such that excess insulating material 68 covers the nanostructures 64 / 66. A removal process is then applied to the insulating material 68 to remove the excess insulating material 68 over the nanostructures 64 / 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, a combination of the foregoing, or similar processes, may be utilized. The planarization process can expose the nanostructures 64 / 66 such that the top surfaces of the nanostructures 64 / 66 and the insulating material 68 are substantially flush or coplanar after the planarization process is completed.

[0028] According to some embodiments, in Figure 5, an insulating material 68 is etched to form a shallow trench isolation (STI) region 70. The shallow trench isolation region 70 is adjacent to the fin 62. The etched insulating material 68 causes the upper portion of the nanostructures 64 / 66 and / or the fin 62 to protrude from between adjacent shallow trench isolation regions 70. The upper portion of the nanostructures 64 / 66 and / or the fin 62 is above the shallow trench isolation region 70. In some cases, a portion of the nanostructures 64 / 66 and / or the fin 62 may be below the top surface of the shallow trench isolation region 70. Furthermore, the top surface of the shallow trench isolation region 70 may have a flat surface, a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof, as shown. The top surface of the shallow trench isolation region 70 may be formed as flat, convex, and / or concave by appropriate etching. A suitable etching process can be used to etch the shallow trench isolation region 70, such as a selective etching process for the material of the insulating material 68 (e.g., etching the material of the insulating material 68 at a faster rate than the materials of the fins 62 and nanostructures 64 / 66). For example, oxide removal can be used, which employs diluted hydrofluoric acid ("dHF") or a similar material.

[0029] The aforementioned process is merely one example of how the fins 62 and nanostructures 64 / 66 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 62 and / or nanostructures 64 / 66. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be etched such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or nanostructures 64 / 66. The epitaxial structures can comprise the aforementioned alternating semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing epitaxial structures, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can also be used together.

[0030] Furthermore, in Figure 5, suitable wells (not shown separately) can be formed in the fins 62, nanostructures 64 / 66, and / or shallow trench isolation regions 70. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology, and a suitable photolithography technique can be used to pattern the photoresist. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. n-type impurities may include phosphorus, arsenic, antimony, or similar impurities, implanted into the region at a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0031] Before or after the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 62, nanostructures 64 / 66, and shallow trench isolation region 70 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique, and a suitable lithography technique can be used to pattern the photoresist. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may include boron, boron fluoride, indium, or similar impurities, implanted into the region at a concentration ranging from about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0032] After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can eliminate the need for implantation, but in-situ and implantation doping can also be used together.

[0033] According to some embodiments, in Figure 6, a dielectric liner 42 is formed over the shallow trench isolation region 70, fins 62, and nanostructures 64 / 66. The dielectric liner 42 may be formed as a conformal layer over the fins 62 and nanostructures 64 / 66 and along the sidewalls of the fins 62 and nanostructures 64 / 66. The dielectric liner 42 may be formed to protect the surfaces of the shallow trench isolation region 70, fins 62, and / or nanostructures 64 / 66 from etching during subsequent processes and as an etch stop layer in some subsequent processes. In some embodiments, a portion of the dielectric liner 42 may subsequently be used as a dummy dielectric layer, a dummy gate dielectric, or a similar component. The dielectric liner 42 may comprise a silicon-based dielectric material, such as silicon oxide, silicon oxynitride, or similar materials. Other materials are also possible. The dielectric liner 42 may be deposited or thermally grown according to suitable techniques.

[0034] According to some embodiments, in Figure 7, a hard mask layer 51 is deposited over the dielectric substrate 42. The hard mask layer 51 then forms a hard mask 52, which protects some surfaces of the shallow trench isolation region 70 from etching during subsequent processes. Thus, the hard mask 52 can be considered a protective layer or a similar component. The hard mask layer 51 is deposited over the shallow trench isolation region 70 and over and along the sidewalls of the fins 62 and / or nanostructures 64 / 66. Thus, in some cases, the hard mask layer 51 can be deposited as a continuous layer. The hard mask layer 51 may contain one or more materials that have high etch selectivity for etching the materials of the dielectric substrate 42, the shallow trench isolation region 70, the fins 62, and / or the nanostructures 64 / 66. In some embodiments, the hard masking layer 51 may comprise nitrides, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxynitride, silicon oxynitride, or similar materials. In other embodiments, the hard masking layer 51 comprises oxides, such as hafnium oxide, zirconium oxide, or similar materials. Other materials are possible, and in some cases, the hard masking layer 51 may comprise multiple layers of different materials. The hard masking layer 51 can be deposited using suitable processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, or similar processes. The deposition process may be conformal. In some cases, the portion of the hard masking layer 51 deposited on the sidewall surface (e.g., the vertical surface) may be thinner than the portion of the hard masking layer 51 deposited on the lateral surface (e.g., the top surface).

[0035] According to some embodiments, in Figures 8A-8C, the upper portion of the hard mask layer 51 is removed to form a hard mask 52. The upper portion of the hard mask layer 51 may include a portion along the sidewalls of the fin 62, a portion along the sidewalls of the nanostructure 64 / 66, and / or a portion above the top surface of the nanostructure 64 / 66. As shown in Figure 8A, the remaining portion of the hard mask layer 51 above the top surface of the shallow trench isolation region 70 forms the hard mask 52. The removal of the upper portion of the hard mask layer 51 can be performed using one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. The etching process may be anisotropic. In some cases, the etching process may thin the lateral portion of the hard mask layer 51 forming the hard mask 52. As shown in Figure 8A, a dielectric liner 42 is located between the hard mask 52 and the shallow trench isolation region 70. Furthermore, the surface of the hard mask 52 can have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as shown in the figure. In some embodiments, the hard mask 52 has a thickness T1 ranging from about 5 nm to about 20 nm, but other thicknesses are also possible. In some cases, a thicker thickness T1 results in a reduction in parasitic capacitance. In some cases, the thickness T1 can be controlled such that the stress applied by the hard mask 52 is similar to the stress applied by the shallow trench isolation region 70.

[0036] According to some embodiments, in Figures 9A-9C, a dummy gate 84 and a mask 86 are formed over the hard mask 52 and the dielectric substrate 42. In some embodiments, a dummy gate layer is formed over the hard mask 52 and the nanostructures 64 / 66 and along the sidewalls of the fins 62 and the nanostructures 64 / 66. A mask layer is formed over the dummy gate layer. The dummy gate layer can be deposited over the dummy dielectric layer and then planarized, for example, by a chemical mechanical polishing process or a similar process. The dummy gate layer can be formed of a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicates, metal oxides, and metals. The material of the dummy gate layer can be deposited by chemical vapor deposition, physical vapor deposition (PVD), sputtering deposition, or other suitable techniques. The dummy gate layer can be formed from other materials that have high etch selectivity for etching insulating materials (e.g., hard mask 52, dielectric substrate 42, and / or shallow trench isolation region 70). In some cases, the dummy gate layer can be formed from multiple layers of different materials. A mask layer can be deposited over the dummy gate layer. The mask layer can be formed from dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxide, or similar materials. In some cases, the mask layer can be formed from multiple layers of different materials.

[0037] Subsequently, the mask layer is patterned using suitable photolithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to a dummy gate layer to form a dummy gate 84. In some embodiments, the pattern of the mask 86 is also transferred to a dielectric substrate 42, wherein portions of the dielectric substrate 42 on the fins 62 and / or nanostructures 66 form dummy gate dielectrics. The dummy gates 84 cover the corresponding channel regions of the nanostructures 64 / 66. The pattern of the mask 86 can be used to physically separate each dummy gate 84 from adjacent dummy gates 84. The dummy gates 84 may also have a length direction that is generally perpendicular to the length direction (e.g., longitudinal) of the corresponding fin 62. The mask 86 may optionally be removed after patterning, for example by any suitable etching technique. In this example, a single dummy gate layer and a single mask layer are formed across the n-type region 50N and the p-type region 50P.

[0038] According to some embodiments, in Figures 10A-10C, a spacer layer 90 is conformally formed over the structure. The spacer layer 90 is formed over the nanostructures 64 / 66 and the hard mask 52. The spacer layer 90 is also formed on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, the dielectric liner 42, the nanostructures 64 / 66, and / or the fins 62. The spacer layer 90 can be formed of one or more dielectric materials. Figures 10A-10C illustrate a spacer layer 90 formed of a single layer of dielectric material, but in other embodiments, the spacer layer 90 can be formed of two or more layers of dielectric material. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or similar materials, which can be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or similar processes. Other insulating materials formed by any suitable process can be used. The spacer layer 90 is then etched to form spacers.

[0039] According to some embodiments, in Figures 11A-11D, the spacer layer 90 is patterned to form gate spacers 92 and fin spacers 94. Any suitable etching process can be performed, such as dry etching, wet etching, similar etching, or a combination thereof, to pattern the spacer layer 90. The etching can be anisotropic. During etching, the spacer layer 90 has portions remaining on the sidewalls of the dummy gate 84 (thus forming the gate spacer 92), and portions remaining on the sidewalls of the fins 62 and / or nanostructures 64 / 66 (thus forming the gate spacer 92). After etching, the fin spacers 94 and / or the gate spacers 92 can have straight sidewalls or can have curved sidewalls. In some embodiments, the etching stops on the hard mask 52. In other embodiments, the hard mask 52 and / or the shallow trench isolation region 70 can also be etched when the spacer layer 90 is patterned. For example, etching may recess portions of the hard mask 52 between fins 62 and / or between gate spacers 92, or it may etch through the hard mask 52 and recess portions of the shallow trench isolation region 70 between fins 62 and / or between gate spacers 92. Depending on the characteristics of the etching process used, etching may stop on the hard mask 52, may recess the hard mask 52 (e.g., to thin it), or may etch through the hard mask 52. Gate spacers 92 and / or fin spacers 94 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0040] Furthermore, lightly doped source / drain (LDD) regions (not shown separately) can be implanted. In embodiments with different device types, similar to the implantation of the aforementioned well, a mask, such as a photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 62 and nanostructures 64 / 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 62 and nanostructures 64 / 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. Lightly doped source / drain regions can have impurity concentrations ranging from about 10¹⁵ atoms / cm³ to about 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0041] It should be noted that the foregoing disclosure generally describes the process for forming spacers and lightly doped source / drain regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0042] According to some embodiments, continuing with Figures 11A-11C, source / drain grooves 96 are patterned in the fins 62, nanostructures 64 / 66, and substrate 50. Epitaxial source / drain regions are then formed in the source / drain grooves 96. The source / drain grooves 96 extend through the nanostructures 64 / 66 and into the fins 62, and in some embodiments, further into the substrate 50. In some embodiments, the fins 62 may be etched such that the bottom surface of the source / drain grooves 96 is higher than or approximately flush with the top surface of the shallow trench isolation region 70. In other embodiments, the bottom surface of the source / drain grooves 96 is lower than the top surface of the shallow trench isolation region 70.

[0043] The source / drain recess 96 can be formed by etching the fins 62, nanostructures 64 / 66, and substrate 50 using an anisotropic etching process, such as reactive ion etching, neutral beam etching, or similar etching. In some embodiments, during the etching process for forming the source / drain recess 96, gate spacers 92 and dummy gates 84 shield a portion of the fins 62, nanostructures 64 / 66, and / or substrate 50. Each layer of nanostructures 64 / 66 and / or fins 62 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recess 96 after it has reached a desired depth. In some embodiments, etching can etch a hard mask 52, which can form a recess extending into a shallow trench isolation region 70 between the gate spacers 92.

[0044] According to some embodiments, in Figures 12A-14B, the first nanostructure 64 is replaced with dummy material 71 to form a dummy region 72. According to some embodiments, in Figures 12A-12B, the remainder of the first nanostructure 64 is removed to form an opening 65 in the region between the second nanostructures 66. The remainder of the first nanostructure 64 can be removed using an etching process through the source / drain recess 96. The etching process can include any suitable etching process that selectively etches the material of the first nanostructure 64 at a rate faster than the material of the second nanostructure 66, fins 62, and / or dielectric substrate 42. The etching process can include wet etching and / or dry etching processes, and the etching can be isotropic. In some embodiments, a trimming process (not shown) is performed to reduce the thickness of the exposed portion of the second nanostructure 66 and to widen the opening 65. In the following text, the second nanostructure 66 may be referred to as nanostructure 66, and the collection of vertically adjacent nanostructures 66 above each fin 62 may be referred to as the "stack" of nanostructures 66.

[0045] According to some embodiments, in Figures 13A-13B and 14A-14B, dummy material 71 is deposited to form dummy regions 72. In some cases, dummy material 71 may be considered a sacrificial material or a sacrificial oxide. In some cases, dummy region 72 may be considered a sacrificial region, dielectric dummy region, dummy nanostructure, dummy gate region, or disposable oxide interposers (DOI). Replacing the first nanostructure 64 with dummy region 72 can provide several advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes may be performed to, for example, activate the dopants in the source / drain regions. When the material of the first nanostructure 64 (e.g., silicon-germanium or similar materials) is exposed to high temperatures, germanium mixing and increased roughness at the interface between nanostructures 64 and 66 may occur. Such manufacturing defects may reduce the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure 66, germanium residue may remain in the channel region of the resulting transistor device, negatively impacting the performance of the channel region. Additionally, mixing may result in less efficient and less defined selective etching of either the first nanostructure 64 or the second nanostructure 66. This can lead to unwanted removal, for example, of a portion of the second nanostructure 66, which can damage the component, reduce yield, and / or decrease device performance. By replacing the first nanostructure 64 with an insulating material (e.g., dummy material 71) prior to a high-temperature process (e.g., source / drain annealing), manufacturing defects can be reduced and device performance can be improved. Furthermore, the etch selectivity between the materials of dummy material 71 and the second nanostructure 66 can be greater than the etch selectivity between nanostructures 64 and 66, allowing for improved etch definition and less etching of the second nanostructure 66.

[0046] According to some embodiments, in Figures 13A-13B, dummy material 71 is deposited in the groove 96 and the opening 65. The deposition of dummy material 71 can be performed by a conformal deposition process, such as chemical vapor deposition, atomic layer deposition, or a similar process. Dummy material 71 may comprise an insulating material, such as silicon oxide or a similar material, that can be selectively etched from the nanostructure 66 and the fin 62. In some embodiments, dummy material 71 and hard mask 52 may be different materials. In other embodiments, dummy material 71 and hard mask 52 may be similar materials. As shown in Figures 13A-13B, dummy material 71 may fill or overfill the opening 65 and may cover the sidewalls of the nanostructure 66. Dummy material 71 may cover the top surface of the fin 62. In some embodiments, dummy material 71 does not completely fill the source / drain groove 96.

[0047] According to some embodiments, in Figures 14A-14B, dummy material 71 is etched to form dummy region 72. The etching can be isotropic or anisotropic. For example, the etching of dummy material 71 can be performed using a wet etching process, which uses materials such as dHF or similar materials. In some embodiments, etching is performed until the sidewalls of dummy material 71 are recessed beyond the sidewalls of nanostructure 66, forming sidewall grooves 97. Therefore, the width of dummy region 72 can be smaller than the width of nanostructure 66. In some cases, sidewall groove 97 can be considered as part of source / drain groove 96. Although the sidewalls of dummy region 72 within sidewall groove 97 are drawn as flat, the sidewalls can be concave or convex.

[0048] According to some embodiments, in Figures 15A-15B, an inner spacer 98 is formed in the sidewall recess 97. In other words, the inner spacer 98 is formed on the sidewall of the dummy region 72. As will be described in more detail later, a source / drain region is subsequently formed in the source / drain recess 96, and the dummy region 72 is subsequently replaced with a corresponding gate structure. The inner spacer 98 serves as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. Furthermore, the inner spacer 98 can be used to prevent damage to the subsequently formed source / drain region by subsequent etching processes.

[0049] In some embodiments, the inner spacer 98 is formed by conformally depositing an insulating material in the source / drain recess 96 and the sidewall recess 97 and subsequently etching the insulating material. The insulating material may be silicon nitride, silicon oxynitride, or a similar material. However, any suitable material may be used, such as a low dielectric constant (low k) material with a dielectric constant value less than about 3.5. The insulating material may be formed by a deposition process, such as atomic layer deposition, chemical vapor deposition, or a similar process. The etching of the insulating material may be anisotropic. For example, the etching process may be dry etching, such as reactive ion etching, neutral beam etching, or a similar etching. After the etching of the insulating material, the remaining portion of the insulating material in the sidewall recess 97 forms the inner spacer 98. The thickness of the inner spacer 98 may be less than, approximately equal to, or greater than the thickness of the adjacent dummy region 72.

[0050] Although the outer wall of the inner spacer 98 is shown to be flush with (e.g., approximately coplanar) with the sidewall of the second nanostructure 66, the outer wall of the inner spacer 98 may extend beyond or be recessed from the sidewall of the second nanostructure 66. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall groove 97. Furthermore, although the sidewall of the inner spacer 98 is shown as flat in Figures 15A-15B, the sidewall of the inner spacer 98 may be concave or convex. As an example, Figure 16A illustrates an embodiment in which the sidewall of the dummy region 72 is concave, the outer wall of the inner spacer 98 is concave, and the inner spacer 98 is recessed from the sidewall of the nanostructure 66. As another example, Figure 16B illustrates an embodiment in which the sidewalls of the dummy region 72 are concave, the outer sidewalls of the inner spacer 98 are flat, and the outer sidewalls of the inner spacer 98 are flush with the sidewalls of the nanostructure 66. Other configurations or sidewall profiles are also possible.

[0051] According to some embodiments, in Figures 17A-17E, epitaxial source / drain regions 100 are formed in the source / drain grooves 96 of the n-type region 50N and the source / drain grooves 96 of the p-type region 50P. The epitaxial source / drain regions 100 may also be referred to as "source / drain regions 100". For example, the epitaxial source / drain region 100 in the n-type region 50N may be referred to as "n-type source / drain region 100", and the epitaxial source / drain region 100 in the p-type region 50P may be referred to as "p-type source / drain region 100". The n-type source / drain region 100 may be formed before, after, or simultaneously with the formation of the p-type source / drain region 100. The epitaxial source / drain region 100 can be formed by epitaxial processes, such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar processes.

[0052] In some embodiments, a semiconductor layer 100' may be formed in the source / drain recess 96 before the epitaxial source / drain region 100 is formed in the source / drain recess 96. The semiconductor layer 100' may comprise, for example, undoped silicon or a similar material. Although the top surface of the semiconductor layer 100' is depicted as flat (e.g., planar), the top surface of the semiconductor layer 100' may be concave or convex. The top surface of the semiconductor layer 100' may be higher than, approximately flush with, or lower than the top surface of the fin 62. In some embodiments, the semiconductor layer 100' does not physically contact the inner spacers 98. In other embodiments, the semiconductor layer 100' may physically contact some of the sidewalls of the inner spacers 98. In some cases, the semiconductor layer 100' may be considered as part of the corresponding epitaxial source / drain region 100. In other embodiments, an insulating layer (not shown) may be deposited in the source / drain groove 96 before the epitaxial source / drain region 100 is formed in the source / drain groove 96.

[0053] In some embodiments, the epitaxial source / drain regions 100 apply stress to the channel regions of the nanostructures 66 within the n-type region 50N and / or the p-type region 50P, thereby improving performance. The epitaxial source / drain regions 100 are formed in the source / drain recesses 96 such that each dummy gate 84 of the p-type region 50P is disposed between corresponding adjacent pairs of epitaxial source / drain regions 100. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 100 from the dummy gates 84, and inner spacers 98 are used to separate the epitaxial source / drain regions 100 from the nanostructures 66 by an appropriate lateral distance, such that the epitaxial source / drain regions 100 do not short-circuit with the gates of the subsequently formed nanostructure field-effect transistors.

[0054] The epitaxial source / drain region 100 in the n-type region 50N can be formed by shielding the p-type region 50P. Then, the n-type source / drain region 100 is epitaxially grown in the source / drain groove 96 of the n-type region 50N. The n-type source / drain region 100 can contain any suitable material suitable for an n-type nanostructure field-effect transistor. For example, if the nanostructure 66 is silicon, the n-type source / drain region 100 can contain a material that applies tensile strain to the nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or similar materials.

[0055] The epitaxial source / drain region 100 in the p-type region 50P can be formed by shielding the n-type region 50N. Then, the p-type source / drain region 100 is epitaxially grown in the source / drain groove 96 in the p-type region 50P. The p-type source / drain region 100 can contain any suitable material suitable for a p-type nanostructure field-effect transistor. For example, if the nanostructure 66 is silicon, the p-type source / drain region 100 can contain a material that applies compressive strain to the nanostructure 66, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or similar materials.

[0056] The epitaxial source / drain regions 100, nanostructures 66, and / or substrates 50 can be implanted with doped material to form the source / drain regions, similar to the previously discussed processes for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration of about 1 × 10¹⁹ atoms / cm³ to about 1 × 10²¹ atoms / cm³. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 100 can be doped in situ during growth.

[0057] As a result of the epitaxial process for forming the epitaxial source / drain regions 100 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 100 has crystal faces that extend laterally beyond the sidewalls of the nanostructure 66. In some embodiments, adjacent epitaxial source / drain regions 100 remain separated after the epitaxial process is completed, as shown in Figure 17D. In other embodiments, these crystal faces cause adjacent epitaxial source / drain regions 100 of the same nanostructure field-effect transistor to merge, as shown in Figure 17E. In the embodiments shown in Figures 17D and 17E, fin spacers 94 may be formed on the top surface of the shallow trench isolation region 70 to block epitaxial growth. In some other embodiments, fin spacers 94 may cover portions of the sidewalls of the nanostructure 66 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the fin spacers 94 can be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the hard mask 52.

[0058] The n-type source / drain region 100 and / or the p-type source / drain region 100 may comprise one or more layers of semiconductor material. Any number of semiconductor material layers may be used in the epitaxial source / drain region 100. Each semiconductor material layer may be formed of a different semiconductor material and may be doped to different dopant concentrations. In an embodiment where the epitaxial source / drain region 100 comprises three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited over the first semiconductor material layer, and a third semiconductor material layer may be deposited over the second semiconductor material layer. In some embodiments, the first semiconductor material layer may have a dopant concentration smaller than that of the second semiconductor material layer and larger than that of the third semiconductor material layer. Other semiconductor material layers, dopant concentrations, or configurations thereof are possible.

[0059] In Figures 18A-18D, a first interlayer dielectric 104 is deposited over the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), hard mask 52, and / or dummy gate 84. The first interlayer dielectric 104 can be formed of a dielectric material, which can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. Suitable dielectric materials may include silica, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. Other insulating materials formed by any suitable process may be used. In some cases, the first interlayer dielectric 104 may extend below the top surface of the hard shield 52 and / or below the bottom surface of the epitaxial source / drain region 100.

[0060] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first interlayer dielectric 104 and the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), hard mask 52, and / or dummy gate 84. The contact etch stop layer 102 may be formed of a dielectric material with high etch selectivity for etching the first interlayer dielectric 104, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or similar materials, which may be formed using any suitable material deposition process, such as chemical vapor deposition, atomic layer deposition, or similar processes. In other embodiments, prior to the deposition of the contact etch stop layer 102 and the first interlayer dielectric 104, a planarization process (e.g., chemical mechanical polishing or grinding) is used to remove a portion of the mask 86 and the gate spacer 92 along the sidewalls of the mask 86.

[0061] According to some embodiments, in Figures 19A-19D, a removal process is performed to make the top surface of the first interlayer dielectric 104 flush with the top surfaces of the gate spacer 92 and the dummy gate 84. In some embodiments, the planarization process removes a portion of the mask 86 and the gate spacer 92 along the sidewalls of the mask 86. The removal process may include a planarization process, such as a chemical mechanical polishing process, a grinding process, an etch-back process, a combination of the foregoing, or a similar process. After the planarization process, the top surfaces of the first interlayer dielectric 104, the gate spacer 92, and the dummy gate 84 may be substantially flush or coplanar (within process variations). Thus, the top surface of the dummy gate 84 may be exposed via the first interlayer dielectric 104. In other embodiments, the planarization process does not remove the mask 86. In such an embodiment, after the planarization process, the first interlayer dielectric 104, gate spacer 92, and mask 86 can be substantially flush or coplanar (within process variations).

[0062] In some embodiments, a capping layer (not shown) is formed over the first interlayer dielectric 104. The capping layer can be formed, for example, by etching the first interlayer dielectric 104 using a suitable etching process, followed by depositing an insulating material over the structure. The insulating material may comprise one or more dielectric materials, such as silicon nitride, silicon oxynitride, or similar materials. A planarization process (e.g., chemical mechanical polishing or grinding) can then be performed to remove excess insulating material from over the structure, leaving the remaining insulating material over the first interlayer dielectric 104 to form the capping layer. In other embodiments, no capping layer is formed.

[0063] Figures 20A-26C illustrate intermediate steps in forming a transistor isolation region 116 (see Figures 26A-26C) according to some embodiments. The transistor isolation region 116 separates and isolates (e.g., "cuts") the subsequently formed gate structure. Thus, in some cases, the transistor isolation region 116 may be considered a gate isolation region or a similar component. In some cases, the transistor isolation region 116 may be considered a Cut Poly On Diffusion Edge (CPODE) structure or a similar component. The techniques described herein allow for the formation of the transistor isolation region 116 with a reduced risk of fin 62 damage and a reduced risk of parasitic transistor formation, as described in more detail below.

[0064] According to some embodiments, in Figures 20A-20C, a hard mask layer 106 is formed over the structure. The hard mask layer 106 may comprise one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, metal oxide, or similar materials. As shown in Figures 20A-20C, the hard mask layer 106 is deposited over the surfaces of the dummy gate 84, gate spacer 92, first interlayer dielectric 104, and contact etch stop layer 102. The deposition of the hard mask layer 106 can be performed using suitable processes, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar processes.

[0065] According to some embodiments, in Figures 21A-21C, an etched mask 108 is formed and patterned over the hard mask layer 106. The etched mask 108 may be a photoresist, a photoresist structure, or a similar component, and may be formed from a single layer or multiple layers. For example, in some embodiments, the etched mask 108 may be a two-layer or three-layer structure including a bottom anti-reflection coating (BARC) and / or a photoresist layer. The etched mask 108 may be patterned using suitable photolithography techniques to form an opening 110 that exposes the underlying hard mask layer 106. The opening 110 corresponds to the pattern of the subsequently formed transistor isolation region 116. Thus, the opening 110 may extend over the region of the dummy gate 84 that is subsequently replaced by the transistor isolation region 116. Figure 21A illustrates an opening 110 extending across two fins 62, but in other embodiments, the opening 110 may extend across only one fin 62 or may extend across more than two fins 62. The opening 110 may have sloping or tapering sidewalls (as shown in the figure), or it may have generally vertical sidewalls.

[0066] According to some embodiments, in Figures 22A-22C, one or more etching processes are performed to extend the opening 110 to the region below the dummy gate 84. In some embodiments, the opening 110 in the etch mask 108 is first transferred to the hard mask layer 106 using one or more etching steps. The etching steps may include suitable anisotropic etching processes. In this way, the hard mask layer 106 can be patterned, wherein the pattern corresponds to the subsequently formed transistor isolation region 116. In some embodiments, the opening 110 in the hard mask layer 106 exposes the region of the dummy gate 84. After the hard mask layer 106 is patterned, the etch mask 108 can be removed using suitable processes, such as etching processes, planarization processes (e.g., chemical mechanical polishing or grinding processes), combinations thereof, or similar processes.

[0067] According to some embodiments, the opening 110 in the hard mask layer 106 is then transferred to the dummy gate 84 using one or more etching processes. The etching process may include, for example, a dry etching process, which selectively etches the material of the dummy gate 84 at a faster rate than the materials of the hard mask layer 106, gate spacer 92, dielectric liner 42, and hard mask 52. In this way, the exposed area of ​​the dummy gate 84 can be removed without substantially etching other layers or materials of the structure. In some cases, the dielectric liner 42 may serve as an etch stop layer, protecting the nanostructure 66 and fin 62 from etching. In other embodiments, the etching process may thin or remove the area of ​​the hard mask 52 exposed by the removal of the dummy gate 84 area. After etching, the exposed sidewalls of the dummy gate 84 may be generally vertical (as shown), tapered, concave, and / or convex.

[0068] According to some embodiments, in Figures 23A-23C, the dielectric liner 42 and the dummy region 72 in the opening 110 are removed. Removing the dielectric liner 42 and the dummy region 72 exposes the nanostructure 66 previously surrounded by the removed area of ​​the dummy gate 84. The upper surfaces (e.g., top surface and / or sidewall surfaces) of the inner spacer 98 and fin 62 may also be exposed. In some embodiments, removing the dielectric liner 42 and the dummy region 72 may include performing an isotropic etching process, such as a wet etching process or a similar process. The etching process may use an etchant that is selective to the material of the dielectric liner 42 and the dummy region 72, while the nanostructure 66, fin 62, inner spacer 98, and hard mask 52 remain relatively unetched. Other etching processes are also possible.

[0069] By forming a hard mask 52 over the shallow trench isolation region 70 as described herein, the shallow trench isolation region 70 is protected from etching during the removal of the dummy region 72. In this way, the dummy region 72 can be removed without etching the shallow trench isolation region 70, which minimizes the risk of defects due to etching or damage to the shallow trench isolation region 70. For example, without the hard mask 52, isotropic etching for removing the dummy region 72 can laterally etch portions of the shallow trench isolation region 70 and remove portions of the shallow trench isolation region 70 near the fin 62 that are not within the opening. Removing the shallow trench isolation region 70 outside the opening 110 increases the risk of several problems, such as increased parasitic capacitance, damage to the fin 62 during subsequent etching processes, or the formation of parasitic transistors that reduce device performance. Therefore, using the hard mask 52 to block isotropic etching reduces the risk of defects, damage, or reduced device performance due to etching of the shallow trench isolation region 70. Additionally, the use of dielectric liner 42 as described herein allows for the selective etching of the dummy gate 84 region in a separate etching step prior to the subsequent etching of the nanostructure 66 and fin 62 (see Figures 24A–24C). Removing the dummy gate 84 in a separate selective etching step allows for reduced etching of the hard mask 52 and a more complete and uniform etching of the nanostructure 66 and fin 62, as described in more detail below.

[0070] According to some embodiments, in Figures 24A-24C, an etching process is performed to etch the nanostructure 66 and fin 62 in the opening 110. The etching process removes the exposed nanostructure 66 within the opening 110 and etches the exposed fin 62 within the opening 110. The etching process can be, for example, an anisotropic dry etching process that selectively etches the nanostructure 66, fin 62, and substrate 50, as described in more detail below. The etching of the fin 62 extends the opening 110 through the shallow trench isolation region 70 and can extend the opening 110 into the substrate 50, as shown in Figures 24A-24B. The exposed portion of the fin 62 can be completely removed by the etching process. Each etched fin 62 forms a separate extension of the opening 110 into the substrate 50. For example, two fins 62 exposed by opening 110 (e.g., shown in Figure 23A) are etched to form two corresponding extensions 110-1 and 110-2 in the substrate 50, as shown in Figure 24A. A hard mask 52 protects the top surface of the shallow trench isolation region 70 from the etching process, such that extensions 110-1 and 110-2 are separated by the area of ​​the hard mask 52 and the portion of the shallow trench isolation region 70 below the area of ​​the hard mask 52. Therefore, using a hard mask 52 over the shallow trench isolation region 70, as described herein, allows for improved control of the etched fins 62 and less loss of the shallow trench isolation region 70 during etching. This can allow for improved etching uniformity and reproducibility, and reduce the chance of defects or damage.

[0071] In some embodiments, the anisotropic etching process for removing nanostructure 66 and / or fins 62 is a plasma dry etching process. In some embodiments, a gas source containing HBr or similar materials can be used to perform the etching process. In some embodiments, during the etching process, other gases such as Cl2, BCl3, O2, CO2, similar materials, or combinations thereof can be added to the gas source to adjust various aspects of the etching process, such as etching rate, etching selectivity (e.g., selectivity between silicon and silicon oxide), and / or etching profile.

[0072] During the etching process, a gas source is ignited into plasma using a plasma etching tool. The plasma etching tool can use an inductively coupled plasma (ICP) / dipole antenna, but other types of plasma tools may also be used. In some embodiments, the radio frequency (RF) power generator of the plasma etching tool generates an RF power source (e.g., an RF signal) of 13.56 MHz or 27 MHz. The etching process can be performed at pressures ranging from about 3 mTorr to about 150 mTorr and temperatures ranging from about 20°C to about 200°C. The power of the RF power source can range from about 100 W to about 2500 W. In some embodiments, the etching process uses pulsed plasma etching technology, wherein the duty cycle of the RF power source is about 5% to 100%. In some embodiments, the etching process includes an RF bias power ranging from about 10 W to about 1200 W. Other process parameters are also possible.

[0073] In some embodiments, to protect the hard mask 52 and maintain the size of the opening 110 during the etching process, a passivation layer is formed (e.g., conformally) above the upper surface of the hard mask 52 and along the sidewalls and bottom of the opening 110. The passivation layer may also be formed on the surface of the nanostructure 66 during removal of the nanostructure 66 and / or on the surface of the fin 62 during removal of the fin 62. The passivation layer may be, for example, a carbon-based passivation layer formed by injecting CH4 into the plasma etching tool during the etching process. A carrier gas (e.g., Ar or N2) may be used to carry the CH4 into the plasma etching tool. In some embodiments, the passivation layer is a SiO-based passivation layer formed by injecting SiCl4 and O2 gases (e.g., simultaneously or sequentially) into the plasma etching tool during the etching process. A carrier gas (e.g., Ar or N2) may be used to carry the SiCl4 and O2 into the plasma etching tool. In some embodiments, additional chemicals, such as HBr or similar materials, are injected together with SiCl4 into the plasma etching tool chamber to promote the dissociation of SiCl4 during the SiO-based passivation layer formation process. The bromine produced by the chemical reaction can further react with SiO2 to form SiBrO. Therefore, in some cases, the composition of the SiO-based passivation layer may include SiBrO.

[0074] After the passivation layer is formed, a through-etching step is performed to remove the passivation layer from the etch leading edge (e.g., from the surface of nanostructure 66, from the surface of fin 62, and / or from the surface of fin 62), so that subsequent etching steps can be performed to remove nanostructure 66 and / or fin 62. In some embodiments, the through-etching step is an anisotropic etching process (e.g., a plasma etching process) using a gas source containing CF4, CHF3, CH2F2, C4F4, similar materials, or combinations thereof. After the through-etching step, the passivation layer at the bottom of opening 110 is removed, while the sidewalls of opening 110 may remain covered by the passivation layer.

[0075] In some embodiments, the etching process for removing the nanostructure 66 and / or fin 62 in the opening 110 includes multiple etching cycles, each of which includes the following three sequential processing steps: 1) forming a passivation layer (e.g., a carbon-based or SiO-based passivation layer) on the hard mask 52 and along the sidewalls and bottom of the opening 110; 2) performing a through-etching step to remove the passivation layer from the etch front; and 3) performing an etching process to remove the nanostructure 66 and / or fin 62.

[0076] In some embodiments, the depth D1 of the opening 110, measured from the top surface of the nanostructure 66, ranges from about 140 nm to about 250 nm, but other depths D1 are also possible. In some embodiments, the bottom surface of the opening 110 is located at or below the bottom surface of the shallow trench isolation region 70. In some embodiments, the etching process thins the exposed hard mask 52 region in the opening. For example, after the etching process, the thickness T2 of the exposed region of the hard mask 52 may be less than the thickness T1 of the unetched hard mask 52 (see Figure 8C). For example, the thickness T2 may range from about 1 nm to about 10 nm. Other thicknesses are also possible. After etching, the exposed region of the hard mask 52 may have a flat, convex, and / or concave top surface. In some cases, the thickness T2 of the central portion of the hard mask 52 may be greater than the thickness T2 at the sidewalls of the hard mask 52. Some additional features of the opening formed by the etching process are described below with reference to Figures 32A-34B.

[0077] In some cases, the geometry of the opening 110 can form a wider region 111 of the opening 110 within the fin 62 during the etching process. The extension of the opening 110 below the hard mask 52 (e.g., extension 110-1 or 110-2) is narrower than the opening 110 above the hard mask 52. This narrowing of the opening 110 can increase the etchant flux density and / or etchant pressure in the region of the opening 110 below and near the top surface of the hard mask 52 when the fin 62 is etched. In some cases, the wider region 111 is formed near the top surface of the shallow trench isolation region 70. The increased etchant density and / or pressure can lead to further etching of the fin 62 in these regions, thus forming the wider region 111. Figure 24B illustrates an example of a wider region 111 of the opening 110. The wider region 111 is the area of ​​the opening 110 within the fin 62, and the areas of the opening 110 above and below the wider region 111 are relatively wide. The relatively large width of the wider region 111 can be measured along the longitudinal direction of the fin 62.

[0078] In some embodiments, the width W1 between the opposing nanostructures 66 of the sidewalls of the opening 110 can range from about 17 nm to about 23 nm. In some embodiments, the width W2 of the wider region 111 can range from about 25 nm to about 35 nm. The width W2 can be about 110% to about 220% of the width W1. In some embodiments, the maximum width W2 of the wider region 111 can be a distance D2 from the top surface of the nanostructure 66, and the distance D2 ranges from about 60 nm to about 75 nm. In some embodiments, the vertical span D3 of the wider region 111 can range from about 40 nm to about 70 nm. Other distances, shapes, positions, sizes, or dimensions are also possible. In some embodiments, the top of the wider region 111 can be on or near the top surface of the hard mask 52. In other embodiments, the top of the wider region 111 can be above the hard mask 52 (e.g., further away from the substrate 50 than the hard mask 52) or below the hard mask 52 (e.g., closer to the substrate 50 than the hard mask 52). In some embodiments, the wider region 111 may extend below the epitaxial source / drain region 100 or into the substrate 50. For example, the size and location of the wider region 111 may be controlled by controlling the thickness of each layer, such as the hard mask 52, the shallow trench isolation region 70, or the fin 62, or by controlling the etching parameters. In some embodiments, the wider region 111 is not formed.

[0079] According to some embodiments, in Figures 25A-25C, a liner 112 and a dielectric filler 114 are deposited in the opening 110. The liner 112 and dielectric filler 114 are deposited as part of forming the transistor isolation region 116, as described below. In some embodiments, the liner 112 is conformally deposited on the surface in the opening 110, including the surfaces of the dummy gate 84, hard mask 52, shallow trench isolation region 70, fin 62, and substrate 50 exposed by the opening 110. The liner 112 may also be deposited on other surfaces in the opening 110, such as the surfaces of the gate spacer 92, inner spacer 98, and nanostructure 66. In some embodiments, the liner 112 is also deposited over the top surface and sidewalls of the hard mask layer 106. The dielectric filler 114 is then deposited on the liner 112 to fill the opening 110. The materials for the liner 112 and dielectric filler 114 can be selected from suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbon nitride, similar materials, or combinations thereof. For example, in some embodiments, the liner 112 comprises silicon oxide and the dielectric filler 114 comprises silicon nitride. Other materials or combinations of materials are also possible. The liner 112 and dielectric filler 114 can be formed using suitable techniques, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar techniques. In other embodiments, the liner 112 may be omitted. In other embodiments, an additional dielectric layer may be deposited on the liner 112 and / or dielectric filler 114 as part of forming the transistor isolation region 116.

[0080] According to some embodiments, in Figures 26A-26C, a planarization process is performed to remove excess substrate 112 and dielectric filler 114 and form transistor isolation region 116. The planarization process may include chemical mechanical polishing, grinding, or similar processes. In some embodiments, the planarization process removes hard masking layer 106 and substrate 112, as well as dielectric filler 114 above hard masking layer 106. The remaining portion of substrate 112 and dielectric filler 114 forms transistor isolation region 116. In some embodiments, after the planarization process, the top surfaces of transistor isolation region 116, dummy gate 84, gate spacer 92, and first interlayer dielectric 104 are substantially flush or coplanar. In embodiments where a capping layer (described above with respect to Figures 19A-19D) is formed above first interlayer dielectric 104, the planarization process may expose the top surface of the capping layer or may remove the capping layer. In some cases, because the wider region 111 extends laterally near the epitaxial source / drain region 100, the dielectric material of the transistor isolation region 116 within the wider region 111 can reduce the parasitic capacitance of the nearby epitaxial source / drain region 100. Thus, the wider region 111 forming the transistor isolation region 116 can improve device performance.

[0081] According to some embodiments, in Figures 27A-27C, the dummy gate 84 is removed in one or more etching steps. Removing the dummy gate 84 forms a groove 118 between the gate spacers 92. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases, which selectively etches the material of the dummy gate 84 at a faster rate than the material of the first interlayer dielectric 104, the gate spacers 92, and the transistor isolation region 116. In other embodiments, a selective wet etching process may be used to remove the dummy gate 84. During removal, the dielectric liner 42 and / or the hard mask 52 may be used as an etch stop layer when etching the dummy gate 84.

[0082] According to some embodiments, in figures 28A-28C, the dummy region 72 is removed, and the groove 118 is extended. In some embodiments, the exposed area of ​​the dielectric liner 42 is also removed along with the dummy region 72. Removing the dielectric liner 42 and the dummy region 72 may comprise an isotropic wet etching process or a similar process. The etching process may use an etchant selective to the materials of the dielectric liner 42 and the dummy region 72, while the nanostructure 66 remains relatively unetched. A hard mask 52 protects the shallow trench isolation region 70 from the effects of the etching process. A capping layer (if present) may protect the first interlayer dielectric 104 from the effects of the etching process.

[0083] The dummy material 71 of the dummy region 72 can be completely removed, or residues of the dummy material 71 can remain on some sidewall portions of the inner spacer 98 in the recess 118 (see, for example, Figure 30). After the dummy region 72 is removed, each recess 118 exposes a portion of the nanostructure 66, which serves as a channel region in the subsequently completed nanostructured field-effect transistor. The portions of the nanostructure 66 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 100.

[0084] According to some embodiments, in Figures 29A-29C, a gate dielectric layer 120 and a gate electrode 122 are formed to replace the gate structure. The gate dielectric layer 120 is conformally deposited in the groove 118. The gate dielectric layer 120 can be formed on the top surface and sidewalls of the substrate 50 and on the exposed top surface, sidewalls, and bottom surface of the nanostructure 66. The gate dielectric layer 120 can also be deposited on the top surface of the first interlayer dielectric 104, the contact etch stop layer 102, the gate spacer 92, and / or the shallow trench isolation region 70. Because the transistor isolation region 116 is formed prior to the gate structure, the gate dielectric layer 120 is deposited on the sidewalls of the transistor isolation region 116. For example, the gate dielectric layer 120 can be deposited along the liner 112 at the sidewalls of the transistor isolation region 116, as shown in Figure 29A.

[0085] According to some embodiments, the gate dielectric layer 120 comprises one or more dielectric layers, such as oxides, metal oxides, similar materials, or combinations thereof. For example, in some embodiments, the gate dielectric layer 120 may comprise a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 120 comprises a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 120 may have a dielectric constant greater than about 7.0, and may comprise metal oxides or silicides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 120 in the n-type region 50N and the p-type region 50P may be the same or different. The method of forming the gate dielectric layer 120 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, and similar processes.

[0086] Multiple gate electrodes 122 are deposited over multiple gate dielectric layers 120, respectively, and the remaining portion of the groove 118 is filled. The gate electrodes 122 may contain metallic materials, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the aforementioned multilayer structures. For example, although a single-layer gate electrode 122 is shown in Figures 29A and 29B, the gate electrode 122 may contain any number of substrates, any number of work function adjustment layers, and filler material. Any combination of layers constituting the gate electrode 122 may be deposited over the surface of the nanostructure 66.

[0087] The formation of the gate dielectric layer 120 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 120 in each region is formed of the same material, and the formation of the gate electrode 122 can occur simultaneously, such that the gate electrode 122 in each region is formed of the same material. In some embodiments, the gate dielectric layer 120 in each region can be formed by different processes, such that the gate dielectric layer 120 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 122 in each region can be formed by different processes, such that the gate electrode 122 can be made of different materials and / or have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose appropriate areas.

[0088] After filling the groove 118, a planarization process, such as a chemical mechanical polishing process, can be performed to remove excess material from the gate electrode 122 and the gate dielectric layer 120, which are located above the top surface of the first interlayer dielectric 104. The remaining material of the gate electrode 122 and the gate dielectric layer 120 thus forms a replacement gate structure of the resulting nanostructured field-effect transistor. The gate electrode 122 and the gate dielectric layer 120 can be collectively referred to as the gate structure or gate stack. A transistor isolation region 116 separates and isolates the area of ​​the gate structure, as shown in Figure 29A.

[0089] Figure 30 illustrates a detailed view of the various elements of Figure 29B, including epitaxial source / drain region 100, gate dielectric layer 120, gate electrode 122, nanostructure 66, and inner spacer 98. The view in Figure 30 may be an enlarged view of a portion of a nanostructured field-effect transistor in an n-type region 50N or a p-type region 50P, and may resemble region 30 shown in Figure 29B. In some embodiments, as shown in Figure 30, residue of dummy material 71 may remain on the inner spacer 98, for example, between the inner spacer 98 and the gate dielectric layer 120. For example, dummy region 72 may not be completely removed, and gate dielectric layer 120 may be formed on the remaining dummy material 71 of dummy region 72. Because dummy material 71 is an insulating material (e.g., silicon oxide or a similar material), the remaining residue does not significantly affect the electrical properties of the resulting device.

[0090] According to some embodiments, in Figures 31A-31D, a second interlayer dielectric 126 is deposited over the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric 104, and the gate structure. In some embodiments, the second interlayer dielectric 126 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric 126 is formed of a dielectric material, such as phospholipid glass, borosilicate glass, boron-doped phospholipid glass, undoped silicate glass, or similar materials, which can be formed by any suitable deposition process, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar processes.

[0091] In some embodiments, an etch stop layer (ESL) 124 is formed prior to the deposition of the second interlayer dielectric 126. The etch stop layer 124 may be formed of a dielectric material that has high etch selectivity for etching the second interlayer dielectric 126, such as silicon nitride, silicon oxide, silicon oxynitride, or similar materials, which may be formed by any suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or similar processes.

[0092] In other embodiments, the gate structure (including the gate dielectric layer 120 and the corresponding upper gate electrode 122) is etched such that the groove (not shown separately) is formed directly above the gate structure between opposing portions of the gate spacer 92. A gate mask (not shown separately) comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or similar materials) may be filled into the groove, followed by a planarization process to remove excess dielectric material. The subsequently formed gate contacts (e.g., gate contact 132 discussed below) penetrate the gate mask to contact the top surface of the recessed gate electrode 122.

[0093] Further in Figures 31A to 31D, a gate contact 132 and a source / drain contact 134 are formed to contact the gate electrode 122 and the epitaxial source / drain region 100, respectively. The gate contact 132 can be physically and electrically coupled to the gate electrode 122. The source / drain contact 134 can be physically and electrically coupled to the epitaxial source / drain region 100.

[0094] As an example of forming the gate contact 132 and the source / drain contact 134, an opening for the gate contact 132 is formed through the second interlayer dielectric 126 and the etch stop layer 124, and an opening for the source / drain contact 134 is formed through the second interlayer dielectric 126, the etch stop layer 124, the first interlayer dielectric 104, the contact etch stop layer 102, and the capping layer (if present). Suitable photolithography and etching techniques can be used to form the openings. A pad (not shown separately) of, for example, a diffusion barrier layer, an adhesive layer, and similar layers, as well as a conductive material, is formed in the openings. The pad may contain titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or similar materials. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric 126. The remaining liner and conductive material form the gate contact 132 and the source / drain contact 134 in the opening. The gate contact 132 and the source / drain contact 134 can be formed in different processes or in the same process. Although illustrated as being formed in the same cross-section, it should be understood that each of the gate contact 132 and the source / drain contact 134 can be formed in different cross-sections to avoid short circuits.

[0095] Optionally, a metal-semiconductor alloy region 133 is formed at the interface between the epitaxial source / drain region 100 and the source / drain contact 134. The metal-semiconductor alloy region 133 may be a silicate region formed by metal silicates (e.g., titanium silicate, cobalt silicate, nickel silicate, etc.), a germanide region formed by metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silica-germanide region formed by both metal silicates and metal germanides, or a similar region. The metal-semiconductor alloy region 133 may be formed by depositing metal in the opening of the source / drain contact 134 before the material of the source / drain contact 134, followed by a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon carbide, silicon germanium, germanium, etc.) of the epitaxial source / drain region 100 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be formed by a deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. After a thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings of the source / drain contact 134 (e.g., from the surface of the metal-semiconductor alloy region 133). Then, some of the material of the source / drain contact 134 can be formed on the metal-semiconductor alloy region 133.

[0096] In some cases, the etching process described above for removing the nanostructure 66 and fin 62 from the opening 110 as per Figures 24A-24C can produce different characteristics depending on the width of the fin 62. Some examples are described below with reference to Figures 32A-34B. Figures 32A, 33A, and 34A show cross-sectional views before etching the nanostructure 66 and fin 62, similar to Figure 23A. Figures 32B, 33B, and 34B show cross-sectional views after etching the nanostructure 66 and fin 62, similar to Figure 24A. In each of Figures 32A, 33A, and 34A, only one fin 62 is exposed and etched by the opening 110, referred to as fin 62A, fin 62B, and fin 62C, respectively. Fins 62A-C are similar to the other fins 62 described herein. The nanostructure 66, fin 62 and their etching intentions in Figures 32A-34B are illustrative examples, and other configurations, sizes or etching results are also possible.

[0097] Figures 32A and 32B illustrate the etching of fin 62A according to some embodiments. For example, fin 62A may have a width WA of about 60 nm or more. The width of the nanostructure 66 above fin 62A is correspondingly similar to the width WA. Figure 32B illustrates the structure after fin 62A is removed using an etching process similar to that described in Figure 24A. As shown in Figure 32B, removing fin 62A forms an extension 110-A from opening 110 into substrate 50. In some cases, the width of extension 110-A may be approximately the same as the width WA. Similar to the process described in Figures 25A-26C, a substrate 112 and dielectric filler 114 may be deposited in opening 110 to form a transistor isolation region 116.

[0098] It should be noted that the extension 110-A includes two protruding regions 110' at the bottom corner of the extension 110-A. The protruding regions 110' are cut-out areas near the sidewalls (e.g., edges) of the extension 110-A, extending deeper than the areas away from the sidewalls of the extension 110-A. For example, the protruding regions 110' can be formed by an etching process that etches the sides of the nanostructure 66 and fin 62A at a faster rate than the central region of the nanostructure 66 and fin 62A. In some embodiments, the depth D4 of the protruding regions 110' can be in the range of about 3 nm to about 15 nm, or the width WP can be in the range of about 15 nm to about 35 nm. Other depths, widths, or other dimensions are possible, and the size of the protruding regions 110' can depend on the width WA of the fin 62 (e.g., fin 62A). For example, in some cases, for a larger fin 62 width (e.g., a larger width WA), the depth and / or width of the protruding regions 110' can be larger. In some embodiments, the size of the protrusion 110' can be controlled by controlling the etching process parameters. Therefore, the subsequently formed transistor isolation region 116 may include a protrusion corresponding to the protrusion 110'. In some cases, the protrusion 110' is not formed. In some cases, as described herein, removing the dummy gate 84 in a separate selective etching step before removing the nanostructure 66 and fin 62 can allow for more uniform, consistent, and complete removal of the fin 62. This can allow for more uniform and reproducible subsequent formation of the transistor isolation region 116, which can improve the isolation provided by the transistor isolation region 116.

[0099] Figures 33A and 33B illustrate the etching of fin 62B according to some embodiments, wherein the width WB of fin 62B is smaller than the width WA of fin 62A. For example, the width WB of fin 62B can be in the range of about 20 nm to about 60 nm. The width of nanostructure 66 above fin 62B is correspondingly similar to the width WB. Figure 33B illustrates the structure after fin 62B is removed using an etching process similar to that described in Figure 24A. As shown in Figure 33B, removing fin 62B forms an extension 110-B from opening 110 into substrate 50. In some cases, the width of extension 110-B can be approximately the same as the width WB. Similar to extension 110-A, protrusion 110' can be formed in extension 110-B. In Figures 33A-33B, the width WB of fin 62B is large enough that the resulting protrusion 110' is separated by raised areas. Similar to the process described in Figures 25A-26C, a liner 112 and dielectric filler 114 can be deposited in the opening 110 to form a transistor isolation region 116.

[0100] Figures 34A and 34B illustrate the etching of fin 62C according to some embodiments, where the width WC of fin 62C is smaller than the width WB of fin 62B. For example, the width WC of fin 62C can be less than about 20 nm. The width of the nanostructure 66 above fin 62C is correspondingly similar to the width WC. Figure 34B illustrates the structure after fin 62C is removed using an etching process similar to that described in Figure 24A. As shown in Figure 34B, removing fin 62B forms an extension 110-C from opening 110 into substrate 50. In Figures 34A-34B, the width WC of fin 62C is small enough that the resulting protrusions 110' overlap and may be indistinguishable. In some cases, small protrusions may exist near the center of extension 110-C. Similar to the process described in Figures 25A-26C, a liner 112 and dielectric filler 114 can be deposited in the opening 110 to form a transistor isolation region 116.

[0101] Several advantages can be achieved in the embodiments. The techniques described herein allow for improved transistor isolation region formation with reduced risk of defects or damage. By forming a hard mask over the shallow trench isolation region, the shallow trench isolation region can be protected from unwanted etching during transistor isolation region formation. This reduces the risk of nearby fins being etched and damaged. In addition, reducing etching of the shallow trench isolation region near the fins can reduce the formation of parasitic transistors after the dielectric material of the transistor isolation region is deposited. In this way, yield and device performance can be improved. Furthermore, using multiple selective etchings to remove dummy gates, dummy regions, nanostructures, and fins allows for more uniform and complete removal during transistor isolation region formation.

[0102] In one embodiment, a method includes forming a fin over a substrate; forming a first isolation region over the substrate; forming a hard mask over the first isolation region, wherein the fin protrudes from the hard mask; forming a dummy nanostructure over the fin; removing the dummy nanostructure; removing a portion of the fin to form an opening extending through the hard mask and the first isolation region; forming a second isolation region over the hard mask and in the opening; and forming a gate structure along the sidewall of the second isolation region. In one embodiment, the first isolation region is an oxide and the hard mask is a nitride. In one embodiment, this method includes forming the first nanostructure over the fin, wherein removing a portion of the fin removes the first nanostructure. In one embodiment, forming the dummy nanostructure over the fin includes: forming a second nanostructure over the fin; and replacing the second nanostructure with a dielectric region. In one embodiment, removing the dummy nanostructure includes performing an isotropic wet etching process. In one embodiment, this method includes forming a dummy gate over the hard mask, the dummy nanostructure, and the fin. In one embodiment, the second isolation region extends on the top surface of the hard mask. In one embodiment, forming the hard mask includes: depositing a hard mask material over the first isolation region and the fin; and removing the upper portion of the hard mask material.

[0103] In one embodiment, a method includes forming a first fin over a substrate; forming a first nanostructure and a second nanostructure over the first fin; forming an isolation region surrounding the first fin; forming a protective layer over the isolation region; forming a dummy gate over the protective layer, the first fin, the first nanostructure, and the second nanostructure; performing a first selective etching process to form an opening in the dummy gate over the first fin; performing a second selective etching process in the opening to remove the second nanostructure; performing a third selective etching process in the opening to remove the first nanostructure and the first fin; and filling the opening with an insulating material. In one embodiment, this method includes depositing a dielectric liner over the isolation region, the first fin, the first nanostructure, and the second nanostructure before forming the protective layer. In one embodiment, the dielectric liner comprises silicon oxide. In one embodiment, the first selective etching process selectively etches the material of the dummy gate from the material of the protective layer. In one embodiment, the second selective etching process selectively etches the material of the second nanostructure over the material of the protective layer. In one embodiment, the second selective etching process thins the protective layer. In one embodiment, the second nanostructure comprises silicon oxide.

[0104] In one embodiment, a device includes a first fin and a second fin above a substrate; an isolation region surrounding the first and second fins; a hard shield above the isolation region and surrounding the first and second fins; a nanostructure above the first fin; an isolation structure extending over the hard shield and through the second fin to the substrate; and a gate structure on a first sidewall of the hard shield, the first fin, the nanostructure, and the isolation structure. In one embodiment, the widest portion of the isolation structure is located below the top surface of the second fin. In one embodiment, the isolation structure is separated from the first fin by the isolation region. In one embodiment, the isolation region and the hard shield are different dielectric materials. In one embodiment, a first portion of the isolation structure near the second sidewall of the isolation structure protrudes more into the substrate than a second portion of the isolation structure away from the second sidewall of the isolation structure.

[0105] The foregoing summary of components in several embodiments enables those skilled in the art to better understand various aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions, and adjustments without departing from the spirit and scope of the embodiments of the present invention. [Simplified Explanation of the Diagram]

[0007] The aspects of embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, many components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various components may be arbitrarily increased or decreased. Figure 1 illustrates an example of a three-dimensional view of a nanostructured field-effect transistor according to some embodiments. Figures 2, 3, 4, 5, 6, 7, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 11C, 11D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 17C, 17D, 17E, 18A, 18B, 18C, 18D, 19A, 19B, 19C, 19D, 20A, 20B, 20 Figures C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, 29A, 29B, 29C, 30, 31A, 31B, 31C, and 31D illustrate cross-sectional views of intermediate stages in the fabrication of nanostructured field-effect transistors according to some embodiments. Figures 32A and 32B illustrate cross-sectional views of intermediate stages in the fabrication of transistor isolation structures according to some embodiments. Figures 33A and 33B illustrate cross-sectional views of intermediate stages in the fabrication of transistor isolation structures according to some embodiments. Figures 34A and 34B illustrate cross-sectional views of intermediate stages in the fabrication of transistor isolation structures according to some embodiments.

Claims

1. A method for forming a semiconductor device, comprising: A fin is formed above a base; A first isolation zone is formed above the base; A hard shield is formed above the first isolation region, from which the fin protrudes; a plurality of dummy nanostructures are formed above the fin; the dummy nanostructures are removed; a portion of the fin is removed to form an opening extending through the hard shield and the first isolation region; a second isolation region is formed above the hard shield and in the opening, wherein the widest portion of the second isolation region is located below the top surface of the fin; and a gate structure is formed along the sidewall of the second isolation region.

2. A method of forming a semiconductor device as claimed in claim 1, wherein the first isolation region is an oxide and the hard mask is a nitride.

3. A method for forming a semiconductor device as claimed in claim 1, wherein forming the dummy nanostructures above the fins comprises: Multiple second nanostructures are formed above the fin; And replacing these second nanostructures with multiple dielectric regions.

4. A method for forming a semiconductor device as described in any one of claims 1 to 3, wherein removing the dummy nanostructures includes performing an isotropic wet etching process.

5. A method of forming a semiconductor device as described in any one of claims 1 to 3, wherein the second isolation region extends on the top surface of the hard mask.

6. A method for forming a semiconductor device as described in any one of claims 1 to 3, wherein forming the hard mask comprises: A hard masking material is deposited in the first isolation zone and above the fin; And remove multiple upper portions of the hard mask material.

7. A method for forming a semiconductor device, comprising: A first fin is formed above a base; A plurality of first nanostructures and a plurality of second nanostructures are formed above the first fin; an isolation region is formed around the first fin; a protective layer is formed above the isolation region; a dummy gate is formed above the protective layer, the first fin, the first nanostructures, and the second nanostructures; a first selective etching process is performed to form an opening in the dummy gate above the first fin; a second selective etching process is performed in the opening to remove the second nanostructures; a third selective etching process is performed in the opening to remove the first nanostructures and the first fin; and the opening is filled with an insulating material, wherein the widest portion of the insulating material is located below the top surface of the first fin.

8. The method of forming a semiconductor device as claimed in claim 7 further includes depositing a dielectric substrate over the isolation region, the first fin, the first nanostructures and the second nanostructures prior to forming the protective layer.

9. A method for forming a semiconductor device as claimed in claim 8, wherein the dielectric substrate comprises silicon oxide.

10. A method of forming a semiconductor device as claimed in any one of claims 7 to 9, wherein the first selective etching process selectively etches the material of the dummy gate from the material of the protective layer, and the second selective etching process selectively etches the material of the second nanostructure above the material of the protective layer.

11. A semiconductor device, comprising: A first fin and a second fin are located above a base; An isolation zone surrounds the first fin and the second fin; A rigid shield above the isolation area and surrounding the first fin and the second fin; a plurality of nanostructures above the first fin; an isolation structure extending over the rigid shield and through the second fin to the substrate, wherein the widest portion of the isolation structure is located below the top surface of the second fin; and a gate structure on a first sidewall of the rigid shield, the first fin, the nanostructures and the isolation structure.

12. The semiconductor device as claimed in claim 11, wherein the isolation structure is separated from the first fin by the isolation region.

13. The semiconductor device as claimed in claim 11, wherein the isolation region and the hard shield are different dielectric materials.

14. The semiconductor device as claimed in claim 11, wherein a first portion of the isolation structure near a second sidewall of the isolation structure protrudes more into the substrate than a second portion of the isolation structure away from the second sidewall of the isolation structure.

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