Semiconductor device and method of forming the same

Abstract

A method for forming a semiconductor device includes: forming a fin-like structure with protrusions above a substrate, the fin-like structure including fins and layers of interlaced first and second semiconductor materials located on the fins; forming shallow trench isolation regions on both sides of the fin-like structure; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation regions; forming a dummy gate structure on the fin-like structure; forming a source / drain opening in the fin-like structure to expose the first and second semiconductor materials; replacing the first semiconductor material under the dummy gate structure as a sacrificial material; and forming a source / drain region in the source / drain opening after the replacement step; and removing the sacrificial material and replacing the dummy gate structure as a replaced gate structure after forming the source / drain region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to shallow trench isolation protection structures for semiconductor devices. [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, or the like) to integrate more components into a given area. However, as the minimum structural dimensions decrease, additional problems arise that need to be addressed. [Summary of the Invention]

[0004] In one embodiment, a method of forming a semiconductor device includes: forming a fin structure with protrusions higher than a substrate, wherein the fin structure includes fins and a layered stack located on the fins, wherein the layered stack includes multiple layers of interleaved first semiconductor material and second semiconductor material; forming a plurality of shallow trench isolation regions on both sides of the fin structure; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation regions; after forming the shallow trench isolation protection structure, forming a dummy gate structure on the fin structure; forming a plurality of source / drain openings in the fin structure on both sides of the dummy gate structure, wherein the source... / The source / drain opening exposes a first semiconductor material and a second semiconductor material; after forming the source / drain opening, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material; after the replacement step, a plurality of source / drain regions are formed in the source / drain opening; after forming the source / drain regions, the dummy gate structure is removed to expose a first portion of the sacrificial material and the second semiconductor material; the exposed sacrificial material is removed, wherein after removing the exposed sacrificial material, the first portion of the second semiconductor material is retained to form a plurality of channel regions of the semiconductor device; and a gate dielectric material and a gate material are formed around the channel regions.

[0005] In one embodiment, a method of forming a semiconductor device includes forming a fin structure protruding above a plurality of shallow trench isolation regions, wherein the shallow trench isolation regions are located on a substrate and on both sides of the fin structure, wherein the fin structure includes fins and layered stacks located on the fins, wherein the layered stacks include a plurality of layers of interleaved first semiconductor materials and second semiconductor materials; covering the upper surface of the shallow trench isolation regions with a shallow trench isolation protection structure, wherein the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer; after the covering step, forming a dummy gate on the fin structure; forming a plurality of source / drain openings on the dummy gate. In the fin-like structures on both sides of the gate; after forming the source / drain openings, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material; after the replacement step, a plurality of source / drain regions are formed in the source / drain openings; an interlayer dielectric layer is formed above the source / drain regions and around the dummy gate; the dummy gate is removed to form a gate trench in the interlayer dielectric layer; wherein the gate trench exposes a first portion of the sacrificial material and the second semiconductor material; the exposed sacrificial material is selectively removed, wherein the first portion of the second semiconductor material after the selective removal step forms a plurality of nanostructures; and a replacement gate structure is formed around these nanostructures.

[0006] In one embodiment, the semiconductor device includes a substrate; fins protruding above the substrate; shallow trench isolation regions located on both sides of the fins; a shallow trench isolation protection structure extending along and contacting the upper surface of the shallow trench isolation regions; a plurality of source / drain regions located on the fins; a plurality of nanostructures located above the fins and between the source / drain regions; and a gate structure located between the source / drain regions and around the nanostructures.

Implementation Method

[0008] The following detailed description is illustrated in conjunction with the accompanying drawings to facilitate understanding of various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] It is understood that the different embodiments or examples provided below may implement different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the invention. For example, a description of forming a first component on a second component includes situations where the two are in direct contact, or where the two are spaced apart by other additional components rather than in direct contact.

[0010] Furthermore, spatial relative terms such as "below," "below," "lower," "above," "above," or similar terms may be used to simplify the description of the relative relationship between one element and another element in the illustration. Spatial relative terms may be extended to elements used in other directions, rather than being limited to the illustrated direction. Elements may also be rotated 90 degrees or other angles, therefore directional terms are only used to describe the direction in the illustration. In the contents disclosed herein, unless otherwise stated, the same or similar reference numerals in different drawings refer to the same or similar components formed using the same or similar materials through the same or similar forming processes. In addition, drawings with the same numbers but different letters (as shown in Figures 12A to 12C) represent different views of the apparatus at the same process stage.

[0011] The disclosed embodiments relate to a shallow trench isolation protection structure formed on a shallow trench isolation region of a nanostructure field-effect transistor device. The shallow trench isolation protection structure can protect the shallow trench isolation region (e.g., the portion directly below a dummy gate structure) during the selective etching of a one-time material in a one-time oxide interposer process used to form the nanostructure field-effect transistor device. In some embodiments, a fin-like structure protruding above the substrate is formed, and shallow trench isolation regions are located on both sides of the fin-like structure. The fin-like structure includes fins and layered stacks on the fins, wherein the layered stacks include layers of interleaved first and second semiconductor materials. The shallow trench isolation protection structure is then formed on the upper surface of the shallow trench isolation region. In one embodiment, the shallow trench isolation protection structure includes a pad layer and a hard mask layer on the pad layer. The disclosed plasma chemical vapor deposition process can form a hard mask layer of inconsistent thickness to facilitate the formation of the shallow trench isolation protection structure. Next, a dummy gate structure is formed on the fin structure, and source / drain openings are formed on both sides of the dummy gate structure. Then, the first semiconductor material in the layered stack and beneath the dummy gate structure is replaced with a sacrificial material such as oxide. Next, source / drain regions are formed in the source / drain openings. Then, a gate replacement process is used to replace the dummy gate structure into a gate replacement structure. During a selective etching process that removes the sacrificial material to release the second semiconductor material and form the nanostructure, the shallow trench isolation protection structure protects the portion of the shallow trench isolation region directly beneath the dummy gate structure from the selective etching process, thus avoiding or reducing shallow trench isolation region loss caused by selective etching. The advantages of using a shallow trench isolation protection structure include reduced parasitic capacitance of the gate replacement structure, improved device performance, and improved production yield.

[0012] Figure 1 is a three-dimensional view of a nanostructured field-effect transistor device 30 in some embodiments. The nanostructured field-effect transistor device 30 includes a semiconductor fin 90 (which can also be considered as a fin) protruding above a substrate 50. A gate 122 (such as a metal gate) is located on the fin, and source / drain regions 112 are formed on both sides of the gate 122. A plurality of nanostructures, such as a second semiconductor material 54 (such as nanowires or nanosheets), are formed on the fin 90 and between the source / drain regions 112. Isolation regions 96 are formed on both sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures, such as the second semiconductor material 54. The gate 122 is located on and around the gate dielectric layer 120.

[0013] Figure 1 also shows the reference cross-sections used in the following figures. Cross-section AA is along the longitudinal axis of the gate 122 and its direction is perpendicular to the current direction between the source / drain regions 112 of the nanostructured field-effect transistor device 30. Cross-section BB is perpendicular to cross-section AA and along the longitudinal axis of the fin 90, and its direction is the current direction between the source / drain regions 112 of the nanostructured field-effect transistor device. Cross-section CC is parallel to cross-section BB and lies between two adjacent fins 90. Cross-section DD is parallel to cross-section AA and extends through the source / drain regions 112 of the nanostructured field-effect transistor device. The following figures will be based on these reference cross-sections for clarity.

[0014] Figures 2, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 20A, 20B, 21A, and 21B are cross-sectional views of a portion of a nanostructured field-effect transistor device 100 at various manufacturing stages in one embodiment.

[0015] In FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, a semiconductor-on-insulator substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer may be provided on the substrate, and the substrate is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide), or combinations thereof.

[0016] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes interleaved layers of first semiconductor material 52 and second semiconductor material 54. In FIG2, the layers of first semiconductor material 52 are labeled as layers of first semiconductor materials 52A, 52B, and 52C, and the layers of second semiconductor material 54 are labeled as layers of second semiconductor materials 54A, 54B, and 54C. In FIG2, the number of layers formed by the first semiconductor material 52 and the second semiconductor material 54 is only a non-limiting example. Other numbers of layers are also possible and are entirely within the scope of embodiments of the present invention.

[0017] In some embodiments, the first semiconductor material 52 is a first epitaxial material such as silicon germanium (SixGe1-x, where x can be 0 to 1), and the second semiconductor material 54 is a second epitaxial material such as silicon. In subsequent processes, the multilayer stack 64 (which can also be considered as an epitaxial material stack) is patterned to form the channel region of the nanostructure field-effect transistor. Specifically, the multilayer stack 64 is patterned and etched to form a nanostructure (such as a nanosheet or nanowire), and the final channel region of the nanostructure field-effect transistor includes multiple horizontally extending nanostructures.

[0018] The method for forming the multilayer stack 64 may be an epitaxial growth process, which may be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the growth chamber may be cyclically exposed to a first set of precursors for selectively growing a first semiconductor material 52, and then exposed to a second set of precursors for selectively growing a second semiconductor material 54. The first set of precursors includes precursors for a first semiconductor material such as silicon-germanium, and the second set of precursors includes precursors for a second semiconductor material 54 such as silicon. In some embodiments, the first set of precursors includes silicon precursors such as silane and germanium precursors such as germanane, and the second set of precursors includes silicon precursors but omits the germanium precursor. The epitaxial growth process may include continuously introducing silicon precursor streams into the growth chamber, and then cyclically introducing germanium precursor streams into the growth chamber during the growth of the first semiconductor material 52; and (2) not introducing germanium precursor streams into the growth chamber during the growth of the second semiconductor material 54. The exposure process can be repeated until the target number of layers are formed.

[0019] In one embodiment, Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 20A, 20B, 21A, and 21B are cross-sectional views of the nanostructured field-effect transistor device 100 in a subsequent manufacturing stage in one embodiment. Figures 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, and 22A are sectional views along section BB in Figure 1. Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19B, 20B, and 21B are sectional views along section AA in Figure 1. Figures 12B, 13B, 14B, 15B, 16B, 17B, and 18B are sectional views along section DD in Figure 1. The number of fins and gate structures shown in the figures are merely non-limiting examples; it should be understood that other numbers of fins and other numbers of gate structures can also be formed.

[0020] In Figures 3A and 3B, the fin structure 91 protrudes above the substrate 50. Each fin structure 91 includes a semiconductor fin 90 (which can also be considered as a fin) and a layered stack 92 located on the semiconductor fin 90. The layered stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layered stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0021] The fin structure 91 can be patterned by any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography with a self-aligned process, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-aligned process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are subsequently used to pattern the fin structure 91.

[0022] In some embodiments, the reserved spacers are used to pattern a mask 94, which is then used to pattern the fin structure 91. The mask 94 may be a single-layer mask or a multi-layer mask, such as a multi-layer mask containing a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B may each be composed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed by deposition or thermal growth according to suitable techniques. The first mask layer 94A and the second mask layer 94B may be different materials with high etch selectivity. For example, the first mask layer 94A may be silicon oxide, and the second mask layer 94B may be silicon nitride. The mask 94 may be formed using an acceptable etching process to pattern the first mask layer 94A and the second mask layer 94B. The mask 94 may then serve as an etching mask for etching the substrate 50 and the multilayer stack 64. Etching can be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. In some embodiments, etching is an isotropic etching process. After the etching process, patterned multilayer stacks 64 form layered stacks 92, and patterned portions of substrate 50 form fins 90 (such as fins 90A and 90B), as shown in Figures 3A and 3B. Retained portions of substrate 50 (such as unpatterned portions) can be considered as substrate 50 in Figures 3A and 3B and subsequent figures. Therefore, in the described embodiment, layered stack 92 also includes layers of interleaved first semiconductor material 52 and second semiconductor material 54. The fins 90 and substrate 50 can be made of the same material. In the examples of Figures 3A and 3B, fins 90A and 90B extend in parallel directions to each other.

[0023] Next, in Figures 4A and 4B, shallow trench isolation regions 96 are formed on the substrate 50 and on both sides of the fin structure 91. In one example of forming the shallow trench isolation region 96, an insulating material may be formed on the substrate 50. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and its formation method may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition (e.g., depositing a chemical vapor deposition-based material in a remote plasma system, followed by curing the material to transform it into another material such as an oxide), similar methods, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the embodiment described, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. An annealing process may be performed after the insulating material is formed.

[0024] In some embodiments, an insulating material is formed such that excess insulating material covers the fin structure 91. In some embodiments, a liner is first formed along the surface of the substrate 50 and the fin structure 91, and the aforementioned filler material is formed on the liner. In some embodiments, the liner may be omitted.

[0025] Next, a removal process is performed on the insulating material to remove excess insulating material from the fin structure 91. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back process, a combination thereof, or a similar process may be used. The planarization process exposes the layered stack 92, making the layered stack 92 flush with the upper surface of the insulating material after the planarization process. The insulating material is then recessed to form shallow trench isolation regions 96. The insulating material is recessed so that the layered stack 92 protrudes from between adjacent shallow trench isolation regions 96. The top of the semiconductor fin 90 may also protrude from between adjacent shallow trench isolation regions 96. Furthermore, the upper surface of the shallow trench isolation region 96 may be a flat surface, a raised surface, a recessed surface (such as dishing), or a combination thereof, as illustrated. The upper surface of the shallow trench isolation region 96 may be flat, raised, and / or recessed by appropriate etching. The shallow trench compartment 96 can be recessed using an acceptable etching process, such as an etching process selective for insulating materials (e.g., etching the insulating material at a rate greater than etching the material of the fins 90 and the layered stack 92). For example, a suitable etchant such as diluted hydrofluoric acid can be used for chemical oxide removal.

[0026] As shown in Figures 4A and 4B, a pad layer 61 is formed on the layered stack 92 and the shallow trench isolation region 96. The pad layer 61 may be a suitable dielectric material such as silicon oxide, and its formation method may employ a suitable deposition method such as chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the pad layer 61 protects the layered stack 92 from damage caused by subsequent etching processes used to form the shallow trench isolation protection structure 68. The pad layer 61 may also be considered as an oxide pad layer. In addition to silicon oxide, other suitable materials may be used, such as dielectric materials with high etch selectivity relative to the layered stack 92 and the subsequently formed hard mask layer 73. In the embodiments described, the pad layer 61 has a substantially uniform thickness. For example, the horizontal portion of the padding layer 61 (such as the portion along the upper surface of the fin structure 91 or along the upper surface of the shallow trench isolation region 96) has a first thickness, and the vertical portion of the padding layer 61 (such as the portion along the sidewall of the fin structure 91) has a second thickness, with the difference between the first thickness and the second thickness being 10% (e.g., the first thickness is between 90% and 110% of the second thickness, or between 95% and 105%). For example, the thickness (e.g., the average thickness) of the padding layer 61 is between about 2 nm and about 4 nm.

[0027] Next, in Figures 5A and 5B, a hard mask layer 73 is formed on the pad layer 61. The composition of the hard mask layer 73 is different from that of the pad layer 61 and the shallow trench isolation region 96. In some embodiments, the material of the hard mask layer 73 is selected to have high etch selectivity relative to the material of the shallow trench isolation region 96, so that the hard mask layer 73 can protect the shallow trench isolation region 96 from loss during subsequent sheet formation processes (such as etching processes) for forming nanostructures such as nanosheets. In one embodiment, the shallow trench isolation region 96 is composed of silicon oxide, while the hard mask layer 73 is composed of silicon nitride. In addition to silicon nitride, the hard mask layer 73 may also be made of other suitable materials such as silicon oxynitride, silicon carbonitride, or the like. Suitable formation methods such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar methods may be used to form the hard mask layer 73.

[0028] In some embodiments, the hard mask layer 73 has an inconsistent thickness. For example, the horizontal portion of the hard mask layer 73 (such as the portion along the upper surface of the fin structure 91 or along the upper surface of the shallow trench isolation region 96) has a thickness T2, while the vertical portion of the hard mask layer 73 (such as the portion along the sidewall of the fin structure 91) has a thickness T1, and the thickness T2 is greater than the thickness T1. In some embodiments, the thickness T2 is about 1.5 times to about 3 times the thickness T1, for example, about two times to about three times.

[0029] The inconsistent thickness of the hard masking layer 73 is advantageous for manufacturing the nanostructure field-effect transistor device 100. As detailed below, subsequent processes remove the sidewall portions (e.g., vertical portions) and the top portion (e.g., along the upper surface of the fin structure 91) of the hard masking layer 73, while retaining the bottom portion (e.g., along the upper surface of the shallow trench isolation region 96) to form a shallow trench isolation protection structure 68. The thicker bottom portion of the hard masking layer 73 in the shallow trench isolation protection structure 68 enhances the protection required for the shallow trench isolation region 96 during subsequent sheet formation processes. Furthermore, the thinner sidewall portions of the hard masking layer 73 in the shallow trench isolation protection structure 68 facilitate the removal of these sidewall portions, shortening process time and increasing throughput. Furthermore, as structural dimensions continue to shrink in advanced semiconductor processes, the distance between adjacent fins 91 poses a significant challenge for depositing materials (such as the hard mask layer 73) in the trenches between adjacent fins 91, given the high aspect ratio of the trenches. The method disclosed herein allows the hard mask layer 73, formed at the bottom of the trench (e.g., above the upper surface of the shallow trench isolation region 96), to have sufficient thickness by thinning the sidewall portions of the hard mask layer 73. The thinned sidewall portions of the hard mask layer 73 also prevent the tops of the hard mask layers 73 on adjacent fins 91 (located above the upper surface of the fins 91) from merging together. Merging of the tops of the hard mask layers 73 prevents subsequent deposition of the hard mask layer 73 on the upper surface of the shallow trench isolation region 96, which could potentially cause failure in the formation of the shallow trench isolation protection structure 68. Therefore, the thinned sidewall portions of the hard mask layer 73 prevent device failure and production yield losses caused by failure in the formation of the shallow trench isolation protection structure.

[0030] In some embodiments, the hard mask layer 73 formed by the plasma-assisted chemical vapor deposition disclosed herein has an inconsistent thickness. It is noteworthy that, compared to conventional plasma-assisted chemical vapor deposition processes (which typically aim to form a material layer of uniform thickness), the disclosed plasma-assisted chemical vapor deposition process can be adapted to form a hard mask layer 73 of inconsistent thickness. The disclosed plasma-assisted chemical vapor deposition process includes multiple deposition cycles, each comprising multiple process steps within a process chamber. In some embodiments, the multiple process steps in a deposition cycle include a first process step, a second process step, and a third process step performed sequentially. After each of the first, second, and third process steps, unused precursors, plasma generated during the process steps, and / or byproducts of the process steps (if present) may be extracted (e.g., purified) by a vacuum mechanism from the process chamber. For ease of explanation, the material layer formed after each deposition cycle of the plasma-assisted chemical vapor deposition process can be considered as a sublayer of the hard mask layer 73.

[0031] In some embodiments, the first process step in the deposition cycle is a plasma process, which forms a silicon layer over an underlying layer (such as a sublayer of the pad layer 61 or a previously formed hard mask layer 73). In one embodiment, a gas source is supplied to the process chamber, and the gas source includes a silicon-containing precursor such as silane. An RF power source is turned on to ignite the gas source to form plasma. Plasma energy causes precursor molecules to break down into reactive species, which diffuse to the underlying layer and react to form the silicon layer. In some embodiments, the gas source contains an etching gas (such as hydrogen) and the silicon-containing precursor. During the first process step, the plasma of the etching gas (such as the plasma of hydrogen) etches the silicon layer and helps to control (e.g., slow down) the growth rate of the silicon layer to better control the contour of the silicon layer. After the first process step, the process chamber can be used to extract unused precursors, etching gas, plasma, and / or byproducts (if present).

[0032] In some embodiments, the second process step in the deposition cycle is a plasma process (such as a plasma etching process), which can adjust (e.g., change) the thickness of the horizontal portion (e.g., along the upper surface of the fin structure 91) and the vertical portion (e.g., along the sidewalls of the fin structure 91) of the silicon layer formed in the first process step. In one embodiment, the plasma process can increase the ratio between the thickness of the horizontal portion of the silicon layer and the thickness of the vertical portion of the silicon layer. The plasma process (such as a plasma etching process) can adjust the ratio between the vertical etching rate and the horizontal etching rate of the plasma process to achieve the effect of adjusting the silicon layer thickness. The ratio between the vertical etching rate and the horizontal etching rate can be adjusted by adjusting the process conditions of the plasma process, such as pressure, temperature, the power of the RF power source, the incident angle of the ions, and / or the time of the plasma process. For example, the horizontal etching rate can be adjusted to be higher than the vertical etching rate, thereby increasing the ratio between the thickness of the horizontal portion of the silicon layer and the thickness of the vertical portion of the silicon layer after the plasma process in the second process step.

[0033] In some embodiments, the plasma process in the second process step uses a hydrogen-containing gas source. The gas source is ignited with a radio frequency power source to form plasma, and the hydrogen plasma etches the silicon layer formed in the first process step. Therefore, the second process step can also be considered as a hydrogen plasma etching process or hydrogen plasma treatment of the silicon layer. Compared to other stronger plasma etching chemicals (such as fluorine-based chemicals), hydrogen plasma etching of the silicon layer is slower and gentler, thus allowing for better control of the thickness of the horizontal / vertical portions of the silicon layer. After the second process step, an in-house process chamber can be used to extract unused etching gas, plasma, and / or byproducts (if present).

[0034] In some embodiments, the third process step in the deposition cycle is a plasma process, which nitrides the silicon layer to form a silicon nitride layer, and can therefore be considered a nitriding process. In some embodiments, the gas source used in the plasma process of the third process step includes nitrogen. The gas source is ignited with an RF power source to form plasma, and the nitrogen plasma reacts with the silicon layer to convert the silicon layer into a silicon nitride layer. Therefore, after the third process step, a sublayer (such as a silicon nitride sublayer) of the hard mask layer 73 can be formed. After the third process step, an unused gas source, plasma, and / or byproducts (if present) can be extracted from the process chamber. The above deposition cycle can be repeated until the hard mask layer 73 reaches the target thickness. For example, the thickness (such as the average thickness) of the hard mask layer 73 can be between about 5 nm and about 12 nm, such as 6 nm or 10 nm.

[0035] It is worth noting that silicon nitride is a non-limiting example of the material used for the hard masking layer 73 in the above example. Other suitable materials such as silicon oxynitride, silicon carbonitride, or the like may also be used as the hard masking layer 73, and different materials used to form the hard masking layer 73 may be employed using the above deposition methods (such as plasma-assisted chemical vapor deposition processes), as understood by those skilled in the art.

[0036] Next, in Figures 6A and 6B, a masking layer 67 is formed on the rigid masking layer 73. In some embodiments, the masking layer 67 is a bottom anti-reflective coating commonly used in three-layer photoresist. For example, the bottom anti-reflective coating is a carbon-containing material such as spin-coated glassy carbon. Therefore, the masking layer 67 can also be regarded as a bottom anti-reflective coating, but it should be understood that other suitable materials can also be used. As shown in Figures 6A and 6B, the bottom anti-reflective coating, such as the masking layer 67, fills the grooves between adjacent fin structures 91 and covers the upper surface of the fin structures 91.

[0037] Next, in Figures 7A and 7B, the under-antireflective coating, such as the mask layer 67, is etched back to expose the top of the hard mask layer 73 above the upper surface of the fin structure 91. Suitable etching processes, such as dry etching, wet etching, combinations thereof, or similar processes, can be performed to etch back the under-antireflective coating, such as the mask layer 67. The etching process can be a time-controlled process to etch back a predetermined amount of the under-antireflective coating, such as the mask layer 67. In some embodiments, the etchant used in the etching process is selective to the material of the under-antireflective coating, such as the mask layer 67 (e.g., having a higher etch rate), so that the under-antireflective coating, such as the mask layer 67, can be removed without substantially affecting the hard mask layer 73.

[0038] Next, in Figures 8A and 8B, the exposed top of the hard masking layer 73 is removed by an etching process. For example, a dry etching process can be performed to remove the exposed top of the hard masking layer 73, and the gas source used includes fluorine-based etching gases. For example, the gas source may include nitrogen trifluoride and hydrogen. In another example, the etching process uses phosphoric acid to remove the exposed top of the hard masking layer 73. In the examples shown in Figures 8A and 8B, the etching process also recesses the under-antireflective coating, such as the masking layer 67, and removes the upper sidewall portion of the hard masking layer 73. Due to the etching selectivity between the pad layer 61 and the under-antireflective coating, such as the masking layer 67, and the hard masking layer 73, the pad layer 61 can remain substantially unetched and cover the sidewalls and upper surface of the fin structure 91. Therefore, the pad layer 61 protects the layered stack 92 (and the subsequently formed nanostructures such as the second semiconductor material 54) from damage caused by the etching process used to form the shallow trench isolation protection structure 68.

[0039] Next, in Figures 9A and 9B, the remaining portion of the underlying anti-reflective coating, such as the mask layer 67, is removed by an etching process. The etching process may be dry etching, wet etching, a combination of the above, or a similar process. In some embodiments, the etching process is a plasma etching process using a gas source containing hydrogen and nitrogen. After removing the remaining portion of the underlying anti-reflective coating, such as the mask layer 67, the remaining portion of the hard mask layer 73 is exposed. The remaining portion of the hard mask layer 73 includes the sidewall portion along the sidewall of the fin structure 91 and the bottom along the upper surface of the shallow trench isolation region 96.

[0040] Next, in Figures 10A and 10B, the sidewall portions of the hard mask layer 73 are removed by an etching process. The etching process may be a dry etching process, a wet etching process, a combination of the above, or a similar process. In some embodiments, a dry etching process is performed to remove the sidewall portions of the hard mask layer 73, which may use a fluorine-based etching gas such as hydrofluoric acid, nitrogen trifluoride, or a combination of the above. In some embodiments, a wet etching process is performed to remove the sidewall portions of the hard mask layer 73. In one embodiment, the wet etching process uses a first etchant such as phosphoric acid for a first etching time, followed by a second etchant such as SC1 (a mixture of deionized water, ammonia, and hydrogen peroxide) for a second etching time.

[0041] It is worth noting that in Figures 10A and 10B, the etching process can be isotropic, thus removing not only (e.g., completely removing) the sidewall portions of the hard mask layer 73, but also some portions of the bottom of the hard mask layer 73 (e.g., portions away from the substrate 50). In other words, the etching process used to remove the sidewall portions of the hard mask layer 73 reduces the bottom thickness of the hard mask layer 73. Recall the previous adjustment of the plasma-assisted chemical vapor deposition process used for the hard mask layer 73 to form a thicker bottom for the hard mask layer 73. The thicker bottom ensures that after the etching process removing the sidewall portions of the hard mask layer 73, the remaining bottom thickness of the hard mask layer 73 is sufficient to properly form the shallow trench isolation protection structure 68 (see Figures 11A and 11B).

[0042] Next, in Figures 11A and 11B, a portion of the padding layer 61 above the retained bottom of the hard masking layer 73 is removed by an etching process. Suitable etching processes such as dry etching, wet etching, a combination thereof, or similar processes can be used to remove the portion of the padding layer 61. In one embodiment, a mixture of hydrofluoric acid and SC1 can be used for a wet etching process to remove the portion of the padding layer 61. After the etching process, the retained portion of the padding layer 61 and the retained portion of the hard masking layer 73 form a shallow trench isolation protection structure 68. As shown in Figures 11A and 11B, the shallow trench isolation protection structure 68 covers the upper surface of the shallow trench isolation region 96, for example, extending along and contacting the upper surface of the shallow trench isolation region 96. The shallow trench isolation protection structure 68 can protect (e.g., mask) the shallow trench isolation region 96 in subsequent sheet formation processes to avoid or reduce the loss of the shallow trench isolation region 96.

[0043] As shown in Figures 11A and 11B, the padding layer 61 of the shallow trench isolation protection structure 68 extends along the sidewall and lower surface of the hard shielding layer 73 of the shallow trench isolation protection structure 68. In some embodiments, the upper surface of the shallow trench isolation protection structure 68 is a flat surface, as shown in Figure 11B. In some embodiments, the upper surface of the shallow trench isolation protection structure 68 is a recessed surface, as shown by the dashed line 69 in Figure 11B. For example, the vertical distance D1 between the upper surface of the shallow trench isolation protection structure 68 and the upper surface of the fin 90 (measured at the first position where the shallow trench isolation area 96 contacts the fin 90) is less than the vertical distance D2 between the upper surface of the shallow trench isolation protection structure 68 and the upper surface of the fin 90 (measured at the second position where the midpoint between two adjacent fins 90 is located). For example, the vertical distance D1 may be 8 nm, while the vertical distance D2 may be 10 nm. In the examples used in the following figures, the shallow trench isolation protection structure 68 has a flat surface, but it should be understood that the upper surface of the shallow trench isolation protection structure 68 may be other shapes such as a recessed surface or a convex surface. These variations, along with other variations, are entirely within the scope of the embodiments of the present invention.

[0044] Next, in Figures 12A to 12C, a dummy gate dielectric layer 97 is formed on the sidewalls and upper surface of the shallow trench isolation protection structure 68 and the fin structure 91. For example, the composition of the dummy gate dielectric layer 97 may be silicon oxide, silicon nitride, a combination thereof, or the like, and its deposition or thermal growth method may be an acceptable technique. In one embodiment, a silicon layer is compliantly formed on the upper surface of the layered stack 92 and the shallow trench isolation protection structure 68, and a thermal oxidation process may be performed to convert the deposited silicon layer into an oxide layer such as the dummy gate dielectric layer 97.

[0045] Next, a dummy gate 102 is formed on the fin structure 91. To form the dummy gate 102, a dummy gate layer may be formed on the dummy gate dielectric layer. The dummy gate layer may be deposited on the dummy gate dielectric layer 97, and then planarized by methods such as chemical mechanical polishing. The dummy gate layer may be a conductive material, which may be selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, or the like. The deposition method of the dummy gate layer may be physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques used in this art.

[0046] Next, a mask 104 is formed on the dummy gate layer. The mask 104 may be composed of silicon nitride, silicon oxynitride, a combination thereof, or the like, and may be patterned using suitable photolithography and etching techniques. In the embodiment described, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using a suitable etching technique to form a dummy gate 102, and then the pattern of the mask 104 is transferred to the dummy gate dielectric layer using a suitable etching technique to form a dummy gate dielectric layer 97. The dummy gate 102 covers individual channel regions of the layered stack 92. The pattern of the mask 104 may be used to physically separate each adjacent dummy gate 102. The length direction of the dummy gate 102 may also be substantially perpendicular to the length direction of the fin structure 91. In some embodiments, the dummy gate 102 and the dummy gate dielectric layer 97 can be considered together as a dummy gate structure.

[0047] Next, an insulating material is compliantly deposited on the layered stack 92, the shallow trench isolation protection structure 68, and the dummy gate 102 to form a gate spacer layer. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer includes multiple sublayers. For example, the first sublayer (sometimes considered as the gate sealing spacer layer) may be formed by thermal oxidation or deposition, while a second sublayer (sometimes considered as the main gate spacer layer) may be compliantly deposited on the first sublayer.

[0048] Figures 12B and 12C are cross-sectional views of the nanostructured field-effect transistor device 100 in Figure 12A along sections EE and FF in Figure 12A, respectively. Sections EE and FF correspond to sections DD and AA in Figure 1, respectively. It is worth noting that the cross-sectional views shown in Figure 12A are along the longitudinal direction (e.g., current direction) of one of the fins 90, while the cross-sectional views along the longitudinal direction (e.g., current direction) of the other fins 90 are the same or similar, unless otherwise stated. Furthermore, the two dummy gates 102 shown in Figure 12A are non-limiting examples, and the number of dummy gates 102 on the fins 90 can be any suitable number.

[0049] Next, in Figures 13A to 13C, the gate spacer layer is etched using an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove the horizontal portions of the gate spacer layer (such as the portions on the shallow trench isolation region 96 and the dummy gate 102), while the vertical portions of the gate spacer layer (such as the portions along the sidewalls of the dummy gate 102 and the dummy gate dielectric layer 97) form the gate spacer 108. In addition, the fin spacer 108F can be formed along the vertical portions of the gate spacer layer along the sidewalls of the fin 90 (see Figure 13B).

[0050] After forming the gate spacer 108, the lightly doped source / drain regions (not shown) can be implanted. Suitable types of impurities (such as p-type or n-type) can be implanted into the exposed layered stack 92 and / or semiconductor fins 90. The n-type impurity can be any suitable n-type impurity such as phosphorus, arsenic, antimony, or the like, while the p-type impurity can be any suitable p-type impurity such as boron, boron difluoride, indium, or the like. The impurity concentration in the lightly doped source / drain regions can be from about 10¹⁵ cm⁻³ to about 10¹⁶ cm⁻³. An annealing process can be used to activate the implanted impurities.

[0051] Next, an opening 110 (which can also be considered as a recess or a source / drain opening) is formed in the layered stack 92. The opening 110 can extend through the layered stack 92 into the fin 90. The opening 110 can be formed by an anisotropic etching process, which uses a dummy gate 102 and a gate spacer 108 as an etching mask. The bottom of the opening 110 exposes the upper surface 90U of the fin 90. The sidewalls of the opening 110 expose the first semiconductor material 52 and the second semiconductor material 54.

[0052] In the example of FIG13B, the isotropic etching process used to form the source / drain opening 110 removes a portion of the shallow trench isolation protection structure 68 that extends beyond the sidewall of the fin spacer 108F, and may also remove a portion of the underlying shallow trench isolation region 96, thereby forming a recess in the shallow trench isolation region 96. As shown in FIG13B, due to the etching of the shallow trench isolation region 96, the shallow trench isolation region 96 has an arc-shaped (e.g., recessed) upper surface 96U. It is worth noting that the portion of the shallow trench isolation protection structure 68 below the dummy gate 102 (e.g., directly below the dummy gate 102) is masked, thus protecting it from anisotropic etching processes and maintaining its integrity.

[0053] As shown in Figure 13B, the portion of the shallow trench isolation protection structure 68 retained beneath the fin spacer 108F can be considered as the retained portion 68R of the shallow trench isolation protection structure 68. The retained portion 68R of the shallow trench isolation protection structure 68 protects the fin 90 from over-etching caused by the anisotropic etching process used to form the source / drain opening 110. Without the retained portion 68R of the shallow trench isolation protection structure 68, over-etching by the anisotropic etching process may expose and / or remove portions of the fin 90 beneath the fin spacer 108F. Over-etching and unintended removal of portions of the fin 90 may cause the fin 90 to collapse and / or, in subsequent source / drain region formation processes, unintended growth of epitaxial source / drain material from the unintended exposed portions of the fin 90. Unintended growth of source / drain material between adjacent fins 90 can cause electrical short circuits between adjacent source / drain regions, leading to device failure. The method disclosed herein forms a retained portion 68R of the shallow trench isolation protection structure 68, avoiding or reducing device failure due to over-etching related problems and improving production yield. This is another advantage of the embodiments of the present invention.

[0054] Next, in Figures 14A to 14C, the first semiconductor material 52 exposed by opening 110 and below the dummy gate 102 is removed. The method for removing the first semiconductor material 52 may be an isotropic etching process such as wet etching or a similar process, using an etchant that is selective for the material of the first semiconductor material 52, while the second semiconductor material 54, fins 90, and shallow trench isolation region 96 remain relatively unetched compared to the first semiconductor material 52. In embodiments where the first semiconductor material 52 comprises silicon germanium and the second semiconductor material 54 comprises silicon or silicon carbide, tetramethylammonium hydroxide, ammonium hydroxide, or the like may be used to selectively remove the first semiconductor material 52. After removing the first semiconductor material 52, gaps 56 (such as blank spaces) are formed between adjacent layers of second semiconductor material 54, and between the fins 90 and the bottommost layer of second semiconductor material 54.

[0055] Next, in Figures 15A to 15C, a disposable material 57 (which can also be considered a sacrificial material) is deposited in the opening 110 to line the sidewalls and bottom of the opening 110. The disposable material 57 also fills the gap 56. The deposition method of the disposable material 57 can be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The disposable material 57 can be a dielectric material. In some embodiments, the disposable material 57 includes one or more layers of silicon oxide, silicon oxynitride, aluminum oxide, or the like. The material selection depends on its characteristics, such as etch selectivity, to allow for precise removal of the disposable material 57 during the formation process without negatively impacting adjacent and underlying structures. The selection of the disposable material 57 depends on the requirements of the semiconductor device being fabricated and the electrical and physical properties of the final product.

[0056] Next, in Figures 16A to 16C, the disposable material 57 outside the gap 56 is removed (see Figure 7A). And the sidewall of the retained portion of the disposable material 57 is recessed from the individual sidewall 54S of the second semiconductor material 54 to form a sidewall recess 58.

[0057] In some embodiments, an anisotropic etching process, such as a dry etching process (e.g., a plasma etching process), is performed to remove disposable material 57 outside the gap 56. An isotropic etching process, such as a wet etching process, is then performed to recess the remaining portion of the disposable material 57 to form a sidewall recess 58. The etchants used in the dry and wet etching processes are selective for the disposable material 57, thus allowing the removal of the disposable material 57 without substantially affecting other materials and / or structures. In some embodiments, multiple etching cycles may be performed to remove the disposable material 57 and form the sidewall recess 58, and each etching cycle includes a dry etching process followed by a wet etching process. The etching cycles are repeated until the sidewall of the disposable material 57 is recessed compared to the sidewall 54S of the second semiconductor material 54. In some embodiments, the wet etching process for etching the disposable material 57 uses hydrofluoric acid, diluted hydrofluoric acid, another fluorine-based etchant, or the like as the etchant. A wet etching process is performed until the sidewalls of the disposable material 57 are recessed compared to the sidewalls 54S of the second semiconductor material 54. The retained portion of the disposable material 57 is sandwiched between the layers of the second semiconductor material 54, or between the fin 90 and the bottommost layer of the second semiconductor material 54, and this retained portion can be considered as a disposable oxide interposer. In a subsequent wafer formation process, the disposable oxide interposer can be selectively removed to release the layers of the second semiconductor material 54 to form a nanostructure (such as a nanosheet or nanowire). This process can be considered as a disposable oxide interposer process.

[0058] In the one-time oxide interposer process, replacing the first semiconductor material 52 with a one-time material 57 offers several advantages. To understand these advantages, consider a manufacturing process in which the first semiconductor material 52 is not replaced with the one-time material 57. In subsequent source / drain formation steps, one or more high-temperature processes can be performed to activate the dopants in the source / drain regions. When the first semiconductor material 52, such as silicon-germanium, is exposed to high temperatures, the germanium in the first semiconductor material 52 may diffuse into and mix with the second semiconductor material 54, such as silicon, which can be considered as mutual mixing between germanium and silicon. Mutual mixing may increase the interface roughness between the first semiconductor material 52 and the second semiconductor material 54 and may cause manufacturing defects that degrade the performance of the final transistor device. Replacing the first semiconductor material 52 with the one-time material 57 before high-temperature processes (such as source / drain annealing) avoids mutual mixing and reduces manufacturing defects, thereby improving device performance. Furthermore, the material of the primary oxide interposer, such as silicon oxide, provides good etch selectivity (e.g., above 10,000) compared to the material of the second semiconductor material 54, such as silicon. Therefore, the process of selectively removing the primary oxide interposer during the wafer formation process only causes little or no damage to the nanostructure, such as the second semiconductor material 54.

[0059] Next, in Figures 17A to 17C, an inner spacer 55 is formed in the sidewall recess 58. Figures 17B and 17C are cross-sectional views of the nanostructured field-effect transistor device 100 in Figure 17A along sections EE and FF, respectively. In some embodiments, to form the inner spacer 55, an inner spacer layer may be formed (e.g., compliantly formed) in the opening 110. The inner spacer layer also fills the sidewall recess 58 of the sacrificial material, such as disposable material 57. The inner spacer layer may be a suitable dielectric material, such as silicon carbonitride, silicon carbonitride oxide, or the like, and its formation method may be a suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar methods. An etching process, such as anisotropic etching, is then performed to remove a portion of the inner spacer layer outside the sidewall recess 58 of the sacrificial material, such as disposable material 57. The reserved portion of the inner spacer layer (such as the portion located within the sidewall recess 58 of the sacrificial material, such as disposable material 57) may form an inner spacer 55. As shown in FIG17A, the opening 110 exposes the sidewall of the second semiconductor material 54 and exposes the upper surface 90U of the fin 90.

[0060] Next, in Figures 18A to 18C, source / drain regions 112 are formed in the opening 110. In the description herein, source / drain regions may be considered individually or together as sources or drains, depending on the context. In the embodiment described, the source / drain regions 112 are composed of epitaxial material and are therefore considered epitaxial source / drain regions. In some embodiments, the epitaxial source / drain regions 112 are formed in the opening 110 to apply stress to individual channel regions of the nanostructured field-effect transistor device, thereby improving performance. In some embodiments, the epitaxial source / drain regions 112 position a dummy gate 102 between individual adjacent pairs of epitaxial source / drain regions 112. In some embodiments, the gate spacer 108 is used to maintain a suitable lateral distance between the epitaxial source / drain region 112 and the dummy gate 102, so that the epitaxial source / drain region 112 is not short-circuited outward to the gate subsequently formed in the final nanostructure field-effect transistor device.

[0061] The epitaxial source / drain region 112 is epitaxially grown in the opening 110. The epitaxial source / drain region 112 may include any acceptable material, such as materials suitable for n-type or p-type devices. For example, the epitaxial source / drain region 112 for forming an n-type device may include materials that apply tensile stress to the channel region, such as silicon, silicon carbide, silicon carbide phosphide, silicon phosphide, or the like. Similarly, the epitaxial source / drain region 112 for forming a p-type device may include materials that apply compressive stress to the channel region, such as silicon germanium, silicon germanium boride, germanium, germanium tin, or the like. The surface of the epitaxial source / drain region 112 may protrude from individual surfaces of the fin 90 and may have crystal faces.

[0062] Dopants can be implanted into the epitaxial source / drain region 112 and / or fins 90 to form the source / drain region, which is similar to the aforementioned process for forming lightly doped source / drain regions. Annealing can then be performed. The impurity concentration of the source / drain region can be between about 10¹⁹ cm⁻³ and about 10²¹ cm⁻³. The n-type and / or p-type impurities used in the source / drain region can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain region 112 can be doped in situ during growth.

[0063] The epitaxial process used to form the epitaxial source / drain region 112 results in the upper surface of the epitaxial source / drain region 112 having crystal planes that extend laterally beyond the sidewalls of the fin 90. In some embodiments, adjacent epitaxial source / drain regions 112 remain separated after the epitaxial process is completed, as shown in FIG18B. In other embodiments, these crystal planes cause adjacent epitaxial source / drain regions 112 to merge.

[0064] Next, a contact etch stop layer 116 is formed (e.g., compliantly formed) on the source / drain region 112 and the dummy gate 102, followed by the deposition of a first interlayer dielectric layer 114 on the contact etch stop layer 116. The constituent material of the contact etch stop layer 116 has a different etch rate than that of the first interlayer dielectric layer 114, such as silicon nitride formed by plasma-assisted chemical vapor deposition, but other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, or similar materials may also be used. Other techniques such as low-pressure chemical vapor deposition, physical vapor deposition, or similar techniques may also be used to form the contact etch stop layer 116.

[0065] The first interlayer dielectric layer 114 may be composed of a dielectric material, and may be deposited by any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material of the first interlayer dielectric layer 114 may include silica, phospholipid glass, borosilicate glass, borosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used.

[0066] Next, in Figures 19A, 19B, 20A, 20B, 21A, and 21B, a gate replacement process is performed, which removes and replaces dummy gate structures (such as dummy gate 102 and dummy gate dielectric layer 97) to form a gate replacement structure 123 (such as a metal gate structure). In some embodiments, cross-sectional views corresponding to the gate replacement process in Figure 18B are not shown because these cross-sectional views are the same as those in Figure 18B.

[0067] Next, in Figures 19A and 19B, the dummy gate 102 is removed by an etching step to form a recess 103 (which can also be considered as a gate trench) between the individual gate spacers 108. In some embodiments, the dummy gate 102 is removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, which may selectively etch the dummy gate 102 without etching the first interlayer dielectric layer 114 and the gate spacers 108. The dummy gate dielectric layer 97 may serve as an etching stop layer during the etching removal of the dummy gate 102. After the dummy gate 102 is removed, the dummy gate dielectric layer 97 may be removed.

[0068] In some embodiments, the dummy gate dielectric layer 97 in the recess 103 is removed. An etching process, such as an isotropic etching process, can be performed to remove the dummy gate dielectric layer 97. In one embodiment, an isotropic etching process is performed using an etching gas containing hydrofluoric acid and ammonia to remove the dummy gate dielectric layer 97. As shown in Figures 19A and 19B, each recess 103 exposes a lower channel region of the nanostructured field-effect transistor. Each channel region is located between adjacent pairs of epitaxial source / drain regions 112.

[0069] Next, in Figures 20A and 20B, a disposable material 57 (such as the portion exposed by the recess 103) is removed to release the second semiconductor material 54, which can be considered as a sheet-like forming process. After the disposable material 57 is removed, the second semiconductor material 54 (such as the portion below the dummy gate 102 before the removal of the dummy gate 102) forms a plurality of horizontally extending nanostructures such as the second semiconductor material 54 (e.g., parallel to the main upper surface of the substrate 50). The nanostructures such as the second semiconductor material 54 can be considered together as the channel region 93 or channel layer of the nanostructure field-effect transistor 100. As shown in Figures 20A and 20B, gaps 53 (such as blank spaces) are formed between the nanostructures such as the second semiconductor material 54 and between the bottommost nanostructure such as the second semiconductor material 54 and the fin 90, and are formed by removing the disposable material 57. In some embodiments, the nanostructure, such as the second semiconductor material 54, is a nanosheet or nanowire, depending on the size (e.g., dimensions and / or aspect ratio) of the nanostructure, such as the second semiconductor material 54.

[0070] In some embodiments, the disposable material 57 may be removed by a selective etching process using an etchant that is selective to the disposable material 57 (e.g., has a higher etching rate) to remove the disposable material 57 without substantially affecting the second semiconductor material 54. In some embodiments, an isotropic etching process, such as a wet etching process or a similar process, is performed to remove the disposable material 57. In embodiments where the disposable material 57 comprises silicon oxide and the second semiconductor material 54 comprises silicon or silicon carbide, hydrofluoric acid, diluted hydrofluoric acid, another fluorine-based etchant, or the like may be used to remove the disposable material 57.

[0071] In some embodiments, the high etch selectivity between the second semiconductor material 54 and the primary material 57 can be greater than or equal to 10,000. In other words, the etch rate at which the isotropic etching process removes the primary material 57 is greater than or equal to 10,000 times the etch rate of the second semiconductor material 54. In this way, the etching process (such as a sheet formation process) used to remove the primary material 57 can cause little or no damage to the nanostructure such as the second semiconductor material 54.

[0072] In some embodiments, the disposable material 57 and the shallow trench isolation region 96 are composed of oxides such as silicon oxide. Without the shallow trench isolation protection structure 68, the sheet forming process can remove the upper portion of the shallow trench isolation region 96 below the recess 103, thus causing the shallow trench isolation region 96 to be recessed. Recessing the shallow trench isolation region 96 reduces the distance between the subsequently formed displacement gate structure and the substrate. Furthermore, during the sheet forming process, the rate at which corner areas of the shallow trench isolation region 96 (such as the area where the upper surface of the shallow trench isolation region 96 contacts the sidewall of the fin 90) are removed can be greater than the rate at which other portions of the shallow trench isolation region 96 are removed. When the subsequently formed displacement gate structure fills the removed corner areas of the shallow trench isolation region 96, protrusions of the displacement gate structure may occur. The reduced distance between the displacement gate structure and the substrate, as well as the protrusions of the displacement gate structure, may cause an increase in the parasitic capacitance of the displacement gate structure. By forming a shallow trench isolation protection structure 68, the present invention can avoid or reduce the loss of the shallow trench isolation area during the sheet forming process, thereby reducing the parasitic capacitance of the nanostructure field-effect transistor device and improving the device performance.

[0073] Next, in Figures 21A and 21B, a gate dielectric layer 120 and a gate 122 are formed to form a substitutional gate structure 123. In some embodiments, the gate dielectric layer 120 is compliantly deposited in the recess 103, such as on the upper surface and sidewalls of the semiconductor fin 90 and on the sidewalls of the gate spacer 108. The gate dielectric layer 120 may also be formed on the upper surface of the first interlayer dielectric layer 114. Notably, the gate dielectric layer 120 encapsulates a nanostructure such as the second semiconductor material 54. In some embodiments, the gate dielectric layer 120 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 120 is composed of a dielectric material with a high dielectric constant. In these embodiments, the gate dielectric layer 120 may have a dielectric constant greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. Methods for forming the gate dielectric layer 120 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0074] Subsequently, gate material is deposited on and around the gate dielectric layer 120, and the gate material fills the remaining portion of the recess 103. The gate material may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although the gate material in the figure is a single layer, it may include any number of pad layers (such as barrier layers), any number of work function adjustment layers, and filler metallic materials. After the gate material is filled, a planarization process such as chemical mechanical polishing may be performed to remove excess portions of the gate dielectric layer 120 and the gate material on the upper surface of the first interlayer dielectric layer 114. Thus, the remaining portions of the gate material and the gate dielectric layer 120 respectively form the gate 122 and the gate dielectric layer 120 of the replacement gate structure 123 of the final nanostructure field-effect transistor device 100. Each gate 122 and its corresponding gate dielectric layer 120 can be considered together as a substitution gate structure 123, a gate stack, a gate structure, or a metal gate structure. Each substitution gate structure 123 extends around an individual nanostructure such as a second semiconductor material 54.

[0075] Additional process steps may be performed to complete the fabrication of the nanostructured field-effect transistor device 100, as understood by those skilled in the art. For example, a second interlayer dielectric layer may be formed on the first interlayer dielectric layer 114. Gate contact plugs and / or source / drain contact plugs may be formed to extend through the second interlayer dielectric layer and / or the first interlayer dielectric layer 114 and electrically coupled to the replacement gate structure 123 and the source / drain region 112. An interconnect structure (containing multiple dielectric layers and conductive structures such as vias and conductive lines located in the multiple dielectric layers) is then formed to form a functional circuit with electrical components (such as nanostructured field-effect transistors) below the interconnect. External interconnects (such as copper pillars or conductive bumps) may then be formed to electrically couple to the interconnect structure and provide electrical connections to external electrical devices. The multiple nanostructured field-effect transistor devices may be diced to separate them into independent devices. Details are not provided here.

[0076] The disclosed embodiments offer several advantages. For example, the use of a disposable oxide interposer process reduces the mixing of germanium and silicon, and the disposable material 57 exhibits significantly higher etch selectivity (e.g., greater than 10,000) between the second semiconductor material 54 and the disposable material 57. Thus, when the sacrificial material, such as the disposable material 57, is removed to form the nanostructure, such as the second semiconductor material 54, the nanostructure is damaged only slightly or not at all. In another example, the disclosed shallow trench isolation protection structure 68 protects the shallow trench isolation region 96 (e.g., the portion under the dummy gate) when the sacrificial material, such as the disposable material 57, is removed, thereby avoiding or reducing the loss of the shallow trench isolation region 96, reducing the parasitic capacitance of the replacement gate structure 123, and improving device performance. In another example, the retained portion 68R of the shallow trench isolation protection structure 68 below the fin spacer 108F can prevent or reduce the collapse of the fin 90, or the unexpected growth or merging of the source / drain material caused by the etching process used for the source / drain opening over-etching the shallow trench isolation region 96.

[0077] Figures 22A and 22B together show flowcharts of a method 1000 for forming a semiconductor device in some embodiments. It should be understood that the methods of the embodiments shown in Figures 22A and 22B are only one example of many possible embodiments. Those skilled in the art will understand that many variations, substitutions, and modifications are possible. For example, various steps shown in Figures 22A and 22B may be added, removed, replaced, rearranged, or repeated.

[0078] As shown in Figures 22A and 22B, step 1010 forms a fin-like structure with protrusions higher than the substrate, wherein the fin-like structure includes fins and layered stacks located on the fins, wherein the layered stacks include interlaced layers of first semiconductor material and second semiconductor material. Step 1020 forms shallow trench isolation regions on both sides of the fin-like structure. Step 1030 forms a shallow trench isolation protection structure on the upper surface of the shallow trench isolation region. Step 1040 After forming the shallow trench isolation protection structure, a dummy gate structure is formed on the fin-like structure. Step 1050 forms source / drain openings in the fin-like structures on both sides of the dummy gate structure, wherein the source / drain openings expose the first semiconductor material and the second semiconductor material. Step 1060 After forming the source / drain openings, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material. Step 1070 After the replacement step, a source / drain region is formed in the source / drain opening. Step 1080: After forming the source / drain regions, remove the dummy gate structure to expose the sacrificial material and a first portion of the second semiconductor material. Step 1090: Remove the exposed sacrificial material, wherein after removing the exposed sacrificial material, retain the first portion of the second semiconductor material to form the channel region of the semiconductor device. Step 1100: Form a gate dielectric material and a gate material around the channel region.

[0079] In one embodiment, a method of forming a semiconductor device includes: forming a fin structure with protrusions higher than a substrate, wherein the fin structure includes fins and a layered stack located on the fins, wherein the layered stack includes multiple layers of interleaved first semiconductor material and second semiconductor material; forming a plurality of shallow trench isolation regions on both sides of the fin structure; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation regions; after forming the shallow trench isolation protection structure, forming a dummy gate structure on the fin structure; forming a plurality of source / drain openings in the fin structure on both sides of the dummy gate structure, wherein the source... The source / drain opening exposes a first semiconductor material and a second semiconductor material; after forming the source / drain opening, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material; after the replacement step, a plurality of source / drain regions are formed in the source / drain opening; after forming the source / drain regions, the dummy gate structure is removed to expose a first portion of the sacrificial material and the second semiconductor material; the exposed sacrificial material is removed, wherein after removing the exposed sacrificial material, the first portion of the second semiconductor material is retained to form a plurality of channel regions of the semiconductor device; and a gate dielectric material and a gate material are formed around the channel regions. In one embodiment, the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer. In one embodiment, the step of forming a shallow trench isolation protection structure includes forming a first dielectric material located on the upper surface of the shallow trench isolation region and along the sidewalls and upper surface of the fin structure; forming a second dielectric material on the first dielectric material, wherein the second dielectric material has a non-uniform thickness; and recessing the first and second dielectric materials below the layered stack, wherein the retained portions of the first and second dielectric materials after the recessing step respectively form a pad layer and a hard mask layer of the shallow trench isolation protection structure. In one embodiment, after forming the second dielectric material and before the recessing step, the second dielectric material along the sidewalls of the fin structure has a first thickness, and the second dielectric material along the upper surface of the shallow trench isolation region has a second thickness, and the second thickness is greater than the first thickness. In one embodiment, the first dielectric material comprises silicon oxide, and the second dielectric material comprises silicon nitride. In some embodiments, the step of forming the second dielectric material includes performing multiple deposition cycles, each deposition cycle including multiple process steps, and the process steps including depositing a silicon layer on the first dielectric material, wherein the silicon layer along the sidewalls of the fin structure has a first thickness and the silicon layer along the upper surface of the shallow trench isolation region has a second thickness; performing an etching process to increase the ratio between the second thickness and the first thickness; and after performing the etching process, processing the silicon layer with a chemical process. In one embodiment, the step of performing the etching process includes performing a first plasma process using a first gas source containing hydrogen. In one embodiment, the step of processing the silicon layer includes performing a second plasma process using a second gas source containing nitrogen.In one embodiment, the method further includes, after the replacement step and before forming the source / drain regions, recessing the sacrificial material from the sidewalls of the second semiconductor material to form a plurality of sidewall recesses in the sacrificial material; and forming a plurality of inner spacers in the sidewall recesses. In one embodiment, the method further includes, after forming the source / drain regions and before removing the dummy gate structure, forming an interlayer dielectric layer around the dummy gate structure and on the source / drain regions. In one embodiment, the sacrificial material and the shallow trench isolation region are composed of a first dielectric material. In one embodiment, the hard mask layer of the shallow trench isolation protection structure is composed of a second dielectric material, wherein the etch chemical used to remove the exposed sacrificial material has a lower etch rate on the second dielectric material than on the first dielectric material.

[0080] In one embodiment, a method of forming a semiconductor device includes forming a fin structure protruding above a plurality of shallow trench isolation regions, wherein the shallow trench isolation regions are located on a substrate and on both sides of the fin structure, wherein the fin structure includes fins and layered stacks located on the fins, wherein the layered stacks include a plurality of layers of interleaved first semiconductor materials and second semiconductor materials; covering the upper surface of the shallow trench isolation regions with a shallow trench isolation protection structure, wherein the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer; after the covering step, forming a dummy gate on the fin structure; forming a plurality of source / drain openings on the dummy gate. In the fin-like structures on both sides of the gate; after forming the source / drain openings, a first semiconductor material under the dummy gate structure is replaced as a sacrificial material; after the replacement step, a plurality of source / drain regions are formed in the source / drain openings; an interlayer dielectric layer is formed above the source / drain regions and around the dummy gate; the dummy gate is removed to form a gate trench in the interlayer dielectric layer; wherein the gate trench exposes a first portion of the sacrificial material and the second semiconductor material; the exposed sacrificial material is selectively removed, wherein the first portion of the second semiconductor material after the selective removal step forms a plurality of nanostructures; and a replacement gate structure is formed around the nanostructures. In one embodiment, the pad layer comprises silicon oxide, and the hard mask layer comprises silicon nitride. In one embodiment, the step of covering the upper surface of the shallow trench isolation region includes: forming a first dielectric material located on the upper surface of the shallow trench isolation region, along the sidewalls of the fin structure, and along the upper surface of the fin structure; forming a second dielectric material on the first dielectric material, wherein the second dielectric material has a non-uniform thickness; and removing the first dielectric material and the second dielectric material from the upper surface of the fin structure and the upper portion of the sidewalls of the fin structure, wherein after removing the first dielectric material and the second dielectric material, the retained portions of the first dielectric material and the retained portions of the second dielectric material respectively form a pad layer and a hard mask layer of the shallow trench isolation protection structure. In one embodiment, the thickness of the second dielectric material along the sidewalls of the fin structure is greater than the thickness of the second dielectric material along the upper surface of the shallow trench isolation region. In one embodiment, the step of forming the second dielectric material includes performing multiple deposition cycles, each deposition cycle including multiple process steps, and the process steps including depositing a silicon layer on the first dielectric material using a first plasma process, wherein the silicon layer along the sidewalls of the fin structure has a first thickness and the silicon layer along the upper surface of the shallow trench isolation region has a second thickness; performing a second plasma process to increase the ratio between the second thickness and the first thickness; and after performing the second plasma process, performing a third plasma process to nitrid the silicon layer.

[0081] In one embodiment, the semiconductor device includes a substrate; fins protruding above the substrate; shallow trench isolation regions located on both sides of the fins; a shallow trench isolation protection structure extending along and contacting the upper surface of the shallow trench isolation regions; a plurality of source / drain regions located on the fins; a plurality of nanostructures located above the fins and between the source / drain regions; and a gate structure located between the source / drain regions and around the nanostructures. In one embodiment, the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer, wherein the pad layer extends along the sidewalls of the hard mask layer. In one embodiment, the shallow trench isolation regions include silicon oxide, and the hard mask layer includes silicon nitride.

[0082] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention. [Simplified Explanation of the Diagram]

[0007] Figure 1 is a three-dimensional view of a nanostructured field-effect transistor device in some embodiments. Figures 2, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, 20A, 20B, 21A, and 21B are cross-sectional views of a portion of a nanostructured field-effect transistor device at various manufacturing stages in one embodiment. Figures 22A and 22B are flowcharts of methods for forming a semiconductor device in some embodiments.

Claims

1. A method for forming a semiconductor device, comprising: A fin-like structure is formed, its protrusions being higher than a substrate. The fin-like structure includes a fin and a layered stack on the fin, wherein the layered stack includes multiple layers of an alternating first semiconductor material and a second semiconductor material. Multiple shallow trench isolation regions are formed on both sides of the fin-like structure. A shallow trench isolation protection structure is formed on the upper surface of the shallow trench isolation regions, and the upper surface of the shallow trench isolation protection structure is lower than the upper surface of the fin. After forming the shallow trench isolation protection structure, a dummy gate structure is formed on the fin-like structure. Multiple source / drain openings are formed in the fin-like structure on both sides of the dummy gate structure, wherein the source / drain openings expose the first semiconductor material and the second semiconductor material. After forming the source / drain openings, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material. After the replacement step, multiple source / drain regions are formed in the source / drain openings. After forming these source / drain regions, the dummy gate structure is removed to expose a first portion of the sacrificial material and the second semiconductor material; Remove the exposed sacrificial material, wherein after removing the exposed sacrificial material, the first portion of the second semiconductor material is retained to form a plurality of channel regions of the semiconductor device; and a gate dielectric material and a gate material are formed around the channel regions.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer.

3. The method for forming a semiconductor device as described in claim 2, wherein the step of forming the shallow trench isolation protection structure includes: A first dielectric material is formed, which is located on the upper surface of the shallow trench isolation region and along the sidewalls and upper surface of the fin structure; A second dielectric material is formed on the first dielectric material, wherein the second dielectric material has a non-uniform thickness; And to recess the first dielectric material and the second dielectric material below the layered stack, wherein the retained portions of the first dielectric material and the retained portions of the second dielectric material after the recessing step respectively form the pad layer and the hard mask layer of the shallow trench isolation protection structure.

4. The method of forming a semiconductor device as claimed in claim 3, wherein after the formation of the second dielectric material and before the recessing step, the second dielectric material along the sidewall of the fin structure has a first thickness, the second dielectric material along the upper surface of the shallow trench isolation region has a second thickness, and the second thickness is greater than the first thickness.

5. A method for forming a semiconductor device, comprising: A fin-like structure is formed, its protrusions being higher than multiple shallow trench isolation regions, wherein the shallow trench isolation regions are located on a substrate and on both sides of the fin-like structure. The fin-like structure includes a fin and a layered stack on the fin, wherein the layered stack includes multiple layers of an interleaved first semiconductor material and a second semiconductor material. A shallow trench isolation protection structure is used to cover the upper surface of the shallow trench isolation regions, wherein the shallow trench isolation protection structure includes a pad layer and a hard mask layer on the pad layer, and the upper surface of the shallow trench isolation protection structure is lower than the upper surface of the fin. After the covering step, a dummy gate is formed on the fin-like structure. Multiple source / drain openings are formed in the fin-like structure on both sides of the dummy gate. After forming the source / drain openings, the first semiconductor material under the dummy gate structure is replaced as a sacrificial material. After the replacement step, multiple source / drain regions are formed in the source / drain openings. An interlayer dielectric layer is formed above the source / drain region and around the dummy gate; the dummy gate is removed to form a gate trench in the interlayer dielectric layer; wherein the gate trench exposes a first portion of the sacrificial material and the second semiconductor material; the exposed sacrificial material is selectively removed, wherein the first portion of the second semiconductor material after the selective removal step forms a plurality of nanostructures; and a displacement gate structure is formed around the nanostructures.

6. A method of forming a semiconductor device as claimed in claim 5, wherein the pad layer comprises silicon oxide and the hard mask layer comprises silicon nitride.

7. A method of forming a semiconductor device as described in claim 5 or 6, wherein the step of covering the upper surface of the shallow trench isolation regions includes: A first dielectric material is formed, which is located on the upper surface of the shallow trench isolation region, along the sidewall of the fin structure, and along the upper surface of the fin structure; A second dielectric material is formed on the first dielectric material, wherein the second dielectric material has a non-uniform thickness; The first dielectric material and the second dielectric material are removed from the upper surface of the fin structure and the upper portion of the sidewall of the fin structure, wherein after the removal of the first dielectric material and the second dielectric material, the remaining portions of the first dielectric material and the remaining portions of the second dielectric material respectively form the padding layer and the hard shielding layer of the shallow trench isolation protection structure.

8. A semiconductor device, comprising: One substrate; A fin-like protrusion protrudes above the substrate; A shallow trench isolation region is located on both sides of the fin; a shallow trench isolation protection structure extends along and contacts the upper surface of the shallow trench isolation region, and the upper surface of the shallow trench isolation protection structure is lower than the upper surface of the fin; a plurality of source / drain regions are located on the fin; a plurality of nanostructures are located on the fin and between the source / drain regions; and a gate structure is located between the source / drain regions and around the nanostructures.

9. The semiconductor device as claimed in claim 8, wherein the shallow trench isolation protection structure includes a pad layer and a hard mask layer located on the pad layer, wherein the pad layer extends along the sidewall of the hard mask layer.

10. The semiconductor device as claimed in claim 9, wherein the shallow trench isolation region comprises silicon oxide and the hard mask layer comprises silicon nitride.

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