Semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device capable of improving operational reliability. The semiconductor memory device of the embodiment includes: a memory cell disposed above a substrate; a high-voltage generating circuit 26-1 disposed between the substrate and the memory cell, generating a high voltage supplied to the memory cell; and a high-voltage generating circuit 26-2 disposed between the substrate and the memory cell, generating the aforementioned high voltage, and having a circuit configuration equivalent to the high-voltage generating circuit 26-1.

Description

Semiconductor memory devices The implementation method relates to a semiconductor memory device. A semiconductor memory device composed of three-dimensionally arranged memory cells is known. The embodiment provides a semiconductor memory device that can improve the reliability of operation. The semiconductor memory device according to the embodiment includes: a memory cell disposed above a substrate; a first voltage generating circuit disposed between the substrate and the memory cell, and generating a first voltage supplied to the memory cell; and a second voltage generating circuit disposed between the substrate and the memory cell, generating the first voltage, and having a circuit configuration equivalent to the first voltage generating circuit. Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, common reference numerals are used to mark constituent elements having the same function and structure. Furthermore, the embodiments shown below illustrate apparatus or methods for embodying the technical concept of the embodiments, and the materials, shapes, structures, and arrangements of the constituent parts are not specific to those described below. Here, as a semiconductor memory device, a three-dimensional stacked NAND flash memory, formed by stacking memory cell transistors on top of a semiconductor substrate, will be used as an example for explanation. In this specification, the memory cell transistor is sometimes referred to as a memory cell. 1. First Embodiment Hereinafter, the semiconductor memory device of the first embodiment will be described. 1.1 Configuration of Semiconductor Memory Device First, an example of the configuration of the semiconductor memory device according to the first embodiment will be described using FIG1. ​​FIG1 is a diagram showing an example of the planar layout of the semiconductor memory device according to the first embodiment. In the following figures including FIG1, two directions parallel to the semiconductor substrate surface (or wafer surface) and orthogonal (or intersecting) to each other are designated as the X direction and the Y direction, and the direction orthogonal (or intersecting) to the surface (XY plane) containing both the X direction and the Y direction is designated as the Z direction. For example, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the direction orthogonal to the semiconductor substrate surface of the semiconductor memory device 10. As shown in FIG1, the semiconductor memory device 10 includes, for example, a memory array chip 100 and a peripheral circuit chip 200. The memory array chip 100 has memory cell arrays 11A, 11B, 11C, 11D, lead-out areas 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, and pad area 13A. The peripheral circuit chip 200 is responsible for communication with an externally located memory controller (not shown). The peripheral circuit chip 200 has peripheral circuit areas 14A, 14B, 14C, 14D, column decoders 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, and pad area 13B. The peripheral circuit areas 14A-14D and the column decoders 15A-15H control the memory cell arrays 11A-11D within the memory array chip 100. The memory array chip 100 and the peripheral circuit chip 200 are formed using different semiconductor substrates. The electrode pads on the surface of the memory array chip 100 and the electrode pads on the surface of the peripheral circuit chip 200 are arranged facing each other, and the electrode pads of the memory array chip 100 and the electrode pads of the peripheral circuit chip 200 are bonded together. In this way, a semiconductor memory device (semiconductor memory chip) 10 is formed. In the memory array chip 100, each memory cell array 11A to 11D can simultaneously perform different operations. Memory cell array 11A is disposed between lead-out regions 12A and 12B arranged in the X direction. Similarly, memory cell arrays 11B, 11C, and 11D are disposed between lead-out regions 12C and 12D, 12E and 12F, and 12G and 12H, respectively. Outlet regions 12A and 12B are used for electrical connection between the memory cell array 11A disposed on the memory array chip 100 and the column decoders 15A and 15B disposed on the peripheral circuit chip 200. Similarly, outlet regions 12C and 12D are used for electrical connection between the memory cell array 11B and the column decoders 15C and 15D. Outlet regions 12E and 12F are used for electrical connection between the memory cell array 11C and the column decoders 15E and 15F. Outlet regions 12G and 12H are used for electrical connection between the memory cell array 11D and the column decoders 15G and 15H. In the pad region 13A, pads for connection between the peripheral circuit chip 200 and the memory controller are provided. The pad region 13A extends in the X direction and is arranged, for example, adjacent to the memory cell arrays 11B and 11D. In the peripheral circuit chip 200, column decoders 15A to 15H are arranged to overlap with or face the lead-out areas 12A to 12H of the memory array chip 100, respectively. For example, column decoders 15A and 15B are electrically connected to the word lines WL provided in the memory cell array 11A. Similarly, column decoders 15C and 15D are electrically connected to the word lines WL provided in the memory cell array 11B. Column decoders 15E and 15F are electrically connected to the word lines WL provided in the memory cell array 11C. Column decoders 15G and 15H are electrically connected to the word lines WL provided in the memory cell array 11D. Peripheral circuit region 14A is, for example, located between column decoders 15A and 15B. Peripheral circuit region 14B is, for example, located between column decoders 15C and 15D. Peripheral circuit region 14C is, for example, located between column decoders 15E and 15F. Peripheral circuit region 14D is, for example, located between column decoders 15G and 15H. Peripheral circuit regions 14A to 14D respectively include, for example, the following sensing amplifier, peripheral circuitry, and redundant circuitry. The pad region 13B is adjacent to the peripheral circuit regions 14B and 14D, and is arranged to overlap with the pad region 13A of the memory array chip 100. For example, wiring leading from the peripheral circuits included in the peripheral circuit regions 14A to 14D is disposed in the pad region 13B. These wirings are led out to the upper surface of the semiconductor memory device 10 via vias and pads. In the following description, memory cell array 11A will be described, and each memory cell array 11B to 11D is the same as memory cell array 11A. Next, the cross-sectional structure of the semiconductor memory device 10 will be described using Figure 2. Figure 2 is a cross-sectional view along line AA in Figure 1, and is a cross-sectional view along the XZ plane containing the memory cell array 11A. Figure 2 shows the cross-sectional structure containing the memory cell array 11A, and the cross-sectional structures containing each memory cell array 11B to 11D are also the same as the cross-sectional structure shown in Figure 2. Furthermore, in Figure 2, the interlayer insulating film between the conductive layers is omitted. Moreover, in the cross-sectional views following Figure 2, the direction of the arrow in the Z direction is referred to as the positive direction, and the direction opposite to the direction of the arrow in the Z direction is referred to as the negative direction. Also, in the following description, "up" and "down" correspond to the upper and lower directions in the respective figures. As shown in Figure 2, the semiconductor memory device 10 has a structure in which a memory array chip 100 and a peripheral circuit chip 200 are bonded together. The cross-sectional structure of the memory array chip 100 is described in detail below. On the semiconductor substrate 30, a conductive layer 31 is disposed in the negative direction of the Z-direction within the dielectric insulating layer. A laminate formed by stacking conductive layers 32, a plurality of conductive layers 33, and conductive layers 34 in the negative direction of the Z-direction is disposed on the conductive layer 31. The conductive layers 31-34 extend in the X-direction. The conductive layers 31-34 have a plate shape along (or parallel to) the XY plane (or the surface of the semiconductor substrate 30). Conductive layer 31 functions as the source line SL. Conductive layer 32 functions as the select gate line SGS. Conductive layers 33 function as multiple character lines WL0 to WL7. Furthermore, in Figure 2, two conductive layers 33 are shown; the remaining conductive layers 33 are omitted. Conductive layer 34 functions as the select gate line SGD. Conductive layers 31 to 34, for example, contain tungsten (W) or polycrystalline silicon. The semiconductor substrate 30, for example, contains a silicon substrate and a silicon epitaxial layer. In a laminate containing conductive layers 32-34, a plurality of memory pillars MP in the form of pillars are provided. Each memory pillar MP extends in the Z direction. Each memory pillar MP is arranged to penetrate conductive layers 32-34 in the Z direction (or the stacking direction), reaching conductive layer 31 from the surface of conductive layer 34. That is, the memory pillar MP is connected to the source line SL through the select gate line SGD, a plurality of word lines WL0-WL7, and the select gate line SGS. A contact plug CP1 is provided in the negative Z direction of the memory cylinder MP. A through-hole 35A, a conductive layer 36A, a through-hole 37A, a conductive layer 38A, another through-hole 37A, and a conductive pad 40A are sequentially provided in the negative Z direction of the contact plug CP1. Here, an example is shown where two conductive layers (or wiring layers, pads) 36A and 38A are provided below the memory cylinder MP, but the number of conductive layers provided below the memory cylinder MP is arbitrary. At the ends of each conductive layer 32-34 extending in the X direction, a through hole 35B is provided via a contact plug CP2. In the through hole 35B, a conductive layer 36B, a through hole 37B, a conductive layer 38A, a through hole 39B, and a conductive pad 40B are sequentially provided in the negative direction of the Z direction. The following is a detailed description of the cross-sectional structure of the peripheral circuit chip 200. On the semiconductor substrate 50, for example, a CMOS (Complementary Metal Oxide Semiconductor) circuit CM including an n-channel MOS (Metal Oxide Semiconductor) field-effect transistor (hereinafter referred to as nMOS transistor) and a p-channel MOS field-effect transistor (hereinafter referred to as pMOS transistor) is provided. The peripheral circuits and column decoders 15A and 15B in the peripheral circuit region 14A are composed of a plurality of CMOS circuits CM. The semiconductor substrate 50 includes, for example, a silicon substrate and a silicon epitaxial layer. As shown in Figure 2, a source region, a drain region 50A, and a device separation region 50B are formed on a semiconductor substrate 50. A gate insulating layer 51 is formed in the positive Z direction of the semiconductor substrate 50 between the source region 50A and the drain region 50A, and a gate electrode 52 is formed on the gate insulating layer 51. The nMOS transistor and the pMOS transistor each include a source region 50A, a drain region 50A, a semiconductor layer of the semiconductor substrate 50, a gate insulating layer 51, and a gate electrode 52. In the source region 50A and drain region 50A, vias 53A are respectively provided in the positive Z direction, and conductive layers 54A are respectively provided in the vias 53A. In the conductive layer 54A, vias 55A, conductive layers 56A, vias 57A, conductive layers 58A, vias 59A, and conductive pads 60A are sequentially provided in the positive Z direction. The conductive pads 60A are disposed on the surface of the peripheral circuit wafer 200 in the positive Z direction. Here, an example is shown where three conductive layers (or wiring layers, pads) 54A, 56A, and 58A are provided above the nMOS transistor and pMOS transistor, but the number of conductive layers provided above the nMOS transistor and pMOS transistor is arbitrary. In another source region 50A and drain region 50A, vias 53B are respectively provided in the positive Z direction, and conductive layers 54B are respectively provided on the vias 53B. On the conductive layer 54B, vias 55B, conductive layer 56B, via 57B, conductive layer 58B, via 59B, and conductive pads 60B are sequentially provided in the positive Z direction. The conductive pads 60B are disposed on the surface of the peripheral circuit chip 200 in the positive Z direction. Here, an example is shown where three conductive layers (or wiring layers, pads) 54B, 56B, and 58B are provided above the nMOS transistor and pMOS transistor, but the number of conductive layers provided above the nMOS transistor and pMOS transistor is arbitrary. The memory array chip 100 and the peripheral circuit chip 200 are respectively bonded together, for example, with conductive pads 40A and 60A, and conductive pads 40B and 60B facing each other. This allows the conductive pads of the memory array chip 100 and the peripheral circuit chip 200, including conductive pads 40A and 60A, and conductive pads 40B and 60B, to be electrically connected to each other. Next, using FIG3, another structural example of the semiconductor memory device of the first embodiment will be described. In FIG2, a semiconductor memory device 10 formed by bonding a memory array chip 100 and a peripheral circuit chip 200 is used as an example, but it is not limited to this. This proposal can also be applied to semiconductor memory devices with other structures. Figure 3 is a cross-sectional view showing another structural example of the semiconductor memory device according to the first embodiment. For example, as shown in Figure 3, this proposal can also be applied to the semiconductor memory device 10A, which has a region 300 on a semiconductor substrate 30 where a peripheral circuit is formed and a region 400 on the region 300 where a memory cell is formed. Furthermore, in Figure 3, the interlayer insulating film between the conductive layers is omitted. The cross-sectional structure of region 300, where the peripheral circuits are formed, will be described below. A CMOS circuit CM, including an nMOS transistor and a pMOS transistor, is disposed on a semiconductor substrate 30. A source region and a drain region 50A, and a device separation region 50B are disposed on the semiconductor substrate 30. A gate insulating layer 51 is disposed in the positive Z direction of the semiconductor substrate 30 between the source region 50A and the drain region 50A, and a gate electrode 52 is disposed on the gate insulating layer 51. The nMOS transistor and the pMOS transistor each include a source region 50A, a drain region 50A, a semiconductor layer of the semiconductor substrate 30, a gate insulating layer 51, and a gate electrode 52. In the source region 50A and drain region 50A, vias 53A are respectively provided in the positive Z direction, and conductive layers 54A are respectively provided on the vias 53A. In the conductive layer 54A, vias 55A, conductive layers 56A, vias 57A, and conductive layers 58A are sequentially provided in the positive Z direction. In the conductive layer 58A, a contact plug CP3 is provided in the Z direction. The contact plug CP3 is arranged to penetrate conductive layers 31-34 in the Z direction. Furthermore, a via 35C is provided in the contact plug CP3 in the Z direction. For example, the via 35C is electrically connected to the conductive layer 36A (or bit line BL) via a wiring layer and a via (not shown). In another source region 50A and drain region 50A, vias 53B are respectively provided in the positive Z direction, and conductive layers 54B are respectively provided on vias 53B. On conductive layer 54B, vias 55B, conductive layer 56B, via 57B, and conductive layer 58B are sequentially provided in the positive Z direction. For example, conductive layer 58B is electrically connected to via 35B via a wiring layer and a via (not shown). The cross-sectional structure of region 400, where memory cells are formed, is described below. Region 400 is disposed on region 300. In the laminate containing conductive layers 32-34 above region 300 on the semiconductor substrate 30, a plurality of memory pillars MP in the form of pillars are disposed. Each memory pillar MP is arranged to extend in the Z direction and penetrate the conductive layers 32-34 in the Z direction. A contact plug CP1 is provided in the positive Z direction of the memory cylinder MP. A through-hole 35A and a conductive layer 36A are sequentially provided on the contact plug CP1 in the positive Z direction. Details of the memory cylinder MP are described below. At the ends of each conductive layer 32-34 extending in the X direction, a through hole 35B is provided in the positive direction of the Z direction via a contact plug CP2. Next, the circuit configuration of memory cell array 11A will be explained using Figure 4. Memory cell array 11A has a plurality of blocks BLK0 to BLKm (m is an integer greater than or equal to 0). Here, the circuit configuration of one block BLK will be explained, and the circuit configurations of the other blocks will be explained in the same way. Furthermore, the circuit configurations of memory cell arrays 11B to 11D are also the same as the circuit configuration of memory cell array 11A. Figure 4 is a circuit diagram of a block BLK within the memory cell array 11A. The block BLK, for example, has a plurality of serial units SU0, SU1, SU2, and SU3. Here, as an example, an example is shown where the block BLK has serial units SU0 to SU3, but the number of serial units in the block BLK can be arbitrarily set. Hereinafter, when denoted as serial unit SU, each of serial units SU0 to SU3 will be represented. Each of the string units SU0 to SU3 has a plurality of NAND strings (or memory strings) NS. The number of NAND strings NS contained in a single string unit SU can be set arbitrarily. The NAND string NS comprises a plurality of memory transistors MT0, MT1, MT2, ..., MT7 and select transistors ST1 and ST2. For ease of explanation, an example is shown here where the NAND string NS has 8 memory transistors MT0 to MT7 and 2 select transistors ST1 and ST2; however, the number of memory transistors and select transistors in the NAND string NS can be arbitrarily set. Hereinafter, when denoted as memory transistor MT, each of the memory transistors MT0 to MT7 will be represented. Each of the memory cell transistors MT0 to MT7 has a control gate and a charge storage layer, and stores data in a non-volatile manner. The memory cell transistors MT0 to MT7 are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. Memory cell transistors (MTs) can store 1 bit of data or more than 2 bits of data. MTs can be either MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, which uses an insulating film as the charge storage layer, or FG (Floating Gate) type, which uses a conductive layer as the charge storage layer. The gates of the plurality of select transistors ST1 contained in the serial unit SU0 are connected to the select gate line SGD0. Similarly, the gates of the select transistors ST1 of each of the serial units SU1 to SU3 are connected to the select gate lines SGD1 to SGD3 respectively. Each select gate line SGD0 to SGD3 is independently controlled by the serial decoder. The gates of the plurality of select transistors ST2 contained in the serial unit SU0 are connected to the select gate line SGS. Similarly, the gates of the select transistors ST2 of each of the serial units SU1 to SU3 are connected to the select gate line SGS. Furthermore, sometimes the gates of the select transistors ST2 of the serial units SU0 to SU3 contained in the block BLK are also connected to individual select gate lines SGS, namely select gate lines SGS0 to SGS3. Select transistors ST1 and ST2 are used to select the serial unit SU in various operations. The control gates of the memory cell transistors MT0 to MT7 contained in block BLK are respectively connected to word lines WL0 to WL7. Each word line WL0 to WL7 is independently controlled by the column decoder. Bit lines BL0 to BLi (where i is an integer greater than or equal to 0) are connected to a plurality of blocks BLK, and to one NAND string NS within a string unit SU contained in a block BLK. That is, bit lines BL0 to BLi are connected to the drains of the select transistor ST1 of a plurality of NAND strings NS located in the same row within a matrix-arranged array of NAND strings NS in a block BLK. Furthermore, source lines SL are connected to a plurality of blocks BLK. That is, source lines SL are connected to the sources of a plurality of select transistors ST2 contained in a block BLK. In summary, a string cell SU comprises a plurality of NAND strings NS connected to different bit lines BL and connected to the same select gate line SGD. Furthermore, a block BLK comprises a plurality of string cells SU that make the word lines WL common. Moreover, the memory cell array 11A comprises a plurality of blocks BLK that make the bit lines BL common. A block (BLK) can be used as a unit for data erasure. That is, the data stored in the memory cell transistors (MTs) within the same block (BLK) can be erased all at once. Furthermore, data can be erased in units of serial units (SU), or in units less than SU. A plurality of memory cell transistors (MTs) sharing a word line (WL) within a single serial unit (SU) is called a unit group (CU). The collection of 1-bit data stored by each of the plurality of memory cell transistors (MTs) within a unit group (CU) is called a page. The memory capacity of a unit group (CU) varies depending on the number of bits of data stored by each memory cell transistor (MT). For example, a unit group (CU) stores 1 page of data when each memory cell transistor (MT) stores 1 bit of data, 2 pages of data when each memory cell transistor (MT) stores 2 bits of data, and 3 pages of data when each memory cell transistor (MT) stores 3 bits of data. Write and read operations for a unit group (CU) are performed on a page-by-page basis. In other words, read and write operations are performed simultaneously on multiple memory cell transistors (MTs) connected to a single word line (WL) in a single serial unit (SU). Furthermore, the memory cell arrays 11A to 11D can also be configured in other ways. For example, the configuration of the memory cell arrays 11A to 11D is described in U.S. Patent Application No. 12 / 407,403, filed on March 19, 2009, entitled "THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY". Furthermore, the configuration of memory cell arrays 11A to 11D is described in U.S. Patent Application No. 12 / 406,524, filed March 18, 2009, entitled "THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY"; U.S. Patent Application No. 12 / 679,991, filed March 25, 2010, entitled "NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME"; and U.S. Patent Application No. 12 / 532,030, filed March 23, 2009, entitled "SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME". All contents of these patent applications are incorporated herein by reference. Next, using Figure 5, the cross-sectional structure of the memory pillars MP (or NAND strings NS) in the memory cell array 11A will be explained. Here, the memory pillars MP within the memory cell array 11A are shown, but the memory pillars MP within each memory cell array 11B to 11D are also shown in the same way. The memory pillar MP includes memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Figure 5 is a cross-sectional view of the memory pillars MP within the memory cell array 11A in the first embodiment. In Figure 5, the memory pillars MP shown in Figure 2 are shown after being rotated 180 degrees, and the memory pillars MP shown in Figure 3 are shown in the state before rotation. Furthermore, the interlayer insulating film between the conductive layers is omitted in Figure 5. As shown in Figure 5, the memory cell array 11A includes a semiconductor substrate 30, conductive layers 31-34, memory pillars MP, contact plugs CP1, vias 35A, and a conductive layer 36A. A conductive layer 31 is disposed above the semiconductor substrate 30. The conductive layer 31 is formed as a flat plate parallel to the XY plane and functions as a source line SL. Furthermore, the main surface of the semiconductor substrate 30 corresponds to the XY plane. On the conductive layer 31, a plurality of slits SLT along the XZ plane are arranged in the Y direction. The structure (or stack) between adjacent slits SLT on the conductive layer 31 corresponds, for example, to one string unit SU. Between adjacent slits SLT on conductive layer 31, conductive layer 32, a plurality of conductive layers 33, conductive layer 34, and conductive layer 36A are sequentially disposed from the bottom layer. In these conductive layers, an interlayer insulating film is deposited between adjacent conductive layers in the Z direction. Conductive layers 32-34 are respectively formed as flat plates parallel to the XY plane. Conductive layer 32 functions as the selector gate line (SGS). The plurality of conductive layers 33, sequentially disposed from the bottom layer, function as word lines WL0-WL7. Conductive layer 34 functions as the selector gate line (SGD). Conductive layers 31-34, for example, contain tungsten (W) or polycrystalline silicon. A plurality of memory pillars MP are arranged in a zigzag pattern, for example, in the X and Y directions. The plurality of memory pillars MP extend (or penetrate) within the stacked layers between the slits SLT in the Z direction. Each memory pillar MP is disposed through conductive layers 34, 33, and 32, extending from the upper surface of conductive layer 34 to the upper surface of conductive layer 31. Each memory pillar MP functions as a NAND string NS. Memory pillars (MPs) may include, for example, a barrier insulating layer 71, a charge storage layer 72, a tunnel insulating layer (also known as a tunnel insulating film) 73, and a semiconductor layer 74. Specifically, a barrier insulating layer 71 is disposed on the inner wall of the memory hole used to form the memory pillar MP. A charge storage layer 72 is disposed on the inner wall of the barrier insulating layer 71. A tunnel insulating layer 73 is disposed on the inner wall of the charge storage layer 72. Furthermore, a semiconductor layer 74 is disposed inside the tunnel insulating layer 73. Alternatively, the memory pillar MP may be configured such that a core insulating layer is disposed inside the semiconductor layer 74. In this configuration of the memory pillar MP, the portion where the memory pillar MP intersects with the conductive layer 32 functions as the select transistor ST2. The portions where the memory pillar MP intersects with the conductive layer 33 function as memory cell transistors MT0 to MT7, respectively. Furthermore, the portion where the memory pillar MP intersects with the conductive layer 34 functions as the select transistor ST1. Semiconductor layer 74 functions as a channel layer for memory cell transistor MT and select transistors ST1 and ST2. Current paths for the NAND string NS are formed within semiconductor layer 74. The charge storage layer 72 has the function of storing the charge injected from the semiconductor layer 74 in the memory cell transistor MT. The charge storage layer 72 includes, for example, a silicon nitride film. The tunnel insulating layer 73 functions as a potential barrier when charge is injected from the semiconductor layer 74 into the charge storage layer 72, or when charge stored in the charge storage layer 72 diffuses into the semiconductor layer 74. The tunnel insulating layer 73 may include, for example, a silicon oxide film. The barrier insulating layer 71 prevents the charge stored in the charge storage layer 72 from diffusing to the conductive layer 33 (word line WL). The barrier insulating layer 71 may include, for example, a silicon oxide layer and a silicon nitride layer. A conductive layer 36A is disposed on the upper surface of the memory cylinder MP via a contact plug CP1 and a via 35A. The conductive layer 36A is a linear wiring layer extending in the Y direction, functioning as a bit line BL. A plurality of conductive layers 36A are arranged in the X direction, and the conductive layer 36A is electrically connected to one memory cylinder MP corresponding to each string cell SU. Specifically, in each string cell SU, a contact plug CP1 is disposed on the semiconductor layer 74 within each memory cylinder MP, a via 35A is disposed on the contact plug CP1, and then the conductive layer 36A is disposed on the via 35A. The conductive layer 36A may contain, for example, copper (Cu), aluminum (Al), or tungsten (W). The contact plug CP1 and the via 35A contain a conductive layer, for example, tungsten (W). Furthermore, the number of character lines WL and select gate lines SGD and SGS is not limited to the above-mentioned number and can be changed according to the number of memory cell transistors MT and select transistors ST1 and ST2. The select gate line SGS can be composed of multiple conductive layers respectively disposed in multiple layers. The select gate line SGD can be composed of multiple conductive layers respectively disposed in multiple layers. Next, the circuit block configuration of the semiconductor memory device 10 (or 10A) according to the first embodiment will be described using Figures 6 and 7. The semiconductor memory device 10 includes peripheral circuits corresponding to the memory cell array and redundant circuits that can be replaced in case of failure of the peripheral circuits. Figure 6 is a diagram showing the circuit block configuration of the memory array chip 100 in the semiconductor memory device 10 of the first embodiment. As described above, memory cell array 11A is disposed between lead-out regions 12A and 12B. Similarly, memory cell arrays 11B, 11C, and 11D are disposed between lead-out regions 12C and 12D, 12E and 12F, and 12G and 12H, respectively. Pad region 13A is disposed adjacent to memory cell arrays 11B and 11D. Figure 7 is a diagram showing the circuit block configuration of the peripheral circuit chip 200 in the semiconductor memory device 10 of the first embodiment. The peripheral circuit chip 200 includes sense amplifiers 16A, 16B, 16C, 16D, peripheral circuits 17A, 17B, 17C, 17D, redundant circuits 18A, 18B, column decoders 15A to 15H, and pad area 13B. As shown in Figure 7, when viewed from above, a sensing amplifier 16A, peripheral circuitry 17A, redundant circuitry 18A, column decoder 15A, and column decoder 15B are arranged in the upper left region. The sensing amplifier 16A and peripheral circuitry 17A are positioned between the column decoders 15A and 15B, which are arranged in the X direction. The sensing amplifier 16A, peripheral circuitry 17A, column decoders 15A, 15B, and redundant circuitry 18A correspond to the memory cell array 11A. A sense amplifier 16B, peripheral circuitry 17B, column decoder 15C, and column decoder 15D are disposed in the lower left region. The sense amplifier 16B and peripheral circuitry 17B are positioned between column decoders 15C and 15D, which are arranged in the X direction. The sense amplifier 16B, peripheral circuitry 17B, column decoders 15C, 15D, and redundant circuitry 18A correspond to the memory cell array 11B. Redundant circuit 18A is disposed between column decoders 15A and 15C arranged in the Y direction and column decoders 15B and 15D arranged in the Y direction. Alternatively, redundant circuit 18A may also be disposed between column decoders 15A and 15B, or between column decoders 15C and 15D. Furthermore, redundant circuit 18A is disposed adjacent to peripheral circuits 17A and 17B. For example, a switching circuit (not shown) is provided between peripheral circuit 17A and redundant circuit 18A, by means of the switching circuit to select either peripheral circuit 17A or redundant circuit 18A. A switching circuit (not shown) is provided between peripheral circuit 17B and redundant circuit 18A, by means of the switching circuit to select either peripheral circuit 17B or redundant circuit 18A. As shown in Figure 7, when viewed from above, a sensing amplifier 16C, peripheral circuitry 17C, redundant circuitry 18B, column decoder 15E, and column decoder 15F are arranged in the upper right region. The sensing amplifier 16C and peripheral circuitry 17C are positioned between the column decoders 15E and 15F, which are arranged in the X direction. The sensing amplifier 16C, peripheral circuitry 17C, column decoders 15E, 15F, and redundant circuitry 18B correspond to the memory cell array 11C. A sense amplifier 16D, peripheral circuitry 17D, column decoder 15G, and column decoder 15H are disposed in the lower right region. The sense amplifier 16D and peripheral circuitry 17D are positioned between column decoders 15G and 15H, which are arranged in the X direction. The sense amplifier 16D, peripheral circuitry 17D, column decoders 15G and 15H, and redundant circuitry 18B correspond to the memory cell array 11D. Redundant circuit 18B is configured between column decoders 15E and 15G arranged in the Y direction and column decoders 15F and 15H arranged in the Y direction. Alternatively, redundant circuit 18B may also be configured between column decoders 15E and 15F, or between column decoders 15G and 15H. Furthermore, redundant circuit 18B is configured adjacent to peripheral circuits 17C and 17D. For example, a switching circuit (not shown) is provided between peripheral circuit 17C and redundant circuit 18B, by means of the switching circuit to select either peripheral circuit 17C or redundant circuit 18B. A switching circuit (not shown) is provided between peripheral circuit 17D and redundant circuit 18B, by means of the switching circuit to select either peripheral circuit 17D or redundant circuit 18B. Redundant circuit 18A has the same configuration and function as peripheral circuits 17A and 17B. Redundant circuit 18B has the same configuration and function as peripheral circuits 17C and 17D. Details of redundant circuits 18A and 18B are described below. When peripheral circuits 17A or 17B malfunction and cannot operate normally, redundant circuit 18A takes over the operation of peripheral circuits 17A or 17B. That is, when peripheral circuits 17A or 17B are defective and malfunctioning, the defective peripheral circuit 17A or 17B is replaced by redundant circuit 18A. Similarly, when peripheral circuits 17C or 17D malfunction and cannot operate normally, redundant circuit 18B takes over the operation of peripheral circuits 17C or 17D. That is, when peripheral circuits 17C or 17D are defective and malfunctioning, the defective peripheral circuit 17C or 17D is replaced by redundant circuit 18B. Furthermore, in the above description of the circuit block structure, the semiconductor memory device 10 was used as an example, but the semiconductor memory device 10A also has the same circuit block structure. Although the semiconductor memory device 10A is not divided into peripheral circuit chip 200 and memory array chip 100, the peripheral circuit chip 200 can be regarded as the region 300 in which peripheral circuits are formed, and the memory array chip 100 can be regarded as the region 400 in which memory cells are formed. Next, using FIG8, the detailed configuration of the circuit blocks of the semiconductor memory device 10 (or 10A) of the first embodiment will be described. FIG8 is a diagram showing the detailed configuration of the circuit blocks of the semiconductor memory device 10. In FIG8, the configuration of the memory cell array 11A and the peripheral circuits corresponding to the memory cell array 11A are shown. The semiconductor memory device 10 includes a memory cell array 11A, column decoders 15A and 15B, a sense amplifier 16A, a data buffer 19, a row decoder 20, an input / output circuit 21, a logic control circuit 22, a ready / busy circuit 23, row logic control circuits 24-1 and 24-2, column logic control circuits 25-1 and 25-2, a high voltage generation circuit 26-1 and 26-2, a low voltage generation circuit 27-1 and 27-2, a driver 28, and a sequencer (or control circuit) 29. The peripheral circuit 17A shown in Figure 7 includes, for example, a row logic control circuit 24-1, a column logic control circuit 25-1, a high voltage generation circuit 26-1, and a low voltage generation circuit 27-1. The redundant circuit 18A includes, for example, a row logic control circuit 24-2, a column logic control circuit 25-2, a high voltage generation circuit 26-2, and a low voltage generation circuit 27-2. Redundant circuit 18A has the same configuration and function as peripheral circuit 17A. That is, row logic control circuit 24-2 has the same configuration and function as row logic control circuit 24-1. Similarly, column logic control circuit 25-2 has the same configuration and function as column logic control circuit 25-1. High voltage generation circuit 26-2 has the same configuration and function as high voltage generation circuit 26-1. Furthermore, low voltage generation circuit 27-2 has the same configuration and function as low voltage generation circuit 27-1. The memory cell array 11A has one or more blocks BLK0, BLK1, BLK2, ..., BLKm. Each block BLK contains a plurality of memory cell transistors corresponding to columns and rows. The memory cell transistor system consists of electrically rewritable non-volatile memory cells. A plurality of word lines, a plurality of bit lines, and source lines are provided in the memory cell array 11A to control the voltage applied to the memory cell transistors. Hereinafter, when denoted as a block BLK, each block BLK0 to BLKm is represented. The specific structure of each block BLK is as described above. The input / output circuit 21 and the logic control circuit 22 are connected to an external device (e.g., a memory controller) (not shown) via a bus. The input / output circuit 21 transmits and receives signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) with the memory controller via the bus. The logic control circuit 22 receives external control signals from the memory controller via a bus. These external control signals include, for example, the chip enable signal CEn, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REen, and the write protection signal WPn. The "n" prefix in the signal name indicates that the signal is active low. The chip enable signal CEn selects the semiconductor memory device (NAND flash memory) 10 and takes effect when the semiconductor memory device 10 is selected. The instruction latch enable signal CLE latches the instruction sent in the form of the DQ signal to the input / output circuit 21. The address latch enable signal ALE latches the address sent in the form of the DQ signal to the input / output circuit 21. The write enable signal WEn saves the data sent in the form of the DQ signal to the input / output circuit 21. The read enable signal REn outputs the data read from the memory cell array 11A in the form of the DQ signal. The write protection signal WPn takes effect when writing and erasing of the semiconductor memory device 10 is prohibited. The ready / busy circuit 23 generates a ready / busy signal R / Bn based on control from the sequencer 29. Signal R / Bn indicates whether the semiconductor memory device 10 is in a ready or busy state. A ready state indicates that it can receive commands from the memory controller. A busy state indicates that it cannot receive commands from the memory controller. The memory controller can determine whether the semiconductor memory device 10 is in a ready or busy state by receiving signal R / Bn from the semiconductor memory device 10. The row logic control circuits 24-1 and 24-2 receive the row address from the input / output circuit 21 and decode the row address. Based on the decoding result of the row address, the row logic control circuits 24-1 and 24-2 set the voltage of the sensing amplifier 16A and control the voltage supplied to the sensing amplifier 16A. The row logic control circuits 24-1 and 24-2 decode the row address, select the bit line BL based on the decoding result, and control the voltage supplied to the selected bit line BL. Column logic control circuits 25-1 and 25-2 receive column addresses from input / output circuit 21 and decode them. Based on the decoding result of the column addresses, column logic control circuits 25-1 and 25-2 output signals indicating the selected block and page of the action object. Furthermore, column logic control circuits 25-1 and 25-2 control the voltage supplied to the word line WL and the selection gate line. The address includes the column address, which may include, for example, the block address specifying the block BLK of the action object, and the page address specifying the word line of the action object within the specified block. The sequencer 29 receives instructions from external devices and inputs to the input / output circuit 21, and controls the semiconductor memory device 10 according to the sequence of these instructions. The sequencer 29 controls, for example, column decoders 15A and 15B, sense amplifier 16A, data register 19, row decoder 20, driver 28, row logic control circuits 24-1 and 24-2, column logic control circuits 25-1 and 25-2, high voltage generation circuits 26-1 and 26-2, and low voltage generation circuits 27-1 and 27-2, to perform write, read, and erase operations. Specifically, the sequencer 29, based on the received write command, controls the driver 28, column decoders 15A and 15B, row decoder 20, data register 19, and sense amplifier 16A to write data to a plurality of memory cell transistors specified by address. Furthermore, the sequencer 29, based on the received read command, controls the column decoders 15A and 15B, driver 28, and sense amplifier 16A to read data from the plurality of memory cell transistors specified by address. Driver 28 receives a plurality of voltages from high voltage generation circuits 26-1 and 26-2, and low voltage generation circuits 27-1 and 27-2. Driver 28 supplies a plurality of voltages selected according to read operation, write operation, and erase operation from the plurality of voltages supplied from high voltage generation circuits 26-1 and 26-2 and low voltage generation circuits 27-1 and 27-2 to column decoders 15A and 15B via a plurality of signal lines. Based on the decoding result of the column address received by the column logic control circuit 25-1 or 25-2, column decoders 15A and 15B select any block BLK, and then select the word lines within the selected block BLK. Subsequently, column decoders 15A and 15B transmit multiple voltages supplied from driver 28 to the selected block BLK. The row decoder 20 selects bit lines based on the decoding result of the row address received by its own logic control circuit 24-1 or 24-2. The data buffer 19 temporarily stores the read or written data during data read or write operations. During data readout, the sense amplifier 16A detects and amplifies the data read from the memory cell transistor to the bit line. The data buffer 19 temporarily stores the readout data from the memory cell transistor and transmits it to the input / output circuit 21. Similarly, during data writeout, the data buffer 19 temporarily stores the write data transmitted from the input / output circuit 21. The sense amplifier 16A then transmits the write data stored in the data buffer 19 to the bit line. 1.2 Operation of the Semiconductor Memory Device In addition to the normally used peripheral circuits 17A or 17B, the semiconductor memory device 10 also includes a redundant circuit 18A that replaces peripheral circuits 17A or 17B when they malfunction. Furthermore, in addition to peripheral circuits 17C or 17D, a redundant circuit 18B is also included that replaces peripheral circuits 17C or 17D when they malfunction. The following describes the operation of switching from peripheral circuit 17A or 17B to redundant circuit 18A within the semiconductor memory device 10. Furthermore, the switching from peripheral circuit 17C or 17D to redundant circuit 18B is the same, and therefore will not be described further. The semiconductor memory device 10 includes, for example, a row logic control circuit 24-1, a column logic control circuit 25-1, a high voltage generation circuit 26-1, and a low voltage generation circuit 27-1 as peripheral circuits 17A or 17B. Furthermore, it includes a row logic control circuit 24-2, a column logic control circuit 25-2, a high voltage generation circuit 26-2, and a low voltage generation circuit 27-2 as redundant circuits 18A for peripheral circuits 17A or 17B. When any of the peripheral circuits 17A or 17B is operating normally, the circuits within peripheral circuits 17A and 17B are used. For example, when the row logic control circuit 24-1, column logic control circuit 25-1, high voltage generation circuit 26-1, and low voltage generation circuit 27-1 are operating normally, these circuits are used. On the other hand, if either of the peripheral circuits 17A or 17B malfunctions and cannot be used, a circuit within the redundant circuit 18A is used to replace the malfunctioning circuit. For example, if the horizontal logic control circuit 24-1 malfunctions and cannot operate normally, the horizontal logic control circuit 24-2 is used to replace the horizontal logic control circuit 24-1. Specifically, the circuit connection to the horizontal logic control circuit 24-1 is disconnected, and the circuit connection to the horizontal logic control circuit 24-2 is executed. Similarly, when column logic control circuit 25-1 malfunctions and cannot operate normally, column logic control circuit 25-2 is used to replace column logic control circuit 25-1. Specifically, the circuit connection to column logic control circuit 25-1 is disconnected, and the circuit connection to column logic control circuit 25-2 is executed. Furthermore, for example, when the high-voltage generating circuit 26-1 malfunctions and cannot operate normally, the high-voltage generating circuit 26-2 is used instead of the high-voltage generating circuit 26-1. Specifically, the circuit connection to the high-voltage generating circuit 26-1 is disconnected, and the circuit connection to the high-voltage generating circuit 26-2 is established. Thus, for example, when the high-voltage generating circuit 26-1 is in operation, the high-voltage generating circuit 26-2 is in a non-operational state; when the high-voltage generating circuit 26-2 is in operation, the high-voltage generating circuit 26-1 is in a non-operational state. Similarly, when the low voltage generating circuit 27-1 malfunctions and cannot operate normally, the low voltage generating circuit 27-2 is used to replace the low voltage generating circuit 27-1. Specifically, the circuit connection to the low voltage generating circuit 27-1 is disconnected, and the circuit connection to the low voltage generating circuit 27-2 is established. The following describes the operation of switching from peripheral circuit 17A or 17B to redundant circuit 18A. Within the memory cell array 11A, there is typically a memory region that stores setting information required for operation. For example, here, this memory region is designated as a block (hereinafter referred to as ROM (Read Only Memory) block) BLK0. When power is supplied to the semiconductor memory device 10, setting information is read from ROM block BLK0, and various settings in the semiconductor memory device 10 are performed based on this setting information. Switching information is pre-memorized in ROM block BLK0. This switching information indicates that when peripheral circuits 17A or 17B are faulty and cannot operate normally, the faulty peripheral circuit will be switched to redundant circuit 18A. When power is supplied to the semiconductor memory device 10, the sequencer 29 reads the switching information from the ROM block BLK0 and, based on the switching information, switches the faulty peripheral circuits 17A or 17B to the redundant circuit 18A. For example, switching information is pre-memorized in ROM block BLK0. This switching information indicates that when the high voltage generating circuit 26-1 malfunctions and cannot operate normally, the high voltage generating circuit 26-1 will be switched to the high voltage generating circuit 26-2 in the redundant circuit 18A. When power is supplied to the semiconductor memory device 10, the sequencer 29 reads the switching information from the ROM block BLK0. Subsequently, based on the switching information, the sequencer 29 switches the high voltage generation circuit 26-1 to the high voltage generation circuit 26-2. As described above, the switching from peripheral circuit 17A or 17B to redundant circuit 18A is performed based on information stored in the memory region within the memory cell array 11A, such as ROM block BLK0. 1.3 Effects of the first embodiment According to the first embodiment, the reliability of operation in the semiconductor memory device can be improved. The effects of the first embodiment will be described in detail below. For example, in a semiconductor memory device with multiple memory cells and their surrounding circuits disposed on the same semiconductor substrate, adding redundant circuitry to the surrounding circuitry would increase the area and thus the cost. Therefore, it is often difficult to implement redundant circuitry. Consequently, if the surrounding circuitry is faulty, the semiconductor memory device may sometimes become a defective product. In the first embodiment, the semiconductor memory device includes: a memory cell transistor (MT) disposed above a semiconductor substrate; a first voltage generation circuit disposed between the semiconductor substrate and the memory cell transistor (MT) and generating a first voltage supplied to the memory cell transistor (MT); and a second voltage generation circuit disposed between the semiconductor substrate and the memory cell transistor (MT) and generating the first voltage, having the same configuration as the first voltage generation circuit. The first voltage generation circuit may be, for example, a row logic control circuit 24-1, a column logic control circuit 25-1, a high voltage generation circuit 26-1, and a low voltage generation circuit 27-1 serving as peripheral circuits 17A or 17B. The second voltage generation circuit may be, for example, a row logic control circuit 24-2, a column logic control circuit 25-2, a high voltage generation circuit 26-2, and a low voltage generation circuit 27-2 serving as redundant circuit 18A. Furthermore, in the event of a malfunction in the first voltage generation circuit, the first voltage generation circuit is switched to the second voltage generation circuit, thereby utilizing the second voltage generation circuit. In this way, a faulty first voltage generation circuit can be salvaged by a second voltage generation circuit, which serves as a redundancy circuit. As a result, the reliability of operation in the semiconductor memory device can be improved, thereby increasing the yield of the semiconductor memory device. Furthermore, in the first embodiment, the semiconductor memory device further includes: a word line WL electrically connected to the gate of a memory cell transistor MT; a bit line BL electrically connected to one end of the memory cell transistor MT; a column logic control circuit 25-1 disposed between the semiconductor substrate and the memory cell transistor MT, which selects the word line WL based on the column address and controls the voltage supplied to the selected word line WL; a column logic control circuit 25-2 disposed between the semiconductor substrate and the memory cell transistor MT, and having a circuit configuration equivalent to the column logic control circuit 25-1; a row logic control circuit 24-1 disposed between the semiconductor substrate and the memory cell transistor MT, which selects the bit line BL based on the row address and controls the voltage supplied to the selected bit line BL; and a row logic control circuit 24-2 disposed between the semiconductor substrate and the memory cell transistor MT, and having a circuit configuration equivalent to the row logic control circuit 24-1. Furthermore, if the column logic control circuit 25-1 malfunctions, it will be switched to column logic control circuit 25-2. If the row logic control circuit 24-1 malfunctions, it will be switched to row logic control circuit 24-2. Therefore, the faulty column logic control circuit 25-1 can be rectified by the redundant column logic control circuit 25-2. The faulty row logic control circuit 24-1 can be rectified by the redundant row logic control circuit 24-2. As a result, the reliability of operation in the semiconductor memory device can be improved, thereby improving the yield of the semiconductor memory device. 2. Second Embodiment Next, the semiconductor memory device of the second embodiment will be described. In the second embodiment, the description will focus on the example of providing photolithography patterns (e.g., alignment marks, dimensional accuracy marks) and monitoring test patterns in the areas where redundant circuitry is configured in the semiconductor memory device 10 shown in FIG. 2 or the semiconductor memory device 10A shown in FIG. 3, the end areas of the semiconductor memory device 10 or 10A, and the pad areas. In the second embodiment, the semiconductor memory device 10 will be used as an example for description. Furthermore, in the second embodiment, the differences between it and the first embodiment will be mainly described. 2.1 Configuration of Semiconductor Memory Device First, the circuit block configuration of the memory array chip 100 in the semiconductor memory device 10 of the second embodiment will be described using FIG9. FIG9 is a diagram showing the circuit block configuration of the memory array chip 100 in the semiconductor memory device 10. The solder pad region 13A is arranged adjacent to the memory cell arrays 11B and 11D. A photolithography pattern 75 and a monitoring test pattern 76 are provided in the solder pad region 13A. The photolithography pattern 75 includes, for example, alignment marks for aligning the photomask and dimensional accuracy marks (or dimensional measurement marks) for evaluating the dimensional accuracy of the pattern. The monitoring test pattern 76 includes, for example, a TEG (Test Element Group). The TEG includes, for example, components such as transistors for characteristic evaluation. Other configurations are the same as those described in Figure 6. Next, the circuit block configuration of the peripheral circuit chip 200 in the semiconductor memory device 10 of the second embodiment will be described using FIG10. FIG10 is a diagram showing the circuit block configuration of the peripheral circuit chip 200 in the semiconductor memory device 10. In the peripheral circuit chip 200 of the first embodiment shown in FIG7, a region with redundant circuits 18A and 18B is provided, and a photolithography pattern 75 and a monitoring test pattern 76 are provided. As shown in Figure 10, when viewed from above, in the left-hand region, the photolithography pattern 75 and the monitoring test pattern 76 are positioned between the column decoders 15A and 15C arranged in the Y direction and the column decoders 15B and 15D arranged in the Y direction. Alternatively, the pattern 75 and the test pattern 76 can also be positioned between column decoders 15A and 15B, or between column decoders 15C and 15D. Furthermore, the pattern 75 and the test pattern 76 are positioned between peripheral circuits 17A and 17B. As shown in Figure 10, when viewed from above, in the right-hand region, the photolithography pattern 75 and the monitoring test pattern 76 are positioned between the column decoders 15E and 15G arranged in the Y direction and the column decoders 15F and 15H arranged in the Y direction. Alternatively, the pattern 75 and the test pattern 76 can also be positioned between column decoders 15E and 15F, or between column decoders 15G and 15H. Furthermore, the pattern 75 and the test pattern 76 are positioned between peripheral circuits 17C and 17D. Furthermore, as shown in Figure 10, when viewed from above, a photolithography pattern 75 and a monitoring test pattern 76 are provided in the end regions adjacent to sensing amplifiers 16A and 16C. Pattern 75 and test pattern 76 are respectively disposed between column decoders 15A and 15B, and between column decoders 15E and 15F. Next, using Figures 11 and 12, details of the alignment mark 75 used as a photolithography pattern and the TEG used as a monitoring test pattern 76 will be explained. Figure 11 is a top view showing an example of alignment marks provided on the peripheral circuit chip 200 of the semiconductor memory device 10. As shown in Figure 11, pattern 75A is disposed on the portions corresponding to the sides of a rectangle, and pattern 75B is disposed at intervals outside pattern 75A. When pattern 75A is formed using the first photomask and pattern 75B is formed using the second photomask, pattern 75B is aligned in such a way that the intervals between pattern 75A and pattern 75B are equal. Figure 12 is a cross-sectional view along line BB in Figure 10, and is a cross-sectional view showing an example of a TEG located in the peripheral circuit chip 200. As shown in Figure 12, a source region, a drain region 80A, and a device separation region 80B are provided on a semiconductor substrate 50. A gate insulating layer 81 is provided in the positive Z direction of the semiconductor substrate 50 between the source region 80A and the drain region 80A, and a gate electrode 82 is provided on the gate insulating layer 81. The nMOS transistor or pMOS transistor TR constituting the TEG includes the source region 80A, the drain region 80A, the semiconductor layer of the semiconductor substrate 50, the gate insulating layer 81, and the gate electrode 82. In the source region 80A and drain region 80A, through-holes 83 are respectively provided in the positive Z direction, and conductive layers 84 are respectively provided in the through-holes 83. In the conductive layer 84, through-holes 85 and conductive pads 86 are sequentially provided in the positive Z direction. In the conductive pads 86, an insulating layer 87 is provided in the positive Z direction. In the insulating layer 87, conductive layers 88 and 89 are sequentially provided in the positive Z direction as a dielectric insulating layer. Furthermore, the conductive pads 86 are covered by the insulating layer 87 and are not electrically connected to upper wiring (e.g., conductive layer 88) or external terminals. 2.2 Effects of the Second Embodiment According to the second embodiment, the same as the first embodiment described above, the reliability of operation in the semiconductor memory device can be improved. The effects of the second embodiment will be described in detail below. Figure 13 is a top view showing wafers arranged within a photomask during the manufacturing process of a semiconductor memory device as a comparative example. For example, as shown in Figure 13, a plurality of semiconductor memory devices (hereinafter referred to as wafers) 10 are arranged within the area of ​​the photomask 201 used by the exposure apparatus. Cutting lines 202 are provided between the plurality of wafers for cutting the wafers one by one. Photolithography patterns (e.g., alignment marks and dimensional accuracy marks) and monitoring test patterns are arranged on the cutting lines 202. While the width of the cleaving line 202 can be reduced technically, there are limits to its miniaturization due to the area required to configure photolithography patterns and monitoring test patterns. Furthermore, the limited area on the cleaving line 202 restricts the types of photolithography patterns and test patterns that can be configured. Therefore, there are often situations where high-performance photolithography patterns and monitoring test patterns with a large amount of available information cannot be configured. Therefore, in the second embodiment, by arranging the photolithography pattern 75 and the monitoring test pattern 76 in the wafer region that is closer to the inner side of the dicing line 202, the area on the dicing line 202 required for arranging the photolithography pattern 75 and the monitoring test pattern 76 can be reduced, thereby reducing the width of the dicing line 202. Furthermore, since the width of the dicing line 202 can be reduced, the number of wafers in each wafer can be increased, thereby reducing the cost of the product (i.e., semiconductor memory device). Furthermore, by using the chip area that is closer to the inner side of the dicing line 202 as the area for configuring the photolithography pattern 75 and the monitoring test pattern 76, it is possible to configure high-performance photolithography patterns and monitoring test patterns that cannot be configured on the dicing line 202 or have a large amount of information available. According to the second embodiment, the reliability of operation in a semiconductor memory device can be improved. Furthermore, the number of wafers (semiconductor memory devices) in each wafer can be increased, thereby reducing the cost of the semiconductor memory device. Furthermore, in the second embodiment, a semiconductor memory device 10 formed by bonding the memory array chip 100 and the peripheral circuit chip 200 as shown in FIG2 was described as an example, but it is not limited to this. It can also be applied to a semiconductor memory device 10A formed by setting the region 300 on which the peripheral circuit is formed and the region 400 on which the memory cell is formed on the region 300 as shown in FIG3 on a semiconductor substrate 30. 3. Other variations are as follows: The above embodiments are described using semiconductor memory device 10 formed by bonding memory array chip 100 and peripheral circuit chip 200, and semiconductor memory device 10A formed by stacking a region 300 on which peripheral circuits are formed and a region 400 on which memory cells are formed on a semiconductor substrate 30. However, it is not limited to these, and can also be applied to semiconductor devices with other structures. Furthermore, in the above embodiments, NAND flash memory was used as an example of a semiconductor memory device, but it is not limited to NAND flash memory. It can be applied to other semiconductor memory devices, and thus to various memory devices other than semiconductor memory devices. While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and also within the scope of the invention described in the claims and their equivalents. [Related Applications] This application enjoys priority based on Japanese Patent Application No. 2019-169371 (filed on September 18, 2019). This application incorporates the entire contents of the basic application by reference to that basic application. 10, 10A: Semiconductor memory device; 11A, 11B, 11C, 11D: Memory cell array; 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H: Lead-out area; 13A: Pad area; 13B: Pad area; 14A, 14B, 14C, 14D: Peripheral circuit area; 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H: Column decoder; 16A, 16B, 16C, 16D: Sensing amplifier; 17A, 17B, 17C, 17D: Peripheral circuit; 18A, 18B: Redundancy circuit; 19: Data register; 20: Row decoder; 21: Input / output circuit; 22: Logic control circuit; 23: Ready / busy circuit; 24-1, 24-2: Row logic control circuit; 25-1, 25-2: Column logic control circuit; 26-1, 26-2: High voltage generation circuit; 27-1, 27-2: Low voltage generation circuit; 28: Driver; 29: Sequencer; 30: Semiconductor substrate; 31-34: Conductive layer; 35A: Through-hole; 35B: Through-hole; 35C: Through-hole; 36A: Conductive layer; 36B: Conductive layer; 37A: Through-hole; 37B: Through-hole; 38A: Conductive layer; 38B: 39A 39B: Through-hole 40A: Conductive pad 40B: Conductive pad 50: Semiconductor substrate 50A: Source or drain region 50B: Component separation region 51: Gate insulating layer 52: Gate electrode 53A: Through-hole 53B: Through-hole 54A: Conductive layer 54B: Conductive layer 55A: Through-hole 55B: Through-hole 56A: Conductive layer 56B: Conductive layer 57A: Through-hole 57B: Through-hole 58A: Conductive layer 58B: Conductive layer 59A: Through-hole 9B: Through-hole 60A: Conductive pad 60B: Conductive pad 71: Barrier insulating layer 72: Charge storage layer 73: Tunnel insulating layer 74: Semiconductor layer 75: Photolithography pattern 75A: Pattern 75B: Pattern 76: Test pattern for monitoring 80A: Source and drain regions 80B: Component separation region 81: Gate insulating layer 82: Gate electrode 83: Through-hole 84: Conductive layer 85: Through-hole 86: Conductive pad 87: Insulating layer 88,89: Conductive layer 100: Memory array chip 200: Peripheral circuit chip 201: Photomask 202: Cut line 300: Region 400: Region BL: Bit line BL0~BL1: Bit line BLK: Block BLK0~BLKm: Block CM: CMOS circuit CP1: Contact plug CP2: Contact plug CP3: Contact plug CU: Cell group MP: Memory column MT: Memory cell transistor MT0~MT7: Memory cell transistor NS: NAND string SGD: Select gate line SGD0~SGD3: Select gate line SGS: Select gate line SL: Source line SLT: Slit ST1, ST2: Select transistor SU: String cell SU0~SU3: String cell TR: nMOS transistor or pMOS transistor WL: Word line WL0~WL7: Word line Figure 1 is a plan view of the semiconductor memory device according to the first embodiment. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view of another structural example of the semiconductor memory device according to the first embodiment. Figure 4 is a circuit diagram of the blocks within the memory cell array in the first embodiment. Figure 5 is a cross-sectional view of the memory pillars within the memory cell array in the first embodiment. Figure 6 is a diagram showing the circuit block configuration of the memory array chip in the first embodiment. Figure 7 is a diagram showing the circuit block configuration of the peripheral circuit chip in the first embodiment. Figure 8 is a diagram showing the detailed configuration of the circuit blocks in the semiconductor memory device according to the first embodiment. Figure 9 is a diagram showing the circuit block configuration of the memory array chip in the semiconductor memory device according to the second embodiment. Figure 10 is a diagram showing the circuit block configuration of the peripheral circuit chip in the semiconductor memory device according to the second embodiment. Figure 11 is a top view showing alignment marks provided on the peripheral circuit chip in the semiconductor memory device according to the second embodiment. Figure 12 is a cross-sectional view showing an example of a TEG (Test Element Group) disposed on a peripheral circuit chip in a semiconductor memory device according to the second embodiment. Figure 13 is a top view showing a wafer arranged in a photomask during the manufacturing process of a semiconductor memory device in a comparative example. 10: Semiconductor memory devices 11A: Memory Cell Array 15A, 15B: Column Decoder 16A: Sensing Amplifier 19: Data Temporary Memory 20: Line Decoder 21: Input / output circuit 22: Logic control circuit 23: Ready / Busy Circuit 24-1, 24-2: Row logic control circuit 25-1, 25-2: Column Logic Control Circuit 26-1, 26-2: High Voltage Generation Circuit 27-1, 27-2: Low Voltage Generation Circuit 28: Driver 29: Sequencer

Claims

1. A semiconductor memory device comprising: a memory cell array; and a pad region adjacent to the memory cell array and including a first pad and a photolithography pattern, the first pad being used to connect a memory controller; the memory controller being disposed outside the semiconductor memory device; and the memory cell array comprising: a plurality of first conductive layers deposited above a substrate in a first direction; and a pillar penetrating the first conductive layers in the first direction.

2. The semiconductor memory device of claim 1, wherein the aforementioned photolithography pattern is: alignment mark.

3. The semiconductor memory device of claim 2, wherein the alignment mark comprises: a first pattern and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

4. The semiconductor memory device as claimed in claim 3, wherein the aforementioned predetermined intervals are equal to each other.

5. The semiconductor memory device as claimed in claim 1, wherein the aforementioned photolithography pattern is: a size measurement mark.

6. The semiconductor memory device of claim 1, wherein the photolithography pattern comprises: a first pattern and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

7. The semiconductor memory device of claim 1, wherein the photolithography pattern comprises: a first pattern disposed on a portion corresponding to the side of a rectangle, and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

8. The semiconductor memory device of claim 1, further comprising: a first wafer including: a first electrode pad, the memory cell array and the pad region; and a second wafer including: a second electrode pad bonded to the first electrode pad.

9. The semiconductor memory device of claim 1 further comprises: a wafer, which includes: a substrate, the memory cell array and the bonding pad region, wherein the memory cell array is disposed above the substrate.

10. The semiconductor memory device of claim 1, wherein the memory cell array comprises memory cells connected in series.

11. A semiconductor memory device comprising: a memory cell array above a substrate; a first circuit on a portion of the substrate below the memory cell array; and a photolithography pattern on another portion of the substrate below the memory cell array, and disposed on a central side of the substrate compared to the first circuit; wherein the memory cell array comprises: a plurality of first conductive layers deposited above the substrate in a first direction; and pillars penetrating the first conductive layers in the first direction.

12. The semiconductor memory device of claim 11, wherein the aforementioned photolithography pattern is: alignment mark.

13. The semiconductor memory device of claim 12, wherein the alignment mark comprises: a first pattern and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

14. The semiconductor memory device of claim 13, wherein the predetermined intervals are equal to each other.

15. The semiconductor memory device of claim 11, wherein the aforementioned photolithography pattern is: a size measurement mark.

16. The semiconductor memory device of claim 11, wherein the photolithography pattern comprises: a first pattern and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

17. The semiconductor memory device of claim 11, wherein the photolithography pattern comprises: a first pattern disposed on a portion corresponding to the side of a rectangle, and a second pattern disposed outside the first pattern, having a predetermined interval therebetween.

18. The semiconductor memory device of claim 11 further comprises: a first wafer including the memory cell array; and a second wafer including the first circuit and the photolithography pattern.

19. The semiconductor memory device of claim 18, wherein the photolithography pattern is disposed between the substrate and the memory cell array.

20. The semiconductor memory device of claim 11 further comprises: a first chip including the memory cell array, the first circuit and the photolithography pattern.

21. The semiconductor memory device of claim 11, further comprising: a plurality of memory cell arrays including the aforementioned memory cell array; and a plurality of column decoders, which are mounted on the aforementioned substrate and connected to the plurality of memory cell arrays; wherein the aforementioned photolithography pattern is disposed between the plurality of column decoders.

22. The semiconductor memory device of claim 11, further comprising: a plurality of memory cell arrays including the aforementioned memory cell array; and a plurality of sense amplifiers, which are mounted on the aforementioned substrate and connected to the plurality of memory cell arrays; wherein the aforementioned photolithography pattern is disposed between the plurality of sense amplifiers.

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