Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure includes an interposer comprising: a substrate, a redistribution structure on a first side of the substrate, and a passivation film on the redistribution structure. The passivation film includes a first etch stop layer on the redistribution structure and a first dielectric layer on the first etch stop layer. The interposer includes vias buried in the passivation film, the vias being electrically coupled to conductive features of the redistribution structure. The interposer includes a bonding film on the passivation film, the bonding film including a second etch stop layer on the passivation film and a second dielectric layer on the second etch stop layer. The interposer also includes bonding pads and a first dummy bonding pad buried in the bonding film, the bonding pads being electrically coupled to the vias, and the first dummy bonding pads being electrically isolated. The semiconductor structure further includes a die attached to the interposer, the die's die connector being bonded to the bonding pads.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure and a method for manufacturing the same, comprising a bonding pad embedded in a bonding film and a dummy bonding pad. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integrated density comes from the continuous shrinking of the smallest feature size, which allows more components to be integrated into a given area.

[0003] As the demand for miniaturized electronic devices continues to grow, the need for smaller, more innovative semiconductor die packaging technologies has also emerged. One example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide high integration and component density. Another example is chip-on-wafer-on-substrate (CoWoS) technology. In some embodiments, to form a CoWoS structure, a plurality of semiconductor wafers are attached to a wafer, followed by a dicing process to separate the wafer into a plurality of interposers, each interposer having one or more semiconductor wafers attached to it. The interposer with attached semiconductor wafers is called a chip-on-wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form the CoWoS structure. Another example is System on Integrated Chip (SoIC) technology, a three-dimensional (3D) die-to-die stacking technology that integrates active and passive dies into a single SoC system. The SoIC platform uses front-end technologies and precise methodologies from silicon wafer fabs to stack dies in a 3D manner. The SoIC platform allows for the integration of known good dies (KGDs) with different die sizes, functionalities, and wafer node technologies. The resulting structures enable ultra-high-density vertical stacking, leading to high performance, low power consumption, and low resistance-inductance-capacitance (RLC). These, along with other advanced packaging technologies, make it possible to produce semiconductor devices with enhanced functionality and small size. [Summary of the Invention]

[0004] This disclosure provides a semiconductor structure including an interposer, wherein the interposer includes: a substrate, a redistribution structure on a first side of the substrate, and a passivation film on the redistribution structure, wherein the passivation film includes a first etch stop layer on the redistribution structure and a first dielectric layer on the first etch stop layer. The interposer includes vias buried in the passivation film, wherein the vias are electrically coupled to conductive features of the redistribution structure. The interposer includes a bonding film on the passivation film, wherein the bonding film includes a second etch stop layer on the passivation film and a second dielectric layer on the second etch stop layer. The interposer also includes bonding pads and a first dummy bonding pad buried in the bonding film, wherein the bonding pads are electrically coupled to the vias, and the first dummy bonding pads are electrically isolated. The semiconductor structure further includes a die attached to the interposer, wherein a die connector of the die is bonded to the bonding pad.

[0005] This disclosure provides a semiconductor structure including an interposer. The interposer includes: a substrate, a redistribution structure located above a first side of the substrate, and a passivation film located above the redistribution structure. The passivation film includes a first etch stop layer located above the redistribution structure and a first dielectric layer located above the first etch stop layer. The interposer includes a via extending through the passivation film and electrically coupled to the topmost conductive feature of the redistribution structure. The interposer includes a bonding film located above the passivation film, wherein the bonding film includes a second etch stop layer located above the passivation film and a second dielectric layer located above the second etch stop layer. The interposer includes a bonding pad extending through the bonding film and electrically coupled to the via, and a first dummy bonding pad embedded in the bonding film. The semiconductor structure further includes a first die attached to the first side of the interposer, wherein a first die connector of the first die is bonded to the bonding pad. The semiconductor structure also includes a molding material located above the first side of the interposer and around the first die.

[0006] This disclosure provides a method for manufacturing a semiconductor structure, including forming an interposer, comprising: forming a redistribution structure over a substrate; forming a passivation film on the redistribution structure by sequentially forming a first etch stop layer and a first dielectric layer on the redistribution structure; forming a via extending through the passivation film and electrically coupled to a topmost conductive feature of the redistribution structure; forming a bonding film on the passivation film by sequentially forming a second etch stop layer and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film. The method further includes: bonding a die connector of a die to the bonding pad; and forming a molding material on the interposer and around the die.

Implementation Method

[0008] The following disclosure provides many different embodiments or examples to implement different features of the embodiments disclosed herein. Reference numerals and / or letters may be repeated in the various examples described in this disclosure. These repetitions are for the purpose of brevity and clarity and do not in themselves represent any relationship between the various embodiments and / or configurations disclosed. In addition, specific examples of components and configurations are described below to simplify the description of the embodiments disclosed herein. Of course, these specific examples are merely illustrative and are not intended to limit the embodiments disclosed herein. For example, in the following description, it is mentioned that a first feature is formed on or above a second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, or it may include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetitions are for the purpose of brevity and clarity and do not in themselves represent any relationship between the various embodiments and / or configurations described.

[0009] Furthermore, spatially related terms may be used herein. For example, terms such as "below," "under," "lower," "above," "higher," and similar terms are used to describe the relationship between one element or feature depicted in the figures and another element(s). In addition to the orientation shown in the figures, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be rotated to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way. In the description of this disclosure, figures with the same numbers but different letters (e.g., Figures 7A and 7B) depict various views of the same semiconductor structure at the same manufacturing stage.

[0010] In some embodiments, the passivation film used as the interposer comprises only an etch stop layer (ESL) and a dielectric layer, which simplifies the film construction and reduces manufacturing costs and process time. Due to the reduced thickness of the passivation film, the vias formed within it have shorter lengths and larger bottom surfaces, which advantageously reduces the resistance of the vias. Furthermore, since there is only one interface between the ESL and the dielectric layer within the passivation film, the risk of delamination between the passivation film and the via is reduced.

[0011] According to one embodiment, Figures 1 to 5, 6A, 6B, 6C, 6D, and 6E illustrate various views (e.g., cross-sectional views, top views) of the semiconductor structure 300 at various stages of its fabrication. The semiconductor structure 300 may be, for example, a SoIC device. In the illustrated embodiment, the semiconductor structure 300 includes an interposer 100 and a die 200 attached to the interposer 100. Figures 1 to 5 illustrate the fabrication process steps for forming the interposer 100. Figures 6A to 6E illustrate various views of the semiconductor structure 300 after the die 200 has been attached to the interposer 100.

[0012] Figure 1 illustrates a cross-sectional view of the interposer 100 in an early stage of manufacturing. The interposer 100 may be part of a wafer that is later cut to form a plurality of interposers 100 (e.g., multiple independent interposers 100), on which grains are attached.

[0013] The interposer 100 in Figure 1 includes a substrate 110, a via 101, a redistribution structure (RDS) 104 formed on the upper surface of the substrate 110, and a conductive pad 121 (e.g., a copper pad) formed on the lower surface of the substrate 110. A passivation layer may be formed on the lower surface of the substrate 110 to cover at least a portion of the conductive pad 121. An external connector 123 (refer to Figure 6A) is then formed on the conductive pad 121 to provide electrical connection with other devices.

[0014] The substrate 110 may be, for example, a doped or undoped silicon substrate, or an active layer of a silicon-on-insulator (SOI) substrate. However, the substrate 110 may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnection functionality.

[0015] In some embodiments, the substrate 110 may include electronic components, such as resistors, capacitors, etc. These electronic components may be active, passive, or a combination thereof. In other embodiments, the substrate 110 does not have active or passive electronic components, but only includes conductive lines and / or vias to provide electrical connections. The above and other variations are intended to be included within the scope of this disclosure.

[0016] The via 101 extends from the upper surface of the substrate 110 to the lower surface of the substrate 110 and provides an electrical connection between the conductive pad 121 and the conductive features of the RDS 104. The via 101 can be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloys, doped polycrystalline silicon, combinations thereof, etc. A barrier layer can be formed between the via 101 and the substrate 110. The barrier layer can include a suitable material, such as titanium nitride, but other materials, such as tantalum nitride, titanium, etc., can be used alternatively.

[0017] RDS 104 is formed on the upper surface of substrate 110. RDS 104 may include one or more dielectric layers 105 (e.g., silicon oxide) and conductive features 103 (e.g., conductive lines, vias) formed in one or more dielectric layers 105. In the example of Figure 1, RDS 104 is illustrated as having one dielectric layer 105 and conductive features 103 (e.g., conductive pads, conductive lines) formed in the dielectric layer 105, but it should be understood that multiple dielectric layers 105 and multiple layers of conductive features may be formed in RDS 104.

[0018] In some embodiments, one or more dielectric layers 105 are formed of materials such as nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.). One or more dielectric layers 105 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, or a combination thereof.

[0019] In some embodiments, the conductive features 103 of the RDS 104 include conductive lines and / or vias formed of a suitable conductive material (e.g., copper, titanium, tungsten, aluminum, etc.). In some embodiments, the conductive features 103 are formed of an alloy, such as an aluminum-copper alloy, a titanium-aluminum-copper alloy, etc. The RDS 104 can be formed, for example, by forming a dielectric layer 105, forming an opening in the dielectric layer 105 to expose the underlying conductive features, forming a seed layer above the dielectric layer 105 and in the opening, forming a patterned photoresist with a designed pattern above the seed layer, plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and above the seed layer, and removing the photoresist and portions of the seed layer where no conductive material is formed. The above process can be repeated until the target number of dielectric layers 105 and conductive features 103 are formed.

[0020] Next, in Figure 2, a passivation film 108 (also referred to as a passivation structure) is formed on RDS 104. In the illustrated embodiment, the passivation film 108 includes an etch stop layer (ESL) 107 and a dielectric layer 109 located on the ESL 107.

[0021] In some embodiments, the ESL 107 is formed of a suitable material, such as silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), silicon carbonitride (e.g., SiCN), silicon oxynitride (SiON), etc., and can be formed by a suitable formation method, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the ESL 107 is used to protect the underlying structure and provide control points for subsequent etching processes. The thickness T1 of the ESL 107 may be between about 300 angstroms and about 5000 angstroms, for example, between 1000 angstroms and 5000 angstroms, or between 3000 angstroms and about 5000 angstroms. In some embodiments, the thickness T1 of the ESL 107 is greater than the typical thickness of the ESL in the passivation film without the intermediate layer of the disclosed structure, which may be less than about 700 angstroms. As will be explained in more detail below, the increased thickness T1 of ESL 107 reliably protects the underlying conductive features (e.g., the topmost conductive feature 103 of RDS 104) from the effects of subsequent etching processes and provides a control point for stopping subsequent etching processes.

[0022] A suitable material (e.g., silicon oxide (e.g., SiO)) is used to form the dielectric layer 109 on the ESL 107, but other suitable materials may also be used. Suitable formation methods (e.g., PVD, CVD, PECVD) can be used to form the dielectric layer 109. In the illustrated embodiment, the thickness T1 of the ESL 107 is not less than one-seventh of the thickness T2 of the dielectric layer 109, and not greater than the thickness T2 (e.g., T2 / 7 ≤ T1 ≤ T2). For example, the thickness T1 may be between about 12.5% ​​and about 50% of the thickness T of the passivation film 108 (e.g., T = T1 + T2). As an example, the thickness T of the passivation film 108 may be between about 0.1 μm and about 3 μm. The lower limit of thickness T (e.g., 0.1 μm) ensures sufficient electrical isolation between the subsequently formed dummy bonding pad 117B and the underlying conductive structure 103, while the upper limit of thickness T (e.g., 3 μm) ensures that the subsequently formed via 115 has low resistance. Further details will be provided below.

[0023] The exposure range of thickness T1 (e.g., T2 / 7 ≤ T1 ≤ T2) ensures that the passivation film 108 functions as designed and provides sufficient protection for the underlying structure (e.g., conductive feature 103). It should be noted that in the illustrated embodiment, the passivation film 108 comprises only a single layer of ESL 107 and a single layer of dielectric layer 109, whereas a typical passivation film for an interposer may comprise multiple interleaved ESLs and multiple dielectric layers. In some embodiments, during the subsequent etching process (for forming via 115) to form the via opening, the ESL 107 (e.g., a carbon- or nitride-containing material) is used to control the stopping point of the etching process. For example, when the etching process reaches ESL 107, an optical emission spectrometer (OES) can be used to detect carbon or nitride elements and signal that the etching process should end as soon as possible. In this way, the etching process can be controlled / adjusted accordingly to stop at the correct time. If the thickness T1 is too small (e.g., less than T2 / 7), ESL 107 may be etched before OES can reliably detect carbon or nitrogen, thus failing to provide sufficient buffer time to stop the etching process and adequate protection for the underlying structure. Conversely, if the thickness T1 is too large (e.g., greater than T2), etching ESL 107 will take too long, increasing process time and cost.

[0024] Next, in Figure 3, a via 115 is formed in the passivation film 108. In some embodiments, the via 115 is formed of a suitable conductive material, such as copper, aluminum-copper alloy, titanium-aluminum-copper alloy, etc. To form the via 115, a via opening is formed to extend through the passivation film 108, exposing the underlying conductive feature 103 (e.g., the topmost conductive pattern of RDS 104). A conductive material is then formed in the via opening, followed by a planarization process, such as chemical-mechanical planarization (CMP), to remove excess conductive material from the upper surface of the passivation film 108 and to achieve a coplanar upper surface between the passivation film 108 and the remaining portion of the conductive material. The remaining portion of the conductive material in the via opening forms the via 115.

[0025] The via opening can be formed by an etching process including two etching steps. For example, a first plasma etching process can be performed as the first etching step, using a first gas source to etch through the dielectric layer 109 and expose the ESL 107. Next, a second plasma etching process can be performed as the second etching step, using a second gas source to etch through the ESL 107. The first gas source may include, for example, C4F6, to selectively etch the dielectric layer 109. The second gas source may include, for example, CF4, CHF3, and O2, to selectively etch the ESL 107. As described above, when the etching process reaches the ESL 107, OES can be used to detect carbon or nitride elements and accordingly control / adjust the etching process to stop at the correct time to avoid damaging the underlying conductive feature 103.

[0026] The advantages are achieved through the structure of the passivation film 108. For example, the passivation film 108 includes only one ESL 107 and one dielectric layer 109, thus there is only one interface between the ESL 107 and the dielectric layer 109. As a result, the via 115 extends through only one interface within the passivation film 108 (e.g., between the ESL 107 and the dielectric layer 109). In some embodiments, the more interfaces of the passivation film 108 the via 115 must extend through, the higher the risk of delamination of the passivation film 108. Since the exposed passivation film 108 has only one interface, the risk of delamination of the passivation film 108 is significantly reduced. Furthermore, since the passivation film 108 has fewer layers, its thickness T is reduced. Therefore, the height H of the via 115 is reduced. In some embodiments, the height H of the via 115 is between about 0.1 μm and about 3 μm, which can be more than 75% lower than the height of a via formed in a passivation film having multiple ESLs and multiple dielectric layers. Since the via 115 typically has tapered sidewalls (due to the characteristics of the etching process forming the via opening), the shorter via 115 has a larger bottom surface area to contact the underlying conductive feature 103. The larger bottom surface area and shorter height of the via 115 advantageously reduce the resistance of the via 115.

[0027] Next, in Figure 4, a bonding film 112 is formed on the passivation film 108. In the illustrated embodiment, the bonding film 112 includes an ESL 111 and a dielectric layer 113. The ESL 111 and dielectric layer 113 may be the same as or similar to the ESL 107 and dielectric layer 109 of the passivation film 108, respectively, and may be formed using the same materials and the same forming method; therefore, details will not be repeated.

[0028] Next, in Figure 5, bonding pads 117 (e.g., 117A and 117B) are formed in the bonding film 112. In some embodiments, the bonding pads 117 are formed of a suitable conductive material, such as copper, aluminum-copper alloy, titanium-aluminum-copper alloy, etc. To form bonding pad 117A, a pad opening is formed to extend through the bonding film 112 to expose the underlying via 115. A conductive material is then formed in the pad opening. A planarization process (e.g., CMP) is then performed to remove excess conductive material from the upper surface of the bonding film 112, achieving a coplanar upper surface between the bonding film 112 and the remaining portion of the conductive material. The remaining portion of the conductive material in the pad opening forms bonding pad 117A.

[0029] It should be noted that, in Figure 5, a dummy bonding pad 117B is also formed in the bonding film 112. In the illustrated embodiment, the dummy bonding pad 117B is electrically isolated. In some embodiments, the dummy bonding pad 117B is formed in the bonding film 112 to achieve a substantially uniform metal density in the bonding film 112, thereby avoiding or reducing surface non-uniformity (e.g., depressions) of the bonding film 112 during planarization processes (e.g., CMP). The dummy bonding pad 117B may be formed simultaneously with the bonding pad 117A and using the same process steps, except that the dummy bonding pad 117B is electrically isolated (e.g., not electrically coupled to the via 115). The dummy bonding pad 117B may or may not have the same shape as the bonding pad 117A, as will be explained in detail below.

[0030] After the bonding pad 117 is formed, the structure in Figure 5 illustrates the interposer 100 disclosed herein. The interposer 100 is used to form the semiconductor structure 300 in Figure 6A.

[0031] Next, in Figure 6A, the die 200 is attached (e.g., bonded) to the interposer 100. Next, a molding material 205 is formed on the interposer 100 surrounding the die 200. In some embodiments, multiple semiconductor structures 300 are formed on the same wafer, and a dicing process can then be performed along the dicing region shown by the dashed line 220 to form individual (e.g., separate) semiconductor structures 300.

[0032] Figure 6A illustrates a die 200 in the semiconductor structure 300 as a non-limiting example, but it should be understood that any suitable number of dies can be attached to the interposer 100. For example, multiple dies can be arranged laterally and / or vertically relative to each other to form 3D stacked dies in the semiconductor structure 300.

[0033] In some embodiments, die 200 includes a substrate 210, electronic components (e.g., transistors, resistors, capacitors, diodes, etc.) formed within / on the substrate 210, and an interconnect structure located above the substrate 210 connecting the electronic components to form the functional circuitry of die 200. Die 200 also includes conductive posts 201A (also referred to as die connectors 201A) providing electrical connections to the circuitry of die 200. Furthermore, die 200 may include dummy conductive posts 201B (also referred to as dummy die connectors 201B) for engaging with dummy bonding pads 117B of the interposer 100. In some embodiments, dummy conductive posts 201B are electrically isolated. Conductive posts 201A and dummy conductive posts 201B may be collectively referred to as conductive post 201 (or die connector 201).

[0034] The substrate 210 of the grain 200 can be a semiconductor substrate (doped or undoped) or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon-germanium, SOI, silicon-germanium on insulator (SGOI), or a combination thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0035] The electronic components of the die 200 include various active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors), etc. The electronic components of the die 200 can be formed in or on the substrate 210 of the die 200 using any suitable method. The interconnect structure of the die 200 includes one or more metal layers (e.g., copper layers) formed in one or more dielectric layers for connecting various electronic components to form functional circuits.

[0036] One or more passivation layers may be formed on the interconnect structure of the grain 200 to provide a certain degree of protection for the structure of the grain 200. The passivation layer may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials (e.g., carbon-doped oxides), extremely low-k dielectric materials (e.g., porous carbon-doped silicon dioxide), or combinations thereof. The passivation layer may be formed by a process such as chemical vapor deposition (CVD), but any suitable process may be used.

[0037] A conductive pad (not shown) may be formed on the passivation layer, the conductive pad extending through the passivation layer to make electrical contact with the interconnect structure of the grain 200. The conductive pad may include aluminum, but other materials (e.g., copper) may also be used alternatively.

[0038] A die connector 201, on which a die 200 is formed, provides a conductive region for circuitry electrically connected to the die 200. The die connector 201 may be a copper pillar, contact bumps (e.g., microbumps), etc., and may include, for example, copper, tin, silver, or other suitable materials. A dielectric layer 203, such as an oxide layer (e.g., SiO), may be formed around the die connector 201.

[0039] In some embodiments, the die connector 201 of the die 200 is bonded to the corresponding bonding pad 117 of the interposer 100 via a direct bonding process (e.g., via direct metal-to-metal bonding and direct dielectric-to-dielectric bonding) without the use of an adhesive material (e.g., solder material). The direct bonding process may include cleaning the surfaces of the die 200 and the interposer 100, aligning the die connector 201 with the corresponding bonding pad 117, and pressing the die connector 201 and the bonding pad 117 together. Heat treatment may be performed to perform the direct bonding process. The final bonding between the die 200 and the interposer 100 includes dielectric-to-dielectric bonding (e.g., dielectric layer 203 to dielectric layer 113) and metal-to-metal bonding (e.g., die connector 201 to bonding pad 117).

[0040] Next, a molding material 205 is formed around the grain 200 on the interposer 100. As an example, the molding material 205 may include an epoxy resin, an organic polymer, a polymer with or without silica-based fillers or glass fillers, or other materials. In some embodiments, the molding material 205 includes a liquid molding compound (LMC), which is a gel-like liquid when applied. The molding material 205 may also include a liquid or a solid when applied. Alternatively, the molding material 205 may include other insulating and / or encapsulating materials. In some embodiments, the molding material 205 is applied using a wafer-level molding process. The molding material 205 may be shaped using, for example, compression molding, transfer molding, molding underfill (MUF), or other methods.

[0041] Next, in some embodiments, a curing process is used to cure the molding material 205. The curing process may include heating the molding material 205 to a predetermined temperature and maintaining it for a predetermined time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination of the foregoing, or a combination of the foregoing and a heating process. Alternatively, the molding material 205 may be cured using other methods. In some embodiments, a curing process is not included.

[0042] After forming the molding material 205, a planarization process (e.g., CMP) can be performed to achieve a flat upper surface of the molding material 205. In the illustrated embodiment, the molding material 205 extends further from the interposer 100 than the grains 200, thereby covering the upper surface of the grains 200. The sidewalls of the molding material 205 are aligned with the corresponding sidewalls of the interposer 100 along the same vertical lines, for example, due to cutting.

[0043] As shown in Figure 6A, an external connector 123 (also referred to as a conductive bump) is formed on the conductive pad 121. The external connector 123 can be any suitable type of external contact, such as microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel-palladium immersion gold (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb layers, combinations thereof, etc. The external connector 123 can be formed on the conductive pad 121 before the dicing process. For example, after forming the molding material 205, the wafer including the semiconductor structure 300 is flipped over, and the side of the wafer having the molding material 205 is attached to the dicing tape. Next, the external connector 123 is formed on the conductive pad 121 using a suitable forming method. The dicing process is then performed to separate the wafer into individual semiconductor structures 300.

[0044] Figure 6B shows an example cross-sectional view of the semiconductor structure 300 along section AA in Figure 6A. Figure 6A corresponds to the cross-sectional view along section BB in Figure 6B.

[0045] Figure 6B illustrates the sidewalls of dielectric layer 113 (which completely overlap with the sidewalls of interposer 100). The sidewalls of grains 200, which are not visible in section AA, are shown as dashed lines in Figure 6B. Figure 6B also illustrates a cross-section of bonding pads 117 (e.g., bonding pad 117A and dummy bonding pad 117B), which has the same shape as the top view of bonding pad 117.

[0046] In the example of Figure 6B, the bonding pads 117A and dummy bonding pads 117B have the same shape (e.g., circular). In Figure 6B, two rows of bonding pads 117 are shown, each row including two bonding pads 117A and one dummy bonding pad 117B (e.g., labeled 117B1 in the top row and 117B2 in the bottom row). In some embodiments, all die connectors 201 of die 200 (e.g., die connectors 201A and dummy die connectors 201B) have the same shape (e.g., in a cross-sectional or top view), which matches the shape of the bonding pads 117A. Since the bonding pads 117A and dummy bonding pads 117B in Figure 6B have the same shape, in the example of Figure 6B, die connectors 201A and 201B, bonding pads 117A and dummy bonding pads 117B all have the same shape. It should be noted that the number, shape, size, and position of the mating pads 117 (e.g., mating pads 117A, 117B1, 117B2) shown in Figure 6B (as well as Figures 6C, 6D, and 6E) are non-limiting examples. The mating pads 117 may also have other numbers, other shapes, other sizes, and other positions, and are fully intended to be included within the scope of this disclosure.

[0047] Figure 6C illustrates another exemplary cross-sectional view of the semiconductor structure 300 along section AA in Figure 6A. In the example of Figure 6C, dummy bonding pad 117B1 has a first shape (e.g., pentagon), dummy bonding pad 117B2 has a second shape (e.g., hexagon), and bonding pad 117A has a third shape (e.g., circular), wherein the first, second, and third shapes are different shapes. Figure 6C also shows a cross-section of a dummy die connector 201B coupled to dummy bonding pads 117B (e.g., dummy bonding pads 117B1 and 117B2) in dashed lines. As shown in Figure 6C, the dummy die connector 201B has the same shape (e.g., circular) as bonding pad 117A. When aligned and engaged, in a top view (or a plan view projecting the die connectors 201 and the bonding pads 117 onto the same plane), each dummy die connector 201B lies within the boundary (e.g., sidewall) of the corresponding dummy bonding pad 117B (e.g., 117B1 or 117B2). Specifically, in Figure 6C, the center of each dummy die connector 201B coincides with (e.g., overlaps with) the center of the corresponding dummy bonding pad 117B, and the sidewall of each dummy die connector 201B is separated from (e.g., does not contact) the sidewall of the corresponding dummy bonding pad 117B. Figure 6C does not show a cross-section of the die connector 201A coupled to the bonding pad 117A because the sidewall of each die connector 201A overlaps with (e.g., completely overlaps with) the sidewall of the corresponding bonding pad 117A.

[0048] Allowing dummy bonding pads 117B to have different shapes and sizes can provide advantages. For example, dummy bonding pads 117B with different shapes can serve as reference points for pick-and-place tools equipped with computer vision technology to identify the orientation / position of bonding pads 117, so that the die 200 (and die connector 201) can be oriented to the correct direction by the pick-and-place tool to engage with the bonding pads 117. Different shapes of dummy bonding pads 117B can also help operators reduce errors during testing or troubleshooting, especially when the die 200 has a symmetrical shape and the position of the die connector 201 remains unchanged even if the die 200 is rotated, for example, by 90 degrees or 180 degrees. Furthermore, by not limiting the size and shape of the dummy bonding pad 117B to match the size and shape of the dummy die connector 201B, the designer of the interposer 100 has greater freedom in selecting the size and shape of the dummy bonding pad 117B, thereby making it easier to achieve a substantially uniform metal density on the surface of the interposer 100, which helps to reduce or avoid surface non-uniformities (such as depressions).

[0049] Figure 6D illustrates another exemplary cross-sectional view of the semiconductor structure 300 along section AA in Figure 6A. Figure 6D is similar to Figure 6C, but with some differences. For example, in the top view (or plan view), the circular shape of the dummy die connector 201B is inscribed within the shape (e.g., hexagonal or pentagonal) of the dummy bonding pad 117B. In other words, the center of the circle coincides with (e.g., overlaps with) the center of the hexagon (or pentagon), and the circle is tangent to each side of the hexagon (or pentagon) at a point, but does not intersect with it.

[0050] Figure 6E illustrates another exemplary cross-sectional view of the semiconductor structure 300 along section AA in Figure 6A. In Figure 6E, dummy bonding pads 117B (e.g., 117B1 and 117B2) have a first shape (e.g., cross-shaped), and bonding pads 117A have a second shape (e.g., circular). The center of each dummy die connector 201B coincides with (e.g., overlaps with) the center of the corresponding dummy bonding pad 117B. It should be noted that although dummy bonding pads 117B1 and 117B2 have the same shape, there is rotation between the shapes of dummy bonding pads 117B1 and 117B2. For example, the two axes L1, L2 of the cross shape of dummy bonding pad 117B2 are aligned with the vertical and horizontal directions of Figure 6E, respectively, and therefore aligned with the row and column directions of the bonding pad array 117A. The two axes L1 and L2 of the cross-shaped dummy bonding pad 117B1 rotate relative to the two axes of the cross-shaped dummy bonding pad 117B2, and therefore are not aligned with the row and column directions of the bonding pad array 117A. Therefore, the angle between the cross-shaped axis L1 (or L2) of the dummy bonding pad 117B and the row (or column) direction of the bonding pad array 117 can be used to distinguish between dummy bonding pads 117B1 and 117B2, and the positions of dummy bonding pads 117B1 and 117B2 can serve as reference points for a pick-and-place tool equipped with computer vision technology to correctly rotate the die 200 for bonding.

[0051] Figure 7A illustrates a cross-sectional view of a semiconductor structure 300A in another embodiment. Semiconductor structure 300A is similar to semiconductor structure 300, but each dummy bonding pad 117B of semiconductor structure 300A includes a dispersed portion of conductive material, rather than a single continuous volume of conductive material. Furthermore, in the example of Figure 7A, die 200 does not have a dummy die connector 201B that engages with the dummy bonding pads 117B. Instead, the upper surface of the dummy bonding pads 117B contacts the dielectric layer 203 of die 200.

[0052] Figure 7B illustrates a cross-sectional view of the semiconductor structure 300A along section AA in Figure 7A. For simplicity, only a portion of the semiconductor structure 300A is shown, including dummy bonding pads 117B1 and 117B2. In the example of Figure 7B, dummy bonding pad 117B1 (or 117B2) is similar to dummy bonding pad 117B1 (or 117B2) in Figure 6C, but a portion of the conductive material is removed and replaced by the material of the bonding film 112, and the remaining portion of dummy bonding pad 117B1 (or 117B2) forms the dispersed portion of dummy bonding pad 117B1 (or 117B2). It should be noted that the outer boundaries of the dispersed portions of dummy bonding pads 117B1 and 117B2 still have pentagonal and hexagonal shapes, respectively. The dummy bonding pads 117B (e.g., 117B1 and 117B2) in Figures 7A and 7B can be formed by forming pad openings with dispersed opening portions in the bonding film 112 and filling the dispersed portions of each pad opening with a conductive material.

[0053] The die 200 in the semiconductor structure 300A does not need to form a dummy die connector 201B, thereby simplifying production and saving costs. In addition, a portion of the dielectric layer 113 located between the dispersed portions of the dummy bonding pad 117B can form a direct dielectric-to-dielectric bond with the dielectric layer 203 of the die 200, thereby improving the bonding strength between the die 200 and the interposer 100.

[0054] Figure 8 illustrates a cross-sectional view of a semiconductor structure 300B in another embodiment. Semiconductor structure 300B is similar to semiconductor structure 300, but with more vertically stacked dies. For example, a first die 200A is bonded to the interposer 100, while a second die 200B is bonded to the upper surface of the first die 200A.

[0055] The first die 200A is similar to die 200, but an additional die connector 201 is formed on the upper surface of the first die 200A away from the interposer 100. Furthermore, a through-substrate-via (TSV) 207 is formed in the first die 200A to electrically couple the die connectors 201 on the upper and lower surfaces of the first die 200A. In the illustrated embodiment, a dummy die connector 201B is formed on the lower surface of the die 200A for engaging with the dummy bonding pad 117B of the interposer 100, while no dummy die connector 201B is formed on the upper surface of the first die 200A.

[0056] The second die 200B is similar to die 200, but does not form a dummy die connector 201B. The die connector 201 of the second die 200B is engaged with the corresponding die connector 201 on the upper surface of the first die 200A. The molding material 205 encapsulates the first die 200A and the second die 200B.

[0057] The embodiments offer advantages. For example, the disclosed passivation film 108 for the interposer 100 comprises only one ESL 107 and one dielectric layer 109, which simplifies the film structure and reduces production costs and process time. Furthermore, due to the reduced thickness of the passivation film 108, the vias 115 formed in the passivation film 108 have a shorter length and a larger bottom surface, which reduces the resistance value of the vias 115. Additionally, the disclosed passivation film 108 has only one interface between the ESL and the dielectric layer within the passivation film 108, which further reduces the risk of delamination between the passivation film 108 and the vias 115. Since the interposer 100 is used to form the semiconductor structure 300 (or 300A, 300B), the passivation film 108 undergoes subsequent high-temperature processes, such as the bonding process for the die 200 and the molding process for forming the molding material 205. The high-temperature process, coupled with the mismatch in the coefficient of thermal expansion (CTE) between the molding material 205 and the interposer 100, may lead to high stress in the passivation film 108, potentially causing delamination of the passivation film 108. Delamination of the passivation film 108 may result in device failure in the semiconductor device 300 (or 300A, 300B). The disclosed passivation film 108 structure reduces the risk of delamination, thereby reducing device failure in the semiconductor structure 300 (or 300A, 300B) and improving production yield.

[0058] Figure 9 illustrates a flowchart of a method 1000 for manufacturing a semiconductor structure in some embodiments. It should be understood that the method of the embodiment shown in Figure 9 is merely an example of many possible embodiments. Those skilled in the art to which this application pertains will recognize many variations, alternatives, and modifications. For example, various steps as shown in Figure 9 may be added, removed, replaced, rearranged, and repeated.

[0059] Referring to Figure 9, in block 1010, forming the interposer includes: forming a redistribution structure (RDS) over a substrate; forming a passivation film on the RDS by sequentially forming a first etch stop layer (ESL) and a first dielectric layer on the RDS; forming a via extending through the passivation film and electrically coupled to the topmost conductive feature of the RDS; forming a bonding film on the passivation film by sequentially forming a second ESL and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film. In block 1020, a die connector of the die is bonded to the bonding pad. In block 1030, a molding material is formed on the interposer and around the die.

[0060] According to some embodiments, the semiconductor structure includes an interposer, wherein the interposer includes: a substrate, a redistribution structure on a first side of the substrate, and a passivation film on the redistribution structure, wherein the passivation film includes a first etch stop layer on the redistribution structure and a first dielectric layer on the first etch stop layer. The interposer includes vias buried in the passivation film, wherein the vias are electrically coupled to conductive features of the redistribution structure. The interposer includes a bonding film on the passivation film, wherein the bonding film includes a second etch stop layer on the passivation film and a second dielectric layer on the second etch stop layer. The interposer also includes bonding pads and a first dummy bonding pad buried in the bonding film, wherein the bonding pads are electrically coupled to the vias, and the first dummy bonding pads are electrically isolated. The semiconductor structure further includes a die attached to the interposer, wherein a die connector of the die is bonded to the bonding pad.

[0061] In some embodiments, the thickness of the passivation film is equal to the sum of the thickness of the first etch stop layer and the thickness of the first dielectric layer.

[0062] In some embodiments, the thickness of the bonding film is equal to the sum of the thickness of the second etch stop layer and the thickness of the second dielectric layer.

[0063] In some embodiments, the first etch stop layer and the second etch stop layer are made of the same material, and the first dielectric layer and the second dielectric layer are made of the same material.

[0064] In some embodiments, the first etch stop layer and the second etch stop layer are silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride, and the first dielectric layer and the second dielectric layer are silicon oxide.

[0065] In some embodiments, a first dummy die connector of the die is coupled to a first dummy bonding pad, wherein the first dummy die connector is electrically isolated.

[0066] In some embodiments, in a top view, the mating pad has a different shape from the first dummy mating pad.

[0067] In some embodiments, the interlayer further includes a second dummy bonding pad embedded in the bonding membrane, wherein, in a top view, each of the bonding pad, the first dummy bonding pad, and the second dummy bonding pad has a different shape.

[0068] In some embodiments, the second dummy die connector of the die is coupled to the second dummy bonding pad, wherein, in a top view, the first dummy die connector, the second dummy die connector, and the die connector have the same shape as the bonding pad.

[0069] In some embodiments, the upper surface of the via is flush with the upper surface of the passivation film away from the substrate, and the lower surface of the via is flush with the lower surface of the passivation film facing the substrate.

[0070] In some embodiments, the upper surface of the bonding pad is flush with the upper surface of the bonding film away from the substrate, and the lower surface of the bonding pad is flush with the lower surface of the bonding film facing the substrate.

[0071] According to some embodiments, the semiconductor structure includes an interposer, the interposer comprising: a substrate, a redistribution structure located above a first side of the substrate, and a passivation film located above the redistribution structure, wherein the passivation film includes a first etch stop layer located above the redistribution structure and a first dielectric layer located above the first etch stop layer. The interposer includes a via extending through the passivation film and electrically coupled to a topmost conductive feature of the redistribution structure. The interposer includes a bonding film located above the passivation film, wherein the bonding film includes a second etch stop layer located above the passivation film and a second dielectric layer located above the second etch stop layer. The interposer includes a bonding pad extending through the bonding film and electrically coupled to the via, and a first dummy bonding pad embedded in the bonding film. The semiconductor structure further includes a first die attached to a first side of the interposer, wherein a first die connector of the first die is bonded to the bonding pad. The semiconductor structure also includes a molding material located above the first side of the interposer and around the first die.

[0072] In some embodiments, the sum of the first thickness of the first etch stop layer and the second thickness of the first dielectric layer is the same as the third thickness of the passivation film.

[0073] In some embodiments, the first dummy die connector of the first die is coupled to the first dummy bonding pad.

[0074] In some embodiments, in a top view, the bonding pad and the first dummy bonding pad have different shapes, and the interlayer further includes a second dummy bonding pad embedded in the bonding film, wherein in a top view, the first dummy bonding pad and the second dummy bonding pad have different shapes, and the second dummy die connector of the first die is bonded to the second dummy bonding pad.

[0075] In some embodiments, the first die connector and the first dummy die connector are located on a first side of the first die, wherein the first die further includes a second die connector located on a second side opposite to the first die, and includes a substrate via for electrically coupling the first die connector and the second die connector, wherein the semiconductor structure further includes a second die attached to the second side opposite to the first die, wherein a third die connector of the second die is coupled to the second die connector of the first die.

[0076] According to some embodiments, a method of manufacturing a semiconductor structure includes forming an interposer, comprising: forming a redistribution structure over a substrate; forming a passivation film on the redistribution structure by sequentially forming a first etch stop layer and a first dielectric layer on the redistribution structure; forming a via extending through the passivation film and electrically coupled to a topmost conductive feature of the redistribution structure; forming a bonding film on the passivation film by sequentially forming a second etch stop layer and a second dielectric layer on the passivation film; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film. The method further includes: bonding a die connector of a die to the bonding pad; and forming a molding material on the interposer and around the die.

[0077] In some embodiments, the method further includes bonding a dummy die connector of the die to a first dummy bonding pad.

[0078] In some embodiments, the mating pad and the first dummy mating pad are formed to have different shapes in a top view.

[0079] In some embodiments, forming the intermediary layer further includes forming a second dummy bonding pad in the bonding film, wherein the first dummy bonding pad and the second dummy bonding pad are formed to have different shapes in a top view.

[0080] The foregoing has outlined the features of many embodiments to enable those skilled in the art to better understand the various embodiments of this disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments of this disclosure without departing from the spirit and scope of the appended claims. [Simplified Explanation of the Diagram]

[0007] The concepts of the embodiments disclosed herein will be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings. Figures 1 to 5, 6A, 6B, 6C, 6D, and 6E illustrate various views of a semiconductor structure according to some embodiments at various stages of manufacturing. Figures 7A and 7B illustrate various views of a semiconductor structure according to other embodiments. Figure 8 illustrates a cross-sectional view of a semiconductor structure according to other embodiments. Figure 9 illustrates a flowchart of a method for manufacturing a semiconductor structure in some embodiments.

Claims

1. A semiconductor structure, comprising: An interposer layer comprising: a substrate; a redistribution structure on a first side of the substrate; a passivation film on the redistribution structure, wherein the passivation film includes a first etch stop layer on the redistribution structure and a first dielectric layer on the first etch stop layer; a via embedded in the passivation film, wherein the via is electrically coupled to a conductive feature of the redistribution structure; a bonding film on the passivation film, wherein the bonding film includes a second etch stop layer on the passivation film and a second dielectric layer on the second etch stop layer; a bonding pad and a first dummy bonding pad embedded in the bonding film, wherein the bonding pad is electrically coupled to the via and the first dummy bonding pad is electrically isolated; and a die attached to the interposer layer, wherein a die connector of the die is bonded to the bonding pad.

2. The semiconductor structure of claim 1, wherein the thickness of the passivation film is equal to the sum of the thickness of the first etch stop layer and the thickness of the first dielectric layer.

3. The semiconductor structure of claim 2, wherein the thickness of the bonding film is equal to the sum of the thickness of the second etch stop layer and the thickness of the second dielectric layer.

4. The semiconductor structure of claim 2, wherein the first etch stop layer and the second etch stop layer are made of the same material and are silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride, wherein the first dielectric layer and the second dielectric layer are made of the same material and are silicon oxide.

5. The semiconductor structure of claim 2, wherein a first dummy die connector of the die is coupled to the first dummy bonding pad, wherein the first dummy die connector is electrically isolated.

6. The semiconductor structure of claim 5, wherein, in a top view, the bonding pad and the first dummy bonding pad have different shapes.

7. The semiconductor structure of claim 2, wherein an upper surface of the via is flush with an upper surface of the passivation film away from the substrate, and a lower surface of the via is flush with a lower surface of the passivation film facing the substrate, wherein an upper surface of the bonding pad is flush with an upper surface of the bonding film away from the substrate, and a lower surface of the bonding pad is flush with a lower surface of the bonding film facing the substrate.

8. A semiconductor structure, comprising: An interposer layer includes: a substrate; a redistribution structure located above a first side of the substrate; a passivation film located above the redistribution structure, wherein the passivation film includes a first etch stop layer located above the redistribution structure and a first dielectric layer located above the first etch stop layer; a via extending through the passivation film and electrically coupled to a topmost conductive feature of the redistribution structure; a bonding film located above the passivation film, wherein the bonding film includes a second etch stop layer located above the passivation film and a second dielectric layer located above the second etch stop layer; a bonding pad extending through the bonding film and electrically coupled to the via; and a first dummy bonding pad embedded in the bonding film; a first die attached to a first side of the interposer layer, wherein a first die connector of the first die is bonded to the bonding pad; and a molding material located above the first side of the interposer layer and around the first die.

9. The semiconductor structure of claim 8, wherein the sum of a first thickness of the first etch stop layer and a second thickness of the first dielectric layer is the same as a third thickness of the passivation film, and a first dummy die connector of the first die is bonded to the first dummy bonding pad.

10. The semiconductor structure of claim 9, wherein, in a top view, the bonding pad has a different shape from the first dummy bonding pad, and the interposer further includes a second dummy bonding pad embedded in the bonding film, wherein, in the top view, the first dummy bonding pad has a different shape from the second dummy bonding pad, and a second dummy die connector of the first die is bonded to the second dummy bonding pad.

11. The semiconductor structure of claim 9, wherein the first die connector and the first dummy die connector are located on a first side of the first die, wherein the first die further includes a second die connector located on a second side opposite to the first die, and includes a substrate via electrically coupling the first die connector and the second die connector, wherein the semiconductor structure further includes a second die attached to the second side opposite to the first die, and a third die connector of the second die is coupled to the second die connector of the first die.

12. A method for manufacturing a semiconductor structure, comprising: Forming an interposer layer includes: forming a redistribution structure over a substrate; forming a passivation film on the redistribution structure by sequentially forming a first etch stop layer and a first dielectric layer thereon; forming a via through the passivation film and electrically coupled to a topmost conductive feature of the redistribution structure; forming a bonding film on the passivation film by sequentially forming a second etch stop layer and a second dielectric layer thereon; forming a bonding pad extending through the bonding film and electrically coupled to the via; and forming a first dummy bonding pad in the bonding film; bonding a die connector of a die to the bonding pad; and forming a molding material on the interposer layer and around the die.

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