Semiconductor device and method of manufacturing semiconductor device

Abstract

The embodiments relate to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device of the embodiment includes: a first electrode comprising silicon; a second electrode in contact with an upper surface of the first electrode; a third electrode disposed above the second electrode; an oxide semiconductor in contact with the upper surface of the second electrode and extending in a first direction from the second electrode toward the third electrode; an insulating film disposed on a side of the oxide semiconductor; and a first conductor in contact with at least a portion of the insulating film. The second electrode comprises: a second conductor comprising a conductive oxide and in contact with a lower surface of the oxide semiconductor; and a third conductor disposed between the second conductor and the first electrode, and comprising a compound having titanium and silicon.

Description

Technical Field

[0001] The implementation method relates to a semiconductor device and a method for manufacturing the semiconductor device. Prior Technology

[0002] Semiconductor devices that use capacitors and transistors are known. Summary of the Invention

[0003] The semiconductor device of the embodiment includes: a first electrode comprising silicon; a second electrode disposed above the upper surface of the first electrode; a third electrode disposed above the second electrode; an oxide semiconductor disposed above the upper surface of the second electrode and extending in a first direction from the second electrode toward the third electrode; an insulating film disposed on a side of the oxide semiconductor; and a first conductor disposed above at least a portion of the insulating film. The second electrode includes: a second conductor comprising a conductive oxide and disposed below the lower surface of the oxide semiconductor; and a third conductor disposed between the second conductor and the first electrode and comprising a compound having titanium and silicon.

[0004] According to this embodiment, a semiconductor device with improved reliability can be provided. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram showing an example of the structure of a memory system including the semiconductor device of the embodiment. Figure 2 is a circuit diagram showing an example of the circuit structure of the memory cell array included in the semiconductor device of the embodiment. Figure 3 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor device of the embodiment. Figure 4 is a cross-sectional view along line IV-IV of Figure 3 showing an example of the cross-sectional structure of the memory cell array included in the semiconductor device of the embodiment. Figure 5 is a cross-sectional view along line VV of Figure 3 showing an example of the cross-sectional structure of the memory cell array included in the semiconductor device of the embodiment. Figure 6 is a cross-sectional view showing an example of the structure of the lower electrode of the transistor included in the semiconductor device of the embodiment. Figure 7 is a cross-sectional view showing an example of the manufacturing method of the semiconductor device of the embodiment. Figure 8 is a cross-sectional view showing an example of the manufacturing method of the semiconductor device of the embodiment. Figure 9 is a cross-sectional view showing an example of the manufacturing method of the semiconductor device of the embodiment. Implementation

[0006] The embodiments will now be described with reference to the drawings. Furthermore, the dimensions and scale of the drawings may not be identical to reality. In the following description, constituent elements having substantially the same function and structure are annotated with the same symbols. Moreover, when elements with the same structure are specifically distinguished from each other, sometimes different characters or numbers are appended to the end of the same symbol.

[0007] Furthermore, in the following description, the connection between two different structures refers to an electrical connection. Moreover, the term "two structural connections" includes cases where the two structures are electrically connected via a structure different from the two structures themselves. Furthermore, an electrical connection can also be achieved via an insulator, provided it functions in the same way as an electrical connection.

[0008] 1 Implementation Method

[0009] The semiconductor device of the embodiment will be described below.

[0010] 1.1 Structure

[0011] The structure of the semiconductor device in the embodiment will be described.

[0012] 1.1.1 Memory System

[0013] FIG1 is used to illustrate the structure of a memory system including an embodiment of a semiconductor device. FIG1 is a block diagram showing an example of the structure of a memory system including an embodiment of a semiconductor device.

[0014] The memory system 100 performs data writing or reading operations according to commands from a host machine outside the memory system 100 (not shown).

[0015] The memory system 100 includes a semiconductor device 1 and a memory controller 2.

[0016] Semiconductor device 1 is a memory device that uses transistors for selecting memory elements. Semiconductor device 1 may use capacitors, for example, to store data. Semiconductor device 1 may be, for example, Dynamic Random Access Memory (DRAM). Memory controller 2 controls semiconductor device 1.

[0017] The semiconductor device 1 includes a memory cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a write circuit 15, a read circuit 16, a column selection circuit 17, a row selection circuit 18, and a sense amplifier 19.

[0018] The memory cell array 11 includes multiple memory cells MC, multiple word lines WL, multiple bit lines BL, and a board line PL. Figure 1 illustrates a memory cell MC, a word line WL, and a bit line BL. Each memory cell MC stores one bit of data. Each memory cell MC is connected between one bit line BL and the board line PL. Furthermore, each memory cell MC is connected to one word line WL. Word lines WL are associated with rows. Bit lines BL are associated with columns. In the memory cell array 11, a memory cell MC is determined by selecting a column and selecting a row.

[0019] The input / output circuit 12 receives control signals CNT, instructions CMD, address signals ADD, and data DAT from the memory controller 2. Furthermore, the input / output circuit 12 sends the data DAT to the memory controller 2. When writing data to the semiconductor device 1, the data DAT represents the written data. When reading data from the semiconductor device 1, the data DAT represents the read data.

[0020] Control circuit 13 receives control signal CNT and instruction CMD from input / output circuit 12. Based on the control signal CNT and instruction CMD, control circuit 13 instructs write circuit 15 to write data to semiconductor device 1. Control circuit 13 also instructs read circuit 16 to read data from semiconductor device 1 based on the control signal CNT and instruction CMD. Furthermore, control circuit 13 instructs voltage generation circuit 14 to generate voltage based on the control signal CNT and instruction CMD.

[0021] The voltage generation circuit 14 generates various voltages based on the instructions of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the memory cell array 11, the write circuit 15, the read circuit 16, the column selection circuit 17, the row selection circuit 18, and the sense amplifier 19.

[0022] The write circuit 15 processes and controls the writing of data to the memory cell MC. The write circuit 15 receives write data Dw from the input / output circuit 12. Write data Dw is the data written to the memory cell MC, which is the target of the data writing operation. The write circuit 15 receives one or more voltages used in the data writing operation from the voltage generation circuit 14. Based on the control of the control circuit 13 and the write data Dw, the write circuit 15 supplies one or more voltages used in the data writing operation to the row selection circuit 18.

[0023] The readout circuit 16 processes and controls the readout data from the self-memory cell MC. The readout circuit 16 receives one or more voltages used during the data readout operation from the voltage generation circuit 14. Based on the control of the control circuit 13, the readout circuit 16 uses the voltage used during the data readout operation to determine the data stored in the memory cell MC. The determined data is supplied to the input / output circuit 12 as readout data Dr.

[0024] The column select circuit 17 receives the address signal ADD from the input / output circuit 12. The column select circuit 17 supplies the voltage received from the voltage generation circuit 14 to the memory cell array 11. Thereby, the column select circuit 17 sets a word line WL associated with the column determined by the received address signal ADD to the selected state.

[0025] The row selection circuit 18 receives the address signal ADD from the input / output circuit 12. The row selection circuit 18 supplies the voltage received from the voltage generation circuit 14 to the memory cell array 11. Thereby, the row selection circuit 18 sets the bit line BL associated with the row determined by the received address signal ADD to the selected state.

[0026] The sensing amplifier 19 uses the voltage received by the self-voltage generation circuit 14 to amplify the voltage of the bit line BL, so as to determine the data stored in the memory cell MC that is to be read during the data readout operation.

[0027] 1.1.2 Circuit Structure of Memory Cell Array

[0028] FIG2 is used to illustrate the circuit structure of the memory cell array included in the semiconductor device of the embodiment. FIG2 is a circuit diagram showing an example of the circuit structure of the memory cell array included in the semiconductor device of the embodiment.

[0029] The memory cell array MCA consists of M word lines WL (WL1~WLM), N bit lines BL (BL1~BLN), and plate lines PL. M and N are positive integers.

[0030] Multiple bit lines BL are each connected to, for example, multiple memory cells MC, M memory cells MC corresponding to the bit lines BL. The M memory cells MC corresponding to the bit lines BL, for example, correspond to M word lines WL respectively.

[0031] Each memory cell (MC) contains a cell capacitor (CC) and a cell transistor (CT).

[0032] A cell transistor (CT) is, for example, an n-type metal-oxide-semiconductor field-effect transistor (MOSFET). Hereinafter, one of the source and drain terminals of a cell transistor CT will be referred to as one end of the cell transistor CT, and the other as the other end. One end of each cell transistor CT is connected to a bit line BL corresponding to that cell transistor CT. The gate of each cell transistor CT is connected to a word line WL corresponding to that cell transistor CT.

[0033] The semiconductor constituting part of the cellular transistor CT includes regions forming channels (channel regions). The semiconductor material includes oxide semiconductors. Furthermore, the semiconductor material may, for example, include oxide semiconductors. Moreover, in the case where the material includes structure A, the material may also contain unintended impurities different from structure A.

[0034] Cell capacitors (CC) are capacitive elements. One electrode of each cell capacitor (CC) is connected to the other electrode of the cell transistor (CT) corresponding to that cell capacitor (CC). The other electrode of each cell capacitor (CC) is connected to the plate line (PL). Cell capacitors (CC) store data based on the charge accumulated in the nodes connected to the cell transistor (CT). Hereinafter, these nodes are also referred to as memory nodes (SN).

[0035] The state of memory cell MC storing data "1" or storing data "0" is determined based on the amount of charge accumulated in memory node SN. Hereinafter, as an example, the state where memory cell MC stores data "1" is defined as a state where the potential of memory node SN is higher than the potential of plate line PL. Furthermore, the state where memory cell MC stores data "0" is defined as a state where the potential of memory node SN is lower than the potential of plate line PL.

[0036] With the structure described above, in each memory cell MC, the cell capacitor CC and the cell transistor CT are connected in series between the bit line BL and the plate line PL corresponding to the memory cell MC.

[0037] 1.1.3 Planar Layout of Memory Cell Array

[0038] FIG3 is used to illustrate the planar layout of the memory cell array 11 included in the semiconductor device 1 of the embodiment. FIG3 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor device of the embodiment. In FIG3, as an example, four word lines WL1 to WL4 and four bit lines BL1 to BL4 are illustrated.

[0039] Furthermore, in the following description, the X direction is a direction that is approximately parallel to the substrate of semiconductor device 1. The X direction corresponds to the extension direction of the word line WL. The Y direction is a direction that is approximately parallel to the substrate of semiconductor device 1 and orthogonal to the X direction. The Y direction corresponds to the extension direction of the bit line BL. The Z direction is a direction that is approximately perpendicular to the substrate. Moreover, in the Z direction, the side facing the memory cell array 11 from the substrate is called the upper side. Moreover, in the Z direction, the side facing the substrate from the memory cell array 11 is called the lower side. Moreover, of the two surfaces of a constituent element orthogonal to the Z direction, the upper side surface is called the upper surface, and the lower side surface is called the lower surface.

[0040] The memory cell array 11 includes multiple pillars PI and multiple upper electrodes TE associated with multiple bit lines BL and multiple word lines WL. Each pillar PI functions as a vertical transistor, for example. Moreover, each pillar PI corresponds to a cell transistor CT. In this embodiment, multiple gate electrodes GE each function as a word line WL.

[0041] Figure 3 shows a group of four columns of PIs. These four columns of PIs correspond to character lines WL1 to WL4, respectively. In each column, the four columns of PIs are arranged along the X-direction. For example, the arrangement of the four columns of PIs in each of two adjacent columns of PIs is the same. Furthermore, the positions of the four columns of PIs in one column differ from the positions of the four columns of PIs in the other column in the X-direction. With the arrangement described above, in two adjacent columns of PIs, the four columns of PIs in one column are offset from the four columns of PIs in the other column. Furthermore, Figure 3 shows the case where each of the four columns of PIs contains four columns of PIs, but the number of columns of PIs and the number of columns of PIs in each column are not limited to this. The number of columns of PIs and the number of columns of PIs in each column can be appropriately changed.

[0042] Each column PI is connected to the corresponding bit line BL via an upper electrode TE. Each bit line BL extends along the Y direction. The bit lines BL are arranged along the X direction. Furthermore, hereinafter, the BL1 side of bit lines BL1 and BL4 is referred to as one end side in the X direction. And the BL4 side of bit lines BL1 and BL4 is referred to as the other end side in the X direction. Each bit line BL is configured such that, when viewed along the Z direction, it at least partially coincides with one of the columns PI in the group of columns PI. Each bit line BL, for example, coincides with one end side of the column PI (in the odd-numbered columns) contained in the column corresponding to word line WL1 or word line WL3, for example, with respect to the X direction. And, the bit line BL, for example, coincides with the other end side of the column PI (in the even-numbered columns) contained in the column corresponding to word line WL2 or word line WL4, for example, with respect to the X direction.

[0043] Each bit line BL is electrically connected to each post PI that coincides with the bit line BL. The number of posts PI that coincide with each bit line BL can be designed to be any number corresponding to the number of word lines WL.

[0044] As described above, each gate electrode GE (word line WL) extends along the X direction. Multiple gate electrodes GE are arranged along the Y direction. Each gate electrode GE is configured to surround the corresponding pillar PI when viewed along the Z direction.

[0045] 1.1.4 Cross-sectional structure of memory cell array

[0046] The cross-sectional structure of the memory cell array 11 included in the semiconductor device 1 of the embodiment will be described with reference to Figures 4 and 5. Figure 4 is a cross-sectional view along line IV-IV of Figure 3, showing an example of the cross-sectional structure of the memory cell array included in the semiconductor device of the embodiment. Figure 5 is a cross-sectional view along line VV of Figure 3, showing an example of the cross-sectional structure of the memory cell array included in the semiconductor device of the embodiment.

[0047] The memory cell array 11 includes multiple conductors 21-29, insulators 31-36, multiple oxide semiconductors 40, multiple gate insulating films 41 and gate insulating films 42, and components SLT.

[0048] An insulator 31 is provided above the substrate S.

[0049] The electrode at one end of each of a plurality of cell capacitors CC is located in the same layer as the insulator 31. Furthermore, hereinafter, the electrode at one end of the cell capacitor CC will also be referred to simply as the cell capacitor CC. The plurality of cell capacitors CC comprises a conductive material. The material may, for example, comprise silicon (Si). The material may, for example, be silicon germanium (SiGe x1). Here, the value x1 is a positive number. The plurality of cell capacitors CC, for example, have a cylindrical shape extending along the Z direction. Furthermore, the shape of the cylindrical shape in the XY cross-section may be either circular or rectangular, and is not particularly limited.

[0050] In the same layer as the insulator 31, above the plurality of cell capacitors CC, a plurality of conductors 21 are provided corresponding to the plurality of cell capacitors CC. The plurality of conductors 21 may include, for example, conductive oxides. The plurality of conductors 21 may include, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo) and oxygen (O). The plurality of conductors 21 may include, for example, indium (In), tin (Sn), and oxygen (O). The plurality of conductors 21 may include, for example, indium tin oxide (ITO). On the lower surface and side surface of each conductor 21, a conductor 22 corresponding to the conductor 21 is provided. The upper surfaces of the plurality of conductors 21 and 22 are flush with the upper surface of the insulator 31. The lower surface of each conductor 22 is in contact with the upper surface of the cell capacitor CC corresponding to the conductor 22. The group of corresponding conductors 21 and 22 functions as the lower electrode BE. The detailed structure of the multiple conductors 22 will be described later.

[0051] Insulator 32, insulator 33 and insulator 34 are sequentially arranged facing upward on the upper surface of insulator 31 and the upper surfaces of multiple conductors 21 and 22.

[0052] Multiple oxide semiconductors 40 are provided corresponding to multiple conductors 21 and 22. Each oxide semiconductor 40 is disposed on the upper surface of the conductor 21 corresponding to the oxide semiconductor 40. Each oxide semiconductor 40 is configured such that the lower surface of the oxide semiconductor 40 is in contact with the upper surface of the conductor 21. The multiple oxide semiconductors 40 penetrate insulators 32 to 34. The multiple oxide semiconductors 40 are, for example, oxide semiconductors. The multiple oxide semiconductors 40, for example, contain at least one element selected from indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn). The oxide semiconductor 40, for example, contains indium gallium zinc oxide (In-Gallium-Zinc Oxide).

[0053] With the structure described above, a conductor 21 corresponding to the oxide semiconductor 40 is provided between the oxide semiconductor 40 and the conductor 22 corresponding to the oxide semiconductor 40. In this structure, the conductor 21 is provided in a manner that reduces the contact resistance between the conductor 22 and the oxide semiconductor 40.

[0054] A gate insulating film 41 is provided on the side surface of each oxide semiconductor 40. The gate insulating film 41 may contain an insulator such as silicon oxide. A gate insulating film 42 is provided on the side surface of each gate insulating film 41. The gate insulating film 42 may contain an insulator such as silicon nitride. Furthermore, it is sufficient to provide at least one gate insulating film on the side surface of each oxide semiconductor 40. That is, the memory cell array 11 only needs to include at least one of the gate insulating films 41 and 42.

[0055] The corresponding oxide semiconductors 40 and gate insulating films 41 and 42 function as pillars (PI). Moreover, each oxide semiconductor 40 is equivalent to a semiconductor constituting part of the cell transistor (CT). The upper surfaces of the plurality of oxide semiconductors 40 and the upper surfaces of the plurality of gate insulating films 41 and 42 are flush with the upper surface of the insulator 34.

[0056] Furthermore, the column PI can also have a conical shape. Moreover, the column PI can also have a bow-shaped shape with the central part bulging along the Z direction.

[0057] In the same layer as the insulator 33, there are multiple conductors 23. Each conductor 23 functions as a gate electrode GE (word line WL). Each conductor 23 extends along the X direction corresponding to a gate electrode GE. Thus, in the XZ cross-section shown in FIG4, the conductor 23 is in contact with the side surface of a plurality of pillars PI arranged along the X direction. Moreover, the multiple conductors 23 are arranged along the Y direction corresponding to a plurality of gate electrodes GE. Thus, in the YZ cross-section shown in FIG5, each conductor 23 is in contact with the side surface of a pillar PI corresponding to the conductor 23.

[0058] An insulator 35 is provided on the upper surface of the insulator 34, the upper surface of the plurality of oxide semiconductors 40, and the upper surface of the gate insulating film 41 and the gate insulating film 42.

[0059] Multiple conductors 24 are provided in the same layer as the insulator 35, corresponding to multiple pillars PI. Each conductor 24 is disposed on the upper surface of the oxide semiconductor 40 of the pillar PI corresponding to the conductor 24. Each conductor 24 is disposed in such a way that it covers the upper surface of the oxide semiconductor 40 corresponding to the conductor 24. The multiple conductors 24, for example, comprise conductive oxides. The multiple conductors 24, for example, comprise at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo) and oxygen (O). The multiple conductors 24, for example, comprise oxides of at least one element selected from indium (In) and tin (Sn). The conductive oxide, for example, comprises at least one compound selected from indium tin oxide and tin oxide.

[0060] On the upper surface of the plurality of conductors 24, a plurality of conductors 25 are provided corresponding to the plurality of conductors 24. The plurality of conductors 25 contain, for example, at least one element selected from titanium (Ti), tin (Sn), zinc (Zn), ruthenium (Ru), and niobium (Nb). Moreover, the plurality of conductors 25 contain, for example, a nitride of at least one of these elements. The plurality of conductors 25 contain, for example, titanium nitride (TiN).

[0061] On the upper surface of the plurality of conductors 25, a plurality of conductors 26 are provided corresponding to the plurality of conductors 25. The plurality of conductors 26 contain, for example, tungsten (W). The upper surface of the plurality of conductors 26 is provided in such a way that it becomes flush with the upper surface of the insulator 35. In the Z direction, the thickness of the plurality of conductors 26 is, for example, greater than the thickness of each of the plurality of conductors 24 and 25.

[0062] In the structure described above, the group of corresponding conductors 24 to 26 functions as the upper electrode TE. Furthermore, each conductor 25 is provided to prevent metal elements contained in the conductor 26 corresponding to the conductor 25 from diffusing into the conductor 24. Therefore, it can be said that the multiple conductors 25 function, for example, as barrier metals.

[0063] On the upper surface of the insulator 35 and the upper surface of the plurality of conductors 26, a plurality of conductors 27 are provided corresponding to a plurality of upper electrodes TE. Each conductor 27 is provided in such a way that it is connected to the conductor 26 of the plurality of upper electrodes TE corresponding to the conductor 27. Each conductor 27 extends along the Y direction corresponding to a bit line BL. The plurality of upper electrodes TE corresponding to each conductor 27 correspond to a plurality of different word lines WL. The plurality of conductors 27 are arranged along the X direction corresponding to the plurality of bit lines BL. The plurality of conductors 27 may contain, for example, titanium nitride (TiN).

[0064] On the upper surface of each conductor 27, there is a conductor 28 corresponding to the conductor 27. The plurality of conductors 28 may contain, for example, tungsten (W).

[0065] On the upper surface of each conductor 28, there is a conductor 29 corresponding to the conductor 27. The plurality of conductors 29 may contain, for example, titanium nitride (TiN).

[0066] In the structure described above, the corresponding conductors 27, 28, and 29 function as bit lines BL. Furthermore, the multiple conductors 27 and 29 are provided to prevent the metal elements contained in the multiple conductors 28 from diffusing into the layer below the multiple conductors 27 and the layer above the multiple conductors 29. Therefore, it can be said that the multiple conductors 27 and 29 function, for example, as barrier metals. Alternatively, the multiple conductors 27 and 29 can also be omitted.

[0067] An insulator 36 is provided on the upper surface of the plurality of conductors 29.

[0068] Above the insulator 34, a plurality of component SLTs are provided. Each component SLT extends along the Y direction. The plurality of component SLTs are arranged along the X direction. Each component SLT is provided in a manner that penetrates conductors 27 to 29. The upper surface of each component SLT is, for example, flush with the upper surface of the insulator 36. The lower surface of each component SLT is, for example, in contact with conductor 26. Furthermore, the lower surface of each component SLT only needs to reach the height of the upper surface of the insulator 35. The plurality of component SLTs are, for example, insulators such as silicon oxide. With the structure described above, two adjacent bit lines BL along the X direction are separated from each other by the component SLTs corresponding to the two bit lines BL. Moreover, the two bit lines BL are insulated from each other by the component SLTs.

[0069] In the XZ section including character line WL1 or character line WL3, each component SLT is, for example, configured to coincide with one end of each upper electrode TE in the X direction. Furthermore, in the XZ section including character line WL2 or character line WL4, each component SLT is, for example, configured to coincide with the other end of each upper electrode TE in the X direction. The XZ section shown in FIG4 illustrates an example where each component SLT is configured to coincide with the other end of the upper electrode TE corresponding to that component SLT.

[0070] 1.1.5 Structure of the lower electrode

[0071] Next, the structure of the lower electrode BE will be explained using FIG6. FIG6 is a cross-sectional view showing an example of the structure of the lower electrode of the transistor included in the semiconductor device of the embodiment.

[0072] Each conductor 22 includes conductor 221, conductor 222 and conductor 223.

[0073] In the conductor 22, a conductor 221 is disposed on the side surface and the lower surface of the conductor 22. The conductor 221 may, for example, contain titanium nitride (TiN). The conductor 221 may further contain oxygen. The conductor 221 may further contain titanium oxide (TiO).

[0074] A conductor 222 is disposed on a side of conductor 221. The side of conductor 222 is, for example, in contact with insulator 31. Conductor 222 may contain, for example, titanium (Ti). Conductor 222 may further contain oxygen. Conductor 222 may further contain titanium oxide (TiO).

[0075] Conductor 223 is located between the lower surfaces of conductors 221 and 222 and the upper surface of the cell capacitor CC, and is disposed in contact with them. Conductor 223 may contain, for example, titanium (Ti) and silicon (Si). Moreover, conductor 223 may also contain germanium (Ge) in addition to titanium (Ti) and silicon (Si). Conductor 223 may also contain oxygen. Conductor 223 is preferably at least one of a compound containing titanium (Ti) and silicon (Si) (TiSi x2) and a compound containing titanium (Ti), silicon (Si) and germanium (Ge) (TiSi x3Ge y1). Here, the values ​​x2, x3, and y1 are positive numbers. Furthermore, these compounds can be identified, for example, by nano-beam diffraction (NBD) and electron energy loss spectroscopy (EELS).

[0076] During the manufacturing process, the conductor 223A, which is formed corresponding to the conductor 223, prevents the formation of oxides between the cell capacitor CC and the conductor 22. For example, when the cell capacitor CC contains silicon germanium, oxygen (O) contained in the conductor 21 and the oxide semiconductor 40 may diffuse and form silicon oxide (SiO x3) at the interface between the cell capacitor CC and the conductor 223A. Here, the value x3 is a positive number. The formation of silicon oxide is suppressed by the conductor 223A. The conductors 223 and 223A are sometimes referred to as barrier layers.

[0077] During the manufacturing process, the conductor 223A corresponding to the conductor 223 effectively prevents the formation of silicon oxide (SiO x3). As a result, the concentration of oxygen (O) atoms (CO) at the interface (boundary) IF between the conductor 223 and the cell capacitor CC is reduced. For example, at the interface (boundary) IF between the conductor 223 and the cell capacitor CC, the concentration of titanium (Ti) atoms (CTi) is higher than the concentration of oxygen (O) atoms (CO). Moreover, for example, at the interface IF, the concentration ratio CO / CTi obtained by dividing the concentration of CO by the concentration of CTi is less than 2 / 3. Furthermore, for example, at the interface, the concentration ratio CO / CTi is less than 1 / 2. Furthermore, the concentration of a certain element can be obtained, for example, by replacing it with the intensity of the element in energy dispersive X-ray spectroscopy (EDX).

[0078] Furthermore, the interface IF between the conductor 223 and the cell capacitor CC is determined, for example, based on the concentration of atoms contained in the cell capacitor CC. When multiple cell capacitors CC contain silicon-germanium (SiGe x1), the interface IF can be determined, for example, based on the concentration of germanium (Ge) atoms. More specifically, the concentration of germanium (Ge) atoms in the cell capacitor CC tends to decrease towards the interface IF. In an embodiment, the interface IF between the conductor 223 and the cell capacitor CC can be defined as the position where the concentration of germanium (Ge) is half the maximum value of the concentration of germanium (Ge) in the cell capacitor CC. The atomic composition profile can be obtained, for example, by a method combining observation using scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX) (STEM-EDX). Moreover, the interface IF between the conductor 223 and the cell capacitor CC can also be determined based on the concentration of silicon (Si) atoms. For example, similar to the case of germanium (Ge), the interface IF between conductor 223 and cell capacitor CC can be set at a position where the concentration of silicon (Si) atoms is half the maximum value of the silicon (Si) concentration in cell capacitor CC.

[0079] Furthermore, for the reasons described later, when multiple cell capacitors CC contain silicon-germanium (SiGe x1), the germanium (Ge) atoms in the cell capacitor CC can also have a concentration distribution along the Z direction. For example, it can be configured such that the concentration of germanium (Ge) atoms in the second part contained between the first part and the conductor 223 is higher than the concentration of germanium (Ge) atoms in the first part contained within the first height range along the Z direction. The silicon-germanium composition of the first part can also be richer in germanium (Ge) than the silicon-germanium composition of the second part.

[0080] 1.2 Manufacturing Method

[0081] Next, the manufacturing method of the semiconductor device 1 according to the embodiment will be described using Figures 7, 8, and 9. Figures 7, 8, and 9 are cross-sectional views showing an example of the manufacturing method of the semiconductor device according to the embodiment. The cross-section shown in Figure 7 corresponds to the cross-sectional view shown in Figure 4. The cross-sections shown in Figures 8 and 9 correspond to the cross-section shown in Figure 6.

[0082] First, an insulator 31 is placed on top of the substrate S.

[0083] Furthermore, multiple holes H are formed corresponding to the regions in insulator 31 that contain multiple cell capacitors CC and multiple lower electrodes BE. The formation of the multiple holes H is performed, for example, using photolithography and anisotropic etching. Anisotropic etching is, for example, reactive ion etching (RIE).

[0084] Then, as shown in Figure 7, multiple cell capacitors CC are formed by embedding them into multiple holes H respectively.

[0085] Furthermore, as shown in Figure 8, conductors 221A and 222A are formed on the cell capacitor CC within each hole H in which the cell capacitor CC is formed. Conductors 221A and 222A correspond to conductors 221 and 222, respectively. Conductor 221A may contain, for example, titanium nitride (TiN). Conductor 222A may contain, for example, titanium (Ti). Moreover, conductors 221 and 222 may contain more oxygen (O) than conductors 221A and 222A, for example, through diffusion of oxygen (O) contained in conductor 21 and oxide semiconductor 40 (described later). Conductors 221A and 222A may have different compositions than conductors 221 and 222. More specifically, conductor 222A is formed in a manner that covers the upper surface of the cell capacitor CC and the side surface of the insulator 31. The conductor 221A is formed by covering the surface of the conductor 222A inside each hole H.

[0086] Furthermore, the structure in which cell capacitors CC and conductors 221A and 222A are formed within each hole H is heat-treated. As a result, in FIG. 8, the portion where conductor 222A connects to cell capacitor CC is formed as shown in FIG. 9, conductor 223A. Conductor 223A corresponds to conductor 223. Conductor 223A may contain, for example, titanium (Ti) and silicon (Si). Moreover, conductor 223A may also contain germanium (Ge) in addition to titanium (Ti) and silicon (Si). Furthermore, conductor 223, like conductors 221 and 222, contains oxygen (O), for example, through diffusion of oxygen (O) contained in conductor 21 and oxide semiconductor 40 (described later). Conductor 223 contains more oxygen (O) than conductor 223A. Conductor 223A may have a different composition than conductor 223. As described above, conductor 223A can suppress the formation of silicon oxide at the interface between cell capacitor CC and conductor 223A.

[0087] Through subsequent heat treatment, for example, the titanium (Ti) contained in conductor 222A reacts with the silicon (Si) or silicon-germanium (SiGe x1) contained in the cell capacitor CC, thereby forming a conductor 223A containing a compound (TiSi x2) or a compound (TiSi x3Ge y1) as shown in FIG. 9. For example, a portion of conductor 222A in FIG. 8 before the heat treatment is transformed into conductor 223A. For example, the portion of conductor 222A in contact with cell capacitor CC is transformed into conductor 223A.

[0088] Here, when the cell capacitor CC contains silicon-germanium (SiGe x1), the reactivity of titanium (Ti) and silicon (Si) may differ from that of titanium (Ti) and germanium (Ge) during the heat treatment. For example, during the heat treatment, the titanium (Ti) contained in the conductor 222A reacts more readily with silicon (Si) than with germanium (Ge). For this reason, the germanium (Ge) atoms in the cell capacitor CC may also have a concentration distribution along the Z direction.

[0089] Then, after conductor 223A is formed, conductor 21 is formed by embedding it into the hole H where conductors 221A and 222A are formed. This forms the structure of the lower electrode BE shown in FIG. 6. Furthermore, multiple conductors 23-29, insulators 32-36, multiple oxide semiconductors 40, multiple gate insulating films 41 and 42, and component SLT are formed above the lower electrode BE. Moreover, for example, during heat treatment after conductor 21 is formed, oxygen (O) contained in conductor 21 and oxide semiconductor 40 diffuses and penetrates into conductors 221A, 222A, and 223A. Thus, conductors 221A, 222A, and 223A become conductors 221, 222, and 223, respectively. Conductor 22 is formed in this way.

[0090] Furthermore, the manufacturing method described illustrates the case where conductor 223A is formed by heat treatment following the formation of cell capacitor CC, conductor 221A, and conductor 222A within each hole H, but it is not limited to this. The heat treatment may also be omitted. That is, for example, conductor 223A can be formed even without heat treatment prior to the formation of conductor 21 after the formation of cell capacitor CC, conductor 221A, and conductor 222A within each hole H.

[0091] 1.3 Effects

[0092] According to the embodiments, the reliability of semiconductor devices can be improved. The effects of the embodiments are described below.

[0093] According to an embodiment, the semiconductor device 1 includes a cell capacitor CC, a lower electrode BE, an upper electrode TE, a pillar PI, and a word line WL. The cell capacitor CC comprises silicon. The lower electrode BE is connected to the upper surface of the cell capacitor CC. The upper electrode TE is disposed above the lower electrode BE. The pillar PI comprises an oxide semiconductor 40 extending in the Z direction and a gate insulating film 42 disposed on the side of the oxide semiconductor 40. The oxide semiconductor 40 is connected to the upper surface of the lower electrode BE. The word line WL is connected to the gate insulating film 42. The lower electrode BE includes a conductor 21 and a conductor 223. The conductor 21 comprises a conductive oxide and is connected to the lower surface of the oxide semiconductor 40. The conductor 223 is disposed between the conductor 21 and the cell capacitor CC and comprises titanium (Ti) and silicon (Si). With the structure described above, according to the embodiment, the formation of a high-resistivity layer between the lower electrode BE and the capacitor CC can be suppressed. Therefore, the reliability of the semiconductor device 1 can be improved.

[0094] Additionally, in the absence of a barrier layer connected to the cell capacitor, the application of thermal load can sometimes cause oxygen contained in the channels of the lower electrode and the cell capacitor to diffuse into the cell capacitor. This can sometimes lead to the formation of a high-resistivity silicon oxide layer between the cell capacitor and the lower electrode. In this case, there is a problem of high resistance in the lower electrode.

[0095] According to the implementation method, the formation of silicon oxides due to oxygen diffusion can be prevented during the manufacturing process.

[0096] As a supplement, the manufacturing steps of the semiconductor device 1 in the embodiment are as follows: forming a hole H in the insulator 31; forming a cell capacitor CC within the hole H; forming a lower electrode BE; and after forming the cell capacitor CC and the lower electrode BE, forming a cell transistor CT on the upper surface of the lower electrode BE. The step of forming the lower electrode BE includes: forming a conductor 223A in contact with the upper surface of the cell capacitor CC; and forming a conductor 21 above the conductor 223A in a manner that is embedded in the hole H. According to the above steps, in the manufacturing steps, the cell transistor CT is formed after the conductor 223A is formed. Thereby, when a thermal load is applied in the step of forming the upper electrode, the conductor 223A can prevent oxygen contained in the oxide semiconductor 40 of the conductor 21 of the lower electrode BE and the cell transistor CT from penetrating into the cell capacitor CC. For example, in Figure 8, when conductor 221A is formed instead of conductor 222A on the cell capacitor CC, silicon oxide may sometimes form at the interface between the cell capacitor CC and conductor 221A. According to the embodiment, by forming conductor 222A on the cell capacitor CC, conductor 223A is formed, thus preventing the formation of oxide between the cell capacitor CC and conductor 22. Therefore, according to the embodiment, the formation of silicon oxide during the manufacturing process can be prevented.

[0097] Furthermore, according to the embodiment, the phenomenon of changes in the characteristics of the cell transistor CT due to the diffusion of oxygen contained in the oxide semiconductor 40 can be suppressed. In other words, the changes in the characteristics of the cell transistor CT caused by the detachment of oxygen from the channels of the cell transistor CT are suppressed.

[0098] Furthermore, when multiple cell capacitors CC contain silicon-germanium (SiGe x1), the contact resistance can be reduced if the upper portion of the cell capacitor CC has a higher concentration of germanium (Ge) than the portion adjacent to the upper portion further below it. Additionally, the higher the concentration of germanium atoms in the silicon-germanium of the upper portion of the cell capacitor CC, the lower the Schottky barrier at the interface between the conductor 223 and the cell capacitor CC can be. This reduces the contact resistance between the conductor 223 and the cell capacitor CC.

[0099] 2 Other

[0100] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and similarly, are included within the scope of the invention described in the claims and their equivalents.

[0101] 1: Semiconductor devices 2: Memory controller 11: Memory Cell Array 12: Input / Output Circuit 13: Control Circuit 14: Voltage generation circuit 15: Writing Circuit 16: Readout Circuit 17: Column Selection Circuit 18: Row selection circuit 19: Sensing Amplifier 21~29, 221, 221A, 222, 222A, 223, 223A: Conductors 31~36: Insulators 40: Oxide Semiconductor 41, 42: Gate insulating film 100: Memory System ADD: Address Signal BE: Lower electrode BL, BL1~BLN: Bit lines CC: Cellular Capacitor CMD command CNT: Control Signal CT: Cellular Electron DAT: Data Dr: Read the data Dw: Write data GE: Gate electrode H: Hole IF: Interface (Boundary) MC: Memory Cell PI: Column PL: Board Line S:Substrate SLT: Component SN: Storage Node TE: Upper electrode IV-IV: Section Line VV: Profile line WL, WL1~WLM: Character lines X, Y, Z: Direction

Claims

1. A semiconductor device, comprising: The first electrode comprises silicon and germanium; The second electrode is in contact with the upper surface of the first electrode; the third electrode is located above the second electrode. An oxide semiconductor is in contact with the upper surface of the second electrode and extends in a first direction from the second electrode toward the third electrode; an insulating film is disposed on the side of the oxide semiconductor; And a first conductor, in contact with at least a portion of the insulating film, wherein the first electrode comprises: a first portion; The second part is disposed between the first part and the second electrode, wherein the concentration of germanium in the second part is higher than the concentration of germanium in the first part, and the second electrode comprises: a second conductor comprising a conductive oxide and in contact with the lower surface of the oxide semiconductor; and a third conductor disposed between the second conductor and the first electrode and comprising titanium and silicon.

2. The semiconductor device of claim 1, wherein the third conductor comprises a compound of titanium and silicon.

3. The semiconductor device as claimed in claim 1, wherein the third conductor further comprises germanium.

4. The semiconductor device of claim 3, wherein the third conductor comprises a compound of titanium, silicon and germanium.

5. The semiconductor device of claim 1, wherein the second electrode further comprises oxygen, and at the interface between the first electrode and the second electrode, the concentration of titanium is higher than the concentration of oxygen.

6. The semiconductor device of claim 5, wherein the concentration ratio of oxygen to titanium at the interface is 2 / 3 or less.

7. The semiconductor device as claimed in claim 6, wherein the concentration ratio at the interface is less than 1 / 2.

8. The semiconductor device of claim 5, wherein the first electrode further comprises germanium, and the germanium concentration at the interface is half the maximum value of the germanium concentration in the first electrode.

9. The semiconductor device of claim 1, wherein the second conductor comprises indium tin oxide.

10. The semiconductor device of claim 1, wherein the second electrode further comprises: a fourth conductor disposed on a lower surface and a side surface of the second conductor and comprising nitrogen and titanium; and a fifth conductor disposed on a side surface of the fourth conductor and comprising titanium.

11. The semiconductor device of claim 10, wherein the third conductor is in contact with the upper surface of the first electrode and the lower surface of the fourth conductor.

12. The semiconductor device of claim 10, wherein the fourth conductor and the fifth conductor further comprise oxygen.

13. The semiconductor device of claim 1, wherein the oxide semiconductor comprises indium gallium zinc oxide.

14. The semiconductor device of claim 1, wherein the oxide semiconductor and the insulating film constitute a vertical transistor.

15. The semiconductor device of claim 1, wherein the first electrode functions as an electrode of a capacitor.

16. A method for manufacturing a semiconductor device, comprising: To form holes in an insulator; A first electrode containing silicon and germanium is formed within the cavity; Form a second electrode; And after forming the first electrode and the second electrode, forming a cellular transistor comprising an oxide semiconductor on the upper surface of the second electrode, the step of forming the second electrode includes: forming a first conductor comprising a metal and silicon above the first electrode; and forming a second conductor above the first conductor, the first electrode comprising: a first portion; and a second portion disposed between the first portion and the second electrode, wherein the concentration of germanium in the second portion is higher than the concentration of germanium in the first portion.

17. A method of manufacturing a semiconductor device as claimed in claim 16, wherein the step of forming the first conductor comprises: forming a third conductor in contact with the upper surface of the first electrode and comprising the metal; and performing a heat treatment after forming the third conductor, thereby transforming a portion of the third conductor into the first conductor.

18. A method of manufacturing a semiconductor device as claimed in claim 16, wherein the step of forming the second electrode further comprises: forming a fourth conductor between the first conductor and the second conductor.

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