Semiconductor memory devices

Abstract

This invention relates to a semiconductor memory device. The semiconductor memory device of this embodiment includes: a first capacitor comprising a first electrode, a second electrode, and a first capacitor insulating film disposed between the first electrode and the second electrode; and a first transistor comprising a first oxide semiconductor layer electrically connected to the second electrode and extending along a first direction, a first gate electrode surrounding the first oxide semiconductor layer, and a third electrode electrically connected to the first oxide semiconductor layer and disposed on the opposite side of the second electrode. The second electrode comprises a first portion, a second portion disposed between the first portion and the first oxide semiconductor layer, and a third portion disposed between the second portion and the first oxide semiconductor layer. A first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction, and a third width of the third portion in the second direction is smaller than the second width.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor memory device. Prior Technology

[0002] Oxide-semiconductor transistors (OSTs) that form channels in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during disconnection. Therefore, OSTs can be used, for example, as switching transistors for memory cells in Dynamic Random Access Memory (DRAM). In the case of using OSTs as switching transistors for memory cells, the oxide semiconductor layer of the OST is electrically connected to the memory node electrode of the capacitor. Summary of the Invention

[0003] The semiconductor memory device of the embodiment includes: a first capacitor comprising a first electrode, a second electrode, and a first capacitor insulating film disposed between the first electrode and the second electrode; and a first transistor comprising a first oxide semiconductor layer, a first gate electrode, a first gate insulating film, and a third electrode, wherein the first oxide semiconductor layer is electrically connected to the second electrode and extends along a first direction, the first gate electrode surrounds the first oxide semiconductor layer, the first gate insulating film is disposed between the first gate electrode and the first oxide semiconductor layer, the third electrode is electrically connected to the first oxide semiconductor layer and has the first oxide semiconductor layer disposed between it and the second electrode, the second electrode comprising a first portion, a second portion disposed between the first portion and the first oxide semiconductor layer, and a third portion disposed between the second portion and the first oxide semiconductor layer, wherein a first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction, and a third width of the third portion in the second direction is smaller than the second width.

[0004] According to embodiments of the present invention, a semiconductor memory device comprising an oxide semiconductor transistor can be provided. Simple Explanation of the Diagram

[0005] Figure 1 is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment. Figure 2 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 3 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 4 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 5 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 6 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 7 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 8 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 9 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 10 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 11 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 12 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 13 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figure 15 is a schematic cross-sectional view showing a comparative semiconductor memory device. Figure 16 is a schematic cross-sectional view showing a semiconductor memory device according to a first modification of the first embodiment. Figure 17 is an enlarged schematic cross-sectional view showing a semiconductor memory device according to a first modification of the first embodiment. Figure 18 is a schematic cross-sectional view showing a semiconductor memory device according to a second modification of the first embodiment. Figure 19 is a schematic cross-sectional view showing a semiconductor memory device according to a second modification of the first embodiment. Figure 20 is a schematic cross-sectional view showing a semiconductor memory device according to the second embodiment. Figure 21 is a schematic cross-sectional view showing a semiconductor memory device according to the second embodiment. Figure 22 is an enlarged schematic cross-sectional view showing a semiconductor memory device according to the second embodiment. Figure 23 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 24 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 25 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 26 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 27 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 28 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 29 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Implementation

[0006] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Furthermore, in the following description, the same or similar components will be marked with the same symbols, and the description of components that have been described once will sometimes be omitted appropriately.

[0007] Furthermore, in this specification, terms such as "upper," "lower," "upper part," "lower part," "above," or "below" are sometimes used for convenience. The terms "upper," "lower," "upper part," "lower part," "above," or "below" are merely terms indicating relative positional relationships within the diagram, not terms specifying positional relationships relative to gravity.

[0008] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness of the components constituting the semiconductor memory device, the distance between components, the grain size, and the crystal orientation can be performed, for example, by transmission electron microscopy (TEM). Moreover, measurements of crystal orientation can be performed, for example, by nanobeam electron diffraction (NBED).

[0009] (First Implementation)

[0010] The semiconductor memory device of the first embodiment includes: a first capacitor comprising a first electrode, a second electrode, and a first capacitor insulating film disposed between the first electrode and the second electrode; and a first transistor comprising a first oxide semiconductor layer, a first gate electrode, a first gate insulating film, and a third electrode. The first oxide semiconductor layer is electrically connected to the second electrode and extends along a first direction. The first gate electrode surrounds the first oxide semiconductor layer. The first gate insulating film is disposed between the first gate electrode and the first oxide semiconductor layer. The third electrode is electrically connected to the first oxide semiconductor layer and has the first oxide semiconductor layer disposed between it and the second electrode. The second electrode comprises a first portion, a second portion disposed between the first portion and the first oxide semiconductor layer, and a third portion disposed between the second portion and the first oxide semiconductor layer. The first width of the first portion in a second direction perpendicular to the first direction is smaller than the second width of the second portion in the second direction, and the third width of the third portion in the second direction is smaller than the second width.

[0011] Figure 1 is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment. The semiconductor memory device of the first embodiment is a semiconductor memory 100. The semiconductor memory 100 of the first embodiment is DRAM. The semiconductor memory 100 uses oxide semiconductor transistors as the switching transistors of the memory cells of the DRAM.

[0012] Figure 1 is a diagram showing a portion of the memory cell array contained in the semiconductor memory 100. Multiple memory cells are arranged in the memory cell array. Figure 1 illustrates the case with four memory cells, but the number of memory cells contained in the memory cell array is not limited to four.

[0013] The memory cell array of the semiconductor memory 100 includes multiple memory cells MC1, MC2, MC3, MC4, multiple word lines WL1, WL2, multiple bit lines BL1, BL2, and a board line PL. The first memory cell MC1 includes a first transistor TR1 and a first capacitor CA1. The second memory cell MC2 includes a second transistor TR2 and a second capacitor CA2. The third memory cell MC3 includes a third transistor TR3 and a third capacitor CA3. The fourth memory cell MC4 includes a fourth transistor TR4 and a fourth capacitor CA4.

[0014] Hereinafter, sometimes one of the multiple memory cells MC1, MC2, MC3, MC4, or multiple memory cells MC1, MC2, MC3, MC4, are collectively referred to as memory cell MC. Also, sometimes one of the multiple character lines WL1, WL2, or multiple character lines WL1, WL2, are collectively referred to as character line WL. Furthermore, sometimes one of the multiple bit lines BL1, BL2, or bit lines BL1, BL2, are collectively referred to as bit line BL.

[0015] Hereinafter, sometimes one of the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4, or sometimes all of the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4, will be collectively referred to as transistor TR. Furthermore, sometimes one of the first capacitor CA1, the second capacitor CA2, the third capacitor CA3, and the fourth capacitor CA4, or sometimes all of the first capacitor CA1, the second capacitor CA2, the third capacitor CA3, and the fourth capacitor CA4, will be collectively referred to as capacitor CA.

[0016] The character line WL is electrically connected to the gate electrode of the transistor TR. The bit line BL is electrically connected to one of the source / drain electrodes of the transistor TR. The other source / drain electrode of the transistor TR is electrically connected to one electrode of the capacitor CA. The other electrode of the capacitor CA is connected to the plate line PL.

[0017] Memory cells (MC) store data by accumulating charge in capacitors (CA). Data writing and reading are performed by turning on transistors (TR).

[0018] By selecting one bit line BL and one word line WL, a memory cell MC can be selected. For example, with a desired voltage applied to the bit line BL, a voltage is applied to the word line WL, thereby turning on the transistor TR to write data to the memory cell MC. Furthermore, by turning on the transistor TR, the voltage change on the bit line BL corresponding to the amount of charge stored in the capacitor CA is detected to read data from the memory cell MC.

[0019] Figures 2, 3, and 4 are schematic cross-sectional views of the semiconductor memory device according to the first embodiment. Figure 2 is a cross-section including the first memory cell MC1 and the second memory cell MC2 of Figure 1.

[0020] Figure 3 is a cross-sectional view of AA' in Figure 2. Figure 4 is a cross-sectional view of BB' in Figure 2. In Figure 2, the vertical direction is referred to as the first direction. In Figure 2, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first direction.

[0021] The semiconductor memory 100 of the first embodiment includes a substrate 10, a substrate insulating layer 12, a plate electrode 14, a first memory node electrode 16a, a second memory node electrode 16b, a first capacitor insulating film 18a, a second capacitor insulating film 18b, a first source / drain electrode 20a, a second source / drain electrode 20b, a first oxide semiconductor layer 22a, a second oxide semiconductor layer 22b, a first gate electrode 24a, a second gate electrode 24b, a first gate insulating film 26a, a second gate insulating film 26b, a bit line 28, and an interlayer insulating layer 30.

[0022] The first memory node electrode 16a includes a first metal region 16a1 and a first oxide conductor region 16a2. Furthermore, the second memory node electrode 16b includes a second metal region 16b1 and a second oxide conductor region 16b2.

[0023] Plate electrode 14 is an example of a first electrode. First memory node electrode 16a is an example of a second electrode. Second memory node electrode 16b is an example of a fourth electrode. First source / drain electrode 20a is an example of a third electrode. Second source / drain electrode 20b is an example of a fifth electrode.

[0024] The first metal region 16a1 is an example of the first region. The first oxide conductor region 16a2 is an example of the second region.

[0025] Hereinafter, the first memory node electrode 16a and the second memory node electrode 16b are sometimes collectively referred to as memory node electrode 16. Also, the first capacitor insulating film 18a and the second capacitor insulating film 18b are sometimes collectively referred to as capacitor insulating film 18. Furthermore, the first source / drain electrode 20a and the second source / drain electrode 20b are sometimes collectively referred to as source / drain electrode 20. Furthermore, the first oxide semiconductor layer 22a and the second oxide semiconductor layer 22b are sometimes collectively referred to as oxide semiconductor layer 22. Furthermore, the first gate electrode 24a and the second gate electrode 24b are sometimes collectively referred to as gate electrode 24. Furthermore, the first gate insulating film 26a and the second gate insulating film 26b are sometimes collectively referred to as gate insulating film 26.

[0026] Substrate 10 is, for example, a semiconductor substrate. Substrate 10 is, for example, a silicon substrate. As substrate 10, an insulating substrate may also be used, for example. Moreover, substrate 10 may be omitted.

[0027] A memory cell array is provided on the substrate 10. A transistor TR and a capacitor CA are provided on the substrate 10. The capacitor CA is disposed between the substrate 10 and the transistor TR.

[0028] A substrate insulating layer 12 is disposed on the substrate 10. The substrate insulating layer 12 is disposed between the substrate 10 and the plate electrode 14. The substrate insulating layer 12 is an insulator. For example, the substrate insulating layer 12 is silicon oxide.

[0029] The capacitor CA includes plate electrodes 14, storage node electrodes 16, and capacitor insulating film 18.

[0030] Plate electrode 14 is disposed on substrate insulating layer 12. Plate electrode 14 is a conductor. Plate electrode 14 may contain, for example, a metal or metal compound. Plate electrode 14 may be, for example, titanium nitride.

[0031] In the equivalent circuit diagram of Figure 1, plate electrode 14 corresponds to plate line PL.

[0032] The memory node electrode 16 is disposed on the plate electrode 14. The memory node electrode 16 extends along a first direction. The memory node electrode 16 is a conductor.

[0033] The first memory node electrode 16a includes, for example, a first metal region 16a1 and a first oxide conductor region 16a2. The second memory node electrode 16b includes, for example, a second metal region 16b1 and a second oxide conductor region 16b2.

[0034] A first oxide conductive region 16a2 is disposed between a first metal region 16a1 and a first oxide semiconductor layer 22a. The first oxide conductive region 16a2 is in contact with both the first metal region 16a1 and the first oxide semiconductor layer 22a.

[0035] The second oxide conductive region 16b2 is disposed between the second metal region 16b1 and the second oxide semiconductor layer 22b. The second oxide conductive region 16b2 is in contact with both the second metal region 16b1 and the second oxide semiconductor layer 22b.

[0036] The first metal region 16a1 and the second metal region 16b1 contain a metal or a metal compound. The first metal region 16a1 and the second metal region 16b1 are, for example, metal nitrides. The first metal region 16a1 and the second metal region 16b1 contain, for example, at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo) and nitrogen (N). The first metal region 16a1 and the second metal region 16b1 are, for example, titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride.

[0037] The first oxide conductor region 16a2 and the second oxide conductor region 16b2 contain oxide conductors. The chemical composition of the first oxide conductor region 16a2 and the second oxide conductor region 16b2 is different from the chemical composition of the first metal region 16a1 and the second metal region 16b1.

[0038] The first oxide conductive region 16a2 and the second oxide conductive region 16b2, for example, comprise at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo) and oxygen (O). The first oxide conductive region 16a2 and the second oxide conductive region 16b2, for example, comprise indium tin oxide. The first oxide conductive region 16a2 and the second oxide conductive region 16b2, for example, are indium tin oxide.

[0039] The first oxide conductive region 16a2 is, for example, polycrystalline. The

[0111] directions of the plurality of crystals contained in the first oxide conductive region 16a2 are aligned toward a first direction. Whether the

[0111] directions of the plurality of crystals contained in the first oxide conductive region 16a2 are aligned toward the first direction is determined, for example, based on an image obtained using TEM. For example, the angle between the

[0111] axes of the plurality of crystals and the first direction is calculated based on an image of a cross-section parallel to the first direction. If the average value of the calculated angle is within 20 degrees, the

[0111] directions of the plurality of crystals are considered to be aligned toward the first direction. Furthermore, whether the

[0111] directions of the plurality of crystals contained in the first oxide conductive region 16a2 are aligned toward the first direction is determined, for example, based on an electron diffraction pattern obtained using nano-beam electron diffraction. For example, if the diffraction point intensity in the

[0111] direction is greater than the diffraction point intensity in other directions, the

[0111] directions of the plurality of crystals are considered to be aligned toward the first direction.

[0040] The second oxide conductive region 16b2 is, for example, polycrystalline. The

[0111] direction of the plurality of crystals contained in the second oxide conductive region 16b2 is aligned with the first direction.

[0041] A capacitor insulating film 18 is disposed between the plate electrode 14 and the memory node electrode 16. The capacitor insulating film 18 is connected to both the plate electrode 14 and the memory node electrode 16.

[0042] The capacitor insulating film 18 is an insulator. The capacitor insulating film 18 may contain, for example, an insulator having a higher dielectric constant than silicon dioxide. The capacitor insulating film 18 may contain, for example, a so-called high-k insulator.

[0043] The capacitor insulating film 18 may contain, for example, zirconium oxide. The capacitor insulating film 18 may have, for example, a laminated structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0044] The plate electrode 14 is disposed outside the memory node electrode 16. As shown in FIG3, in the AA' section perpendicular to the first direction, the plate electrode 14 surrounds the memory node electrode 16. In the AA' section, the plate electrode 14 surrounds the capacitor insulating film 18. In the AA' section, the capacitor insulating film 18 surrounds the memory node electrode 16.

[0045] The transistor TR includes an oxide semiconductor layer 22, a gate electrode 24, a gate insulating film 26, a memory node electrode 16, and a source / drain electrode 20. The memory node electrode 16 functions as the source / drain electrode of the transistor TR.

[0046] An oxide semiconductor layer 22 is disposed on the memory node electrode 16. The oxide semiconductor layer 22 is disposed between the memory node electrode 16 and the source / drain electrode 20.

[0047] The oxide semiconductor layer 22 is electrically connected to the memory node electrode 16 and the source / drain electrode 20. For example, the oxide semiconductor layer 22 is connected to the memory node electrode 16 and the source / drain electrode 20. The oxide semiconductor layer 22 extends along a first direction.

[0048] In the oxide semiconductor layer 22, a channel is formed that becomes a current path when the transistor TR is turned on.

[0049] The oxide semiconductor layer 22 is an oxide semiconductor. For example, the oxide semiconductor layer 22 is amorphous.

[0050] The oxide semiconductor layer 22 comprises at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), calcium (Ca) and cadmium (Cd) and oxygen (O).

[0051] The oxide semiconductor layer 22 may contain, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), along with zinc (Zn) and oxygen (O). The oxide semiconductor layer 22 may contain, for example, indium gallium zinc oxide. The oxide semiconductor layer 22 may be, for example, indium gallium zinc oxide.

[0052] The oxide semiconductor layer 22 has, for example, a chemical composition different from that of the memory node electrode 16 and the source / drain electrode 20.

[0053] The oxide semiconductor layer 22 contains, for example, oxygen pores. The oxygen pores in the oxide semiconductor layer 22 function as donors.

[0054] The gate electrode 24 faces the oxide semiconductor layer 22. As shown in FIG4, the gate electrode 24 surrounds the oxide semiconductor layer 22 in a cross-section BB' perpendicular to the first direction. The gate electrode 24 is disposed around the oxide semiconductor layer 22. The transistor TR is a so-called surrounding gate transistor (SGT).

[0055] Gate electrode 24 is a conductor. Gate electrode 24 may be, for example, a metal, a metal compound, or a semiconductor. Gate electrode 24 may contain, for example, tungsten (W). Gate electrode 24 may be, for example, tungsten.

[0056] In the equivalent circuit diagram of FIG1, gate electrode 24 corresponds to word line WL. For example, first gate electrode 24a corresponds to first word line WL1. And, for example, second gate electrode 24b corresponds to second word line WL2.

[0057] A gate insulating film 26 is disposed between the oxide semiconductor layer 22 and the gate electrode 24. As shown in FIG4, the gate insulating film 26 surrounds the oxide semiconductor layer 22 in a cross-section BB' perpendicular to the first direction. The gate insulating film 26 is disposed between the memory node electrode 16 and the source / drain electrode 20. The gate insulating film 26 is, for example, in contact with the memory node electrode 16 and the source / drain electrode 20.

[0058] The gate insulating film 26 is an insulator. The gate insulating film 26 may contain, for example, silicon (Si) and nitrogen (N). The gate insulating film 26 may contain, for example, silicon nitride.

[0059] Source / drain electrodes 20 are disposed on the oxide semiconductor layer 22. Source / drain electrodes 20 are connected to the oxide semiconductor layer 22. Source / drain electrodes 20 are disposed on the opposite side of the oxide semiconductor layer 22 to the memory node electrode 16. The oxide semiconductor layer 22 is disposed between the memory node electrode 16 and the source / drain electrodes 20.

[0060] The source / drain electrode 20 may contain, for example, an oxide conductor. The source / drain electrode 20 may contain, for example, the same oxide conductor as the memory node electrode 16.

[0061] The source / drain electrode 20 may contain, for example, at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W), and molybdenum (Mo) and oxygen (O). The source / drain electrode 20 may contain, for example, indium tin oxide. The source / drain electrode 20 may be, for example, indium tin oxide.

[0062] Bit line 28 is disposed on transistor TR. Bit line 28 extends along the second direction. Bit line 28 is disposed on source / drain electrode 20. Bit line 28 is connected to source / drain electrode 20.

[0063] Bit line 28 is a conductor. Bit line 28 may contain, for example, a metal or a metal compound. Bit line 28 may contain, for example, at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). Bit line 28 may have, for example, a multilayer structure of titanium nitride and tungsten.

[0064] Bit line 28 corresponds to bit line BL in the equivalent circuit diagram of Figure 1. For example, bit line 28 corresponds to the first bit line BL1.

[0065] An interlayer insulating layer 30 is disposed around the memory cell MC. For example, the interlayer insulating layer 30 is disposed around the first memory cell MC1 and the second memory cell MC2.

[0066] Interlayer insulation 30 is an insulator. Interlayer insulation 30 may contain, for example, silicon oxide.

[0067] Figure 5 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 5 is an enlarged schematic cross-sectional view of a portion of Figure 1. In Figure 5, a portion of the memory node electrode 16, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26 of the first memory cell MC1 and the second memory cell MC2 are shown.

[0068] The first memory node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is disposed between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is disposed between the first oxide semiconductor layer 22a and the second portion 16ay.

[0069] The third part 16az is the uppermost part of the first memory node electrode 16a. The third part 16az is, for example, connected to the first oxide semiconductor layer 22a.

[0070] The first width (W1 in Figure 5) of the second direction of the first part 16ax is smaller than the second width (W2 in Figure 5) of the second direction of the second part 16ay. Furthermore, the third width (W3 in Figure 5) of the second direction of the third part 16az is smaller than the second width W2.

[0071] The upper part of the first memory node electrode 16a has a barrel shape in a cross-section parallel to the first direction.

[0072] The first part 16ax is located, for example, in the first metal region 16a1. The second part 16ay is located, for example, in the first oxide conductor region 16a2. The third part 16az is located, for example, in the first oxide conductor region 16a2.

[0073] For example, the first width W1 is more than 0.5 times and less than 0.9 times the second width W2. Furthermore, for example, the third width W3 is more than 0.7 times and less than 0.95 times the second width W2. Also, for example, the third width W3 is greater than the first width W1.

[0074] The second memory node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is disposed between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is disposed between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0075] The sixth part 16bz is the uppermost part of the second memory node electrode 16b. The sixth part 16bz is, for example, connected to the second oxide semiconductor layer 22b.

[0076] The first width of the second direction of the fourth part 16bx (W4 in Figure 5) is smaller than the second width of the second direction of the fifth part 16by (W5 in Figure 5). Moreover, the sixth width of the second direction of the sixth part 16bz (W6 in Figure 5) is smaller than the fifth width W5.

[0077] The upper part of the second memory node electrode 16b has a barrel shape in a cross-section parallel to the first direction.

[0078] The fourth part, 16bx, is located, for example, in the second metal region 16b1. The fifth part, 16by, is located, for example, in the second oxide conductor region 16b2. The sixth part, 16bz, is located, for example, in the second oxide conductor region 16b2.

[0079] For example, the fourth width W4 is more than 0.5 times and less than 0.9 times the fifth width W5. Furthermore, for example, the sixth width W6 is more than 0.7 times and less than 0.95 times the fifth width W5. For example, the sixth width W6 is greater than the fourth width W4.

[0080] As shown in Figure 5, the shortest distance (d in Figure 5) between the first memory node electrode 16a and the second memory node electrode 16b in the second direction is, for example, less than the first width W1. Moreover, as shown in Figure 5, the shortest distance (d in Figure 5) between the first memory node electrode 16a and the second memory node electrode 16b in the second direction is, for example, less than the fourth width W4.

[0081] The first oxide conductive region 16a2, for example, covers the side of the first metal region 16a1. Furthermore, the second oxide conductive region 16b2, for example, covers the side of the second metal region 16b1.

[0082] Figure 6 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the first embodiment. Figure 6 is the CC' section of Figure 5. The CC' section is a section perpendicular to the first direction.

[0083] As shown in FIG6, for example in the CC' section, the first oxide conductive region 16a2 surrounds at least a portion of the first metal region 16a1. Furthermore, as shown in FIG6, for example in the CC' section, the second oxide conductive region 16b2 surrounds at least a portion of the second metal region 16b1.

[0084] Next, an example of the manufacturing method of the semiconductor memory device according to the first embodiment will be described.

[0085] A method for manufacturing a semiconductor memory device according to a first embodiment includes: forming a first pillar having a multilayer structure comprising a first conductor, an insulator, and a second conductor, with at least the upper surface being the second conductor, protruding from the periphery and extending along a first direction; forming a second pillar having a multilayer structure comprising the first conductor, the insulator, and the second conductor, with at least the upper surface being the second conductor, protruding from the periphery and extending along the first direction, and located in a second direction perpendicular to the first direction relative to the first pillar; forming oxide conductors on the upper surfaces of the first pillar and the second pillar in such a manner that the oxide conductors formed on the upper surfaces of the first pillar and the second pillar are not in contact with each other; removing corner portions of the upper surfaces of the oxide conductors formed on at least the upper surface of the first pillar; removing corner portions of the upper surfaces of the oxide conductors formed on at least the upper surface of the second pillar; and embedding an insulating film between the first pillar and the second pillar.

[0086] Figures 7, 8, 9, 10, 11, 12, 13, and 14 are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment. Figures 7 to 14 respectively show cross-sections corresponding to Figure 2. Figures 7 to 14 are diagrams illustrating an example of a method for manufacturing a semiconductor memory 100.

[0087] The following is an example of a case where the substrate insulating layer 12 is silicon oxide, the plate electrode 14 is titanium nitride, the metal region of the memory node electrode 16 is titanium nitride, the oxide conductor region of the memory node electrode 16 is indium tin oxide, the capacitor insulating film 18 is zirconium oxide, the source / drain electrode 20 is indium tin oxide, the oxide semiconductor layer 22 is indium gallium zinc oxide, the gate electrode 24 is tungsten, the gate insulating film 26 is silicon nitride, and the interlayer insulating layer 30 is silicon oxide.

[0088] First, a first silicon oxide film 51, a first titanium nitride film 52, a second silicon oxide film 53, and a first silicon nitride film 54 are formed on the substrate 10. The first silicon oxide film 51, the first titanium nitride film 52, the second silicon oxide film 53, and the first silicon nitride film 54 are formed, for example, by chemical vapor deposition (CVD).

[0089] The first silicon oxide film 51 ultimately becomes the substrate insulating layer 12. The first titanium nitride film 52 ultimately becomes part of the plate electrode 14. The second silicon oxide film 53 ultimately becomes part of the interlayer insulating layer 30.

[0090] Next, a first opening 55 (Fig. 7) is formed, penetrating through the first silicon nitride film 54 and the second silicon oxide film 53 and reaching the first titanium nitride film 52. The first opening 55 is formed, for example, using photolithography and reactive ion etching (RIE).

[0091] Next, a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58 are embedded in the first opening 55. The second titanium nitride film 56, the zirconium oxide film 57, and the third titanium nitride film 58 are formed, for example, using atomic layer deposition (ALD). Furthermore, before the formation of the zirconium oxide film 57, the second titanium nitride film 56 is patterned in the first opening 55.

[0092] Next, the zirconium oxide film 57 and the third titanium nitride film 58 on the surface of the first silicon nitride film 54 are removed (Figure 8). The removal of the zirconium oxide film 57 and the third titanium nitride film 58 can be performed, for example, by chemical mechanical polishing (CMP).

[0093] The second titanium nitride film 56 ultimately becomes part of the plate electrode 14. The zirconium oxide film 57 ultimately becomes the capacitor insulating film 18. The third titanium nitride film 58 ultimately becomes part of the memory node electrode 16.

[0094] Next, a portion of the first silicon nitride film 54 and the zirconium oxide film 57 is removed (Figure 9). The first silicon nitride film 54 and the portion of the zirconium oxide film 57 are removed, for example, by a wet etching method.

[0095] By removing the first silicon nitride film 54, a portion of the third titanium nitride film 58 protrudes from the upper surface of the second silicon oxide film 53, thereby forming a titanium nitride pillar 58x protruding from the surrounding insulator.

[0096] Column 58x has a laminated structure consisting of a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58. The upper surface and sides of column 58x are made of titanium nitride.

[0097] Next, an indium tin oxide film 60 (Fig. 10) is formed on the upper surface of the pillar 58x of the third titanium nitride film 58. The indium tin oxide film 60 is formed under conditions where the growth rate in the upward direction is faster than the growth rate in the lateral direction. Moreover, the indium tin oxide film 60 is formed under conditions of poor step coverage.

[0098] The width of the indium tin oxide film 60 formed on the upper surface of the pillar 58x in the second direction is greater than the width of the pillar 58x in the second direction. Moreover, the indium tin oxide films 60 formed on the upper surfaces of two adjacent pillars 58x along the second direction are formed in a manner in which they are not in contact with each other.

[0099] The indium tin oxide (ITO) film 60 is formed, for example, under conditions where the

[0111] direction of the plurality of crystals contained in the ITO film 60 is aligned in a direction perpendicular to the upper surface of the pillar 58x of the third titanium nitride film 58. The ITO film 60 is formed, for example, with the

[0111] direction of the plurality of crystals contained in the ITO film 60 aligned in a first direction. By forming the ITO film 60 with the

[0111] direction of the plurality of crystals contained in the ITO film 60 aligned in the first direction, the upward growth rate of the ITO film 60 is faster than the lateral growth rate.

[0100] The indium tin oxide film 60 is formed, for example, by covering a portion of the side surface of the pillar 58x. The indium tin oxide film 60 is formed under conditions of rapid upward growth, thus suppressing the possibility of indium tin oxide films 60 on adjacent pillars 58x coming into contact. Furthermore, the indium tin oxide film 60 is formed under conditions of poor step coverage, so it is almost impossible for a second silicon oxide film 53 to form on the upper surface between adjacent pillars 58x.

[0101] The indium tin oxide film 60 is formed, for example, by physical vapor deposition (PVD) with differential coverage. Alternatively, the indium tin oxide film 60 is formed, for example, by sputtering with differential coverage.

[0102] Next, the corners of the upper surface of the indium tin oxide film 60 are removed (Fig. 11). The corners of the upper surface of the indium tin oxide film 60 are set into a front cone shape.

[0103] For example, the corners of the upper surface of the indium tin oxide film 60 are removed by RIE (Rapid Etching). Furthermore, the corners of the upper surface of the indium tin oxide film 60 are removed by wet etching.

[0104] For example, by etching the corners of the upper surface of the indium tin oxide film 60, the indium tin oxide film 60 can be removed even when the upper surface of the second silicon oxide film 53 between the two pillars 58x is covered by the indium tin oxide film 60.

[0105] Next, a third silicon oxide film 61 is formed on the indium tin oxide film 60 and the second silicon oxide film 53. The third silicon oxide film 61 is formed, for example, by a CVD method. By making the corners of the upper surface of the indium tin oxide film 60 into a front cone shape, the embedding of the third silicon oxide film 61 between two adjacent pillars 58x is improved. The third silicon oxide film 61 ultimately becomes part of the interlayer insulating layer 30.

[0106] Next, the third silicon oxide film 61 on top of the indium tin oxide film 60 is removed (Figure 12). The removal of the third silicon oxide film 61 is performed, for example, using the CMP method.

[0107] Next, a fourth silicon oxide film 62 is formed on the indium tin oxide film 60 and the third silicon oxide film 61. The fourth silicon oxide film 62 is formed, for example, by a CVD method. The fourth silicon oxide film 62 ultimately becomes part of the interlayer insulating layer 30.

[0108] Next, a tungsten film 63 is formed on the fourth silicon oxide film 62. The tungsten film 63 is formed, for example, by a CVD method.

[0109] Next, the tungsten film 63 is patterned. The patterning of the tungsten film 63 is performed, for example, by photolithography and RIE. The tungsten film 63 ultimately becomes the gate electrode 24.

[0110] Next, a fifth silicon oxide film 64 (Figure 13) is formed on the tungsten film 63. The fifth silicon oxide film 64 is formed, for example, by a CVD method. The fifth silicon oxide film 64 ultimately becomes part of the interlayer insulating layer 30.

[0111] Next, a second opening 65 (Fig. 14) is formed, penetrating the fifth silicon oxide film 64, the tungsten film 63, and the fourth silicon oxide film 62 to reach the indium tin oxide film 60. The second opening 65 is formed, for example, using photolithography and RIE.

[0112] Next, a silicon nitride gate insulating film 26 and an indium gallium zinc oxide oxide oxide semiconductor layer 22 are formed in the second opening 65. Then, an indium tin oxide source / drain electrode 20 is formed on the oxide semiconductor layer 22. Subsequently, a tungsten bit line 28 is formed on the source / drain electrode 20.

[0113] Using the above manufacturing method, the semiconductor memory 100 shown in Figures 2, 3, 4, 5 and 6 is manufactured.

[0114] Next, the function and effects of the semiconductor memory device of the first embodiment will be explained.

[0115] In the case of using oxide semiconductor transistors (OSTs) as switching transistors in DRAM memory cells, the oxide semiconductor layer of the OST is electrically connected to the memory node electrodes of the capacitor. From the viewpoint of improving the characteristics of DRAM memory cells, it is desirable to reduce the connection resistance between the OST layer and the memory node electrodes. By reducing the connection resistance between the OST layer and the memory node electrodes, for example, the operating speed of the memory cell can be increased.

[0116] Figure 15 is a schematic cross-sectional view of a comparative semiconductor memory device. The comparative semiconductor memory 900 is a DRAM. The semiconductor memory 900 uses oxide semiconductor transistors as the switching transistors for the memory cells of the DRAM. Figure 15 corresponds to Figure 2 of the first embodiment.

[0117] The semiconductor memory 900 of the comparative form differs from the semiconductor memory 100 of the first embodiment in that the width of the upper part of the memory node electrode 16 in the second direction is fixed. Furthermore, unlike the semiconductor memory 100 of the first embodiment, the upper part of the memory node electrode 16 is quadrilateral rather than barrel-shaped in a cross-section parallel to the first direction. Moreover, the semiconductor memory 900 differs from the semiconductor memory 100 of the first embodiment in that the first oxide conductive region 16a2 does not cover the side surface of the first metal region 16a1. Furthermore, the semiconductor memory 900 differs from the semiconductor memory 100 of the first embodiment in that the second oxide conductive region 16b2 does not cover the side surface of the second metal region 16b1.

[0118] In the comparative form of the semiconductor memory 900, the width of the upper part of the memory node electrode 16 in the second direction is fixed. Therefore, there is a risk that the resistance of the upper part of the memory node electrode 16 will increase, and the connection resistance between the oxide semiconductor layer 22 and the memory node electrode 16 will increase.

[0119] In the semiconductor memory 100 of the first embodiment, the width of the upper portion of the memory node electrode 16 in the second direction is locally widened. Therefore, the resistance of the upper portion of the memory node electrode 16 decreases, and the connection resistance between the oxide semiconductor layer 22 and the memory node electrode 16 decreases.

[0120] In the comparative form of the semiconductor memory 900, the first oxide conductive region 16a2 and the first metal region 16a1 of the first memory cell MC1 are only connected on the upper surface of the first metal region 16a1. Therefore, there is a risk that the interface resistance between the first oxide conductive region 16a2 and the first metal region 16a1 may increase. Consequently, there is a risk that the connection resistance between the first oxide semiconductor layer 22a and the first memory node electrode 16a may increase. For the same reason, there is a risk that the connection resistance between the second oxide semiconductor layer 22b of the second memory cell MC2 and the second memory node electrode 16b may increase.

[0121] In the semiconductor memory 100 of the first embodiment, the first oxide conductive region 16a2 of the first memory cell MC1 is connected to the first metal region 16a1 on its upper surface and side surface. Therefore, the interface resistance between the first oxide conductive region 16a2 and the first metal region 16a1 is reduced, and the connection resistance between the first oxide semiconductor layer 22a and the first memory node electrode 16a is reduced. For the same reason, the connection resistance between the second oxide semiconductor layer 22b of the second memory cell MC2 and the second memory node electrode 16b is reduced.

[0122] From the viewpoint of further reducing the interface resistance between the first oxide conductive region 16a2 and the first metal region 16a1, it is preferable, as shown in FIG. 6, that in a cross-section perpendicular to the first direction, the first oxide conductive region 16a2 surrounds at least a portion of the first metal region 16a1. For the same reason, it is preferable that, in a cross-section perpendicular to the first direction, the second oxide conductive region 16b2 surrounds at least a portion of the second metal region 16b1.

[0123] In the comparative form of the semiconductor memory 900, the width of the upper portion of the memory node electrode 16 in the second direction is fixed. Therefore, when an opening for forming the oxide semiconductor layer 22 is provided above the memory node electrode 16, the alignment margin between the opening and the upper surface of the memory node electrode 16 becomes smaller. Consequently, the manufacture of the semiconductor memory 900 may become difficult.

[0124] In the semiconductor memory 100 of the first embodiment, the width of the upper portion of the memory node electrode 16 in the second direction is locally widened. Therefore, when an opening for forming the oxide semiconductor layer 22 is provided on the memory node electrode 16, the alignment margin between the opening and the upper portion of the memory node electrode 16 is increased. Therefore, the manufacture of the semiconductor memory 100 is facilitated.

[0125] In the semiconductor memory 100 of the first embodiment, the corner of the upper surface of the upper portion of the memory node electrode 16 is formed into a front cone shape. Therefore, the embedding performance when forming an insulating film on the memory node electrode 16 is improved. For example, the embedding performance of the insulating film in the portion between the first oxide conductor region 16a2 and the second oxide conductor region 16b2 is improved. Therefore, for example, the manufacturing yield of the semiconductor memory 100 is improved.

[0126] The first width W1 of the first portion 16ax of the first memory node electrode 16a is preferably more than 0.5 times and less than 0.9 times the second width W2, and more preferably more than 0.6 times and less than 0.8 times the second width W2.

[0127] By exceeding the lower limit, the width of the upper portion of the first memory node electrode 16a in the second direction increases, and the resistance of the memory node electrode 16 decreases. Furthermore, by exceeding the lower limit, the width of the upper portion of the first memory node electrode 16a in the second direction increases, and when the opening for forming the oxide semiconductor layer 22 is provided on the memory node electrode 16, the alignment margin between the opening and the upper portion of the memory node electrode 16 increases.

[0128] Furthermore, by keeping the distance below the upper limit, the distance between the first memory node electrode 16a and the second memory node electrode 16b can be ensured, thereby suppressing electrical short circuits between the first memory node electrode 16a and the second memory node electrode 16b.

[0129] For the same reasons mentioned above, the fourth width W4 of the fourth portion 16bx of the second memory node electrode 16b is preferably more than 0.5 times and less than 0.9 times the fifth width W5, and more preferably more than 0.6 times and less than 0.8 times the fifth width W5.

[0130] The third width W3 of the first memory node electrode 16a is preferably more than 0.7 times and less than 0.95 times the second width W2, and more preferably more than 0.8 times and less than 0.9 times the second width W2.

[0131] By exceeding the lower limit, the width of the upper surface of the first memory node electrode 16a in the second direction increases, and the resistance of the memory node electrode 16 decreases. Furthermore, by exceeding the lower limit, the width of the upper surface of the first memory node electrode 16a in the second direction increases, and when the opening for forming the oxide semiconductor layer 22 is provided on the memory node electrode 16, the alignment margin between the opening and the upper surface of the memory node electrode 16 increases.

[0132] Furthermore, by being below the upper limit value, the angle of the front cone of the upper surface of the upper part of the storage node electrode 16 becomes larger, further improving the embeddability when forming an insulating film on the first storage node electrode 16a.

[0133] For the same reasons mentioned above, the sixth width W6 of the second memory node electrode 16b is preferably more than 0.7 times and less than 0.95 times the fifth width W5, and more preferably more than 0.8 times and less than 0.9 times.

[0134] From the viewpoint of reducing the resistance of the first memory node electrode 16a, the third width W3 of the first memory node electrode 16a is preferably greater than the first width W1. From the viewpoint of reducing the resistance of the second memory node electrode 16b, the sixth width W6 of the second memory node electrode 16b is preferably greater than the fourth width W4.

[0135] From the viewpoint of reducing the resistance of the memory node electrode 16, the shortest distance (d in FIG5) between the first memory node electrode 16a and the second memory node electrode 16b in the second direction is preferably smaller than the first width W1 of the first memory node electrode 16a and the fourth width W4 of the second memory node electrode 16b.

[0136] According to the semiconductor memory 100 of the first embodiment, the connection resistance between the oxide semiconductor layer 22 and the memory node electrode 16 can be reduced.

[0137] (First variation)

[0138] The semiconductor memory device of the first variation of the first embodiment differs from the semiconductor memory device of the first embodiment in that the second electrode further includes a third region of the semiconductor surrounded by the first region. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0139] Figure 16 is a schematic cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment. The semiconductor memory device in the first modification is a semiconductor memory 101. Figure 16 corresponds to Figure 2 of the first embodiment.

[0140] The first memory node electrode 16a further includes a first semiconductor region 16a3. The first semiconductor region 16a3 is an example of a third region.

[0141] The first semiconductor region 16a3 is surrounded by the first metal region 16a1. The first semiconductor region 16a3 contains a semiconductor. The first semiconductor region 16a3 is, for example, polycrystalline silicon-germanium containing conductive impurities. The first semiconductor region 16a3 is, for example, polycrystalline silicon containing conductive impurities.

[0142] The second memory node electrode 16b further includes a second semiconductor region 16b3.

[0143] The second semiconductor region 16b3 is surrounded by the second metal region 16b1. The second semiconductor region 16b3 contains a semiconductor. The second semiconductor region 16b3 is, for example, polycrystalline silicon-germanium containing conductive impurities. The second semiconductor region 16b3 is, for example, polycrystalline silicon containing conductive impurities.

[0144] In manufacturing the semiconductor memory 101, for example, the first metal region 16a1 that is in contact with the bottom and side surfaces of the first semiconductor region 16a3 and the first metal region 16a1 that is in contact with the upper surface of the first semiconductor region 16a3 are formed as separate films. Similarly, the second metal region 16b1 that is in contact with the bottom and side surfaces of the second semiconductor region 16b3 and the second metal region 16b1 that is in contact with the upper surface of the second semiconductor region 16b3 are formed as separate films.

[0145] Figure 17 is an enlarged schematic cross-sectional view of a semiconductor memory device according to a first variation of the first embodiment. Figure 17 is an enlarged schematic cross-sectional view of a portion of Figure 16. Figure 17 shows a portion of the memory node electrode 16 of the first memory cell MC1 and the second memory cell MC2, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26. Figure 17 corresponds to Figure 5 of the first embodiment.

[0146] The first memory node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is disposed between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is disposed between the first oxide semiconductor layer 22a and the second portion 16ay.

[0147] The third portion 16az, which is the uppermost part of the first memory node electrode 16a, is connected to the first oxide semiconductor layer 22a, for example.

[0148] The first width of the second direction of the first part 16ax (W1 in Figure 17) is smaller than the second width of the second direction of the second part 16ay (W2 in Figure 17). Furthermore, the third width of the second direction of the third part 16az (W3 in Figure 17) is smaller than the second width W2.

[0149] The first part 16ax is provided, for example, spanning the first metal region 16a1 and the first semiconductor region 16a3. The second part 16ay is located, for example, in the first oxide conductor region 16a2. The third part 16az is located, for example, in the first oxide conductor region 16a2.

[0150] The second memory node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is disposed between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is disposed between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0151] The sixth portion 16bz, which is the uppermost part of the second memory node electrode 16b, is connected to the second oxide semiconductor layer 22b, for example.

[0152] The first width of the second direction of the fourth part 16bx (W4 in Figure 17) is smaller than the fifth width of the second direction of the fifth part 16by (W5 in Figure 17). Moreover, the sixth width of the second direction of the sixth part 16bz (W6 in Figure 17) is smaller than the fifth width W5.

[0153] The fourth part 16bx is provided, for example, spanning the second metal region 16b1 and the second semiconductor region 16b3. The fifth part 16by is located, for example, in the second oxide conductor region 16b2. The sixth part 16bz is located, for example, in the second oxide conductor region 16b2.

[0154] The semiconductor memory 101 according to the first variant of the first embodiment, like the semiconductor memory 100 of the first embodiment, can reduce the connection resistance between the oxide semiconductor layer 22 and the memory node electrode 16.

[0155] (Second variation)

[0156] The semiconductor memory device differs from that of the first embodiment in that the second variation of the first embodiment further includes a first insulating layer disposed between the second electrode and the first gate electrode and in contact with the second electrode, and in a cross-section perpendicular to the first direction, the first insulating layer surrounds the first oxide semiconductor layer. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0157] Figure 18 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. The semiconductor memory device in the second modification is a semiconductor memory 102. Figure 18 corresponds to Figure 2 of the first embodiment.

[0158] The semiconductor memory 102 includes a first upper surface insulating layer 27a and a second upper surface insulating layer 27b. The first upper surface insulating layer 27a is an example of the first insulating layer.

[0159] A first upper surface insulating layer 27a is disposed between the first memory node electrode 16a and the first gate electrode 24a. The first upper surface insulating layer 27a is disposed on top of the first memory node electrode 16a. The first upper surface insulating layer 27a is in contact with the first memory node electrode 16a.

[0160] A second upper surface insulating layer 27b is disposed between the second memory node electrode 16b and the second gate electrode 24b. The second upper surface insulating layer 27b is disposed above the second memory node electrode 16b. The second upper surface insulating layer 27b is in contact with the second memory node electrode 16b.

[0161] Figure 19 is a schematic cross-sectional view of a semiconductor memory device according to a second variation of the first embodiment. Figure 19 is a cross-sectional view of DD' in Figure 18.

[0162] As shown in Figure 19, the first upper surface insulating layer 27a surrounds the first oxide semiconductor layer 22a in a cross-section DD' perpendicular to the first direction. Furthermore, the second upper surface insulating layer 27b surrounds the second oxide semiconductor layer 22b in a cross-section DD' perpendicular to the first direction.

[0163] The first upper surface insulating layer 27a and the second upper surface insulating layer 27b are insulators. The chemical composition of the first upper surface insulating layer 27a and the second upper surface insulating layer 27b is different from that of the interlayer insulating layer 30. The first upper surface insulating layer 27a and the second upper surface insulating layer 27b may contain, for example, silicon nitride or aluminum oxide.

[0164] The first upper surface insulating layer 27a and the second upper surface insulating layer 27b function as hard masks on the memory node electrode 16, for example, during the fabrication of the semiconductor memory 102. Furthermore, for example, the first upper surface insulating layer 27a and the second upper surface insulating layer 27b function as etch stop films when the openings of the embedded oxide semiconductor layer 22 are formed on the memory node electrode 16.

[0165] The semiconductor memory 102 according to the second variation of the first embodiment, like the semiconductor memory 100 of the first embodiment, can reduce the connection resistance between the oxide semiconductor layer 22 and the memory node electrode 16.

[0166] Based on the first embodiment and its variations, a semiconductor memory device comprising an oxide semiconductor transistor and having low connection resistance between the oxide semiconductor layer of the oxide semiconductor transistor and the memory node electrode can be realized.

[0167] (Second Implementation)

[0168] The semiconductor memory device of the second embodiment differs from that of the semiconductor memory device of the first embodiment in that, in a cross-section perpendicular to the first direction, the second electrode surrounds the first electrode. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0169] Figures 20 and 21 are schematic cross-sectional views of the semiconductor memory device according to the second embodiment.

[0170] Figure 21 is a cross-sectional view of EE' in Figure 20.

[0171] The semiconductor memory 200 of the second embodiment includes a substrate 10, a substrate insulating layer 12, a plate electrode 14, a first memory node electrode 16a, a second memory node electrode 16b, a first capacitor insulating film 18a, a second capacitor insulating film 18b, a first source / drain electrode 20a, a second source / drain electrode 20b, a first oxide semiconductor layer 22a, a second oxide semiconductor layer 22b, a first gate electrode 24a, a second gate electrode 24b, a first gate insulating film 26a, a second gate insulating film 26b, a bit line 28, and an interlayer insulating layer 30.

[0172] The first memory node electrode 16a includes a first metal region 16a1 and a first oxide conductor region 16a2. Furthermore, the second memory node electrode 16b includes a second metal region 16b1 and a second oxide conductor region 16b2.

[0173] Plate electrode 14 is an example of a first electrode. First memory node electrode 16a is an example of a second electrode. Second memory node electrode 16b is an example of a fourth electrode. First source / drain electrode 20a is an example of a third electrode. Second source / drain electrode 20 is an example of a fifth electrode.

[0174] The first metal region 16a1 is an example of the first region. The first oxide conductor region 16a2 is an example of the second region.

[0175] Hereinafter, the first memory node electrode 16a and the second memory node electrode 16b are sometimes collectively referred to as memory node electrode 16. Also, the first capacitor insulating film 18a and the second capacitor insulating film 18b are sometimes collectively referred to as capacitor insulating film 18. Furthermore, the first source / drain electrode 20a and the second source / drain electrode 20b are sometimes collectively referred to as source / drain electrode 20. Furthermore, the first oxide semiconductor layer 22a and the second oxide semiconductor layer 22b are sometimes collectively referred to as oxide semiconductor layer 22. Furthermore, the first gate electrode 24a and the second gate electrode 24b are sometimes collectively referred to as gate electrode 24. Furthermore, the first gate insulating film 26a and the second gate insulating film 26b are sometimes collectively referred to as gate electrode 24.

[0176] The plate electrode 14 is disposed inside the memory node electrode 16. As shown in FIG21, in the EE' section perpendicular to the first direction, the memory node electrode 16 surrounds the plate electrode 14. In the EE' section, the memory node electrode 16 surrounds the capacitor insulating film 18. In the EE' section, the capacitor insulating film 18 surrounds the plate electrode 14.

[0177] As shown in Figure 21, in the EE' section perpendicular to the first direction, the first memory node electrode 16a surrounds the plate electrode 14. In the EE' section, the first metal region 16a1 surrounds the plate electrode 14. In the EE' section, the first memory node electrode 16a surrounds the first capacitor insulating film 18a. In the EE' section, the first capacitor insulating film 18a surrounds the plate electrode 14.

[0178] As shown in Figure 21, in the EE' section perpendicular to the first direction, the second memory node electrode 16b surrounds the plate electrode 14. In the EE' section, the second metal region 16b1 surrounds the plate electrode 14. In the EE' section, the second memory node electrode 16b surrounds the second capacitor insulating film 18b. In the EE' section, the second capacitor insulating film 18b surrounds the plate electrode 14.

[0179] Figure 22 is an enlarged schematic cross-sectional view of the semiconductor memory device according to the second embodiment. Figure 22 is an enlarged schematic cross-sectional view of a portion of Figure 20. Figure 22 shows a portion of the memory node electrode 16 of the first memory cell MC1 and the second memory cell MC2, a portion of the oxide semiconductor layer 22, and a portion of the gate insulating film 26. Figure 22 corresponds to Figure 5 of the first embodiment.

[0180] The first memory node electrode 16a includes a first portion 16ax, a second portion 16ay, and a third portion 16az. The second portion 16ay is disposed between the first oxide semiconductor layer 22a and the first portion 16ax. The third portion 16az is disposed between the first oxide semiconductor layer 22a and the second portion 16ay.

[0181] The third portion 16az, which is the uppermost part of the first memory node electrode 16a, is connected to the first oxide semiconductor layer 22a, for example.

[0182] The first width of the second direction of the first part 16ax (W1 in Figure 22) is smaller than the second width of the second direction of the second part 16ay (W2 in Figure 22). Furthermore, the third width of the second direction of the third part 16az (W3 in Figure 22) is smaller than the second width W2.

[0183] The first part 16ax is, for example, located across the first metal region 16a1 on the left and right sides, sandwiching the plate electrode 14 in the middle. The second part 16ay is, for example, located in the first oxide conductor region 16a2. The third part 16az is, for example, located in the first oxide conductor region 16a2.

[0184] The second memory node electrode 16b includes a fourth portion 16bx, a fifth portion 16by, and a sixth portion 16bz. The fifth portion 16by is disposed between the second oxide semiconductor layer 22b and the fourth portion 16bx. The sixth portion 16bz is disposed between the second oxide semiconductor layer 22b and the fifth portion 16by.

[0185] The sixth portion 16bz, which is the uppermost part of the second memory node electrode 16b, is connected to the second oxide semiconductor layer 22b, for example.

[0186] The first width of the second direction of the fourth part 16bx (W4 in Figure 22) is smaller than the fifth width of the second direction of the fifth part 16by (W5 in Figure 22). Moreover, the sixth width of the second direction of the sixth part 16bz (W6 in Figure 22) is smaller than the fifth width W5.

[0187] The fourth part 16bx is, for example, located across the second metal region 16b1 on the left and right, sandwiching the plate electrode 14 in the middle. The fifth part 16by is, for example, located in the second oxide conductor region 16b2. The sixth part 16bz is, for example, located in the second oxide conductor region 16b2.

[0188] Next, an example of the manufacturing method of the semiconductor memory device according to the second embodiment will be described.

[0189] Figures 23, 24, 25, 26, 27, 28, and 29 are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figures 23 to 29 respectively show cross-sections corresponding to Figure 20. Figures 23 to 29 are figures illustrating an example of a method for manufacturing a semiconductor memory 200.

[0190] The following is an example of a case where the substrate insulating layer 12 is silicon oxide, the plate electrode 14 is titanium nitride, the metal region of the memory node electrode 16 is titanium nitride, the oxide conductor region of the memory node electrode 16 is indium tin oxide, the capacitor insulating film 18 is zirconium oxide, the source / drain electrode 20 is indium tin oxide, the oxide semiconductor layer 22 is indium gallium zinc oxide, the gate electrode 24 is tungsten, the gate insulating film 26 is silicon nitride, and the interlayer insulating layer 30 is silicon oxide.

[0191] First, a first silicon oxide film 51, a first titanium nitride film 52, and a second silicon oxide film 53 are formed on the substrate 10. The first silicon oxide film 51, the first titanium nitride film 52, and the second silicon oxide film 53 are formed, for example, by a CVD method.

[0192] The first silicon oxide film 51 ultimately becomes the substrate insulating layer 12. The first titanium nitride film 52 ultimately becomes part of the plate electrode 14. The second silicon oxide film 53 ultimately becomes part of the interlayer insulating layer 30.

[0193] Next, a first opening 55 (Fig. 23) is formed, penetrating the second silicon oxide film 53 and reaching the first titanium nitride film 52. The first opening 55 is formed, for example, using photolithography and RIE.

[0194] Next, a second titanium nitride film 56 is embedded in the first opening 55. The second titanium nitride film 56 is formed, for example, using a CVD method.

[0195] Next, the second titanium nitride film 56 (Figure 24) is removed from the surface of the second silicon oxide film 53. The removal of the second titanium nitride film 56 is performed, for example, using the CMP method. The second titanium nitride film 56 ultimately becomes part of the plate electrode 14.

[0196] Next, the second silicon oxide film 53 is removed (Figure 25). The second silicon oxide film 53 is removed, for example, by wet etching. A pillar is formed by the second titanium nitride film 56.

[0197] Next, a zirconium oxide film 57 and a third titanium nitride film 58 are formed on the pillar formed by the second titanium nitride film 56 (Figure 26). The zirconium oxide film 57 and the third titanium nitride film 58 are formed, for example, using the ALD method.

[0198] The zirconium oxide film 57 ultimately becomes the capacitor insulating film 18. The third titanium nitride film 58 ultimately becomes part of the memory node electrode 16.

[0199] A zirconium oxide film 57 and a third titanium nitride film 58 are formed on the pillar formed by the second titanium nitride film 56, thereby forming a titanium nitride pillar 58x protruding from the surrounding area.

[0200] Column 58x has a laminated structure consisting of a second titanium nitride film 56, a zirconium oxide film 57, and a third titanium nitride film 58. The upper surface and sides of column 58x are made of titanium nitride.

[0201] Next, an indium tin oxide film 60 (Fig. 27) is formed on the upper surface of column 58x. The indium tin oxide film 60 is formed under conditions where the growth rate in the upward direction is faster than the growth rate in the lateral direction. Moreover, the indium tin oxide film 60 is formed under conditions of poor step coverage.

[0202] The width of the indium tin oxide film 60 formed on the upper surface of the pillar 58x in the second direction is greater than the width of the pillar 58x in the second direction. Moreover, the indium tin oxide films 60 formed on the upper surfaces of two adjacent pillars 58x along the second direction are formed in a manner in which they are not in contact with each other.

[0203] The indium tin oxide (ITO) film 60 is formed, for example, under conditions where the

[0111] direction of the plurality of crystals contained in the ITO film 60 is aligned in a direction perpendicular to the upper surface of the pillar 58x of the third titanium nitride film 58. The ITO film 60 is formed, for example, with the

[0111] direction of the plurality of crystals contained in the ITO film 60 aligned in a first direction. By forming the ITO film 60 with the

[0111] direction of the plurality of crystals contained in the ITO film 60 aligned in the first direction, the upward growth rate of the ITO film 60 is faster than the lateral growth rate.

[0204] The indium tin oxide film 60 is formed, for example, by covering a portion of the side surface of the pillar 58x. The indium tin oxide film 60 is formed under conditions of rapid upward growth, thus suppressing contact between the indium tin oxide films 60 on adjacent pillars 58x. Furthermore, the indium tin oxide film 60 is formed under conditions of poor step coverage, thus almost no third titanium nitride film 58 is formed on the upper surface between adjacent pillars 58x.

[0205] The indium tin oxide film 60 is formed, for example, by a PVD method with poor step coverage. The indium tin oxide film 60 is also formed, for example, by a sputtering method with poor step coverage.

[0206] Next, the indium tin oxide film 60 is used as a mask to remove the third titanium nitride film 58 between two adjacent pillars 58x. The third titanium nitride film 58 is removed, for example, by a re-etching process (RIE). A hard mask may also be formed on the indium tin oxide film 60 before etching by the RIE process.

[0207] Next, the corners of the upper surface of the indium tin oxide film 60 are removed (Fig. 28). The corners of the upper surface of the indium tin oxide film 60 are made into a forward cone shape. Furthermore, the removal of the corners of the upper surface of the indium tin oxide film 60 can also be performed before removing the third titanium nitride film 58 between two adjacent pillars 58x.

[0208] For example, the corners of the upper surface of the indium tin oxide film 60 are removed by the RIE method for removing the third titanium nitride film 58. Furthermore, the corners of the upper surface of the indium tin oxide film 60 are removed by a wet etching method.

[0209] For example, the indium tin oxide film 60 can be removed when the indium tin oxide film 60 is formed on the upper surface of the third titanium nitride film 58 between the two pillars 58x by etching the corners of the upper surface of the indium tin oxide film 60.

[0210] Next, a third silicon oxide film 61 is formed on the indium tin oxide film 60. The third silicon oxide film 61 is formed, for example, by CVD. By making the corners of the upper surface of the indium tin oxide film 60 into a front cone shape, the embedding of the third silicon oxide film 61 between two adjacent pillars 58x is improved. The third silicon oxide film 61 ultimately becomes part of the interlayer insulating layer 30.

[0211] Next, the third silicon oxide film 61 on top of the indium tin oxide film 60 is removed (Figure 29). The removal of the third silicon oxide film 61 is performed, for example, using the CMP method.

[0212] Subsequently, using the same manufacturing method as the semiconductor memory 100 of the first embodiment, a transistor is formed on the indium tin oxide film 60. On the indium tin oxide film 60, a tungsten gate electrode 24, a silicon nitride gate insulating film 26, an indium gallium zinc oxide oxide semiconductor layer 22, an indium tin oxide source / drain electrode 20, and a tungsten bit line 28 are formed.

[0213] Using the manufacturing methods described above, the semiconductor memory 200 shown in Figures 20, 21 and 22 is manufactured.

[0214] According to the second embodiment, similar to the first embodiment, a semiconductor memory device including an oxide semiconductor transistor and having low connection resistance between the oxide semiconductor layer of the oxide semiconductor transistor and the memory node electrode can be realized.

[0215] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, a component of one embodiment may be replaced or modified with a component of another embodiment. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0216] 10:Substrate 12: Substrate insulating layer 14: Plate electrode (first electrode) 16a: First memory node electrode (second electrode) 16a1: First metallic region (first region) 16a2: First oxide conductor region (second region) 16a3: First semiconductor region 16ax: Part 1 16ay: Part Two 16az: Part Three 16b: Second memory node electrode (fourth electrode) 16b1: Second metal region 16b2: Second oxide conductor region 16b3: Second semiconductor region 16bx: Part Four 16by: Part 5 16bz: Part Six 18a: First capacitor insulating film 18b: Second capacitor insulating film 20a: First source / drain electrode (third electrode) 20b: Second source / drain electrode (fifth electrode) 22a: First oxide semiconductor layer 22b: Second oxide semiconductor layer 24a: First gate electrode 24b: Second gate electrode 26a: First gate insulating film 26b: Second gate insulating film 27a: First upper surface insulating layer (first insulating layer) 27b: Second upper surface insulating layer 28, BL1, BL2: Bit lines 30: Interlayer insulation layer 51: First silicon oxide film 52: First titanium nitride film 53: Second silicon oxide film 54: First silicon nitride film 55: First opening 56: Second titanium nitride film 57: Zirconia film 58: Third titanium nitride film 58x: Column 60: Indium Tin Oxide Film 61: Third silicon oxide film 62: Silicon oxide film 63: Tungsten film 64: Fifth silicon oxide film 65: Second opening 100, 101, 102, 200: Semiconductor memory (semiconductor memory device) 900: Semiconductor memory; CA: Capacitor CA1: First capacitor CA2: Second capacitor CA3: Third capacitor CA4: Fourth capacitor d: shortest distance MC1: First Memory Cell MC2: Second Memory Cell MC3: Third Memory Cell MC4: Fourth Memory Cell PL: Board Line TR: Transistor TR1: First transistor TR2: Second transistor TR3: Third transistor TR4: Fourth Transistor W1: First width W2: Second width W3: Third width W4: Fourth Width W5: Fifth Width W6: Sixth Width WL1: First character line WL2: Second character line

Claims

1. A semiconductor memory device, comprising: The first capacitor includes a first electrode, a second electrode, and a first capacitor insulating film disposed between the first electrode and the second electrode; The first transistor comprises a first oxide semiconductor layer, a first gate electrode, a first gate insulating film, and a third electrode. The first oxide semiconductor layer is electrically connected to the second electrode and extends along a first direction. The first gate electrode surrounds the first oxide semiconductor layer. The first gate insulating film is disposed between the first gate electrode and the first oxide semiconductor layer. The third electrode is electrically connected to the first oxide semiconductor layer and has the first oxide semiconductor layer disposed between it and the second electrode. The second electrode comprises a first portion, a second portion disposed between the first portion and the first oxide semiconductor layer, and a third portion disposed between the second portion and the first oxide semiconductor layer. The first width of the first portion in a second direction perpendicular to the first direction is smaller than the second width of the second portion in the second direction. The third width of the third portion in the second direction is smaller than the second width. The first portion comprises a metal or a metal compound. The second portion and the third portion comprise an oxide conductor, and the oxide conductor is in contact with the upper surface and side surface of the metal or metal compound.

2. The semiconductor memory device as claimed in claim 1, wherein the third portion is connected to the first oxide semiconductor layer.

3. The semiconductor memory device as claimed in claim 1, further comprising a substrate, wherein the first capacitor is disposed between the substrate and the first transistor.

4. The semiconductor memory device as claimed in claim 1, wherein the first width is more than 0.5 times and less than 0.9 times the second width, and the third width is more than 0.7 times and less than 0.95 times the second width.

5. The semiconductor memory device as claimed in claim 1, wherein the third width is greater than the first width.

6. The semiconductor memory device of claim 1, wherein the second electrode comprises a first region and a second region, the first region comprising the first portion of the metal or metal compound, the second region being disposed between the first region and the first oxide semiconductor layer, being in contact with the first region and the first oxide semiconductor layer, and comprising the second portion and the third portion of the oxide conductor.

7. The semiconductor memory device of claim 6, wherein in a cross-section perpendicular to the first direction, the second region surrounds at least a portion of the first region.

8. The semiconductor memory device as claimed in claim 6, wherein the second region comprises at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), manganese (Mn), tin (Sn), titanium (Ti), tantalum (Ta), calcium (Ca), tungsten (W) and molybdenum (Mo) and oxygen (O).

9. The semiconductor memory device of claim 6, wherein the second region is polycrystalline and the [111] orientation of the plurality of crystals contained in the second region is aligned toward the first direction.

10. The semiconductor memory device of claim 6, wherein the first region comprises at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo) and nitrogen (N).

11. The semiconductor memory device of claim 1, wherein in a cross-section perpendicular to the first direction, the first electrode surrounds the second electrode.

12. The semiconductor memory device of claim 1, wherein in a cross-section perpendicular to the first direction, the second electrode surrounds the first electrode.

13. The semiconductor memory device as claimed in claim 1, further comprising: A first insulating layer is disposed between the second electrode and the first gate electrode and is in contact with the second electrode. In a cross-section perpendicular to the first direction, the first insulating layer surrounds the first oxide semiconductor layer.

14. The semiconductor memory device of claim 13, wherein the first insulating layer comprises silicon nitride or aluminum oxide.

15. The semiconductor memory device as claimed in claim 1, further comprising: The second capacitor includes a fourth electrode and a second capacitor insulating film disposed between the first electrode and the fourth electrode; The second transistor includes a second oxide semiconductor layer, a second gate electrode, a second gate insulating film, and a fifth electrode. The second oxide semiconductor layer is electrically connected to the fourth electrode and extends along the first direction. The second gate electrode surrounds the second oxide semiconductor layer. The second gate insulating film is disposed between the second gate electrode and the second oxide semiconductor layer. The fifth electrode is electrically connected to the second oxide semiconductor layer and has the second oxide semiconductor layer between it and the fourth electrode. The fourth electrode includes a fourth portion, a fifth portion disposed between the fourth portion and the second oxide semiconductor layer, and a sixth portion disposed between the fifth portion and the second oxide semiconductor layer. The fourth width of the fourth portion in the second direction is smaller than the fifth width of the fifth portion in the second direction, and the sixth width of the sixth portion in the second direction is smaller than the fifth width.

16. The semiconductor memory device of claim 15, wherein the shortest distance between the second electrode and the fourth electrode in the second direction is less than the first width and the fourth width.

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