Light-emitting element and display device having the same

Abstract

A light-emitting element includes: a first semiconductor layer; a second semiconductor layer opposite to the first semiconductor layer; and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each include at least one first side having a straight line shape and at least one second side having a curved shape.

Description

Light-emitting element and display device including the light-emitting element The present invention relates to a light-emitting element and a display device comprising the light-emitting element, and more specifically, to a light-emitting element having improved external light extraction efficiency and a display device comprising the light-emitting element. As display devices used in computer screens, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) that are configured to emit their own light and liquid crystal displays (LCDs) that require an independent light source. Display devices have a wide range of applications, from computer screens and televisions to personal mobile devices, and research is underway on display devices with a wide display area and reduced size and weight. Furthermore, display devices incorporating light-emitting diodes (LEDs) have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs can be quickly switched on or off, exhibiting excellent luminous efficiency, high shock resistance, good stability, and the ability to display high-brightness images. One objective of this invention is to provide a light-emitting element with improved light extraction efficiency and a display device comprising the light-emitting element. Another objective of the present invention is to provide a light-emitting element and a display device comprising the light-emitting element, wherein light emitted from the light-emitting element is extracted in a direction toward the front surface of the display device. The purpose of this invention is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description. To achieve the above objectives, the light-emitting element according to an embodiment of the present invention includes: a first semiconductor layer; a second semiconductor layer opposite to the first semiconductor layer; and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each include at least one first side having a straight line shape and at least one second side having a curved shape. To achieve the above objectives, a display device according to another embodiment of the present invention includes: a substrate comprising a plurality of sub-pixels; a plurality of transistors disposed on the substrate; and a light-emitting element disposed in each of the plurality of sub-pixels on the substrate. Further details of the embodiments are included in the implementation and drawings. According to the present invention, light emitted from the light-emitting element is reflected in a disordered manner within the light-emitting element, so that the light trapped within the light-emitting element and not extracted can be minimized or at least reduced, thereby improving the external light extraction efficiency. According to the present invention, light emitted toward the side surface of the light-emitting element is extracted in the direction toward the front surface of the display device, thereby improving the efficiency of extracting light to the outside. According to the present invention, the brightness uniformity of light emitted to the side surface of the light-emitting element can be improved. The effects of the present invention are not limited to those listed above, and many other different effects are included in the present invention. The advantages and features of the present invention, as well as methods for achieving these advantages and features, will become clear from the following detailed description of exemplary embodiments, together with the accompanying drawings. However, the present invention is not limited to the exemplary embodiments disclosed herein, but will be practiced in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of the invention. The shapes, dimensions, proportions, angles, quantities, etc., shown in the accompanying drawings to describe exemplary embodiments of the invention are merely examples, and the invention is not limited thereto. Throughout this specification, similar element symbols generally denote similar elements. Furthermore, in the following description of the invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the scope of the invention. Terms such as "comprising," "having," and "including" as used herein are generally intended to allow for the addition of additional components unless used in conjunction with the term "only." Unless explicitly stated otherwise, any reference to the singular may include the plural. Even if not explicitly stated, components are interpreted as including a general tolerance range. When using terms such as "above," "over," "below," and "immediately following" to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used in conjunction with the terms "immediately" or "directly." When one element or layer is placed "on" another element or layer, the other layer or element can be directly inserted onto or between the other element. Although the terms "first," "second," etc., are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component in the technical concept of this invention. Throughout the instruction manual, similar component symbols usually represent similar components. The dimensions and thickness of each component shown in the accompanying drawings are shown for ease of description, and the invention is not limited to the dimensions and thickness of the components shown. Features of various embodiments of the present invention may be partially or wholly dependent on or combined with each other, and may be interlocked and operated in various technical ways, and embodiments may be implemented independently or in association with each other. In the following, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figure 1 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present invention. Referring to Figure 1, the light-emitting element ED includes: a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation layer 126. Light-emitting elements (EDs) can have various structures, such as lateral, vertical, and flip structures. A lateral ED includes a first electrode and a second electrode horizontally disposed on opposite sides of the light-emitting layer. A vertical ED includes a first electrode and a second electrode disposed on the upper and lower sides of the light-emitting layer. Flip EDs have essentially the same structure as lateral EDs. Lateral EDs have a first electrode and a second electrode horizontally disposed on the upper side of the light-emitting layer, while flip EDs have a first electrode and a second electrode horizontally disposed on the lower side of the light-emitting layer. In the following description, it is assumed that the ED has a vertical structure. However, the type of ED is not limited to this. EDs can have lateral or flip structures that apply the spirit of the present invention. A first semiconductor layer 121 is disposed below the light-emitting element ED. The first semiconductor layer 121 can be a layer formed by doping a specific material with n-type or p-type impurities. For example, the first semiconductor layer 121 can be a layer formed by doping materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type or p-type impurities. In this case, the p-type impurity can be magnesium (Mg), zinc (Zn), beryllium (Be), etc. The n-type impurity can be silicon (Si), germanium (Ge), tin (Sn), etc. However, the present invention is not limited thereto. In the present invention, the first semiconductor layer 121 is defined as an n-type semiconductor layer, that is, a layer doped with n-type impurities. However, the present invention is not limited thereto. The light-emitting layer 122 and the second semiconductor layer 123 are disposed on the first semiconductor layer 121. The light-emitting layer 122 emits light by receiving positive holes and negative electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be configured as a single-layer or multi-quantum-well (MQW) structure. For example, the light-emitting layer 122 can be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, the present invention is not limited thereto. The second semiconductor layer 123 is disposed on the light-emitting layer 122. The second semiconductor layer 123 can be a layer formed by doping a specific material with n-type or p-type impurities. For example, the second semiconductor layer 123 can be a layer formed by doping materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type or p-type impurities. Furthermore, p-type impurities can be magnesium (Mg), zinc (Zn), beryllium (Be), etc. n-type impurities can be silicon (Si), germanium (Ge), tin (Sn), etc. However, the present invention is not limited thereto. In the present invention, the second semiconductor layer 123 is defined as a p-type semiconductor layer, that is, a layer doped with p-type impurities. However, the present invention is not limited thereto. The first electrode 124 is disposed below the first semiconductor layer 121. The first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. For example, the first electrode 124 is disposed on the bottom surface of the first semiconductor layer 121 and covers the bottom surface of the first semiconductor layer 121. The first electrode 124 may be made of a conductive material, such as an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, the invention is not limited thereto. For example, the first electrode 124 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, the invention is not limited thereto. The encapsulation layer 126 may be disposed to at least partially surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125. The encapsulation layer 126 may protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. For example, the encapsulation layer 126 may cover the side surface of the first semiconductor layer 121, the side surface of the light-emitting layer 122, and the side surface of the second semiconductor layer 123. The encapsulation layer 126 may cover the entire side surface of the first semiconductor layer 121. However, the invention is not limited thereto. The light-emitting element (ED) may include light-emitting elements configured to emit light beams of various colors. For example, the light-emitting element (ED) may be one of a red light-emitting element, a blue light-emitting element, and a green light-emitting element. However, the invention is not limited thereto. Figure 2 is a plan view schematically showing the planar shape of a light-emitting element according to an embodiment of the present invention. Figure 3 is a plan view schematically showing another example of the planar shape of a light-emitting element according to an embodiment of the present invention. Figure 4 is a plan view schematically showing yet another example of the planar shape of a light-emitting element according to an embodiment of the present invention. Figure 5 is a plan view schematically showing yet another example of the planar shape of a light-emitting element according to an embodiment of the present invention. Figures 2 to 5 schematically show the planar shapes of the light-emitting elements ED, without distinguishing specific configuration elements of the light-emitting elements ED. The planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may each include a first side SI1 with a straight line shape and a second side SI2 with a curved shape. First, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may each include a plurality of first sides SI1 and a plurality of second sides SI2. When the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include a plurality of first sides SI1 and a plurality of second sides SI2, the plurality of first sides SI1 and the plurality of second sides SI2 can be alternately arranged. Therefore, the plurality of first sides SI1 can be arranged in positions facing each other, and the plurality of second sides SI2 can be arranged in positions facing each other. First, referring to Figures 2 and 3, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include a plurality of first sides SI1 and a plurality of second sides SI2. The planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may include first sides SI1 and second sides SI2 arranged alternately in a clockwise direction. Therefore, in each of the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED, the second side SI2 may be disposed on opposite sides of the first side SI1. For example, as shown in Figure 2, when the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include four sides, the two first sides SI1 with straight lines can be arranged facing each other on the upper and lower sides, and the two second sides SI2 with arc shapes can be arranged facing each other on the left and right sides. For example, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED can be in the shape of a Bunimovich stadium. As shown in Figure 3, in each of the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED, the corner regions each have a curved shape. For example, the corner regions may have a circular shape. For example, when the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each contain eight sides, the four first sides SI1 with straight lines may be arranged facing each other at the top, bottom, left, and right sides, and the four second sides SI2 with arc shapes may be arranged facing each other at the upper left, upper right, lower left, and lower right corner portions. For example, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may be a Sinai billiard shape. However, Figure 3 shows that the second sides SI2 have an inwardly concave shape. However, the invention is not limited to this. The second sides SI2 may be configured to have an outwardly convex shape. Next, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may each include a first side SI1 and a second side SI2. When the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include a first side SI1 and a second side SI2, one end of the first side SI1 may be connected to one end of the second side SI2. For example, the two opposite ends of the first side SI1 and the two opposite ends of the second side SI2 may be connected to each other. Referring to Figures 4 and 5, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include a first side SI1 and a second side SI2. Specifically, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED may each include a first side SI1 with a straight line shape and a second side SI2 with an arc shape. For example, in each of the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED, the two opposite ends of the first side SI1 may be connected to the two opposite ends of the second side SI2. For example, as shown in FIG4, when the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include two sides, the second side SI2 with an arc shape can be disposed on one side of the first side SI1 with a straight shape, and the two opposite ends of the first side SI1 can be respectively connected to the two opposite ends of the second side SI2. In each of the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED, the length of the first side SI1 can be less than the diameter of the second side SI2. For example, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED can each be a "D" shape formed by straight cutting a portion of a circle. In the shape formed by straight cutting a portion of a circle, the first side SI1 can be a chord, that is, a chord that does not pass through the center of the circle. The shape formed by straight cutting a portion of a circle can be a "D" shape, and the area of ​​the "D" shape can be greater than the area of ​​a semicircle. However, the present invention is not limited thereto. The area of ​​the "D" shape can be less than the area of ​​a semicircle. Furthermore, as shown in Figure 5, when the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED each include two sides, the second side SI2 with an arc shape can be disposed on one side of the first side SI1 with a straight shape, and the two opposite ends of the first side SI1 can be respectively connected to the two opposite ends of the second side SI2. For example, in each of the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED, the length of the first side SI1 can be equal to the diameter of the second side SI2. For example, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 of the light-emitting element ED can be semi-circular. Figures 6A to 6I are plan view top views for comparing and explaining the effect of the planar shape of a light-emitting element according to an embodiment of the present invention. In the following description, the effects of the embodiments of the present invention will be described in more detail with reference to examples and comparative examples. However, the following examples are for illustrative purposes only, and the scope of the embodiments of the present invention is not limited to the following examples. The embodiments and comparative examples will be described based on the planar shape of the top surface of the light-emitting element ED, all of which have the same area. [Comparative Example 1] As shown in Figure 6A, in Comparative Example 1, a square planar shape was prepared. In Figure 6A, L represents the length of one side constituting the square shape. [Comparative Example 2] As shown in Figure 6B, in Comparative Example 2, a rectangular planar shape was prepared. In Figure 6B, L represents the length of one side of the square shape in Figure 6A. [Comparative Example 3] As shown in Figure 6C, in Comparative Example 3, a circular planar shape was prepared. In Figure 6C, r is as shown in Equation 1 below. [Equation 1] [Comparative Example 4] As shown in Figure 6D, in Comparative Example 4, a hexagonal planar shape was prepared. In Figure 6D, r is as shown in Equation 2 below. [Equation 2] [Comparative Example 5] As shown in Figure 6E, in Comparative Example 5, an octagonal planar shape was prepared. In Figure 6E, r is as shown in Equation 3 below. [Equation 3] [Comparative Example 6] As shown in Figure 6F, in Comparative Example 6, a trapezoidal planar shape was prepared. In Figure 6F, D is as shown in Equation 4 below. D is the height of the trapezoidal shape. [Equation 4] [Example 1] As shown in Figures 2 and 6G, in Example 1, a planar shape resembling the Bunimovich stadium was prepared. In Figure 6G, r is as shown in Equation 5 below. [Equation 5] [Example 2] As shown in Figures 4 and 6H, in Example 2, a planar shape of the "D" shape was prepared by cutting a portion of a circle with a straight line. In Figure 6H, r is as shown in Equation 6 below. [Equation 6] [Example 3] As shown in Figures 5 and 6I, a semi-circular planar shape was prepared in Example 3. In Figure 6I, r is as shown in Equation 7 below. [Equation 7] The light extraction ratio of the light-emitting element manufactured as described above was measured. The amount of light extracted from the light-emitting element (ED) was measured as the light extraction ratio. The results are shown in Table 1 below. In this case, the light extraction ratio refers to the ratio of light extracted to the outside of the light-emitting element to the light emitted from the light-emitting element. [Table 1] Referring to Table 1, it can be seen that, compared with Comparative Example 1, which has a square planar shape, Comparative Example 2, which has a rectangular planar shape, Comparative Example 3, which has a circular planar shape, Comparative Example 4, which has a hexagonal planar shape, Comparative Example 5, which has an octagonal planar shape, and Comparative Example 6, which has a trapezoidal planar shape, the light extraction rate is higher in Examples 1, 2 and 3, which have planar shapes including straight sides and curved sides. According to the experimental results, the external light extraction efficiency can be improved when the planar shape includes both straight and curved edges. Figure 7 is a schematic configuration diagram of a display device according to an embodiment of the present invention. For ease of description, Figure 7 only shows the display panel PN, gate driver GD, data driver DD, and timing controller TC among the various constituent elements of the display device 100. Referring to FIG7, the display device 100 includes: a display panel PN, comprising a plurality of sub-pixels SP; a gate driver GD configured to supply various types of signals to the display panel PN; and a timing controller TC configured to control the data driver DD and the gate driver GD. The gate driver GD supplies multiple scan signals to multiple scan lines SL in response to multiple gate control signals provided by the timing controller TC. Figure 7 shows a single gate driver GD configured to be spaced apart from one side of the display panel PN. However, the number and configuration of gate drivers GD are not limited to this. The data driver DD supplies data voltage to multiple data lines DL in response to multiple data control signals and image data provided by the timing controller TC. The data driver DD can convert image data into data voltage using a reference gamma voltage and supply the converted data voltage to the multiple data lines DL. The timing controller TC calibrates the externally input image data and supplies the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronization signals, namely, a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signals and data control signals to them. The display panel PN is configured to display images to the user and includes a plurality of subpixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL may intersect each other, and a plurality of subpixels SP may be formed at the intersection points between the scan lines SL and the data lines DL. The display area AA and the non-display area NA can be defined on the display panel PN. The display area AA is the area on the display device 100 that displays an image. The display area AA may include: a plurality of subpixels SP constituting a plurality of pixels, and pixel circuitry configured to operate the plurality of subpixels SP. The plurality of subpixels SP is the smallest unit constituting the display area AA. The plurality of subpixels SP can constitute a single pixel. Thin-film transistors, etc., used to operate the plurality of light-emitting elements can be respectively disposed in the plurality of subpixels SP. The plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, in the case of an inorganic light-emitting display panel PN, the light-emitting elements may be light-emitting diodes (LEDs) or micro light-emitting diodes (micro LEDs or μLEDs). Multiple signal lines for transmitting various types of signals to the plurality of sub-pixels SP are provided in the display area AA. For example, the multiple signal lines may include: multiple data lines DL for supplying data voltage to the plurality of sub-pixels SP, and multiple scan lines SL for supplying scan signals to the plurality of sub-pixels SP. The multiple scan lines SL may extend in one direction within the display area AA and connect to the plurality of sub-pixels SP. The multiple data lines DL may extend in the display area AA in a direction different from the stated one direction and connect to the plurality of sub-pixels SP. Furthermore, low-potential power lines, high-potential power lines, etc., may be further provided in the display area AA. However, the present invention is not limited thereto. The non-display area NA can be defined as an area where no image is displayed, that is, the area extending from the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs, such as gate driver ICs and data driver ICs. Meanwhile, the non-display area NA can be located on the rear surface of the display panel PN, that is, on the surface where no sub-pixels SP exist. Alternatively, the non-display area NA can be excluded. However, the present invention is not limited to the configuration shown in the figures. Meanwhile, drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-display area NA via the gate-in-panel (GIP) method, or between multiple sub-pixels SP in the display area AA via the gate-in-active area (GIA) method. For example, the data driver DD and the timing controller TC can be formed on separate flexible films and printed circuit boards, and the display panel PN, data driver DD and timing controller TC can be electrically connected by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. As another example, when the gate driver GD is mounted in the display area AA via the GIA method and side traces are formed to connect the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN, thereby bonding the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. Therefore, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN via the above method, a virtually bezel-less design can be achieved. Figure 8 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present invention. Referring to FIG8, the substrate 110 is a component for supporting various components included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. In addition, the substrate 110 may contain a plastic such as a polymer, and may be made of a flexible material. A light-shielding layer LS is disposed below each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light from entering the active layer ACT of the driving transistor DT from the underside of the substrate 110. The light-shielding layer LS can block light from entering the active layer ACT of the driving transistor DT, thereby minimizing or at least reducing leakage current. A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the invention is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 can be excluded. However, the invention is not limited thereto. The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes: an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. An active layer ACT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the invention is not limited thereto. A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer used to insulate the active layer ACT from the gate electrode GE. The gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto. The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, the present invention is not limited thereto. A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be insulating layers for protecting components disposed below the first interlayer insulating layer 113 and components disposed below the second interlayer insulating layer 114, and each may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto. A capacitor electrode C is disposed on the first interlayer insulating layer 113. The capacitor electrode C can be disposed such that it overlaps with the gate electrode GE when the first interlayer insulating layer 113 is inserted therebetween. Therefore, the capacitor electrode C can maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period of time. The source electrode SE and drain electrode DE are disposed on the second interlayer insulating layer 114 and electrically connected to the active layer ACT. The source electrode SE and drain electrode DE can each be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, the invention is not limited thereto. Meanwhile, the arrangement of a first interlayer insulating layer 113 and a second interlayer insulating layer 114, i.e., a plurality of insulating layers, disposed between the gate electrode GE, the source electrode SE, and the drain electrode DE has been described in this invention. However, only a single insulating layer may be disposed between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, the invention is not limited thereto. Next, an auxiliary electrode BCNT is disposed on the gate insulating layer 112. The auxiliary electrode BCNT is an electrode configured to apply a voltage to the light-shielding layer LS disposed below the buffer layer 111. For example, the light-shielding layer LS can be electrically connected to other components disposed on the substrate 110 through the auxiliary electrode BCNT and receive voltage. The light-shielding layer LS, which receives voltage through the auxiliary electrode BCNT, does not operate as a floating gate, thereby minimizing or at least reducing the change in the critical voltage of the driving transistor DT caused by the floating light-shielding layer LS. A power line PL is disposed on the second interlayer insulating layer 114. The power line PL can be electrically connected to the light-emitting element ED together with the driving transistor DT, causing the light-emitting element ED to emit light. For example, the power line PL can be a low-potential power line for supplying a low-potential power supply voltage, or a high-potential power line for supplying a high-potential power supply voltage. However, the invention is not limited thereto. The power line PL can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, the invention is not limited thereto. An organic insulating layer 115 is disposed on the driving transistor DT and the power line PL. The organic insulating layer 115 can planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The organic insulating layer 115 can be configured as a single layer or multiple layers and is made of, for example, a photoresist or an acrylic organic material. However, the present invention is not limited thereto. A plurality of first reflective electrodes RE1 and a plurality of second reflective electrodes RE2, spaced apart from each other, are disposed on an organic insulating layer 115. The plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 can be used to electrically connect a plurality of light-emitting elements ED to a power line PL and a driving transistor DT, and also serve as reflectors, reflecting light emitted from the plurality of light-emitting elements ED toward the upper side or the lower side of the substrate 110. The plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 can each be made of a conductive material with excellent reflective properties, reflecting light emitted from the light-emitting elements ED toward the upper side. For example, the plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 can each be made of a metallic material with excellent reflective properties, such as aluminum (Al), silver (Ag), copper (Cu), palladium (Pd), or alloys thereof. However, the invention is not limited thereto. A plurality of first reflective electrodes RE1 can electrically connect the light-emitting element ED to the driving transistor DT. The plurality of first reflective electrodes RE1 can be connected to the source electrode SE or drain electrode DE of the driving transistor DT through contact holes formed in the organic insulating layer 115. Furthermore, the first reflective electrodes RE1 can be electrically connected to the second electrode 125 of the light-emitting element ED. A plurality of second reflective electrodes RE2 can be electrically connected to the power line PL and the light-emitting element ED. The plurality of second reflective electrodes RE2 can be electrically connected to the power line PL through contact holes formed in the organic insulating layer 115. Furthermore, the plurality of second reflective electrodes RE2 can be electrically connected to the common electrode CE through contact holes in the first planarization layer 116 and the second planarization layer 117. Therefore, the first electrode 124 and the first semiconductor layer 121 of the light-emitting element ED can be electrically connected to the power line PL through the plurality of second reflective electrodes RE2 and the common electrode CE. A light-emitting element ED is disposed on a first reflective electrode RE1 in each of the plurality of sub-pixels SP. The plurality of light-emitting elements ED can be elements configured to emit light using current, and include light-emitting elements configured to emit red, green, blue, etc. The plurality of light-emitting elements ED can achieve various colors of light, including white light, by using combinations of red, green, blue, etc. For example, each of the plurality of light-emitting elements ED can be a light-emitting diode (LED) or a micro LED. However, the present invention is not limited thereto. The plurality of light-emitting elements ED are light-emitting elements for displaying images to a user viewing the display panel PN on the front surface of the substrate 110. Light emitted from the plurality of light-emitting elements ED can propagate to the upper side of the substrate 110. At least a portion of the light emitted from the plurality of light-emitting elements ED can be reflected by the plurality of first reflective electrodes RE1 and the plurality of second reflective electrodes RE2 and propagate to the upper side of the substrate 110. A black matrix BM is disposed on the organic insulating layer 115 and between a plurality of light-emitting elements ED. The black matrix BM can be disposed to surround the periphery of the light-emitting element ED in each of the plurality of sub-pixels SP. The black matrix BM can block a portion of the light emitted from the light-emitting element ED and propagating to the adjacent sub-pixel SP, so that the colors of the light beams emitted from the plurality of sub-pixels SP do not mix together. The black matrix BM can guide the light emitted from the light-emitting element ED such that the light is extracted to the upper side of the substrate 110 and corresponds only to the area of ​​the sub-pixel SP on which the light-emitting element ED is disposed. Furthermore, the black matrix BM can block a portion of the light emitted from the light-emitting element ED and propagating to another adjacent sub-pixel SP, so that the colors of the light beams emitted from the plurality of sub-pixels SP and the colors of the light beams emitted from another adjacent sub-pixel SP do not mix together. A first planarization layer 116 and a second planarization layer 117 are disposed around a plurality of light-emitting elements ED. The first planarization layer 116 is disposed on a plurality of first reflective electrodes RE1 and a plurality of second reflective electrodes RE2, while the second planarization layer 117 is disposed on the first planarization layer 116. The first planarization layer 116 and the second planarization layer 117 may be disposed to fill the space between the black matrix BM and fix and protect the plurality of light-emitting elements ED. For example, the first planarization layer 116 and the second planarization layer 117 may each be configured as a single layer or multiple layers and made of photoresist or acrylic organic materials. However, the present invention is not limited thereto. A common electrode CE is disposed on the second planarization layer 117 and on the front surface of the substrate 110. The common electrode CE is an electrode for electrically connecting the power line PL and the plurality of light-emitting elements ED. The common electrode CE can be electrically connected to the plurality of second reflective electrodes RE2 through contact holes in the first planarization layer 116 and the second planarization layer 117. Therefore, the common electrode CE can be electrically connected to the power line PL through the plurality of second reflective electrodes RE2. Furthermore, the common electrode CE can be electrically connected to the first electrode 124 of each of the plurality of light-emitting elements ED through contact holes in the second planarization layer 117. The common electrode CE can be made of a transparent conductive material and transmits light emitted from the light-emitting element ED. Light emitted from the light-emitting element ED, which is disposed below the common electrode CE, can pass through the common electrode CE and propagate towards the upper side of the substrate 110. For example, the common electrode CE can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present invention is not limited thereto. The display device 100 according to an embodiment of the present invention can extract light emitted from the light-emitting element ED to the outside of the light-emitting element ED, thereby minimizing or at least reducing the light trapped inside the light-emitting element ED that is not extracted. A typical light-emitting element has a planar shape comprising a polygon containing straight lines, such as a quadrilateral planar shape. In this case, the angle of incidence of light entering the side surface of the light-emitting element in the in-plane direction is necessarily greater than the angle of total internal reflection of light propagating towards the outside of the light-emitting element. Therefore, there is a problem of light loss because total internal reflection within the light-emitting element traps the light, preventing it from being extracted from the inside of the light-emitting element to the outside. Therefore, in the light-emitting element ED according to an embodiment of the present invention, the planar shapes of the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123 each include a plurality of first sides SI1 having a straight line shape and a plurality of second sides SI2 having a curved shape, and the plurality of first sides SI1 and the plurality of second sides SI2 can be alternately arranged. In this case, the plurality of first sides SI1 can be arranged facing each other, and the plurality of second sides SI2 can be arranged facing each other. Therefore, the planar shape of the light-emitting element (ED) includes both straight lines and curves, allowing light entering the ED to be reflected at random reflection angles. This random reflection of light emitted from the ED minimizes the amount of unextracted light trapped within the element, thereby improving the efficiency of external light extraction. Figure 9 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present invention. Except for the reflective layer RL and the plurality of first reflective electrodes RE1a, the display device 200 in Figure 9 is substantially the same in configuration as the display device 100 in Figure 8. Therefore, repeated descriptions of identical components will be omitted. Referring to FIG9, a first planarization layer 116 and a second planarization layer 117 may be disposed to surround the side surface of the light-emitting element ED. A first planarization layer 116 may be disposed on an organic insulating layer 115. The first planarization layer 116 may include an opening 116a in which a light-emitting element ED is disposed. The first planarization layer 116 may have a sloped surface inclined around the light-emitting element ED. The opening 116a may have a sloped surface. The first planarization layer 116 may be configured as a single layer or multiple layers and made of, for example, a photoresist or an acrylic organic material. However, the invention is not limited thereto. A first reflective electrode RE1a and a reflective layer RL may be disposed on the first planarization layer 116. The reflective layer RL may be disposed on a portion of the organic insulating layer 115 opened by the opening portion 116a and electrically connected to the second electrode 125 of the light-emitting element ED. The reflective layer RL may be disposed on the inclined surface of the first planarization layer 116. The reflective layer RL may be disposed to extend from the portion of the organic insulating layer 115 opened by the opening portion 116a to the inclined surface of the first planarization layer 116 and a portion of the first planarization layer 116. The first reflective electrode RE1a may be disposed on the first planarization layer 116, integrated with the reflective layer RL, and configured to electrically connect the light-emitting element ED to the driving transistor DT. The first reflective electrode RE1a may be connected to the source electrode SE or drain electrode DE of the driving transistor DT through contact holes formed in the organic insulating layer 115 and the first planarization layer 116. The second reflective electrode RE2 can be disposed on the organic insulating layer 115. The second reflective electrode RE2 can electrically connect a plurality of light-emitting elements ED to the power line PL and the driving transistor DT. The second reflective electrode RE2 can electrically connect the power line PL and the light-emitting elements ED. The second reflective electrode RE2 can be electrically connected to the power line PL through contact holes formed in the organic insulating layer 115. Furthermore, the second reflective electrode RE2 can be electrically connected to the common electrode CE through contact holes in the first planarization layer 116 and the second planarization layer 117. Therefore, the first electrode 124 and the first semiconductor layer 121 of the light-emitting element ED can be electrically connected to the power line PL through the second reflective electrode RE2 and the common electrode CE. The first reflective electrode RE1a and the second reflective electrode RE2 can electrically connect a plurality of light-emitting elements ED to the power line PL and the driving transistor DT. The reflective layer RL, the first reflective electrode RE1a and the second reflective electrode RE2 can be used as a reflector to reflect light emitted from the plurality of light-emitting elements ED toward the upper side of the substrate 110. The reflective layer RL, the first reflective electrode RE1a, and the second reflective electrode RE2 can each be made of a conductive material with excellent reflective properties, and reflect the light emitted from the light-emitting element ED upwards. For example, a plurality of reflective layers RL, a plurality of first reflective electrodes RE1a, and a plurality of second reflective electrodes RE2 can each be made of a metallic material with excellent reflective properties, such as aluminum (Al), silver (Ag), copper (Cu), palladium (Pd), or alloys thereof. However, the invention is not limited thereto. The first reflective electrode RE1a and the second reflective electrode RE2 can be referred to as reflective layers because the first reflective electrode RE1a and the second reflective electrode RE2 reflect the light emitted from the light-emitting element ED upwards. The second planarization layer 117 may be disposed on the first planarization layer 116, the reflective layer RL, and the first reflective electrode RE1a. The second planarization layer 117 may be disposed on the first planarization layer 116 and configured to fill the opening portion 116a of the first planarization layer 116. The first planarization layer 116 and the second planarization layer 117 may be configured to fill the space between the black matrix BM and fix and protect the plurality of light-emitting elements ED. In a display device 200 according to another embodiment of the present invention, the planar shape of the light-emitting element ED includes straight lines and curves, such that light entering the light-emitting element ED is reflected at random reflection angles, thereby minimizing or at least reducing the light trapped inside the light-emitting element that is not extracted, thereby improving the external light extraction efficiency. According to another embodiment of the present invention, the display device 200 can extract light emitted in the direction toward the side surface of the light-emitting element ED in the direction toward the front surface of the display device 200 through the reflective layer RL. Light emitted from the light-emitting element ED may be extracted not only in one direction but also toward the side surface. In this case, the light extracted toward the side surface of the light-emitting element ED will be trapped in the display device 200 and cannot be extracted in the direction toward the front surface of the display device 200, resulting in a decrease in light extraction efficiency. Therefore, in the display device 200 according to another embodiment of the present invention, the opening portion 116a in which the light-emitting element ED is disposed may be provided in the first planarization layer 116, and an inclined surface may be formed in the opening portion 116a. The reflective layer RL may be provided on the upper part of the organic insulating layer 115 exposed through the opening portion 116a of the first planarization layer 116, and the reflective layer RL may be provided on the inclined surface of the first planarization layer 116. Therefore, the reflective layer RL is disposed at the lower part of the light-emitting element ED and at a position surrounding the side surface of the light-emitting element ED, so that light emitted in the direction of the side surface of the light-emitting element ED can be extracted in the direction of the front surface of the display device 200, thereby improving the efficiency of extracting light to the outside. In the following description, a display device comprising a reflective layer configured to surround a light-emitting element will be described in more detail with reference to Figures 10A to 13. Figure 10A is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in Figure 2. Figure 10B is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in Figure 3. Figure 10C is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in Figure 4. Figure 11 is a plan view schematically showing the planar shapes of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention. Figure 12 is a plan view schematically showing another example of the planar shapes of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention. Figure 13 is a plan view schematically showing yet another example of the planar shapes of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention. For ease of description, Figures 11 to 13 only show the light-emitting element ED and the reflective layer RL among the various constituent elements of the display device 200. Referring to Figures 2 and 10A, in the far-field emission pattern of the light-emitting element ED shown in Figure 2, the amount of light can be uniformly distributed along the straight shape of the first side SI1 with a straight shape, while the amount of light can be concentrated in the direction of the emission azimuth angle φ of 35° to 45° on the second side SI2 with a curved shape (e.g., the direction of 40°). Referring to Figures 3 and 10B, in the far-field emission pattern of the light-emitting element ED shown in Figure 3, the amount of light can be uniformly distributed along the straight shape of the first side SI1, which has a straight shape, while the amount of light can be concentrated in the direction of the emission azimuth angle φ of 40° to 50° on the second side SI2, which has a curved shape (e.g., the direction of 45°). Referring to Figures 4 and 10C, in the far-field emission pattern of the light-emitting element ED shown in Figure 4, the amount of light can be uniformly distributed along the straight shape of the first side SI1 with a straight shape, while the amount of light can be concentrated in the direction of the emission azimuth angle φ of 45° to 55° on the second side SI2 with a curved shape (e.g., the direction of 50°). In a display device 200 according to another embodiment of the present invention, the planar shape of the light-emitting element ED includes straight lines and curves. The amount of light emitted on the first side SI1 of the planar shape of the light-emitting element ED, which has a straight line shape, is uniform, while the amount of light emitted on the second side SI2 of the planar shape of the light-emitting element ED, which has a curved shape, is concentrated at a specific angle. Therefore, similar to the shape of a commonly used reflective layer, when the reflective layer surrounds the light-emitting element and the planar shape of the reflective layer is formed with equal intervals and has the same shape as the planar shape of the light-emitting element, as shown in Figures 10A to 10C, uneven brightness may occur because the amount of light emitted varies with the azimuth angle. Therefore, referring to Figures 11 to 13, in a display device 200 according to another embodiment of the present invention, a notch N is formed at a position in the direction of the azimuth angle where the light emission is concentrated in the planar shape of the reflective layer RL surrounding the light-emitting element ED, so that the light in the direction of the azimuth angle can be dispersed, thereby improving the brightness uniformity and extracting light. In a display device 200 according to another embodiment of the present invention, the planar shape of the reflective layer RL surrounding the light-emitting element ED may include a plurality of third sides SI3, a plurality of fourth sides SI4, and a plurality of fifth sides SI5. When the planar shape of the reflective layer RL includes a plurality of third sides SI3, a plurality of fourth sides SI4, and a plurality of fifth sides SI5, the plurality of third sides SI3 may be positioned facing each other, and the plurality of fourth sides SI4 may be positioned facing each other. In this case, the plurality of fifth sides SI5 may be provided to connect the plurality of third sides SI3 and the plurality of fourth sides SI4. In this case, the plurality of fifth sides SI5 may be positioned to surround the curved second side SI2 of the light-emitting element ED. Referring also to Figures 10A to 10C, in a display device 200 according to another embodiment of the present invention, the light emission of the light-emitting element ED is uniform in the direction of the first side SI1, which has a straight shape, and the light emission is concentrated in a specific direction toward the second side SI2, which has a curved shape. For example, even if the light intensity of the light emission at the two opposite ends of the first side SI1 is greater than the light emission at the angle θ of the maximum light emission point emitting the maximum amount of light from the second side SI2, the emission angle of the first side SI1 is dispersed, so the far field can be uniformly distributed. Therefore, even without a notch, the light intensity can be uniformly distributed in the region of the first side SI1. Therefore, in a display device 200 according to another embodiment of the present invention, a notch N contained in the planar shape of the reflective layer RL may be provided in at least one of the plurality of fifth sides SI5 surrounding the second side SI2 of the light-emitting element ED. In the planar shape of the reflective layer RL of the display device 200 according to another embodiment of the present invention, the notch N can be positioned on a straight line of the maximum emission azimuth angle (i.e., emission vector) derived from the far-field pattern, based on the angle of the maximum emission point at the location of the maximum emission point derived from the near-field emission pattern of the light-emitting element ED. Specifically, the notch N can be configured such that the center of the notch N is positioned on a straight line of the maximum emission azimuth angle derived from the far-field pattern, based on the angle of the maximum emission point derived from the near-field emission pattern of the light-emitting element ED. For example, the shape of the notch N may include a groove having a curved surface recessed along the direction of the light-emitting element ED. However, the present invention is not limited thereto. Referring to Figures 2 and 11, the angle θ of the maximum emission point derived from the near-field emission pattern of the light-emitting element ED shown in Figure 2 is 0°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light-emitting element ED in Figure 10A is 40°. As shown in Figure 11, the position of the notch N contained in the planar shape of the reflective layer RL can be formed based on the angle θ of the maximum emission point at a position that is in a straight line with respect to the emission azimuth angle φ (i.e., in the 40° direction, with the 0° direction of the second side SI2 at the center of the light-emitting element ED as a reference). For example, the normal vector of the notch N contained in the planar shape of the reflective layer RL is 180° relative to the maximum emission azimuth angle φ of the light-emitting element ED. Referring to Figures 3 and 12, the angle θ of the maximum emission point derived from the near-field emission pattern of the light-emitting element ED shown in Figure 3 is 45°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light-emitting element ED in Figure 10B is 45°. As shown in Figure 12, the position of the notch N contained in the planar shape of the reflective layer RL can be formed based on the angle θ of the maximum emission point at a position that is straight relative to the emission azimuth angle φ (i.e., in the 45° direction, with the 45° direction of the second side SI2 at the center of the light-emitting element ED as a reference). Referring to Figures 4 and 13, the angle θ of the maximum emission point derived from the near-field emission pattern of the light-emitting element ED shown in Figure 4 is 48°, and the maximum emission azimuth angle φ derived from the far-field pattern of the second light-emitting element ED in Figure 10C is 50°. As shown in Figure 13, the position of the notch N contained in the planar shape of the reflective layer RL can be formed based on the angle θ of the maximum emission point at a position that is straight relative to the emission azimuth angle φ (i.e., in the 50° direction, with the 48° direction of the second side SI2 at the center of the light-emitting element ED as a reference). In a display device 200 according to another embodiment of the present invention, a notch N is formed at a position in the azimuth direction of the light emission concentration in the planar shape of the reflective layer RL surrounding the light emission element ED, such that the light from the notch N in the azimuth direction in the region of concentrated light emission is dispersed, thereby improving brightness uniformity and extracting light. In a display device 200 according to another embodiment of the present invention, the shape and size of the notch N can be used without limitation, and the shape and degree of light emission dispersion can be adjusted by adjusting the size and shape of the notch N and the angle of the inclined surface at the periphery of the reflective layer RL in the light-emitting element ED. In a display device 200 according to another embodiment of the present invention, light extraction can be improved as the spacing between the light-emitting element ED and the notch N contained in the planar shape of the reflective layer RL decreases. However, the present invention is not limited thereto. The spacing can be adjusted to take into account the margin of the transfer process. In a display device 200 according to another embodiment of the present invention, the planar shape of the light-emitting element ED includes straight lines and curves, such that light entering the light-emitting element ED is reflected at random reflection angles, thereby minimizing or at least reducing the light trapped inside the light-emitting element that is not extracted, thereby improving the external light extraction efficiency. In a display device 200 according to another embodiment of the present invention, a reflective layer RL is provided to surround the lower part of the light-emitting element ED and the side surface of the light-emitting element ED, such that light emitted toward the side surface of the light-emitting element ED can be extracted in the direction toward the front surface of the display device 200, thereby improving the efficiency of extracting light to the outside. In a display device 200 according to another embodiment of the present invention, a notch N is formed at a position in the azimuth direction of the light emission concentration in the planar shape of the reflective layer RL surrounding the light-emitting element ED. In the region of concentrated light emission, the notch N will disperse the light in the azimuth direction, which can improve light extraction efficiency and brightness uniformity. Figure 14 is a cross-sectional view of a sub-pixel of a display device according to yet another embodiment of the present invention. Except for the first planarization layer 316 and the second planarization layer 317, the display device 300 in Figure 14 is substantially the same in configuration as the display device 100 in Figure 8. Therefore, repeated descriptions of identical components will be omitted. Referring to FIG14, a first planarization layer 316 and a second planarization layer 317 are disposed to surround a plurality of light-emitting elements ED. The first planarization layer 316 is disposed to surround the plurality of light-emitting elements ED, while the second planarization layer 317 is disposed to surround the first planarization layer 316. The first planarization layer 316 and the second planarization layer 317 may be disposed to surround the plurality of light-emitting elements ED. The first planarization layer 316 and the second planarization layer 317 may be disposed to fill the space between the black matrix BM and to fix and protect the plurality of light-emitting elements ED. For example, the first planarization layer 316 and the second planarization layer 317 may each be configured as a single layer or multiple layers and made of photoresist or acrylic organic materials. However, the present invention is not limited thereto. At least one of the first planarization layer 316 and the second planarization layer 317 may contain scattering particles P. The scattering particles P may be dispersed and disposed in the first planarization layer 316 and the second planarization layer 317. The scattering particles P may be made of a material that irregularly reflects or scatters light. For example, the scattering particles P may be nanoparticles made of a material containing titanium (Ti). For example, the scattering particles P may be particles having a nanometer (nm) scale and formed through a sol-gel process. However, the invention is not limited thereto. According to another embodiment of the present invention, the display device 300 allows light emitted towards the side surface of the light-emitting element to be extracted in the direction towards the front surface of the display device 200. Light emitted from the light-emitting element may be extracted not only in one direction but also towards the side surface. In this case, the light extracted towards the side surface of the light-emitting element becomes trapped within the display device 200 and cannot be extracted in the direction towards the front surface of the display device, resulting in poor light extraction efficiency. Therefore, in the display device 300 according to another embodiment of the present invention, a first planarization layer 316 and a second planarization layer 317 may be disposed around a plurality of light-emitting elements ED. The first planarization layer 316 and the second planarization layer 317 may contain scattering particles P made of a material that irregularly reflects or scatters light. Therefore, the scattering particles P are contained in the first planarization layer 316 and the second planarization layer 317 disposed around the plurality of light-emitting elements ED, such that light emitted towards the side surface of the light-emitting element ED can be extracted in the direction towards the front surface of the display device 300, thereby improving the efficiency of extracting light to the outside. Exemplary embodiments of the present invention may also be described below. According to one aspect of the present invention, a light-emitting element includes: a first semiconductor layer; a second semiconductor layer opposite to the first semiconductor layer; and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer and the light-emitting layer each include at least one first side having a straight line shape and at least one second side having a curved shape. In each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, one end of the first side may be connected to one end of the second side. The second side can have an arc shape. Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer can be a semi-circular shape. Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer can be a "D" shape formed by cutting a portion of a circle with a straight line. The planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer each include a plurality of first sides and a plurality of second sides, and the plurality of first sides face each other, while the plurality of second sides may face each other. The first and second sides can be set alternately. The corner regions of each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer may have a circular shape. Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer can be in the shape of a Bunimovich stadium. Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer can be in the shape of a Sinai billiard table. The light-emitting element may further include: a first electrode disposed on a first semiconductor layer; and a second electrode disposed opposite to the first electrode and below the second semiconductor layer. According to another aspect of the present invention, the display device includes: a substrate comprising a plurality of sub-pixels; a plurality of transistors disposed on the substrate; and a light-emitting element disposed in each of the plurality of sub-pixels on the substrate. The light-emitting element may further include: a planarization layer disposed on a plurality of transistors and configured to surround a side surface of the light-emitting element; and a reflective layer disposed on the planarization layer and configured to surround a side surface of the light-emitting element. The light-emitting element may include: a first semiconductor layer; a second semiconductor layer opposite to the first semiconductor layer; and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer and the light-emitting layer each include at least one first side having a straight line shape and at least one second side having a curved shape, and the planar shape of the reflective layer may include a plurality of third sides, a plurality of fourth sides and a plurality of fifth sides, the plurality of third sides facing each other, the plurality of fourth sides facing each other, and the plurality of fifth sides connecting the plurality of third sides and the plurality of fourth sides. A plurality of fifth sides may be positioned to surround a second side, the planar shape of the reflective layer may include a notch disposed on at least one of the plurality of fifth sides, and the display device may include a notch recessed along the direction of the light-emitting element. The light-emitting element may further include a planarization layer disposed on a plurality of transistors and configured to surround the side surface of the light-emitting element, the planarization layer may contain scattering particles. Although exemplary embodiments of the invention have been described in detail with reference to the accompanying drawings, the invention is not limited thereto and may be practiced in many different forms without departing from the inventive concept. Therefore, exemplary embodiments of the invention are provided for illustrative purposes only and are not intended to limit the inventive concept. The scope of the inventive concept is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the invention. The scope of protection of the invention should be interpreted based on the appended claims, and all inventive concepts within their equivalent scope should be interpreted as falling within the scope of the invention. This application claims priority to Korean Patent Application No. 10-2024-0028058, filed on February 27, 2024, and Korean Patent Application No. 10-2024-0136522, filed on October 8, 2024, both of which are incorporated herein by reference in their entirety. 100, 200, 300: Display device; 110: Substrate; 111: Buffer layer; 112: Gate insulating layer; 113: First interlayer insulating layer; 114: Second interlayer insulating layer; 115: Organic insulating layer; 116, 316: First planarization layer; 116a: Opening portion; 117, 317: Second planarization layer; 121: First semiconductor layer; 122: Light-emitting layer; 123: Second semiconductor layer; 124: First electrode; 125: Second electrode; 126: Encapsulation layer; AA: Display area; ACT: Active layer; BM: Black matrix; BCNT: Auxiliary electrode; C: Capacitor electrode; CE: Common electrode; D: Height; DD: Data driver; DT: Driving transistor; DL: Data line; DE: Drain electrode; DT: Driving transistor; ED: Light-emitting element; GD: Gate driver; GE: Gate electrode; L: Length; LS: Light-shielding layer; N: Notch; NA: Non-display area; P: Scattering particles; PN: Display panel; PL: Power line; r: Radius; RL: Reflective layer; RE1, RE1a: First reflective electrode; RE2: Second reflective electrode; SI1: First side; SI2: Second side; SI3: Third side; SI4: Fourth side; SI5: Fifth side; SP: Sub-pixel; SL: Scan line; SE: Source electrode; TC: Timing controller; φ: Azimuth angle; θ: Angle The above and other features, characteristics, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG1 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present invention; FIG2 is a plan view schematically showing the planar shape of a light-emitting element according to an embodiment of the present invention; FIG3 is a plan view schematically showing another example of the planar shape of a light-emitting element according to an embodiment of the present invention; FIG4 is a plan view schematically showing yet another example of the planar shape of a light-emitting element according to an embodiment of the present invention; FIG5 is a plan view schematically showing yet another example of the planar shape of a light-emitting element according to an embodiment of the present invention; FIGS. 6A to 6I are plan views for comparing and explaining the effects of the planar shape of a light-emitting element according to an embodiment of the present invention; FIG7 is a schematic configuration diagram of a display device according to an embodiment of the present invention; FIG8 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present invention; FIG9 is a cross-sectional view of a sub-pixel of a display device according to another embodiment of the present invention; FIG10A is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in FIG2; FIG10B is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in FIG3. Figure 10C is a view showing the simulation results of the far-field emission pattern of the light-emitting element shown in Figure 4; Figure 11 is a plan view schematically showing the planar shape of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention; Figure 12 is a plan view schematically showing another example of the planar shape of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention; Figure 13 is a plan view schematically showing yet another example of the planar shape of the light-emitting element and the reflective layer of a display device according to another embodiment of the present invention; and Figure 14 is a cross-sectional view of a sub-pixel of a display device according to yet another embodiment of the present invention. ED: Light-emitting element SI1: First side SI2: Second side

Claims

1. A light-emitting element, comprising: A first semiconductor layer; A second semiconductor layer, opposite to the first semiconductor layer; And a light-emitting layer is located between the first semiconductor layer and the second semiconductor layer, wherein the planar shapes of the first semiconductor layer, the second semiconductor layer and the light-emitting layer each include at least one first side having a straight line shape and at least one second side having a curved shape, and wherein the first semiconductor layer, the second semiconductor layer and the light-emitting layer have the same planar shape.

2. The light-emitting element as described in claim 1, wherein, In each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer, one end of the at least one first side is connected to one end of the at least one second side.

3. The light-emitting element as described in claim 1, wherein, At least one of the second sides has an arc shape.

4. The light-emitting element as described in claim 2, wherein, Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer is semi-circular.

5. The light-emitting element as described in claim 2, wherein, Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer is a D-shape formed by straight-line cutting a portion of a circle.

6. The light-emitting element as described in claim 1, wherein, The at least one first edge comprises a plurality of first edges, and the at least one second edge comprises a plurality of second edges, and the plurality of first edges face each other, and the plurality of second edges face each other.

7. The light-emitting element as described in claim 6, wherein, The plurality of first sides are alternately set with the plurality of second sides.

8. The light-emitting element as described in claim 6, wherein, The corner regions of each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer are circular.

9. The light-emitting element as described in claim 6, wherein, The planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer are each in the shape of a Bunimovich stadium.

10. The light-emitting element as described in claim 6, wherein, Each of the planar shapes of the first semiconductor layer, the second semiconductor layer, and the light-emitting layer is in the shape of a Sinai billiard table.

11. The light-emitting element as described in claim 1, further comprising: A first electrode is located on the first semiconductor layer; And a second electrode, which is opposite to the first electrode and located below the second semiconductor layer.

12. A display device, comprising: A substrate comprising a plurality of sub-pixels; a plurality of transistors located on the substrate; And a light-emitting element as described in claim 1, wherein the light-emitting element is disposed in each of the plurality of sub-pixels on the substrate.

13. The display device as described in claim 12, further comprising: A planarization layer is located on the plurality of transistors, and the planarization layer surrounds one side surface of the light-emitting element; And a reflective layer, located on the planarization layer, the reflective layer surrounding the side surface of the light-emitting element.

14. The display device as claimed in claim 13, wherein, The planar shape of the reflective layer includes a plurality of third sides, a plurality of fourth sides, and a plurality of fifth sides, wherein the plurality of third sides face each other, the plurality of fourth sides face each other, and the plurality of fifth sides connect the plurality of third sides to the plurality of fourth sides.

15. The display device as described in claim 14, wherein, The plurality of fifth sides are positioned around the at least one second side, wherein the planar shape of the reflective layer includes a notch located on at least one of the plurality of fifth sides.

16. The display device as described in claim 15, wherein, The notch is recessed along the direction of the light-emitting element.

17. The display device as claimed in claim 16, wherein, The notch is positioned on a straight line derived from the maximum emission azimuth angle derived from the far-field pattern, based on the angle of the maximum emission point at the location of the maximum emission quantity derived from the near-field emission pattern of the light-emitting element.

18. The display device as described in claim 12, further comprising: A planarization layer is located on the plurality of transistors, the planarization layer surrounds one side surface of the light-emitting element, wherein the planarization layer contains scattering particles.

19. A display device, comprising: A substrate comprising a plurality of sub-pixels; a plurality of transistors located on the substrate; The light-emitting element as described in claim 1 is disposed in each of the plurality of sub-pixels on the substrate; And a planarization layer, located on the plurality of transistors and surrounding one side surface of the light-emitting element.

20. The display device as claimed in claim 19, further comprising: A reflective electrode is located below the planarization layer.

21. The display device as claimed in claim 19, further comprising: A black matrix surrounds the periphery of the light-emitting element.

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