Memory devices and methods for manufacturing the same

Abstract

Embodiments of this disclosure provide a memory device including a first portion and a second portion of a memory array. The first portion includes a plurality of first read-only memory cells, each of which includes a first transistor having a first conductivity type and electrically coupled to a first word line and a first bit line. The second portion includes a plurality of second read-only memory cells, each of which includes a second transistor having a second conductivity type and electrically coupled to a second word line and a second bit line. The first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The semiconductor industry is experiencing rapid growth due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. [Summary of the Invention]

[0003] None

Implementation Method

[0005] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, this document may use spatial relative terms such as "below," "under," "lower," "above," "upper," etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0007] A read-only memory (ROM) array is a semiconductor memory chip array in which data is permanently stored. A ROM array consists of multiple ROM cells, each including a transistor in an "on" or "off" state. Each ROM cell stores data bits reflecting the on or off state (e.g., binary). In the prior art, to improve performance, the ROM cells (or the corresponding transistors) of a ROM array are typically formed with the same conductivity type (e.g., n-type). However, forming all n-type transistors on a single substrate presents various processing or manufacturing problems, such as uneven distribution of n-type and p-type patterns across the substrate, which adversely affects polishing. Therefore, existing ROM devices / arrays are not entirely satisfactory in certain aspects.

[0008] This disclosure provides various embodiments of a memory device (e.g., a memory array), wherein the memory device includes a plurality of unique memory cells having a uniform n-type / p-type distribution. For example, a first group of unique memory cells may be formed as n-type, and a second group of unique memory cells may be formed as p-type, wherein the first group of unique memory cells and the second group of unique memory cells may be uniformly distributed on a substrate. In one embodiment, some n-type unique memory cells (forming a corresponding subset of the first group) and some p-type unique memory cells (forming a corresponding subset of the second group) may be arranged alternately along a first lateral direction, wherein the first lateral direction may be the length direction of the word line (WL) of the memory array. In another embodiment, all n-type unique memory cells (forming the first group) and all p-type unique memory cells (forming the second group) may be arranged adjacent to each other along the first lateral direction (word line direction). Furthermore, input / output (I / O) circuits of the same conductivity type and corresponding number can be formed, wherein the I / O circuits are adjacent to each of the first group (n-type) unique memory cells or the second group (p-type) unique memory cells along a second lateral direction perpendicular to the first lateral direction. When the unique memory cells have this configuration, the unique memory cells of the memory device can avoid the aforementioned manufacturing problems, which is beneficial to improving the manufacturing yield of the memory device.

[0009] Figure 1 is a block diagram illustrating an exemplary memory device 100 (or memory circuitry) according to various embodiments. The memory device 100 may include a storage device for connection to an external host device (not shown). It should be understood that, as shown in Figure 1, the memory device 100 is a simplified example, and therefore the memory device 100 may include any of a variety of other components while still remaining within the scope of this disclosure.

[0010] As shown in the example of Figure 1, the memory device 100 includes a memory array 102, word line circuitry 104, I / O circuitry 106, and a controller 108 (or logic control circuitry). In some embodiments, the controller 108 may be operatively coupled to a memory controller (not shown) via a bus, wherein the bus may transmit and / or receive data based on an interface. The memory device 100 is a memory for storing data. The memory array 102 includes a plurality of memory subarrays or memory libraries. Each memory subarray (or memory library) includes a plurality of memory cells. In some embodiments, each memory cell may include a read-only memory cell, wherein the read-only memory cell (e.g., the read-only memory cell 200 of Figure 2) may be formed by one or more transistors. The memory array 102 may be formed as an array having a plurality of columns and a plurality of rows (e.g., two-dimensional or three-dimensional), with each read-only memory cell disposed at the intersection of a corresponding column and a corresponding row. Furthermore, the memory array 102 may include a plurality of word lines arranged along columns and a plurality of bit lines (BLs) arranged along rows. However, it should be understood that the memory array 102 may include a plurality of any other memory cells, while still remaining within the scope of this disclosure.

[0011] The controller 108 may provide address information (ADD) to the word line circuit 104 and / or the I / O circuit 106. ADD includes, for example, a row address (RAd) and a column address (CAd). In some embodiments, the column address and row address may be used to select word lines and bit lines, respectively. For example, the word line circuit 104 may include a word line (or column) decoder and one or more column multiplexers, and the I / O circuit 106 may include a bit line keeper circuit, a bit line pre-charge circuit, a bit line (or row) decoder, one or more row multiplexers, an output latch, a design for testability / test (DFT) circuit, and a buffer.

[0012] The word line circuit 104 may receive column addresses from the controller 108. Based on the column address, the word line circuit 104 (which may include or integrate drivers (circuit)) accesses the corresponding word line. The word line circuit 104 may apply a generated voltage to the corresponding access line (e.g., word line) based on, for example, the column address. For example, the word line circuit 104 may select one of the word lines through three decoding stages: pre-decoding, decoding, and post-decoding. The pre-decoding stage determines which of the potential hierarchical memory blocks contains data and re-encodes the address bits to reduce the fanout of the word line decoder for a single block. One or more word line decoders will respond with the address. Then, the post-decoding stage may select a single word line. In some embodiments, the word line circuit 104 may be implemented by a set of 2M logic gates (e.g., NAND gates, NOR gates, etc.) arranged in a regular, dense manner.

[0013] I / O circuit 106 may receive row addresses from controller 108. Based on the row address, I / O circuit 106 (which may include or integrate a column decoder) accesses the corresponding bit line. For example, before accessing (reading) one of the unique memory cells via the corresponding bit line, the bit line precharge circuit of I / O circuit 106 may precharge the bit lines of memory array 102 to a logic high state, and the logic high state may be maintained by bit line hold circuitry. Then, one of the bit lines is selected based on the row address. Simultaneously or subsequently with the selection of the corresponding word line based on the column address, at least one unique memory cell of memory array 102 may be selected based on both the column address and the row address, and the logic state of the selected unique memory cell may be read by I / O circuit 106. For example, the I / O circuit 106 can receive a small signal from the selected unique memory cell and amplify the small signal into a large signal, thereby identifying the logical state of the data stored in the selected unique memory cell.

[0014] In some embodiments, the memory array 102, word line circuit 104, I / O circuit 106, and controller 108 may be arranged in the configuration shown in Figure 1. For example, the word line circuit 104 may be arranged adjacent to the memory array 102 along the Y direction, where the Y direction may be the length direction of the word lines of the memory array 102, and the I / O circuit 106 may be arranged adjacent to the memory array 102 along the X direction, where the X direction may be the length direction of the bit lines of the memory array 102. Furthermore, the unique memory cells of the memory array 102 may include a first group of n-type unique memory cells and a second group of p-type unique memory cells. Each n-type unique memory cell has a corresponding portion of the I / O circuit 106 formed with the same conductivity type (n-type) and is arranged adjacent to each other along the X direction. Each p-type unique memory cell has a corresponding portion of the I / O circuit 106 formed with the same conductivity type (p-type) and is arranged adjacent to each other along the X direction, which will be discussed below.

[0015] Figure 2 illustrates an exemplary circuit diagram of a single unique memory cell 200 according to some embodiments. A plurality of such unique memory cells 200 may be configured as the memory array 102 shown in Figure 1. Although the unique memory cell 200 of Figure 2 includes a transistor, it should be understood that the circuit diagram of Figure 2 is for illustrative purposes only and is not intended to limit the scope of this disclosure. Therefore, the unique memory cell 200 shown in Figure 2 may include any of a variety of other components (e.g., one or more additional transistors) while still remaining within the scope of this disclosure.

[0016] As shown in the figure, the memory cell 200 includes a transistor 210, wherein the transistor 210 has a gate, a first source / drain, and a second source / drain. The gate is connected to a word line, the drain is connected to a bit line, and the source is selectively connected to a power supply voltage, such as ground (VSS). In some embodiments, the memory cell 200 being in a logic "1" or "0" state may depend on whether the second source / drain of the transistor 210 is connected to ground. For example, when the second source / drain is connected to ground, the memory cell 200 presents logic 1; and when the second source / drain is disconnected from ground, the memory cell 200 presents logic 0. In some other embodiments (not shown in Figure 2), the memory cell 200 being in a logic "1" or "0" state may depend on whether the first source / drain of the transistor 210 is connected to a bit line. For example, when the first source / drain terminal is connected to the bit line, only memory cell 200 displays logic 1; and when the first source / drain terminal is disconnected from the bit line, only memory cell 200 displays logic 0.

[0017] Figures 3, 4, and 5 illustrate various layouts or configurations of the unique memory cells of the memory array 102 according to various embodiments, including configuration 300, configuration 400, and configuration 500. Generally, according to various embodiments of the present disclosure, each of configurations 300 to 500 includes a separate layout for forming a plurality of n-type unique memory cells and a plurality of p-type unique memory cells along the substrate. It should be understood that the configurations in Figures 3 to 5 are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0018] In Figure 3, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, 102H, and 102I, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, 106H, and 106I. In some embodiments, I / O portions 106A to 106I (e.g., physically) are respectively arranged adjacent to array portions 102A to 102I along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the unique memory cell formed in array portion 102A has the same conductivity type as the transistor formed in I / O portion 106A. Furthermore, each unique memory cell formed in array portion 102A to array portion 102I is electrically coupled to a corresponding one of the aligned I / O portions 106A to I / O portion 106I via at least one bit line (e.g., bit line BL A), and electrically coupled to word line circuit 104 via at least one word line (e.g., word line WLA). The bit line may extend along the X direction, and the word line may extend along the Y direction.

[0019] In some embodiments, the unique memory cells in array portions 102A to 102C and the transistors in the corresponding I / O portions 106A to 106C are all formed in n-type; the unique memory cells in array portions 102D to 102F and the transistors in the corresponding I / O portions 106D to 106F are all formed in p-type; and the unique memory cells in array portions 102G to 102I and the transistors in the corresponding I / O portions 106G to 106I are all formed in n-type. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102I and the controller 108 (along the Y direction) adjacent to the I / O portion 106I are all formed in n-type. In other words, the corresponding portions of the memory array 102 and I / O circuit 106, which are arranged adjacent to the character line circuit 104 and the controller 108, may have transistors formed with the same conductivity type.

[0020] Although configuration 300 shows only one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 300 can be generalized to include a plurality of memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be disposed on the opposite side of I / O circuitry 106 shown in Figure 3, relative to memory array 102. Therefore, the corresponding I / O circuitry of the other memory array may be disposed on the opposite side of the other memory array, relative to I / O circuitry 106 shown in Figure 3.

[0021] In Figure 4, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, and 106H. In some embodiments, I / O portions 106A to 106H (e.g., physically) are respectively arranged adjacent to array portions 102A to 102H along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the unique memory cell formed in array portion 102A has the same conductivity type as the transistor formed in I / O portion 106A. Furthermore, the unique memory cell formed in each array portion 102A to array portion 102I is electrically coupled to a corresponding one of the aligned I / O portions 106A to I / O portion 106I via at least one bit line (e.g., bit line BL A), and electrically coupled to word line circuit 104 via at least one word line (e.g., word line WLA). The bit line may extend along the X direction, and the word line may extend along the Y direction.

[0022] In some embodiments, the individual memory cells in array portions 102A to 102D and the transistors in the corresponding I / O portions 106A to 106D are all formed as p-type transistors; while the individual memory cells in array portions 102E to 102H and the transistors in the corresponding I / O portions 106E to 106H are all formed as n-type transistors. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102H and the controller 108 (along the Y direction) adjacent to the I / O portion 106H are formed as n-type transistors. In other words, the corresponding portions of the memory array 102 and the I / O circuit 106 adjacent to the word line circuit 104 and the controller 108 may have the same conductivity type.

[0023] Although configuration 400 shows only one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 400 can be generalized to include a plurality of memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be disposed on the other side of I / O circuitry 106 shown in Figure 4, relative to memory array 102. Therefore, the corresponding I / O circuitry of the other memory array may be disposed on the other side of the other memory array, relative to I / O circuitry 106 shown in Figure 4.

[0024] In Figure 5, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H, and the I / O circuit 106 (or its layout) can be divided into I / O portions 106A, 106B, 106C, 106D, 106E, 106F, 106G, and 106H. In some embodiments, I / O portions 106A to 106H (e.g., physically) are respectively arranged adjacent to array portions 102A to 102H along the X direction, and the physically aligned array portions and I / O portions are formed with the same conductivity type. For example, I / O portion 106A is physically aligned with array portion 102A along the X direction, and the unique memory cell formed in array portion 102A has the same conductivity type as the transistor formed in I / O portion 106A. Furthermore, the unique memory cell formed in each array portion 102A to array portion 102I is electrically coupled to a corresponding one of the aligned I / O portions 106A to I / O portion 106I via at least one bit line (e.g., bit line BL A), and electrically coupled to word line circuit 104 via at least one word line (e.g., word line WLA). The bit line may extend along the X direction, and the word line may extend along the Y direction.

[0025] In some embodiments, the only memory cells in array portions 102A and 102B and the transistors in the corresponding I / O portions 106A and 106B are all formed in p-type; the only memory cells in array portions 102C and 102D and the transistors in the corresponding I / O portions 106C and 106D are all formed in n-type; the only memory cells in array portions 102E and 102F and the transistors in the corresponding I / O portions 106E and 106F are all formed in p-type; and the only memory cells in array portions 102G and 102H and the transistors in the corresponding I / O portions 106G and 106H are all formed in n-type. In some embodiments, the transistors of the word line circuit 104 (along the Y direction) adjacent to the memory array portion 102H and the controller 108 (along the Y direction) adjacent to the I / O portion 106H are formed in an n-type configuration. In other words, the corresponding portions of the memory array 102 and the I / O circuit 106 adjacent to the word line circuit 104 and the controller 108 may have the same conductivity type.

[0026] Although configuration 500 only shows one memory array and its corresponding word line circuitry, I / O circuitry, and controller, it should be understood that configuration 500 can be generalized to include a plurality of memory arrays (and corresponding circuitry). In these embodiments, another memory array having a similar configuration to memory array 102 may be disposed on the other side of I / O circuitry 106 shown in Figure 5 relative to memory array 102. Therefore, the corresponding I / O circuitry of the other memory array may be disposed on the other side of the other memory array relative to I / O circuitry 106 shown in Figure 5.

[0027] In some embodiments, configurations 300 to 500 (as shown in Figures 3 to 5, respectively) may be used for memory arrays (and their corresponding circuitry) formed along a single layer. The term "layer" as used herein may refer to a single semiconductor substrate, a single wafer, a single metallization layer disposed on a semiconductor substrate, or any processed layer. For example, transistors for memory arrays, word line drivers, I / O circuitry, and controllers may be formed as one of the following transistor structures: gate-all-around (GAA) transistors, nanosheet transistors, fin field-effect transistors (FinFETs), planar transistors, etc., located on a semiconductor substrate. However, it should be understood that embodiments of this disclosure further include configurations that may be used for memory arrays formed across vertically spaced layers, which will be discussed below.

[0028] Figures 6, 7, 8, and 9 illustrate various layouts or configurations of the unique memory cells of the memory array 102 according to various embodiments, including configuration 600, configuration 700, configuration 800, and configuration 900. Generally, according to various embodiments of this disclosure, each of configurations 600 to 900 includes a corresponding layout for forming a plurality of n-type unique memory cells and a plurality of p-type unique memory cells on a plurality of levels on a substrate. It should be understood that the configurations in Figures 6 to 9 are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0029] In Figure 6, the memory array 102 (or its layout) can be divided into array portion 102A and array portion 102B. For clarity, the corresponding I / O portions are not shown. Only the array portion 102A, where the memory cells are formed in an n-type configuration, is formed in the lower layer (or layer) above the substrate, and only the array portion 102B, where the memory cells are formed in a p-type configuration, is formed in the upper layer (or layer) above the substrate. In some embodiments, the transistors of the memory cells forming the array portions 102A and 102B are provided with complementary field-effect transistor (CFET) structures. For example, the components of the transistor in the array portion 102A (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistor in the array portion 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0030] In Figure 7, the memory array 102 (or its layout) can be divided into array portion 102A and array portion 102B. For clarity, the corresponding I / O portions are not shown. Only the array portion 102A, where the memory cells are formed in a p-type configuration, is formed in the lower layer (or layer) above the substrate, and only the array portion 102B, where the memory cells are formed in an n-type configuration, is formed in the upper layer (or layer) above the substrate. In some embodiments, the transistors of the memory cells forming the array portions 102A and 102B are provided with complementary field-effect transistor structures. For example, the components of the transistor in the array portion 102A (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistor in the array portion 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0031] In Figure 8, the memory array 102 (or its layout) can be divided into array portions 102A, 102B, 102C, and 102D. For clarity, the corresponding I / O portions are not shown. Array portions 102A, where only the memory cells are formed in an n-type configuration, are formed in the lower layer (or layer) above the substrate; array portions 102B, where only the memory cells are formed in a p-type configuration, are formed in the lower layer (or layer); array portions 102C, where only the memory cells are formed in an n-type configuration, are formed in the upper layer (or layer) above the substrate; and array portions 102D, where only the memory cells are formed in a p-type configuration, are formed in the upper layer (or layer). In some embodiments, the transistors of the individual memory cells forming array portions 102A to 102D are provided with complementary field-effect transistor structures. For example, the components of the transistors in array portions 102A and 102B (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistors in array portions 102C and 102D (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0032] In Figure 9, the memory array 102 (or its layout) can be divided into array section 102A, array section 102B, array section 102C, array section 102D, array section 102E, array section 102F, array section 102G and array section 102H. For clarity, the corresponding I / O sections are not shown. The array portion 102A, in which only p-type memory cells are formed, is formed in the lower layer (or layer) above the substrate; the array portion 102B, in which only n-type memory cells are formed, is formed in the lower layer (or layer); the array portion 102C, in which only p-type memory cells are formed, is formed in the lower layer (or layer); the array portion 102D, in which only n-type memory cells are formed, is formed in the lower layer (or layer); the array portion 102E, in which only n-type memory cells are formed, is formed in the upper layer (or layer) above the substrate; the array portion 102F, in which only p-type memory cells are formed, is formed in the upper layer (or layer); the array portion 102G, in which only n-type memory cells are formed, is formed in the upper layer (or layer); and the array portion 102H, in which only p-type memory cells are formed, is formed in the upper layer (or layer). In some embodiments, the transistors forming the unique memory cells of the array portions 102A to 102H are provided with complementary field-effect transistor structures. For example, the components of the transistors in array portions 102A to 102D (e.g., channels, source / drain structures, gate structures, etc.) are formed in the lower layer, while the components of the transistors in array portions 102E to 102H (e.g., channels, source / drain structures, gate structures, etc.) are formed in the upper layer.

[0033] Figure 10 illustrates a flowchart of an exemplary method 1000 for forming a memory device (e.g., including a memory array and its corresponding circuitry) according to various embodiments of the present disclosure. In some embodiments, the memory device may be formed based on the configuration shown above with respect to Figures 3 through 9. Therefore, the following discussion of method 1000 may refer to some of the above figures. It should be noted that method 1000 as shown in Figure 10 is merely an example and is not intended to limit the scope of the present disclosure. Therefore, it should be understood that the order of steps in method 1000 of Figure 10 may be changed; for example, additional steps may be provided before, during, and after method 1000, and only some steps may be briefly described herein.

[0034] Method 1000 begins at step 1010, forming a first portion of a memory array in a first region on a substrate. In some embodiments, the first portion of the memory array includes a plurality of first read-only memory cells, and each of the first read-only memory cells includes a first transistor having a first conductivity type. In the example of Figure 3, the first portion of the memory array may include memory array portions 102A to 102C and array portions 102G to 102I. These different memory portions of the first portion may be disposed in the first region, wherein the first region has a plurality of regions physically spaced apart from each other along the Y direction. In the example of Figure 4, the first portion of the memory array may include memory array portions 102E to 102H. These different memory portions of the first portion may be disposed in the first region, wherein the first region has a plurality of regions physically adjacent to each other along the Y direction. In the example of Figure 5, the first part of the memory array may include memory array portion 102C, array portion 102D, array portion 102G, and array portion 102H. These different memory portions of the first part may be disposed in a first region, wherein the first region has a plurality of regions physically spaced apart along the Y direction.

[0035] Method 1000 continues to step 1020, forming a second portion of a memory array in a second region on a substrate, wherein the second region is arranged relative to the first region along a first lateral direction. In some embodiments, the second portion of the memory array includes a plurality of second unique memory cells, and each of the second unique memory cells includes a plurality of second transistors having a second conductivity type. In the example of Figure 3, the second portion of the memory array may include memory array portions 102D to array portions 102F. These different memory portions of the second portion may be disposed in the second region, wherein the second region is inserted between a plurality of regions of the first region along the Y direction. In the example of Figure 4, the second portion of the memory array may include memory array portions 102A to array portions 102D. These different memory portions of the second portion may be disposed in the second region, wherein the second region is physically adjacent to the first region along the Y direction. In the example of Figure 5, the second portion of the memory array may include memory array portions 102A, array portions 102B, array portions 102E, and array portions 102F. These different memory portions in the second part can be located along the Y direction next to or between multiple regions of the first region.

[0036] Method 1000 continues to step 1030, forming a word line driver in a third region on the substrate, wherein the third region is disposed relative to the first region and the second region along a first lateral direction. In the examples of Figures 3 to 5, the word line driver may be included in or integrated with the word line circuit 104. In some embodiments, the word line driver may be operatively coupled to each of a first portion and a second portion of the memory array. In other words, the word line driver may be operatively shared by the first portion and the second portion of the memory array.

[0037] Method 1000 continues to step 1040, forming a first word line electrically coupled to a first portion of the memory array by a word line driver, a second word line electrically coupled to a second portion of the memory array by a word line driver, a first bit line electrically coupled to the first portion of the memory array, and a second bit line electrically coupled to the second portion of the memory array. In some embodiments, the first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction. Furthermore, the first word line may be coupled to the respective gate terminal of the first unique memory cell, the second word line may be coupled to the respective gate terminal of the second unique memory cell, the first bit line may be coupled to the respective source terminal or drain terminal of the first unique memory cell, and the second bit line may be coupled to the respective source terminal or drain terminal of the second unique memory cell.

[0038] In one embodiment of this disclosure, a memory device is disclosed. The memory device includes a plurality of first memory cells formed in a plurality of first regions on a substrate, each of the first memory cells including a first transistor having a first conductivity type. The memory device includes a plurality of second memory cells formed in a plurality of second regions on a substrate, each of the second memory cells including a second transistor having a second conductivity type. The memory device includes a plurality of first access lines extending along a first lateral direction, each of the first access lines being connected to a group of first memory cells in the first region or a group of second memory cells in the second region. The memory device includes a plurality of second access lines extending along a second lateral direction perpendicular to the first lateral direction, each of the second access lines being connected to each first memory cell in a corresponding group of the plurality of first regions or each second memory cell in a corresponding group of the plurality of second regions. The first regions and the second regions are arranged along the first lateral direction.

[0039] In another embodiment of this disclosure, a memory device is disclosed. The memory device includes a first portion of a memory array, the first portion including a plurality of first memory cells, each of the first memory cells including a first transistor having a first conductivity type and electrically coupled to a first word line and a first bit line. The memory device includes a second portion of a memory array, the second portion including a plurality of second memory cells, each of the second memory cells including a second transistor having a second conductivity type and electrically coupled to a second word line and a second bit line. The first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction. The first portion and the second portion of the memory array are arranged adjacent to each other along the first lateral direction.

[0040] In another embodiment of this disclosure, a method for manufacturing a memory device is disclosed, the method comprising the following steps: forming a first portion of a memory array in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of the first read-only memory cells including a first transistor having a first conductivity type. forming a second portion of the memory array in a second region on the substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of the second read-only memory cells including a second transistor having a second conductivity type. forming a word line driver in a third region of the substrate, wherein the word line driver is operatively coupled to the first portion and the second portion of the memory array. In some embodiments, the first region, the second region, and the third region are arranged along a first lateral direction.

[0041] As used herein, the terms "about" and "approximately" generally indicate that a value may vary from a specified value depending on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term "about" may indicate that the value varies within, for example, 10% to 30% of the specified value (e.g., ±10%, ±20%, or ±30% of the specified value).

[0042] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practices, the various features are not drawn to scale. In practice, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion. Figure 1 illustrates an exemplary block diagram of a memory device according to some embodiments. Figures 2, 3, 4, 5, 6, 7, 8, and 9 illustrate various configurations of the memory array of the memory device of Figure 1 according to some embodiments. Figure 10 illustrates a flowchart of an exemplary method for forming a memory device according to some embodiments. [Biomaterial Storage]

[0044] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory device, comprising: A plurality of first memory cells are formed in a plurality of first regions on a substrate, each of the first memory cells including a first transistor having a first conductivity type; a plurality of second memory cells are formed in a plurality of second regions on the substrate, each of the second memory cells including a second transistor having a second conductivity type; a plurality of first access lines extend along a first lateral direction, each of the first access lines being connected to a group of the first memory cells in the first regions or a group of the second memory cells in the second regions; and a plurality of second access lines extend along a second lateral direction perpendicular to the first lateral direction, each of the second access lines being connected to each of the first memory cells in a corresponding group of the first regions or each of the second memory cells in a corresponding group of the second regions, wherein the first regions and the second regions are arranged along the first lateral direction.

2. The memory device as claimed in claim 1, wherein each of the first regions is inserted between adjacent regions of the second regions along the first lateral direction.

3. The memory device as claimed in claim 1, wherein the first regions are disposed adjacent to the second regions along the first lateral direction.

4. The memory device as described in claim 1, further comprising: A plurality of first input / output transistors having the first conductivity type; and a plurality of second input / output transistors having the second conductivity type.

5. The memory device as claimed in claim 4, wherein the first input / output transistors are formed in a plurality of third regions on the substrate, and the second input / output transistors are formed in a plurality of fourth regions on the substrate.

6. The memory device as claimed in claim 5, wherein each of the third regions is disposed adjacent to a corresponding one of the first regions along the second lateral direction perpendicular to the first lateral direction, and each of the fourth regions is disposed adjacent to a corresponding one of the second regions along the second lateral direction.

7. A memory device, comprising: A first portion of a memory array includes a plurality of first memory cells, each of the first memory cells including a first transistor having a first conductivity type and electrically coupled to a first word line and a second bit line; and a second portion of the memory array includes a plurality of second memory cells, each of the second memory cells including a second transistor having a second conductivity type and electrically coupled to a second word line and a second bit line, wherein the first word line and the second word line extend along a first lateral direction, and the first bit line and the second bit line extend along a second lateral direction perpendicular to the first lateral direction, and wherein the first portion of the memory array and the second portion of the memory array are disposed adjacent to each other along the first lateral direction.

8. The memory device as described in claim 7, further comprising: A third portion of the memory array includes a plurality of third memory cells, each of which includes a third transistor having the first conductivity type and electrically coupled to a third word line and the first word line.

9. The memory device as described in claim 7, further comprising: A fourth portion of the memory array includes a plurality of fourth memory cells, each of which includes a fourth transistor having the second conductivity type and electrically coupled to a fourth word line and the second bit line.

10. A method of manufacturing a memory device, comprising: A first portion of a memory array is formed in a first region on a substrate, wherein the first portion of the memory array includes a plurality of first read-only memory cells, each of which includes a first transistor having a first conductivity type; a second portion of the memory array is formed in a second region on the substrate, wherein the second portion of the memory array includes a plurality of second read-only memory cells, each of which includes a second transistor having a second conductivity type; and a word line driver is formed in a third region on the substrate, wherein the word line driver is operatively coupled to the first portion and the second portion of the memory array, wherein the first region, the second region and the third region are arranged along a first lateral direction.

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