Memory cell, memory device and semiconductor device

Abstract

The memory cell includes first and second active regions and first, second, third, and fourth gate structures. The first, second, third, and fourth gate structures are configured to interface with the first active region, respectively, to form first, second, third, and fourth transistors for the memory cell write port. The second and third gate structures are further configured to interface with the second active region, forming fifth and sixth transistors for the memory cell write port. The memory cell further includes a fifth gate structure configured to interface with the second active region, forming a seventh transistor for the memory cell read port. The second active region has a first segment providing a channel region for the seventh transistor and a second segment providing channel regions for the fifth and sixth transistors. The first and second segments have different widths.

Description

[Technical Field]

[0001] This invention relates to memory cells, memory devices, and semiconductor devices, and particularly to multi-port memory cells, memory devices, and semiconductor devices with optimized active region width. [Previous Technology]

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to generations of integrated circuits, each smaller and more complex than the last. In the development of ICs, functional density (i.e., the number of interconnected components per unit wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This miniaturization process generally provides benefits through increased production efficiency and reduced associated costs. However, this miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] Semiconductor memory is an electronic data storage device implemented based on semiconductor integrated circuits, which has a faster access time than other types of data storage technologies. For example, Static Random-Access Memory (SRAM) devices are commonly used in integrated circuits. SRAM devices are very popular in high-speed communications, image processing, and system-on-chip (SoC) applications. An SRAM cell can read or write a bit in nanoseconds, while the access time of rotating storage devices (such as hard disks) is in the millisecond range.

[0004] With the advent of the deep sub-micron era, SRAM devices have become increasingly popular due to their suitability for lithography layouts, including active regions, polysilicon wires, and metal layers. Multi-port SRAM devices have become particularly prevalent. For example, two-port (2P) SRAM devices allow parallel operations, such as 1R (read) 1W (write) or 2R (read) operations, thus offering higher bandwidth than single-port SRAM devices. However, in the deep sub-micron era, SRAM cells are typically large, especially for multi-port SRAM cells, due to insufficient area utilization. With advancements in process nodes, there is a growing demand for a multi-port SRAM architecture that can reduce cell size while maintaining key performance indicators such as, but not limited to, Voltage Dynamic Data Retention (VDDR), maximum operating voltage (Vmax), minimum operating voltage (Vmin), α ratio, and β ratio. [Summary of the Invention]

[0005] Embodiments of this disclosure provide a memory cell, including: a first active region and a second active region, wherein both the first active region and the second active region extend longitudinally along a first direction; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are arranged sequentially from the first gate structure to the fourth gate structure in the first direction, each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally along a second direction perpendicular to the first direction, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to engage with the first active region to respectively form one of the memory cells. The memory cell has a first transistor, a second transistor, a third transistor, and a fourth transistor, and a second gate structure and a third gate structure are further configured to connect with a second active region to form a fifth transistor and a sixth transistor for writing to the memory cell; and a fifth gate structure extending longitudinally along a second direction, wherein the fifth gate structure is configured to connect with the second active region to form a seventh transistor for reading from the memory cell, wherein the second active region has a first segment and a second segment, the first segment providing a channel region for the seventh transistor, and the second segment providing a channel region for the fifth transistor and the sixth transistor, the first segment having a first width, and the second segment having a second width different from the first width.

[0006] Additionally, embodiments of this disclosure provide a semiconductor device, including: a write port for a memory cell, wherein the write port includes at least one of a pull-up (PU) transistor, a pull-down (PD) transistor, and a transmission gate (PG) transistor; and a read port for a memory cell, wherein the read port includes a PG transistor, wherein: the PG transistor in the write port is an n-type transistor, the PG transistor in the read port is a p-type transistor, the channel regions of the PD transistor in the write port and the channel regions of the PG transistor in the write port are disposed on a first active region, the channel regions of the PU transistor in the write port and the channel regions of the PG transistor in the read port are disposed on a second active region, the second active region extends parallel to the first active region, and the second active region has a variable width.

[0007] Additionally, embodiments of this disclosure provide a memory device, including: a first transmission gate (PG) transistor, a second transmission gate (PG) transistor, a first pull-down (PD) transistor, and a second pull-down (PD) transistor, sharing a first active region extending along a first direction; a first pull-up (PU) transistor, a second pull-up (PU) transistor, and a read port transmission gate (R-PG) transistor, sharing a second active region extending along the first direction; and an isolation structure adjacent to the gate structure of the first PG transistor and extending longitudinally along a second direction perpendicular to the first direction, wherein the second active region is divided into a first segment and a second segment by the isolation structure, and the width of the first segment is different from the width of the second segment.

Implementation Method

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. To simplify this disclosure, specific elements and layout examples are described below. These are, of course, merely examples and are not intended to be limiting. For example, when the first feature described below is located above or on top of the second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between the first and second features, so the first and second features are not necessarily in direct contact.

[0010] Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplification and clarity and does not imply a specific relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosures, the formation, connection, or coupling of a feature to another feature may include embodiments where the first and second features are in direct contact, or embodiments where other features are formed between these features such that these features may not be in direct contact. Furthermore, to simplify the relationship between a feature and another feature in this disclosure, relative spatial terms such as "below," "above," "horizontal," "vertical," "above," "below," "over," "below," etc., and their derivatives (e.g., "horizontally," "downward," "upward," etc.) are used. These relative spatial terms are intended to cover different orientations of the device and its features. Furthermore, when describing numbers or ranges of numbers, terms such as "about," "approximately," etc., are used, unless otherwise stated, and these terms are intended to include numbers differing from the described number by ±10%. For example, the term "about 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0011] This disclosure generally relates to memory devices, and in particular to multi-port static random-access memory (SRAM) cells. Two-port (2P) SRAM cells and their corresponding layouts are provided according to various exemplary embodiments. Variations of certain embodiments are discussed. Furthermore, certain embodiments can be applied to logic circuits.

[0012] Some exemplary embodiments relate to, but are not limited to, multi-gate devices. Multi-gate devices are introduced to improve gate control by increasing gate-to-channel coupling, reducing off-state current, and minimizing short-channel effects (SCE). One type of multi-gate device is the Fin Field Effect Transistor (FinFET). The name FinFET comes from its fin-like structure, which extends from the substrate on which it is formed to form the channel of the field effect transistor. Another type of multi-gate device is the gate-all-around (GAA) transistor, introduced in part to address the performance challenges associated with FinFETs. The name GAA transistor comes from its gate structure, which surrounds the channel region (e.g., stacked nanosheets) and provides the channel with access in four directions. Gate-all-around (GAA) architectures are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows for large-scale scaling while maintaining gate control and reducing short-channel effects (SCE). The following description will continue to illustrate one or more GAA paradigms to demonstrate various embodiments of this disclosure. However, it should be understood that this application is not intended to be limited to specific types of devices, except as expressly stated. For example, certain aspects of this disclosure can also be applied to FinFET-based or planar transistor-based implementations.

[0013] A dual-port static random access memory (SRAM) cell includes a pull-down (PD) transistor, a pull-up (PU) transistor, and a pass-gate (PG) transistor in the write port, as well as one or more read-port pass-gate (R-PG) transistors in the read port. In some embodiments, transistors having the same conductivity type (e.g., n-type or p-type) are formed in the same active region. The active region of a transistor refers to the region containing the source region, drain region, and channel region under the gate structure. In this context, the active region is also referred to as the "oxide-definition (OD) region". For multi-gate transistors, the active region may be a three-dimensional (3D) structure. Massively shrinking the size of integrated circuits (ICs) has led to increasingly dense active regions with continuously decreasing widths. To improve transistor performance, the active region is typically set to a fixed width to ensure that each transistor formed thereon has the widest possible channel area, especially for p-type transistors, which are more susceptible to insufficient current drive than n-type transistors. In some embodiments of this disclosure, during GAA transistor formation, a dielectric dummy layer replaces the sacrificial layer prior to the gate replacement process. Particularly for p-type transistors, this approach reduces the diffusion of impurities (e.g., germanium) from the sacrificial layer to the channel layer, thereby enhancing the channel integrity of the GAA transistor (e.g., reducing etch losses due to impurity diffusion and maintaining flat edges) and current drive capability. This improved current drive capability ensures that p-type transistors maintain satisfactory performance even when the active region does not reach its maximum width. Therefore, allowing the active region width to be variable provides additional tuning parameters for fine-tuning SRAM performance.

[0014] The structural details of the apparatus disclosed herein are described in the accompanying drawings. The drawings summarize the features of several embodiments to enable those skilled in the art to better understand the following detailed description. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0015] Figures 1A and 1B show a perspective view and a top view, respectively, of an integrated circuit (IC) device 10 implemented using GAA transistors, such as an SRAM device. Referring to Figure 1A, the IC device 10 includes a substrate 12. The substrate 12 may include basic (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as silicon-germanium alloys, gallium phosphide aluminum, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium arsenide, indium gallium phosphide, indium gallium arsenide phosphide alloys, and / or other suitable materials. The substrate 12 may be a single-layer material with a uniform composition. Alternatively, the substrate 12 may include multilayer materials with similar or different compositions, which are suitable for the manufacture of IC devices. In one example, substrate 12 may be a silicon-on-insulator (SOI) substrate with a semiconductor silicon layer formed on a silicon oxide layer. In another example, substrate 12 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain (S / D) regions, can be formed in or on substrate 12. These doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron), depending on design requirements. Doped regions can be formed directly on substrate 12, or in P-well, N-well, dual-well structures, or using protrusion structures. Doped regions can be formed through dopant atom implantation, in-situ doped epitaxial growth, and / or other suitable techniques.

[0016] Three-dimensional active regions 14 are formed on substrate 12. Each active region 14 includes an extended nanostructure 26 (as shown in FIG. 2), which is vertically stacked within a defined channel region in the active region and located above the fin substrate. The fin substrate protrudes upward from substrate 12. Source / drain structures 16 are formed within a defined source / drain region in the active region and located above the fin substrate. The source / drain structures 16 are adjacent to both ends of the nanostructure 26. The source / drain structures 16 may contain an epitaxial layer epitaxially grown on the fin substrate. It is worth noting that although the width of the source / drain structures 16 is uniform in the Y direction, this is only for illustrative purposes. As discussed below with reference to FIGS. 12 to 21, jogs may occur in the active region. These jogs may cause variations in the width of different segments of the active region, thereby causing variations in the width of the source / drain structures 16. Typically, a wider segment in the active region corresponds to a wider source / drain structure 16, and vice versa.

[0017] The IC device 10 further includes isolation structures 18 (or isolation features 18) formed on the substrate 12. These isolation structures 18 are used to electrically isolate the various components of the IC device 10. The isolation structures 18 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structures 18 may include shallow trench isolation (STI) features. In one embodiment, the isolation structure 18 is formed by etching trenches on the substrate 12, which is performed simultaneously with the formation of the active region 14. These trenches may be filled with the isolation materials described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as isolation structures 18. Alternatively, the isolation structure 18 may include a multilayer structure, for example, having one or more thermal oxide inner layers.

[0018] The IC device 10 also includes a gate structure 20 (or gate stack 20, simply referred to as gate 20) above and associated with the active region 14. Gate structure 20 may be a dummy gate structure (e.g., comprising an oxide gate dielectric layer and a polysilicon gate electrode), or it may be a high-k metal gate (HKMG) structure comprising a high-k gate dielectric layer and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown herein, gate structure 20 may also include additional material layers, such as interface layers, sealing layers, other suitable layers, or combinations thereof.

[0019] Referring to FIG1B, a plurality of active regions 14 are arranged along the X direction, and a plurality of gate structures 20 are arranged along the Y direction, i.e., typically perpendicular to the active regions 14. A transistor is formed at the intersection of the active regions 14 and the gate structures 20. In many embodiments, the IC device 10 also includes other features, such as gate spacers arranged on the sidewalls of the gate structures 20, and many other features.

[0020] FIG2 is a schematic cross-sectional view of a fragment along section line AA in FIG1A, showing various layers (layers) that can be fabricated on substrate 12 according to various aspects of the present disclosure. In FIG2, these layers include device layers DL and multilayer interconnects MLI located above device layers DL. Device layers DL include devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device elements (e.g., doped wells, gate structures, and / or source / drain features). In some embodiments, device layers DL include substrate 12, doped regions 15 (e.g., n-type wells and / or p-type wells) disposed in substrate 12, isolation features 18, and transistors T. In the illustrated embodiment, transistor T includes suspended nanostructures 26 (channel components 26) and gate structures 20 located between source / drain features 16, wherein gate structures 20 cover and / or surround suspended nanostructures 26. These nanostructures 26 may include nanosheets, nanotubes, or nanowires, or other nanostructures extending in the X direction. Each gate structure 20 has a metal gate structure, which consists of a gate electrode 22 located above the gate dielectric 24 and a gate spacer 25 disposed along the sidewall of the metal gate structure.

[0021] Multilayer interconnect (MLI) is used to electrically couple various devices and / or components in a device layer DL, enabling these devices and / or components to operate according to the design requirements of the memory. In the illustrated embodiment, the multilayer interconnect MLI includes a contact layer CO, a via zero layer V0, a ​​metal zero layer M0, a via first layer V1, a metal first layer M1, a via second layer V2, a metal second layer M2, a via third layer V3, and a metal third layer M3. This disclosure considers multilayer interconnect MLIs with more or fewer layers, for example, a multilayer interconnect MLI with N metal layers (layers) where N is an integer from 2 to 10. Each multilayer interconnect MLI layer includes conductive elements (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., inter-layer dielectric (ILD) layers and contact etch stop layers (CESL)). In some embodiments, conductive elements at the same level (e.g., M1 layer) in a multilayer interconnect (MLI) are formed simultaneously. In some embodiments, the top surface and / or bottom surface of the conductive elements at the same level are relatively flat. The CO layer includes a source / drain contact MD disposed in the dielectric layer 28; the V0 layer includes a gate via VG, a source / drain contact via VD, and a butt contact disposed in the dielectric layer 28; the M0 layer includes an M0 metal line disposed in the dielectric layer 28, wherein the gate via VG connects the gate structure to the M0 metal line, the source / drain via V0 connects the source / drain to the M0 metal line, and the butt contact connects the gate structure and the source / drain structure together and is connected to the M0 metal line. Layer V1 includes a V1 via disposed in dielectric layer 28, wherein the V1 via connects the M0 metal line to the M1 metal line; layer M1 includes the M1 metal line disposed in dielectric layer 28; layer V2 includes a V2 via disposed in dielectric layer 28, wherein the V2 via connects the M1 metal line to the M2 metal line; layer M2 includes the M2 metal line disposed in dielectric layer 28; layer V3 includes a V3 via disposed in dielectric layer 28, wherein the V3 via connects the M2 metal line to the M3 metal line. For simplicity and ease of understanding, Figure 2 has been simplified to better illustrate the innovative concepts disclosed herein. Additional functions may be added to the layers of the memory, and in other embodiments, some described functions may be replaced, modified, or deleted. Figure 2 is only an example and may not reflect the actual cross-sectional view of the IC device 10 and / or SRAM cell 100, which will be discussed in detail below.

[0022] Please refer to Figure 3, which shows a schematic diagram of a dual-port SRAM cell 100. The dual-port SRAM cell 100 includes a write port 100W and a read port 100R. The write port 100W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and transmission gate transistors PG-1 and PG-2. In the illustrated embodiment, pull-up transistors PU-1 and PU-2 are p-type transistors, while transmission gate transistors PG-1 and PG-2, and pull-down transistors PD-1 and PD-2 are n-type transistors.

[0023] The drain of pull-up transistor PU-1 is coupled to the drain of pull-down transistor PD-1, while the drain of pull-up transistor PU-2 is coupled to the drain of pull-down transistor PD-2. Pull-up transistors PU-1 and PD-1 are cross-coupled with pull-up transistors PU-2 and PD-2 to form a data latch. The gates of pull-up transistors PU-1 and PD-1 are coupled and connected to the common drain of pull-up transistors PU-2 and PD-2 to form a storage node SN; the gates of pull-up transistors PU-2 and PD-2 are coupled and connected to the common drain of pull-up transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to the power supply voltage Vdd (also known as Vcc), and the sources of pull-down transistors PD-1 and PD-2 are coupled to the voltage Vss. In some embodiments, Vss can be an electrically grounded voltage.

[0024] The storage node SN of the data latch is coupled to the bit line W_BL of the write port 100W via the transmission transistor PG-2, and the complementary storage node SNB is coupled to the complementary bit line W_BLB of the write port 100W via the transmission transistor PG-1. The storage node SN and the complementary storage node SNB are complementary nodes and are usually at opposite logic levels (logic high or logic low). The gates of the transmission transistors PG-1 and PG-2 are coupled to the word line W_WL of the write port 100W.

[0025] The read port 100R of the SRAM cell 100 includes a read port transmission gate transistor R-PG, which is connected between the bit line R_BL and the storage node SN (or to the gates of the pull-up transistor PU-1 and pull-down transistor PD-1). The gate of the read port transmission gate transistor R-PG is coupled to the word line R_WL of the read port 200R. In the illustrated embodiment, the read port transmission gate transistor R-PG is a p-type transistor. That is, in this dual-port SRAM cell 100, the transmission gate transistor of the write port is an n-type transistor, while the transmission gate transistor of the read port is a p-type transistor.

[0026] Figure 4 shows a simplified schematic layout 200 of a dual-port SRAM cell 100, including a write port 100W and a read port 100R. The write port 100W includes transfer transistors PG-1, PG-2, pull-up transistors PU-1, PU-2, pull-down transistors PD-1, and pull-down transistor PD-2. The read port 100R includes a read port transfer gate transistor R-PG. For visual clarity and simplification, Figure 4 shows the active regions, gate structures, and some gate cut features of these transistors, while omitting interconnect components such as contacts, vias, and metal lines.

[0027] As shown in FIG4, the dual-port SRAM cell 100 includes active regions 202 and 204. These active regions 202 and 204 extend along direction X in FIG4. In the illustrated embodiment, each region of active regions 202 and 204 may contain (or be implemented as) the nanostructure 26 discussed in FIG2. In other embodiments, active regions 202 and 204 may also include fin structures. Active region 202 is an element of write port 100W, while the side portion of active region 204 is an element of read port 100R, and the remaining portion is an element of write port 100W. In other words, active region 204 is used by both read port 100R and write port 100W. In the illustrated embodiment, active region 204 belongs to pull-up transistor PU-1, pull-up transistor PU-2, and read port transmission gate transistor R-PG, all of which are p-type transistors. Therefore, active region 204 is formed on N-type well 206. Meanwhile, the active region 202 comprises transmission transistor PG-1, pull-down transistor PD-1, pull-down transistor PD-2, and transmission transistor PG-2, all of which are n-type transistors. Therefore, the active region 202 is formed on the P-type well 208 (or P-type substrate).

[0028] The dual-port SRAM cell 100 further includes gate structures 212, 214, 216, 218, and 220. Gate structures 212-220 each extend along the Y direction in FIG. 4. Each of these gate structures 212-220 may include (or be implemented as) the gate structure 20 discussed in FIG. 2 above. Gate structures 212, 214, 216, and 220 are elements of the write port 100W, while gate structure 218 is an element of the read port 100R. Gate structures 214 and 216 each traverse two active regions 202 and 204. Therefore, gate structure 214 is shared by pull-down transistor PD-1 and pull-up transistor PU-1, and gate structure 216 is shared by pull-down transistor PD-2 and pull-up transistor PU-2.

[0029] The dual-port SRAM cell 100 further includes multiple gate-cut dielectric features, including a dielectric feature 230 extending in the X direction and a dielectric feature 232 extending in the Y direction. In the illustrated embodiment, dielectric feature 230 is located between active regions 202 and 204, and is adjacent to gate structures 218 and 220. Furthermore, dielectric feature 230 is located above the interface between N-type well 206 and P-type well 208. Dielectric feature 230 divides the otherwise continuous gate structure into two isolated segments, corresponding to gate structures 218 and 220, respectively. Dielectric feature 230 is formed by filling corresponding cut-metal-gate (CMG) trenches at the dielectric feature locations. Dielectric feature 230 is also referred to as CMG feature 230.

[0030] Dielectric feature 232 is formed through a continuous poly-on-diffusion-edge (CPODE) process. For the purposes of this disclosure, "diffusion edge" can be equated to "active edge," where, for example, the active edge is adjacent to an adjacent active region. Dielectric feature 232 is also referred to as CPODE feature 232. Prior to the CPODE process, the active edge may include a dummy GAA structure having a dummy gate structure (e.g., a polysilicon gate) and a multilayer vertically stacked nanostructure serving as a channel layer. Furthermore, internal spacers may be disposed at the side ends of adjacent nanostructures. In various examples, source / drain epitaxial features may be disposed on both sides of the dummy GAA structure, such that adjacent source / drain epitaxial features contact the internal spacers and nanostructures of the dummy GAA structure. A subsequent CPODE etching process removes the dummy gate structure and channel layer, forming a CPODE trench from the dummy GAA structure. The dielectric material filling the CPODE trench for isolation is called a CPODE feature. In some embodiments, after the CPODE feature is formed, the remaining dummy gate structure is replaced by a metal gate structure during gate replacement (gate last) process. In other words, in some embodiments, the CPODE feature replaces a portion of the originally continuous gate structure and is defined between corresponding gate spacers of the replaced portion of the gate structure. In contrast, the CMG feature truncates the originally continuous gate structure and extends into the adjacent region of the gate structure. In FIG. 4, the CPODE feature 232 contacts and aligns with the gate structure 212. The CPODE feature 232 extends in the Y direction, through the N-type well 206 and into another P-type well 208 of the adjacent SRAM cell. That is, two adjacent SRAM cells may share the CPODE feature 232. Furthermore, in some embodiments, the CPODE feature 232 may extend deeper into the underlying substrate than the CMG feature 230.

[0031] Referring again to Figure 4, the boundary 240 of the dual-port SRAM cell 100 is shown as a dashed line. It is worth noting that some active regions and gate structures may extend beyond the shown boundary 240, as these elements may also form part of adjacent SRAM cells. The boundary 240 is rectangular, and its length in the X direction exceeds its length in the Y direction. The first dimension of the boundary 240 in the X direction is called the cell width W, and the second dimension in the Y direction is called the cell height H. When the dual-port SRAM cell 100 is reused in the memory array, the cell width W can be referred to as the memory cell pitch in the X direction, and the cell height H can be referred to as the memory cell pitch in the Y direction.

[0032] The cell size of the dual-port SRAM cell 100 is the cell width W multiplied by the cell height H, where the cell width W is approximately four times the polysilicon pitch (e.g., the center-to-center distance between two adjacent gate structures in direction X), and the cell height H is approximately twice the isolation pitch (e.g., the center-to-center distance between two adjacent STI features in direction Y). Representing a unit area of ​​one polysilicon pitch and one isolation pitch as a unit area, each unit area including the intersection of the gate structure and the active region, the cell size of the dual-port SRAM cell 100 is approximately eight times the unit area to accommodate seven transistors: transfer transistor PG-1, transfer transistor PG-2, pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, pull-down transistor PD-2, and read port transfer gate transistor R-PG. Since only one unit area is not used to form a functional transistor but is instead used to accommodate the intersection of the CPODE feature and the active region, this area utilization is considered high.

[0033] The width of the active region 202 of the n-type transistor is denoted as width WN, the width of the active region 204 of the p-type transistor is denoted as width WP, and the critical dimension (CD) or gate width of each gate structure 212 to gate structure 220 is denoted as gate width G. In some embodiments, the gate width G ranges from approximately 10 nm to 20 nm, the width WN ranges from approximately 11 nm to 35 nm, and the width WP ranges from approximately 11 nm to 35 nm. In some embodiments, the width WP is equal to the width WN (WP=WN) to balance the speed of the read port and the speed of the write port. In some embodiments, the width WP is greater than the width WN (WP>WN) to better meet the speed requirements of the read port. In some embodiments, the width WP is less than the width WN (WP<WN) to better meet the speed requirements of the write port. Due to the limitation of the current carrying capacity of the p-type transistor, the current driving capability of the p-type transistor is generally lower than that of the n-type transistor. To address this issue, the active region 204 may conventionally have a fixed width WP to ensure that each p-type transistor formed thereon has the widest possible usable channel area. However, this disclosure employs a modified approach from GAA transistor fabrication (discussed in detail later in Figures 22-42), which improves etch selectivity during gate replacement. This improvement significantly enhances the current drive capability of GAA transistors, particularly for p-type transistors. Therefore, this improvement allows certain transistors formed on the active region 204 to have different widths without compromising current drive capability. In other words, in some embodiments, the active region 204 can now have a variable width WP, a concept that will be further elaborated upon later in this disclosure.

[0034] Figure 5 shows another schematic alternative layout 200' of the dual-port SRAM cell 100. Many aspects of this alternative layout 200' are the same as those of the layout 200 shown in Figure 4. For clarity and consistency, similar elements appearing in Figures 4 and 5 are labeled with the same codes, and the details of these elements will not necessarily be repeated below. Unlike layout 200, in the alternative layout 200', there is no CPODE feature 232, but instead an additional CMG feature 230' and an additional gate structure 212'. The CMG feature 230' is located between the active region 202 and the active region 204, and is adjacent to the gate structure 212 and the gate structure 212'. In addition, the dielectric feature 230' is located above the interface between the N-type well 206 and the P-type well 208. The dielectric feature 230' divides the otherwise continuous gate structure into two isolated parts, corresponding to the gate structure 212 and the gate structure 212', respectively. The gate structure 212' covers the edge of one end of the active region 204. Meanwhile, the other end of the active region 204 does not extend beyond the other side of the gate structure 212 along the X direction. Therefore, a non-functional transistor Tnf is formed at the intersection of the end of the active region 204 and the gate structure 212'.

[0035] Figure 6 illustrates an SRAM array layout 300 according to the present disclosure. Referring to Figure 6, four dual-port SRAM cells 100a, 100b, 100c, and 100d are arranged along directions X and Y to form a 2x2 SRAM cell array. Each SRAM cell in the array can use the layout 200 shown in Figure 4. In some embodiments, two adjacent SRAM cells in direction X are symmetrical on their common boundary, and two adjacent SRAM cells in direction Y are also symmetrical on their common boundary. That is, SRAM cell 100b is a copy of SRAM cell 100a but flipped along the Y-axis; SRAM cell 100c is a copy of SRAM cell 100a but flipped along the X-axis; and SRAM cell 100d is a copy of SRAM cell 100b but flipped along the X-axis. Figure 6 has been simplified for a clearer understanding of the innovative concepts of the present disclosure. For example, the figure shows the active region, gate structure, CPODE feature, N-well, P-well, and cell boundary, while some other features are omitted. As shown in Figure 6, the SRAM array layout 300 includes alternating N-wells 206 and P-wells 208 along the Y-axis. In other words, each P-well 208 is adjacent to an N-well 206, and the N-well 206 is adjacent to another P-well 208, and this pattern is repeated continuously. In the embodiment shown in Figure 6, the gate structure in each dual-port SRAM cell does not extend beyond its respective cell boundary, and each CPODE feature is shared by two adjacent SRAM cells arranged along the Y-direction.

[0036] FIG7A is a schematic cross-sectional view along section line AA in FIG6, which, according to various aspects of the present disclosure, cuts through the length direction of the active region 204. FIG7B is a schematic cross-sectional view along section line BB in FIG6, which, according to various aspects of the present disclosure, cuts through the CPODE feature. Referring to FIG7A and FIG7B, the active region 204 passes through SRAM cell 100a and SRAM cell 100b, but is sandwiched between the CPODE features in SRAM cell 100a and SRAM cell 100b. The CPODE feature replaces the metal gate structure that was originally closest to the cell edge. The distance between the CPODE features in SRAM cell 100a and SRAM cell 100b (CPODE to CPODE spacing) is 7 times the polymer spacing. To illustrate the layout of the CPODE features more clearly, Figure 7A also shows additional CPODE features located to the left of SRAM cell 100a and additional CPODE features located to the right of SRAM cell 100b, which are arranged along the X direction.

[0037] Between the CPODE features in SRAM cell 100a and SRAM cell 100b, the active region 204 includes a channel region composed of nanostructures 26, and the source / drain structure 16 is adjacent to the end of the nanostructure 26. Gate structures surround the nanostructures 26 and form pull-up transistors PU-1, PU-2, and read port transfer gate transistors R-PG in SRAM cell 100a, and read port transfer gate transistors R-PG, PU-2, and PU-1 in SRAM cell 100b. The active region 204 is located on an N-type well 206, while the active region 202 is located on a P-type well 208. The source / drain structure 16 formed on the active region 204 is a P-type epitaxial structure, and the source / drain structure 16 formed on the active region 202 is an N-type epitaxial structure. The isolation structure 18 may include a shallow trench isolation (STI) structure. In one embodiment, the isolation structure 18 is formed by etching trenches on the substrate 12 during the formation of active regions 202 and 204. The isolation structure 18 may include a multilayer structure, for example, having an oxide inner pad layer 18a (e.g., a thermal silicon dioxide inner pad layer), a first dielectric layer 18b (e.g., silicon oxynitride), and a second dielectric layer 18c (e.g., silicon dioxide). Notably, a hard mask layer 50 is deposited on the isolation structure 18. The composition of the hard mask layer 50 differs from that of the isolation structure 18, thus ensuring that each of them can be selectively etched without materially damaging the other layer. The hard mask layer 50 may be a single layer or multiple layers. For example, the hard mask layer 50 may include an oxide inner pad layer 50a (e.g., silicon dioxide or silicon oxynitride) and a nitride layer 50b (e.g., silicon nitride or silicon oxynitride), with the nitride layer 50b deposited on the oxide inner pad layer 50a. The hard mask layer 50, stacked between the isolation structure 18 and the CPODE feature, is a distinguishing feature in the employed GAA transistor process (discussed in detail later in Figures 22 through 42).

[0038] Figure 8 shows another alternative layout 300' of the SRAM array. This alternative layout 300' has many similarities to the layout 300 shown in Figure 6. For clarity and consistency, similar elements in Figures 6 and 8 are numbered the same, and the details of these elements will not necessarily be repeated below. Unlike layout 300, in alternative layout 300', the end portion of the active region 204 extending beyond the CPODE feature has a smaller width WP' (WP' < WP). The places where the width of the active region changes abruptly are called "jogs". In the illustrated embodiment, the jogs of the active region 204 are located below the CPODE feature, and these jogs are all located on one side of the active region 204, facing the adjacent active region 202. There are no jogs on the other side of the active region 204, facing the adjacent active region 204.

[0039] Figure 9 shows an alternative layout 300'' of the SRAM array. The alternative layout 300'' is similar to the alternative layout 300' shown in Figure 8 in many aspects. For clarity and consistency, similar elements appearing in Figures 8 and 9 are numbered the same, and the details of these elements will not be repeated below. Unlike layout 300', in the alternative layout 300'', the bends in the active region 204 are located on both sides of the active region 204.

[0040] Figure 10 shows an alternative layout 400 for the SRAM array. Referring to Figure 10, a series of dual-port SRAM cells 100a, 100b, 100c, and 100d are arranged along directions X and Y to form a 2x2 SRAM cell array. Each SRAM cell in the array can use the alternative layout 200' shown in Figure 5. Many aspects of the alternative layout 400 are the same as those of the layout 300 shown in Figure 6. For clarity and consistency, similar elements in Figures 6 and 10 are numbered the same, and the details of these elements will not be repeated below. Unlike layout 300, there is no CPODE feature in the alternative layout 400; instead, an additional gate structure covers the edges of both ends of the active region 204, forming a non-functional transistor Tnf. Meanwhile, the ends of the active region 204 do not extend beyond the other side of this additional gate structure along direction X.

[0041] Figure 11 is a schematic cross-sectional view of a segment of section line CC in Figure 10, showing the active region 204 cut along its length according to various aspects of this disclosure. Unlike the cross-sectional view shown in Figure 7A, the active region 204 is sandwiched between the isolation feature 18 and an additional gate structure of the non-functional transistor Tnf located at the end of the active region 204. A hard mask layer 50 is deposited on the isolation feature 18. Gate spacers 25 and dielectric layers 28 (possibly including a contact etch stop layer (CESL) and an interlayer dielectric layer (ILD layer)) are disposed on the hard mask layer 50. The hard mask layer 50, stacked between the isolation structure 18 and the gate spacers 25, is a distinguishing feature in the GAA transistor process employed (discussed in detail later in Figures 22 to 42).

[0042] Figure 12 illustrates an alternative layout 500 for an SRAM array, which is achieved by modifying layout 300 in Figure 6. Many aspects of the alternative layout 500 are the same as those of layout 300 shown in Figure 6. For clarity and consistency, similar elements appearing in Figures 6 and 12 are numbered the same, and the details of these elements will not be repeated below. Unlike layout 300, in the alternative layout 500, the active region 204 does not have a fixed width WP, but rather is a segment that provides a transistor channel region for the read port transmission gate transistor R-PG, the width of which is a smaller width WP' (WP > WP'). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). As mentioned above, the width WN can be less than or greater than the width WP, depending on the performance requirements of the device. By providing wider channel regions for pull-up transistors PU-1 and PU-2 and narrower channel regions for the read port transfer transistor R-PG, the voltage dynamic data retention (VDDR) of the SRAM device can be improved, for example, by approximately 30mV to 80mV. In some embodiments, the ratio of width WP' to width WP (WP' / WP) may range from approximately 0.75 to approximately 1 (0.75 < WP' / WP < 1). This range is not arbitrary or stochastic. If the ratio is not greater than approximately 0.75, the channel width of the read port transfer transistor R-PG may be too small to provide sufficient current drive capability; if the ratio is not less than 1, the current drive capability of pull-up transistors PU-1 and PU-2 cannot be stronger than that of the read port transfer transistor R-PG, thus failing to improve VDDR. In some embodiments, the width difference (WP-WP') may range from approximately 2 nanometers to approximately 8 nanometers. In the illustrated embodiment, all bends in the active region 204 are located on one side of the active region 204, facing the adjacent active region 202. On the other side of the active region 204, facing the adjacent active region 204, there are no bends. Each bend in the active region 204 is located along direction X between the gate structure of the pull-up transistor PU-2 and the gate structure of the read port transmission gate transistor R-PG, for example, at the midpoint of the two gate structures.

[0043] Figure 13 illustrates an alternative layout 600 for the SRAM array, which is derived by modifying the alternative layout 400 in Figure 10. Many aspects of the alternative layout 600 are the same as those of the alternative layout 400 shown in Figure 10. For clarity and consistency, similar elements appearing in Figures 10 and 13 are numbered the same, and the details of these elements will not be repeated below. Unlike the alternative layout 400, in the alternative layout 600, the width of the active region 204 is no longer a fixed width WP, but a segment that provides a channel region for the read port to transmit the thyristor R-PG, the width of which is a smaller width WP' (WP > WP'). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). As mentioned above, the width WN can also be less than or greater than the width WP, depending on the performance requirements of the device. By providing wider channel regions for pull-up transistors PU-1 and PU-2 and narrower channel regions for the read port transfer transistor R-PG, the voltage dynamic data retention (VDDR) of the SRAM device can be improved, for example, by approximately 30mV to 80mV. In some embodiments, the ratio of width WP' to width WP (WP' / WP) may range from approximately 0.75 to approximately 1 (0.75 < WP' / WP < 1). This range is not arbitrary or stochastic. If the ratio is not greater than approximately 0.75, the channel width of the read port transfer transistor R-PG may be too small to provide sufficient current drive capability; if the ratio is not less than 1, the current drive capability of pull-up transistors PU-1 and PU-2 cannot be stronger than that of the read port transfer transistor R-PG, thus failing to improve VDDR. In some embodiments, the width difference (WP-WP') may range from approximately 2 nanometers to approximately 8 nanometers. In the illustrated embodiment, all bends in the active region 204 are located on one side of the active region 204, facing the adjacent active region 202. On the other side of the active region 204, facing the adjacent active region 204, there are no bends. Each bend in the active region 204 is located along direction X between the gate structure of the pull-up transistor PU-2 and the gate structure of the read port transmission gate transistor R-PG, for example, at the midpoint of the two gate structures.

[0044] Figure 14 illustrates an alternative layout 700 for an SRAM array, which is achieved by modifying layout 300 in Figure 6. Many aspects of the alternative layout 700 are the same as those of layout 300 shown in Figure 6. For clarity and consistency, similar elements appearing in Figures 6 and 14 are numbered the same, and the details of these elements will not be repeated below. Unlike layout 300, in the alternative layout 700, the active region 204 does not have a fixed width WP, but rather is a segment providing transistor channel regions for pull-up transistors PU-1 and PU-2, the width of which is extended to a larger width WP' (WP' > WP). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). Depending on the performance requirements of the device, the width WN may also be selected to be less than or greater than the width WP, but must be less than the width WP'. By providing wider channel regions for pull-up transistors PU-1 and PU-2, and narrower channel regions for the read port transfer gate transistor R-PG, the VDDR of the SRAM device can be improved, for example, by increasing it by about 30mV to about 80mV. In some embodiments, the ratio of WP' to WP (WP' / WP) ranges from approximately 1 to 1.25 (1 < WP' / WP < 1.25). This range is not arbitrary or stochastic. If the ratio is not less than about 1.25, the channel widths of pull-up transistors PU-1 and PU-2 may be too large and too close to the adjacent active region 202; if the ratio is not greater than 1, the current drive capability of pull-up transistors PU-1 and PU-2 may not be stronger than that of the read port transfer gate transistor R-PG, thus failing to improve VDDR. In some embodiments, the width difference (WP-WP') may range from about 2 nanometers to about 10 nanometers. In the illustrated embodiment, the bends in the active region 204 are located on both sides of the active region 204. Each bend in the active region 204 is located along the direction X between the gate structure of the pull-up transistor PU-2 and the gate structure of the read port transmission transistor R-PG, for example, at the midpoint of the two gate structures, or below the corresponding CPODE feature.

[0045] Figure 15 illustrates an alternative layout 800 for the SRAM array, which is obtained by modifying the alternative layout 400 in Figure 10. Many aspects of the alternative layout 800 are the same as those of the alternative layout 400 shown in Figure 10. Similar elements appearing in Figures 10 and 15 are numbered the same, and the details of these elements will not be repeated below. Unlike the alternative layout 400, in the alternative layout 800, the active region 204 does not have a fixed width WP, but rather is a segment providing transistor channel regions for pull-up transistors PU-1 and PU-2, the width of which is extended to a larger width WP' (WP' > WP). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). Depending on the performance requirements of the device, the width WN may also be selected to be less than or greater than the width WP, but must be less than the width WP'. By providing wider channel regions for pull-up transistors PU-1 and PU-2, and narrower channel regions for the read port transfer gate transistor R-PG, the VDDR of the SRAM device can be improved, for example, by increasing it by about 30mV to about 80mV. In some embodiments, the ratio of WP' to WP (WP' / WP) ranges from approximately 1 to 1.25 (1 < WP' / WP < 1.25). This range is not arbitrary or stochastic. If the ratio is not less than about 1.25, the channel widths of pull-up transistors PU-1 and PU-2 may be too large and too close to the adjacent active region 202; if the ratio is not greater than 1, the current drive capability of pull-up transistors PU-1 and PU-2 may not be stronger than that of the read port transfer gate transistor R-PG, thus failing to improve VDDR. In some embodiments, the width difference (WP-WP') may range from about 2 nanometers to about 10 nanometers. In the illustrated embodiment, the bends in the active region 204 are located on both sides of the active region 204. Each bend in the active region 204 is located along the direction X between the gate structure of the pull-up transistor PU-2 and the gate structure of the read port transmission transistor R-PG, for example, at the midpoint of the two gate structures.

[0046] Figure 16 illustrates an alternative layout 800' of the SRAM array, which is a variant of the alternative layout 800 in Figure 15. Unlike the alternative layout 800, in the alternative layout 800', all bends in the active region 204 are located on one side of the active region 204, facing the adjacent active region 202. On the other side of the active region 204, facing the adjacent active region 202, there are no bends.

[0047] Figure 17 illustrates an alternative layout 800'' of the SRAM array, which is a variant of the alternative layout 800 in Figure 15. Unlike the alternative layout 800, in the alternative layout 800'', all bends in the active regions 204 are located on the same side of the active regions 204, facing the adjacent active regions 204. The other side of the active regions 204, facing the adjacent active region 202, has no bends. The choice of alternative layouts 800, 800', and 800'' depends primarily on the distance requirements between adjacent active regions of the same or different types, especially when design rules impose restrictions on the minimum distance between adjacent active regions of the same or different types.

[0048] Figure 18 illustrates an alternative layout 900 for the SRAM array, which is obtained by modifying layout 300 in Figure 6. Many aspects of the alternative layout 900 are the same as those of layout 300 shown in Figure 6. For clarity and consistency, similar elements appearing in Figures 6 and 18 are numbered the same, and the details of these elements will not be repeated below. Unlike layout 300, in the alternative layout 900, the active region 204 does not have a fixed width WP, but rather is a segment providing transistor channel regions for pull-up transistors PU-1 and PU-2, the width of which is a smaller width WP' (WP > WP'). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). Depending on the performance requirements of the device, the width WN may also be selected to be less than or greater than the width WP, but must be greater than the width WP'. By providing narrower channel regions for pull-up transistors PU-1 and PU-2, and a larger channel region for the read port transfer gate transistor R-PG, the minimum operating voltage (Vmin) of the SRAM device can be improved. In some embodiments, the ratio of width WP' to width WP (WP' / WP) may range from about 0.75 to about 1 (0.75 < WP' / WP < 1). This range is not arbitrary or determined arbitrarily. If the ratio is not greater than about 0.75, the channel widths of pull-up transistors PU-1 and PU-2 may be too small to provide sufficient current drive capability; if the ratio is greater than 1, the current drive capability of the read port transfer gate transistor R-PG may not be stronger than that of pull-up transistors PU-1 and PU-2, and the voltage Vmin cannot be improved. In some embodiments, the width difference (WP-WP') may range from about 2 nanometers to about 8 nanometers. In the illustrated embodiment, all bends of the active region 204 are located on one side of the active region 204, which faces the adjacent active region 202. On the other side of active region 204, facing the adjacent active region 204, there is no bend. Each bend of active region 204 is located along direction X between the gate structure of pull-up transistor PU-2 and the gate structure of read port transmission transistor R-PG, for example, at the midpoint of the two gate structures.

[0049] Figure 19 illustrates an alternative layout 1000 for the SRAM array, which is obtained by modifying the alternative layout 400 in Figure 10. Many aspects of the alternative layout 1000 are the same as those of the alternative layout 400 shown in Figure 10. For clarity and consistency, similar elements appearing in Figures 10 and 19 are numbered the same, and the details of these elements will not be repeated below. Unlike the alternative layout 400, in the alternative layout 1000, the active region 204 does not have a fixed width WP, but rather is a segment providing transistor channel regions for pull-up transistors PU-1 and PU-2, the width of which has a smaller width WP' (WP > WP'). To further implement this embodiment, the width WN of the active region 202 is equal to the width WP (WN = WP). Depending on the performance requirements of the device, the width WN may also be selected to be less than or greater than the width WP, but must be greater than the width WP'. By providing narrower channel regions for pull-up transistors PU-1 and PU-2, and a larger channel region for the read port transfer gate transistor R-PG, the minimum operating voltage (Vmin) of the SRAM device can be improved. In some embodiments, the ratio of width WP' to width WP (WP' / WP) may range from about 0.75 to about 1 (0.75 < WP' / WP < 1). This range is not arbitrary or determined arbitrarily. If the ratio is not greater than about 0.75, the channel widths of pull-up transistors PU-1 and PU-2 may be too small to provide sufficient current drive capability; if the ratio is greater than 1, the current drive capability of the read port transfer gate transistor R-PG may not be stronger than that of pull-up transistors PU-1 and PU-2, and the voltage Vmin cannot be improved. In some embodiments, the width difference (WP-WP') may range from about 2 nanometers to about 8 nanometers. In the illustrated embodiment, all bends of the active region 204 are located on one side of the active region 204, which faces the adjacent active region 202. On the other side of active region 204, facing the adjacent active region 204, there is no bend. Each bend of active region 204 is located along direction X between the gate structure of pull-up transistor PU-2 and the gate structure of read port transmission transistor R-PG, for example, at the midpoint of the two gate structures.

[0050] Figure 20 illustrates an alternative layout 1000' of the SRAM array, which is a variant of the alternative layout 1000 in Figure 19. Unlike the alternative layout 1000, in the alternative layout 1000', the bends of the active region 204 are located on both sides of the active region 204.

[0051] Figure 21 illustrates an alternative layout 1000'' of the SRAM array, which is a variation of the alternative layout 1000 in Figure 19. Unlike alternative layout 1000, in alternative layout 1000'', all bends in the active regions 204 are located on the same side of the active regions 204, facing the adjacent active regions 204. The other side of the active regions 204, facing the adjacent active regions 202, has no bends. The choice of alternative layout 1000, alternative layout 1000', and alternative layout 1000'' depends primarily on the distance requirements between adjacent active regions of the same or different types, especially when design rules impose restrictions on the minimum distance between adjacent active regions of the same or different types.

[0052] To support fine-tuning of SRAM device performance by introducing variable active region widths (e.g., WP and WP' in Figures 12 to 21), it is necessary to ensure that transistors have sufficient performance margin (design margin), particularly for p-type transistors formed on p-type active regions. In view of this requirement, this disclosure implements a modified GAA transistor manufacturing method that improves the current drive capability of the GAA transistor. Therefore, this improvement allows the active region width to be varied without compromising the transistor's current drive capability. The manufacturing process will now be described in detail, with reference to the following figures. In this regard, Figure 22 is a flowchart illustrating a method 2000 for forming a semiconductor device from a work-in-progress (WIP) according to an embodiment of this disclosure. Method 2000 is merely an example and is not intended to limit this disclosure to what is shown in method 2000. Additional steps may be provided before, during, and after method 2000, and certain steps may be replaced, deleted, or rearranged to suit other embodiments of the method. For simplicity, not all steps will be described in detail herein. Method 2000 will be described in conjunction with Figures 23 to 42, which are segmental cross-sectional views of the semi-finished structure 3000 at different stages of the manufacturing process, according to an embodiment of method 2000 in Figure 22. Since the semi-finished structure 3000 will be manufactured into a semiconductor device or semiconductor structure, such as IC device 10 (including a memory array containing SRAM cells 100), the semi-finished structure 3000 (WIP structure 3000) may, as needed, be referred to herein as a semiconductor device 3000 or a memory device 3000.

[0053] According to Figures 22 and 23, method 2000 includes forming alternating semiconductor layer stacks 3004 on a WIP structure 3000 in block 2002. As shown in Figure 23, the WIP structure 3000 includes a substrate 3002. The substrate 3002 can be implemented as substrate 12 in the IC device 10 described above. In some embodiments, substrate 3002 can be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 3002 can have various doping configurations depending on design requirements, as is known in the art. In the case of a p-type semiconductor device, n-type doping profiles (i.e., n-type wells) may be formed on substrate 3002. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In the case of an n-type semiconductor device, p-type doping profiles (i.e., p-type wells) may be formed on substrate 3002. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping methods may include ion implantation dopant and / or diffusion processes. The substrate 3002 may also include other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), germanium-tin (GeSn), or diamond. Alternatively, the substrate 3002 may include compound semiconductors and / or alloy semiconductors. Furthermore, the substrate 3002 may selectively include an epitaxial layer (epi layer), which may be strain-treated to enhance performance, and may include silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structures, and / or have other suitable enhancing features.

[0054] In some embodiments, the stack 3004 above the substrate 3002 includes a sacrificial layer 3006 interleaved with a channel layer 3008 containing a first semiconductor, the sacrificial layer 3006 containing a second semiconductor. Alternatively, the sacrificial layer 3006 and the channel layer 3008 are arranged alternately. The composition of the first semiconductor and the second semiconductor may be different. In some embodiments, the sacrificial layer 3006 comprises silicon germanium (SiGe) or germanium tin (GeSn), while the channel layer 3008 comprises silicon (Si). It should be noted that the sacrificial layer 3006 and the channel layer 3008 are each arranged in three alternating layers, as shown in FIG10, which is for illustrative purposes only and is not intended to exceed the scope specifically described in the claim. It is understood that any number of epitaxial layers can be formed in the stack 3004. The number of layers depends on the desired number of channel layers in the semiconductor device 3000. In some embodiments, the number of channel layers 3008 is between 2 and 10.

[0055] The sacrificial layer 3006 and channel layer 3008 in stack 3004 can be deposited using molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes. As previously described, in at least some examples, the sacrificial layer 3006 comprises an epitaxially grown silicon-germanium (SiGe) layer, while the channel layer 3008 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 3006 and channel layer 3008 are substantially dopant-free (i.e., have an external dopant concentration ranging from about 0 atoms / cm³ to about 1 x 10¹⁷ atoms / cm³), for example, without intentional doping during the epitaxial growth process of stack 3004.

[0056] According to Figures 22 and 24, method 2000 includes forming a fin structure 3012 from a stack 3004 and a substrate 3002 in block 2004. In some embodiments, the two fin structures 3012 shown in Figure 24 may be implemented as two active regions 202 and 204 in an SRAM cell 100. To pattern the stack 3004, a hard mask layer may be deposited on the stack 3004 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed on the pad oxide layer. The fin structure 3012 can be patterned from the stack 3004 and the substrate 3002 using lithography and etching processes. Lithography processes may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, etching processes may include dry etching (e.g., reactive ion etching (RIE etching)), wet etching, and / or other etching methods. As shown in FIG24, in the etching process of block 2004, trenches extending vertically through a portion of the stack 3004 and the substrate 3002 are formed. These trenches define fin structures 3012. In some embodiments, dual patterning or multiple patterning processes may be used to define fin structures having, for example, smaller spacing than that achievable with a single direct lithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using a lithography process. Subsequently, spacers are formed next to the patterned material layer using a self-aligned process. After removing the material layers, the remaining spacers or mandrels can be used to pattern the fin structure 3012 by etching a portion of the stack 3004 and the substrate 3002. As shown in FIG24, the fin structure 3012, which includes a sacrificial layer 3006 and a channel layer 3008, extends vertically in the Z direction and longitudinally in the X direction. Each fin structure 3012 includes a base fin structure 3012B, which is patterned from the substrate 3002 and the patterned stack 3004, and the patterned stack 3004 is located directly above the base fin structure 3012B.

[0057] Referring again to Figures 22 and 24, method 2000 includes forming an isolation structure 3014 around the base fin structure 3012B of the fin structure 3012 in block 2006. This isolation structure 3014 can be implemented as the isolation structure 18 in the aforementioned IC device 10. In some embodiments shown in Figure 24, the isolation structure 3014 is located on the sidewall of the base fin structure 3012B. In some embodiments, the isolation structure 3014 can be formed in a trench to isolate the fin structure 3012 from adjacent fin structures. The isolation structure 3014 can also be referred to as a shallow trench isolation (STI) structure 3014. For example, in some embodiments, a dielectric layer is first deposited on the substrate 3002, and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low dielectric constant dielectric layer, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited using chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, through chemical mechanical planarization (CMP). The planarized dielectric layer is then further recessed or pulled back using dry etching, wet etching, and / or combinations thereof to form the STI structure 3014 shown in Figure 24. After recessing, the fin structure 3012 is higher than the STI structure 3014, while the base fin structure 3012B is embedded or buried within the STI structure 3014.

[0058] Referring to Figures 22 and 25, method 2000 includes forming a hard mask layer 3015 over the STI structure 3014 and around the top portion of the base fin structure 3012B in block 2008. The hard mask layer 3015 may be implemented as the hard mask layer 50 shown in Figures 7B and 11. The composition of the hard mask layer 3015 differs from that of the STI structure 3014 to ensure that they can be selectively etched without materially damaging each other. In some embodiments, the STI structure 3014 comprises an oxide, and the hard mask layer 3015 comprises a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride). For example, in some embodiments, a nitride-containing material is first deposited on the STI structure 3014, and trenches are filled with the nitride. In various examples, nitride-containing materials can be deposited using chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited nitride-containing material is then thinned and planarized, for example, through chemical mechanical planarization (CMP). The planarized nitride-containing material is further recessed or rolled back using dry etching, wet etching, and / or combinations thereof to form a hard mask layer 3015. After rollback, the fin structure 3012 protrudes above the hard mask layer 3015, while the base fin structure 3012B is embedded or buried within the combination of the STI structure 3014 and the hard mask layer 3015.

[0059] Referring to Figures 22 and 26-27, method 2000 includes forming a dummy gate stack 3020 above the channel region 3012C of the fin structure 3012 in block 2010. The dummy gate stack 3020 serves as a reserved location for undergoing various processing steps and will be removed and replaced by a functional gate structure in subsequent processes. In some embodiments shown in Figure 27, which is a cross-sectional view taken along section line DD in Figure 26, the dummy gate stack 3020 is formed above the fin structure 3012, and the fin structure 3012 may be divided into a channel region 3012C located below the dummy gate stack 3020, and a source / drain region 3012SD not located below the dummy gate stack 3020. The channel region 3012C is adjacent to the source / drain 3012SD. As shown in Figure 27, the channel region 3012C is located between the two source / drain regions 3012SD and extends along the direction X.

[0060] The formation of the dummy gate stack 3020 may include depositing and patterning layers within the dummy gate stack 3020. Referring to FIG26, the dummy dielectric layer 3016, the dummy electrode layer 3018, and the gate top hard mask layer 3022 may be uniformly deposited over the WIP structure 3000. The dummy dielectric layer 3016 may be formed on the fin structure 3012 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or other suitable processes. In some cases, the dummy dielectric layer 3016 may comprise silicon oxide. Subsequently, the dummy electrode layer 3018 may be deposited on the dummy dielectric layer 3016 using a CVD process, an ALD process, or other suitable processes. In some cases, the dummy electrode layer 3018 may comprise polycrystalline silicon. For patterning, the gate-top hard mask layer 3022 can be deposited on the dummy electrode layer 3018 using CVD, ALD, or other suitable processes. For example, the patterning process may include lithography (e.g., lithography or electron beam lithography) and etching. The lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The lithography process forms a patterned photoresist layer. This patterned photoresist layer then serves as an etching mask, used in the etching process to pattern the gate-top hard mask layer 3022, the dummy electrode layer 3018, and the dummy dielectric layer 3016. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some implementations, the gate top hard mask layer 3022 may include a silicon oxide layer 3023 and a silicon nitride layer 3024 on the silicon oxide layer 3023. As shown in FIG27, the dummy gate stack 3020 is patterned so that it is located only above the channel region 3012C and not above the source / drain region 3012SD.

[0061] Referring to Figures 22 and 28, method 2000 includes depositing a gate spacer layer 3026 on a WIP structure 3000, including over a dummy gate stack 3020, in block 2012. In some embodiments, the gate spacer layer 3026 is deposited conformally on the WIP structure 3000, including on the top surface and sidewalls of the dummy gate stack 3020. For simplicity, the term "conformally" is used herein to refer to a layer of material having a uniform thickness across the various regions. The gate spacer layer 3026 may be a single layer or multiple layers. At least one layer of the gate spacer layer 3026 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 3026 can be deposited on top of the dummy gate stack 3020 through processes such as CVD, subatmospheric CVD (SACVD), ALD, or other suitable processes.

[0062] Referring to Figures 22 and 29, method 2000 includes anisotropically recessing the source / drain region 3012SD of the fin structure 3012 in block 2014 to form a source / drain trench 3028. This anisotropic etching may include dry etching or a suitable etching process that etches a portion of the source / drain region 3012SD and the substrate 3002. The resulting source / drain trench 3028 extends vertically through the depth of the stack 3004 and partially into the substrate 3002. Examples of dry etching processes for block 2014 may use oxygen-containing gases, fluorine-containing gases (e.g., carbon tetrafluoride, sulfur hexafluoride, methane difluoride, methane trifluoride, and / or ethylene hexafluoride), chlorine-containing gases (e.g., chlorine, methane trichloride, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (e.g., hydrobromic acid and / or methane tribromide), iodine-containing gases, other suitable gases, and / or plasma, and / or combinations thereof. As shown in Figure 29, the source / drain region 3012SD of the fin structure 3012 is recessed, exposing the sidewalls of the sacrificial layer 3006 and the channel layer 3008. The source / drain trench 3028 is defined to include the bottom surface and lower sidewalls in the substrate 3002, as it extends below the stack 3004 and into the substrate 3002.

[0063] Referring to Figures 22 and 30, method 2000 includes, in block 2016, releasing multiple layers of channel layers 3008 in the channel region as channel components 3008. These channel components 3008 may correspond to nanostructures 26 in the IC device 10. Depending on the design, the channel components 3008 may be presented as nanowires, nanosheets, or other nanostructures. After the source / drain trench 3028 is formed, sacrificial layers 3006 alternating between the channel layers 3008 in the channel region 3012C are selectively removed. The selective removal of the sacrificial layers 3006 releases the channel layers 3008, forming the channel components 3008 shown in Figure 30. The selective removal of the sacrificial layers 3006 creates voids between and around adjacent channel components 3008. This selective removal of the sacrificial layers 3006 can be achieved through selective dry etching, selective wet etching, or other selective etching processes. This example of a selective dry etching process may involve the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Another example of a selective wet etching process may involve APM etching (e.g., an ammonia-hydrogen peroxide-water mixture).

[0064] Referring to Figures 22 and 31, method 2000 includes depositing a dielectric dummy layer 3030 around channel components 3008 and over source / drain trenches 3028 in block 2018. The dummy layer 3030 may comprise silicon oxide and may be deposited using plasma-enhanced chemical vapor deposition (PECVD) or ALD. The dummy layer 3030 fills the voids between channel components 3008 and covers the ends of the sidewalls of channel components 3008. Furthermore, the dummy layer 3030 is in direct contact with the sidewalls of the gate spacer layer 3026 and the top surface of the substrate 3002.

[0065] Referring to Figures 22 and 32, method 2000 includes forming an internal spacer recess 3032 in block 2020. A dummy layer 3030 is selectively and partially recessed to form the internal spacer recess 3032, while the gate spacer layer 3026, the dummy gate stack 3020, the exposed portion of the substrate 3002, and the channel layer 3008 are substantially unetched. In one embodiment, when the channel layer 3008 is substantially composed of silicon (Si) and the dummy layer 3030 is composed of silicon oxide, the selective recessing of the dummy layer 3030 can be performed using a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process may use carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or mixtures thereof. An exemplary selective wet etching process may use hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0066] Referring to Figures 22 and 33, method 2000 includes depositing an internal spacer layer 3034 on an internal spacer recess 3032 in block 2022. The composition of the internal spacer layer 3034 differs from that of the dielectric dummy layer 3030 to ensure that they can be selectively etched without causing substantial damage to the other layer. In some embodiments, the internal spacer layer 3034 may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON). In some embodiments, the internal spacer layer 3034 may be deposited using CVD or ALD processes.

[0067] Referring to Figures 22 and 34, method 2000 includes etching back the internal spacer layer 3034 in block 2024 to form an internal spacer 3036 over the internal spacer recess 3032. In some embodiments, the etching back in block 2024 may include using a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. An exemplary dry etching process may use boron chloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or mixtures thereof. In the illustrated embodiment, the internal spacer 3036 extends horizontally and is located directly below the dummy gate stack 3020. Alternatively, the internal spacer 3036 may be substantially held below the gate spacer layer 3026 without extending to a position below the dummy gate stack 3020.

[0068] Referring to Figures 22 and 35, method 2000 includes forming a source / drain feature 3050 on a source / drain region 3012SD in block 2028. The source / drain feature 3050 may be implemented as a source / drain feature 16 in the IC device 10. Although not explicitly shown, method 2000 may include a cleaning process to clean the surface of the WIP structure 3000 prior to the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide, or a mixture of deionized water, hydrochloric acid, and hydrogen peroxide, or a mixture of sulfuric acid and hydrogen peroxide (SPM), and hydrofluoric acid for removing oxides. A dry cleaning process may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which is then extracted for removal.

[0069] In some embodiments, the source / drain feature 3050 includes a bottom epitaxial feature 3052 and a main epitaxial feature 3054 located above the bottom epitaxial feature 3052. The source / drain feature 3050 may be n-type or p-type. When the source / drain feature 3050 is n-type, the bottom epitaxial feature 3052 may include undoped silicon (Si) or undoped silicon germanium (SiGe), while the main epitaxial feature 3054 may include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When the source / drain feature 3050 is p-type, the bottom epitaxial feature 3052 may comprise undoped silicon (Si) or undoped silicon germanium (SiGe), while the main epitaxial feature 3054 may comprise silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or a combination thereof. As used herein, "undoped semiconductor material" means that it is considered undoped when it is not intentionally doped. In some alternative embodiments, the bottom epitaxial feature 3052 may contain corresponding dopant to reduce leakage current into the substrate 3002. For example, in an n-type source / drain feature 3050, the bottom epitaxial feature 3052 may comprise a p-type dopant, such as boron (B). As another example, in a p-type source / drain feature 3050, the bottom epitaxial feature 3052 may comprise an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source / drain feature 3050 can be fabricated using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain feature 3050 can be achieved through in-situ doping.

[0070] As shown in Figures 22 and 36 to 41, method 2000 includes block 2030, which replaces the dummy gate stack 3020 and dummy layer 3030 with gate structure 3060 (also referred to as metal gate structure 3060). Operation of block 2030 may include the following steps: depositing a contact etch stop layer 3056 (CESL 3056) over the source / drain feature 3050 (as shown in Figure 36), depositing an interlayer dielectric layer 3058 (ILD layer 3058) over the CESL 3056 (as shown in Figure 36), removing the dummy gate stack 3020 (as shown in Figure 37), removing the dummy layer 3030 (as shown in Figures 38 and 39), and depositing gate structure 3060 to cover each channel component 3008 (as shown in Figures 40 and 41). Referring to Figure 36, a CESL 3056 is deposited on a WIP structure 3000, including source / drain features 3050. The CESL 3056 may comprise silicon nitride or aluminum nitride. In some embodiments, the CESL 3056 may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). Next, an ILD layer 3058 is deposited over the CESL 3056. In some embodiments, the ILD layer 3058 comprises, for example, tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silicate such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 3058 may be deposited using chemical vapor deposition (CVD), flowable CVD (FCVD), spin coating, or other suitable deposition techniques. After the ILD layer 3058 is deposited, the WIP structure 3000 can be planarized to expose the dummy gate stack 3020. For example, the planarization process can include chemical mechanical planarization (CMP). Once the dummy gate stack 3020 is exposed, its removal can be performed. Removal of the dummy gate stack 3020 can include one or more selective etching processes that selectively target the material of the dummy gate stack 3020. For example, the removal of the dummy gate stack 3020 can be accomplished through selective wet etching, selective dry etching, or a combination of both, processes that selectively etch the material of the dummy gate stack 3020.

[0071] After removing the dummy gate stack 3020, the dummy layer 3030 located in the channel region 3012C is exposed. A separate etching process can be performed to selectively remove the dummy layer 3030 in the channel region 3012C. For example, a selective wet etching process or a selective dry etching process can be performed to remove the dummy layer 3030. One example is a selective wet etching process, which can use diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Another example is a selective dry etching process, which can use anhydrous hydrofluoric acid (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. Selective etching of the dummy layer 3030 etches the channel component 3008 at a lower rate, thus protecting the integrity of the channel component 3008. The hard masking layer 3015 also protects the STI feature 3014, preventing etch loss during the removal of the dummy layer 3030. The presence of the hard masking layer 3015 is one of the distinguishing features between this method and conventional methods, especially during the formation of the GAA transistor. After selectively removing the dummy layer 3030, the channel component 3008 in the channel region 3012C is exposed again, as shown in Figures 38 and 39.

[0072] After the channel component 3008 is released, as shown in Figures 40 and 41, a gate structure 3060 is formed and covers each channel component 3008. The gate structure 3060 includes a gate dielectric layer 3062, which is located between the channel component 3008 and the substrate 3002 in the channel region 3012C, and a gate electrode layer 3064, which is located on top of the gate dielectric layer 3062.

[0073] The gate dielectric layer 3062 may include an interface layer and a high-k dielectric layer located on the interface layer. The interface layer may include dielectric materials such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the high-k dielectric layer may also comprise other high-k dielectric materials, such as titanium dioxide (TiO2), hafnium cobalt oxide (HfZrO), tantalum pentoxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), chromium dioxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium chromium oxide (HfLaO), chromium silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The high-k dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate dielectric layer 3062 also covers the sidewalls of the internal spacer 3036.

[0074] The gate electrode layer 3064 of the gate structure 3060 may include a multilayer structure, such as various combinations of metal layers with selected work function metals (referred to as work function metal layers, WFM layers) to enhance device performance, as a padding layer, wetting layer, adhesion layer, metal alloy, or metal silicate. For example, the gate electrode layer 3064 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), rhodium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer 3064 may be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In some embodiments, a chemical mechanical planarization (CMP) process may be performed to remove excess metal, thereby providing a flat top surface for the gate structure 3060. The gate structure 3060 includes a portion located between channel components 3008 in the channel region 3012C. In some embodiments, the gate structure 3060 may be an n-type gate structure or a p-type gate structure. An n-type gate structure includes an n-type work function metal layer closer to the channel component 3008; while a p-type gate structure includes a p-type work function metal layer closer to the channel component 3008.

[0075] Figure 42 shows a plan view of one of the channel components 3008 at the end of the gate replacement process in some embodiments. The channel component 3008, as a nanostructure (e.g., a nanosheet or nanowire), connects opposing source / drain features 3050 and provides channel regions for the respective transistors. In some embodiments of the gate replacement process, a dummy gate stack is initially formed as a reserved location and subsequently replaced by a functional gate structure. After the epitaxial source / drain features are formed, sacrificial material between the nanostructures in the GAA transistor is removed. Ideally, due to the different material compositions, there should be a high etch selectivity between the sacrificial material (e.g., silicon-germanium) and the nanostructure (e.g., silicon) to protect the nanostructure from etching loss during the removal of the sacrificial material. However, atoms other than silicon (e.g., germanium) in the sacrificial material may diffuse into the nanostructure as impurities during annealing processes (e.g., the annealing process used when forming the epitaxial source / drain features). The diffusion of these impurities reduces etch selectivity and can lead to etch loss of the nanostructure during the removal of the sacrificial material. For example, due to additional etch loss, the edges of the nanostructure may become uneven, exhibiting a curved profile. Therefore, the width of the channel component 3008 will differ at both ends (denoted as We) and at the center (denoted as Wc). This deviation may range from about 5% to about 50%, or proportionally, We / Wc may range from about 1.05 to about 1.5 (1.05 < We / Wc < 1.5). This significant curved profile at the edges of the nanostructure can lead to variations in the gate structure profile, resulting in inhomogeneities in device performance. In contrast, the technique disclosed herein replaces the sacrificial material with a dielectric dummy layer 3030 prior to the subsequent annealing process, thereby preventing the diffusion of impurities. Therefore, the channel component 3008 is released by removing the dielectric dummy layer 3030. The etch selectivity between the dielectric dummy layer 3030 and the channel component 3008 is significantly greater than that between the sacrificial layer 3006 and the channel component 3008. By design, the etch selectivity of the dielectric dummy layer 3030 to the channel component 3008 can exceed 10000:1, ensuring that the channel component 3008 remains substantially intact. Therefore, the width deviation between the ends and the center of the channel component is limited to within 5%, or proportionally, the We / Wc ranges from approximately 1 to 1.05 (1 < We / Wc < 1.05). Consequently, in some embodiments, the current drive capability is improved by 20% to 50%. This performance improvement provides additional design flexibility, allowing the width of the active region to be adjusted as described above.

[0076] In one exemplary aspect, this disclosure relates to a memory cell. The memory cell includes a first active region and a second active region. Each of the first and second active regions extends along a first direction. The memory cell also includes a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, which are arranged sequentially from the first gate structure to the fourth gate structure and along the first direction. Each of the first, second, third, and fourth gate structures extends along a second direction perpendicular to the first direction. These first, second, third, and fourth gate structures are configured to engage with the first active region to form first, second, third, and fourth transistors, respectively, for a memory cell write port, and the second and third gate structures further contact the second active region to form fifth and sixth transistors for the memory cell write port. The memory cell also includes a fifth gate structure extending along the second direction. The fifth gate structure is configured to contact the second active region to form a seventh transistor for the memory cell read port. The second active region has a first segment providing a channel region for a seventh transistor, and a second segment providing channel regions for a fifth and a sixth transistor. The first segment has a first width, and the second segment has a second width, which is different from the first width. In some embodiments, the first width is smaller than the second width. In some embodiments, the ratio of the first width to the second width ranges from approximately 0.75 to 1. In some embodiments, the first width is larger than the second width. In some embodiments, the ratio of the first width to the second width ranges from approximately 1 to 1.25. In some embodiments, the first active region has a third width, which is equal to either the first width or the second width. In some embodiments, the first, second, third, and fourth transistors are n-type transistors, while the fifth, sixth, and seventh transistors are p-type transistors. In some embodiments, the memory cell further includes an isolation structure disposed between the first active region and the second active region, and a hard mask layer disposed on the isolation structure. The hard mask layer and the isolation structure have different material compositions. In some embodiments, the second active region includes a first edge facing the first active region and a second edge away from the first active region, the second active region having a bend at the transition between the first segment and the second segment located on the first edge, and the second edge being flat. In some embodiments, the second active region includes a first edge facing the first active region and a second edge away from the first active region. The second active region has a first bend and a second bend at the transition between the first segment and the second segment. The first bend is located on the first edge, and the second bend is located on the second edge.

[0077] In another embodiment, this disclosure relates to a semiconductor device. The semiconductor device includes a write port for a memory cell, wherein the write port includes at least one pull-up (PU) transistor, one pull-down (PD) transistor, and one transmission gate (PG) transistor, and also includes a read port for the memory cell, wherein the read port includes a PG transistor. The PG transistor in the write port is an n-type transistor, and the PG transistor in the read port is a p-type transistor. Channel regions of the PD transistor in the write port and the channel regions of the PG transistor in the write port are disposed on a first active region. Channel regions of the PU transistor in the write port and the channel regions of the PG transistor in the read port are disposed on a second active region extending parallel to the first active region. The second active region has a variable width. In some embodiments, the first active region has a fixed width. In some embodiments, the second active region has a first segment corresponding to the channel region of the PG transistor in the read port and a second segment corresponding to the channel region of the PU transistor in the write port. The first segment is narrower than the second segment. In some embodiments, the width ratio of the first segment and the second segment ranges from approximately 0.75 to 1. In some embodiments, the second active region has a first segment corresponding to the channel region of the PG transistor in the read port and a second segment corresponding to the channel region of the PU transistor in the write port, wherein the first segment is wider than the second segment. In some embodiments, the width ratio of the first segment and the second segment ranges from approximately 1 to 1.25.

[0078] In another exemplary aspect, this disclosure relates to a memory device. The memory device includes: a first transfer gate (PG) transistor, a second PG transistor, a first pull-down (PD) transistor, and a second PD transistor, sharing a first active region extending along a first direction; a first pull-up (PU) transistor, a second PU transistor, and a read port transfer gate (R-PG) transistor, sharing a second active region extending along the first direction; and an isolation structure that contacts the gate structure of the first PG transistor and extends along a second direction perpendicular to the first direction. The second active region is divided into a first segment and a second segment by the isolation structure, and the first segment and the second segment have different widths. In some embodiments, the second segment provides a channel region for the first PU transistor, the second PU transistor, and the R-PG transistor. In some embodiments, the width of the second segment is greater than the width of the first segment. In some embodiments, the edges of the first segment and the second segment facing the first active region are aligned, while the relative edges of the first segment and the second segment facing the first active region are not aligned.

[0079] The foregoing has summarized features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0008] This disclosure is best understood from the following detailed description, which should be read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Figures 1A and 1B respectively show perspective and top views of memory device portions according to some embodiments of this disclosure. Figure 2 shows cross-sectional views of various layers of the memory device according to some embodiments of this disclosure. Figure 3 shows a circuit diagram of a dual-port SRAM cell according to some embodiments of this disclosure. Figures 4 and 5 show schematic layout diagrams of the dual-port SRAM cell in Figure 3 according to some embodiments of this disclosure. Figures 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 show schematic layout diagrams of SRAM arrays of the dual-port SRAM cell in Figure 3 according to other embodiments of this disclosure. Figures 7A, 7B, and 11 illustrate cross-sectional views of an SRAM array portion according to some embodiments of the present disclosure. Figure 22 illustrates a flowchart of a method for fabricating an integrated circuit having multiple SRAM cells according to some embodiments of the present disclosure. Figures 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, and 41 illustrate cross-sectional views during the process of fabricating an integrated circuit of SRAM cells according to the method in Figure 22, according to some embodiments of the present disclosure. Figure 42 illustrates a plan view of a channel element in a gate-all-around (GAA) transistor in an integrated circuit according to some embodiments of the present disclosure.

Claims

1. A memory unit, comprising: A first active region and a second active region, wherein both the first active region and the second active region extend longitudinally along a first direction; A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are arranged sequentially from the first gate structure to the fourth gate structure in the first direction. Each of the first, second, third, and fourth gate structures extends longitudinally along a second direction perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to connect with the first active region to form a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, for a write port of one of the memory cells. The second and third gate structures are further configured to connect with the second active region to form a fifth transistor and a sixth transistor for the write port of the memory cell. A fifth gate structure extends longitudinally along the second direction, and is configured to connect with the second active region to form a seventh transistor for a read port of one of the memory cells. The second active region has a first segment and a second segment. The first segment provides a channel region for the seventh transistor, and the second segment provides multiple channel regions for the fifth transistor and the sixth transistor. The first segment has a first width, and the second segment has a second width that is different from the first width.

2. The memory cell as claimed in claim 1, wherein the first width is smaller than the second width; wherein the ratio of the first width to the second width is approximately between 0.75 and 1.

3. The memory cell as claimed in claim 1, wherein the first width is greater than the second width; wherein the ratio of the first width to the second width is approximately between 1 and 1.

25.

4. The memory cell as described in claim 1, wherein the first active region has a third width, the third width being equal to the first width or the second width.

5. The memory cell as claimed in claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are n-type transistors, and the fifth transistor, the sixth transistor and the seventh transistor are p-type transistors.

6. The memory unit as described in claim 1, further comprising: An isolation structure is set between the first active area and the second active area; And a hard masking layer disposed on the isolation structure, wherein the hard masking layer and the isolation structure are composed of different materials.

7. The memory cell as claimed in claim 1, wherein the second active region includes a first edge facing the first active region and a second edge facing away from the first active region, the second active region including a bend located at the transition between the first segment and the second segment, the bend being located on the first edge, and the second edge being flat.

8. The memory cell as claimed in claim 1, wherein the second active region includes a first edge facing the first active region and a second edge facing away from the first active region, the second active region including a first bend and a second bend located at the transition between the first segment and the second segment, the first bend being located on the first edge and the second bend being located on the second edge.

9. A semiconductor device, comprising: A write port of a memory cell, wherein the write port includes at least one of a pull-up (PU) transistor, a pull-down (PD) transistor, and a transmission gate (PG) transistor; and a read port of the memory cell, wherein the read port includes a PG transistor, wherein: the PG transistor in the write port is an n-type transistor, the PG transistor in the read port is a p-type transistor, a channel region of the PD transistor in the write port and a channel region of the PG transistor in the write port are disposed on a first active region, a channel region of the PU transistor in the write port and a channel region of the PG transistor in the read port are disposed on a second active region, the second active region extending parallel to the first active region, and the second active region having a variable width.

10. The semiconductor device as claimed in claim 9, wherein the first active region has a fixed width.

11. The semiconductor device of claim 9, wherein the second active region has a first segment and a second segment, the first segment corresponding to the channel region of the PG transistor in the read port, the second segment corresponding to the channel region of the PU transistor in the write port, and the first segment being narrower than the second segment; wherein the width ratio of the first segment and the second segment is in the range of approximately 0.75 to 1.

12. The semiconductor device of claim 9, wherein the second active region has a first segment and a second segment, the first segment corresponding to the channel region of the PG transistor in the read port, the second segment corresponding to the channel region of the PU transistor in the write port, and the first segment being wider than the second segment; wherein the ratio of the first segment to the second segment is in the range of approximately 1 to 1.

25.

13. A memory device, comprising: A first transmission gate (PG) transistor, a second transmission gate (PG) transistor, a first pull-down (PD) transistor, and a second pull-down (PD) transistor share a first active region extending along a first direction; a first pull-up (PU) transistor, a second pull-up (PU) transistor, and a read port transmission gate (R-PG) transistor share a second active region extending along the first direction; and an isolation structure adjacent to a gate structure of the first PG transistor and extending longitudinally along a second direction perpendicular to the first direction, wherein the second active region is divided into a first segment and a second segment by the isolation structure, and the width of the first segment is different from the width of the second segment.

14. The memory device as claimed in claim 13, wherein the second segment provides a plurality of channel regions to the first PU transistor, the second PU transistor, and the R-PG transistor; wherein the width of the second segment is wider than the width of the first segment.

15. The memory device as claimed in claim 13, wherein the plurality of edges of the first segment and the second segment facing away from the first active region are aligned, while the plurality of edges of the first segment and the second segment facing the first active region are not aligned.

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