Memory apparatus and memory device with enhanced thermal conductivity and method of forming same

Abstract

This invention describes systems, apparatus, and methods related to memory devices having enhanced thermal conductivity. Embodiments of this technology may include adding thermal paths to one or more layers in a memory device structure, such as materials having a thermal conductivity value less than a threshold value. The added material provides a path for heat dissipation from the memory device.

Description

Technical Field

[0001] The present invention relates generally to electronic devices, and more particularly to memory devices having structures with enhanced thermal conductivity. Prior Art

[0002] A device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, a device may include a memory device such as a volatile memory device, a non-volatile memory device, or a combination thereof. Memory devices, such as dynamic random access memory (DRAM), utilize electrical energy to store and access data.

[0003] With technological advancements and increasing applications in embedded systems, the market is constantly seeking faster, more efficient, and smaller devices. To meet market demands, semiconductor devices are being pushed to their limits through various improvements. These improvements generally include increased circuit density, increased circuit capacity, higher operating speed, improved reliability, increased data retention, and other metrics. However, attempts to meet market demands by increasing bandwidth capacity, for example, are often limited by the thermal conductivity of the device's materials. Simple diagram description

[0004] FIG1 is a block diagram of an apparatus according to an embodiment of the present technology.

[0005] 2 illustrates a cross-sectional view of a device having a thermal path according to one or more embodiments of the present technology.

[0006] 3A illustrates a cross-sectional view of the formation of an isolation layer in a memory device structure according to one or more embodiments of the present technology.

[0007] 3B illustrates a cross-sectional view of the formation of local interconnects and wiring in a memory device structure according to one or more embodiments of the present technology.

[0008] 3C illustrates a cross-sectional view of the formation of a base dielectric layer of a memory device structure according to one or more embodiments of the present technology.

[0009] 4A illustrates a cross-sectional view of the formation of a cell structure in a base dielectric layer in a memory device structure according to one or more embodiments of the present technology.

[0010] 4B illustrates a cross-sectional view of the formation of an isolation region for a thermal path in a memory device structure according to one or more embodiments of the present technology.

[0011] 4C illustrates a cross-sectional view of the formation of a thermal path in a memory device structure according to one or more embodiments of the present technology.

[0012] 5A illustrates a cross-sectional view of the formation of a thermal path from a base dielectric layer and connected to an isolation layer in a memory device structure according to one or more embodiments of the present technology.

[0013] 5B illustrates a cross-sectional view of the formation of a thermal path through a base dielectric layer and connected to an isolation layer in a memory device structure according to one or more embodiments of the present technology.

[0014] 5C illustrates a cross-sectional view of a thermal path in a memory device according to one or more embodiments of the present technology.

[0015] 6A illustrates a cross-sectional view of the formation of a through-hole in a memory device structure according to one or more embodiments of the present technology.

[0016] 6B illustrates a cross-sectional view of the formation of a via in an end-of-line layer of a memory device structure according to one or more embodiments of the present technology.

[0017] 7 illustrates a cross-sectional view of thermal paths on a memory device connected to a logic circuit of an apparatus according to one or more embodiments of the present technology.

[0018] 8A is a flow chart illustrating an exemplary method for designing a thermal path for a memory device structure according to one or more embodiments of the present technology.

[0019] 8B is a flow chart illustrating an exemplary method for creating a thermal path in one or more layers of a memory device structure, according to one or more embodiments of the present technology.

[0020] 9 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Implementation Method

[0021] As described in more detail below, the technology disclosed herein relates to an apparatus, such as a memory device with enhanced thermal conductivity, a memory system, a system having a memory device, and related methods. Memory devices, such as dynamic random access memory (DRAM), include materials and structures configured to utilize electrical energy to store and access data. With the growth of high-performance computing, such as artificial intelligence, virtual reality, and machine learning, the bandwidth requirements for memory devices are increasing. However, the performance of conventional memory systems has been limited by the thermal conductivity of the materials used in memory devices.

[0022] Embodiments of the present technology can improve the thermal conductivity of a memory device by adding materials (e.g., aluminum oxide, aluminum nitride, etc.) to the memory device structure. The added materials can be more thermally conductive than the dielectric materials used within the memory device structure. Furthermore, the thermally conductive material can be added at targeted locations to provide a thermal path configured to transfer heat energy out of the memory device. For example, the thermally conductive material can be positioned on the same layer as the memory cells and adjacent to the memory cells. Furthermore, the thermally conductive materials can overlap across layers (e.g., aligned along a vertical line / direction), thereby providing a vertically coupled thermal or heat dissipation path. The resulting vertical heat dissipation path can utilize the rising nature of heat energy to improve heat dissipation efficiency and, when implemented in a stacked assembly, provide a new heat dissipation path for devices positioned at the bottom of the stack. Furthermore, when implemented in a circuit having a repeating pattern (such as in a memory array), the location of the thermally conductive material can also follow the repeating pattern, increasing heat dissipation from the overall device / assembly.

[0023] Furthermore, compared to conventional devices, thermally conductive materials can be added to areas previously occupied by dielectric materials. Thus, the embodiments described herein can replace prior dielectric materials (using, for example, thermally conductive electrical insulators such as aluminum nitride) to provide heat dissipation paths within conventional insulating structures.

[0024] In some embodiments, thermally conductive material may be added during the front-end-of-line (FEOL) fabrication phase. The FEOL layer may include an isolation layer interconnected with a complementary metal-oxide-semiconductor (CMOS) formation and local wiring. To form or add thermally conductive material during the FEOL fabrication phase, a base dielectric layer may be formed on the isolation layer. A cell structure (e.g., individual memory cells) may then be formed in the base dielectric layer. Adjacent to the cell structure, an isolation region for a thermal path may be formed in the base dielectric layer. The base dielectric layer may be used to electrically isolate the thermal path region from the surrounding circuitry and from the contacts, vias, and / or TSVs, such as by maintaining or forming vertical portions or walls surrounding the thermal path portion.

[0025] A thermal path can be formed in the dielectric layer at the thermal path region by adding a thermally conductive, non-conductive material (such as aluminum oxide or aluminum nitride). The thermal path can be formed by a spin-on coating process containing the thermally conductive material as a filler in the base dielectric layer. In some embodiments, the thermal path is formed by a combination of processes such as physical vapor deposition (PVD), molybdenum (MO), or cut metal dielectric (CMD) to form a thermally conductive layer as a functional film that is removed by a polishing process. The manufacturing process can be completed by performing a back-end-of-line (BEOL) process to form the wiring of the memory device.

[0026] As described in detail below, embodiments of the present technology can offer technical advantages over conventional technologies by providing an extended thermal path to improve device performance. For example, the cell area of ​​a typical memory device is approximately 50% of the total device area. The cell material has a relatively higher thermal conductivity than the dielectric films used in semiconductor manufacturing processes. A thermal path made of a material with a higher thermal conductivity than the cell material creates a path for heat energy to escape the device. Furthermore, the size, shape, and content of the thermally conductive material can be used to reduce mismatches in thermal conductivity across lateral directions / planes, thereby reducing potential warpage issues.

[0027] Embodiments of the present technology introduce a thermal path within a dielectric region to provide higher thermal conductivity while maintaining electrical integrity by: 1) using materials such as aluminum oxide and aluminum nitride to minimize electrical interaction with circuitry; 2) isolating the via / contact / TSV region to eliminate technical difficulties in forming the via / contact / TSV structure within the material used for the thermal path; and 3) using materials such as aluminum oxide and aluminum nitride to improve the thermal conductivity of the equivalent layer of the thermal path (e.g., to 6.7 W / m·K, an improvement of 22%, resulting in temperature reductions of, for example, 7.8% for single DRAM, 9% for dual DRAM, and 9.9% for triple DRAM). Embodiments of the present technology can be applied to semiconductors or other electrical devices, such as NAND flash memory, NOR flash memory, central processing units (CPUs), and graphics processing units (GPUs), that have one or more dielectrics positioned between circuit layers (e.g., CMOS layers). The various features described below can be combined to increase heat dissipation from circuit layers and across one or more dielectrics. Additionally or alternatively, embodiments of the present technology can be applied to various device applications, such as 3D DRAM, stacked wafer (WoW) 3D NAND memory, heterogeneous devices, and the like.

[0028] FIG1 is a block diagram of a device 100 according to an embodiment of the present technology. For example, device 100 may include a DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.), or a portion of such a DRAM comprising one or more dies / chips. In some embodiments, device 100 may include DDR-type synchronous DRAM (SDRAM) integrated on a single semiconductor chip or on multiple semiconductor chips.

[0029] Device 100 may include a memory cell array, such as memory array 150. Memory array 150 may include a plurality of memory banks (e.g., memory banks 0 through 15), and each memory bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and bit lines. Memory cells may include any of several different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, or the like. Selection of a word line WL may be performed by a row decoder 140, and selection of a bit line BL may be performed by a row decoder 145. Sense amplifiers (SAMPs) may be provided for corresponding bit lines BL and connected to at least one respective local I / O line pair (LIOT / B), which in turn may be coupled to at least one respective main I / O line pair (MIOT / B) via a transfer gate (TG) that may function as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing their operation.

[0030] Device 100 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus, respectively, to receive a command signal (CMD) and an address signal (ADDR). Device 100 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, data terminals DQ, RDQS, DBI, and DMI, and power supply terminals VDD, VSS, and VDDQ.

[0031] The command terminal and the address terminal can be supplied with an address signal and a memory bank address signal (not shown in FIG1 ) from the outside. The address signal and the memory bank address signal supplied to the address terminal can be transmitted to an address decoder 110 via a command / address input circuit 105 (e.g., a command circuit). The address decoder 110 can receive the address signals and supply a decoded column address signal (XADD) to the column decoder 140 and a decoded row address signal (YADD) to the row decoder 145. The address decoder 110 can also receive the memory bank address signal and supply the memory bank address signal to both the column decoder 140 and the row decoder 145.

[0032] The command and address terminals can be supplied with a command signal (CMD), an address signal (ADDR), and a chip select signal (CS) from a memory controller. The command signal can represent various memory commands from the memory controller (e.g., including access commands, which may include read commands and write commands). The chip select signal can be used to select device 100 to respond to the command and address provided to the command and address terminals. When an active chip select signal is provided to device 100, the command and address can be decoded and memory operations can be performed. The command signal can be provided as an internal command signal ICMD to a command decoder 115 via command / address input circuit 105. Command decoder 115 can include circuitry for decoding internal command signal ICMD to generate various internal signals and commands used to perform memory operations (e.g., a column command signal for selecting a word line and a row command signal for selecting a bit line). The command decoder 115 may further include one or more registers for tracking various counts or values, such as a count of refresh commands received by the apparatus 100 or self-refresh operations (eg, a self-refresh entry / exit sequence) performed by the apparatus 100 .

[0033] Read data can be read from memory cells in memory array 150 specified by a column address (e.g., an address provided with an action command) and a row address (e.g., an address provided with a read command). The read command can be received by command decoder 115, which can provide an internal command to input / output circuit 160, causing the read data to be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by read delay information RL, which can be programmed in device 100, for example, in a mode register (not shown in FIG. 1 ). The read delay information RL can be defined based on the number of clock pulses of the CK clock signal. For example, the read delay information RL can be the number of clock pulses of the CK signal at which the associated read data is provided after receiving the read command by device 100.

[0034] Write data can be supplied to data terminals DQ, DBI, and DMI. A write command can be received by command decoder 115, which can provide an internal command to input / output circuit 160. This allows the write data to be received by a data receiver in input / output circuit 160 and supplied to memory array 150 via input / output circuit 160 and read / write amplifier 155. The write data can be written to memory cells specified by column and row addresses. The write data can be supplied to the data terminals at a time defined by write delay information (WL). This write delay information (WL) can be programmed in device 100, for example, in a mode register (not shown in FIG. 1 ). The write delay information (WL) can be defined based on the number of clock pulses of the CK signal. For example, the write delay information (WL) can be the number of clock pulses of the CK signal after receiving a write command by device 100 and when the associated write data is received.

[0035] The power supply terminals can be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to an internal voltage generator circuit 170. Internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. Internal potential VPP can be used in row decoder 140, internal potentials VOD and VARY can be used in sense amplifiers included in memory array 150, and internal potential VPERI can be used in many other circuit blocks.

[0036] The power supply terminal may also be supplied with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 160 along with the power supply potential VSS. In one embodiment of the present technology, the power supply potential VDDQ may be the same as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 to prevent power supply noise generated by the input / output circuit 160 from propagating to other circuit blocks.

[0037] The clock terminal and the data clock terminal can be supplied with an external clock signal and a complementary external clock signal. External clock signals CK and CKF can be supplied to a clock input circuit 120 (e.g., an external clock circuit). The CK and CKF signals can be complementary. The complementary clock signals can have opposite clock levels and transition between opposite clock levels simultaneously. For example, when a clock signal is at a low clock level, a complementary clock signal is at a high clock level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0038] An input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by a clock / enable signal from the command decoder 115, an input buffer can receive the clock / enable signal. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICK. The internal clock signal ICK can be supplied to an internal clock circuit 130. The internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the internal clock signal ICK received from the command / address input circuit 105 and a clock enable (not shown in FIG. 1 ). For example, the internal clock circuit 130 can include a clock path (not shown in FIG. 1 ) that receives the internal clock signal ICK and provides various clock signals to the command decoder 115. The internal clock circuit 130 can further provide input / output (IO) clock signals. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining an output timing of read data and an input timing of write data.

[0039] Device 100 can be connected to any of several electronic devices, or a component thereof, that can utilize memory for temporary or permanent information storage. For example, a host device of device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, a router, etc.), a digital image, audio, and / or video recorder, a vehicle, an appliance, a toy, or any of several other products. In one embodiment, the host device can be directly connected to device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a networked connection or through an intermediary device).

[0040] Thermally conductive material may be added at one or more locations within the structure of device 100. The thermally conductive material may provide a thermal path configured to transfer thermal energy out of device 100. For example, the thermally conductive material may be located at the same layer as memory array 150 and adjacent to memory array 150.

[0041] FIG2 illustrates a cross-sectional view of a device (e.g., device 100 of FIG1 or a portion thereof) having a thermal path 206 according to one or more embodiments of the present technology. Thermal path 206 may be formed adjacent to a cell structure 202 and embedded in a base dielectric layer 204. In some embodiments, thermal path 206 is located in a non-cell portion of a memory array (e.g., memory array 150 of FIG1 ). In some embodiments, thermal path 206 may be disposed between a metal layer and a circuit / CMOS layer. For example, thermal path 206 may be disposed within a front-end-of-line (FEOL) layer. Thermal path 206 may comprise a thermally conductive, non-conductive material, such as aluminum oxide or aluminum nitride, that does not interfere with other circuitry. Thermal path 206 may provide a path for transferring heat energy away from base dielectric layer 204 and memory device structure 200. For example, thermal path 206 may be located above CMOS circuitry and provide a path for heat energy to flow upward from the CMOS circuitry. Additionally, the thermal path 206 may provide a path for removing thermal energy from the cellular structure 202. In some embodiments, the thermal path may be a continuous material 206. In some other embodiments, the thermal path may be formed to provide maximum heat transfer in a desired direction.

[0042] Figures 3A through 6B illustrate various stages or structures formed during a manufacturing process for the apparatus 100 of Figure 1. Figure 3A illustrates a cross-sectional view of the formation of an isolation layer in a memory device structure 300 according to one or more embodiments of the present technology. The isolation layer may include one or more trenches 304 formed in a substrate 302 (e.g., a silicon wafer).

[0043] 3B illustrates a cross-sectional view of the formation of CMOS 308, local interconnects 306, and wiring (not shown) in a memory device structure 330 according to one or more embodiments of the present technology. CMOS 308, local interconnects 306, and wiring may be formed around or across one or more trenches 304. Various circuit components may be formed by depositing or forming components on an isolation layer.

[0044] FIG3C illustrates a cross-sectional view of the formation of a base dielectric layer (e.g., base dielectric layer 204) of a memory device structure 360 ​​according to one or more embodiments of the present technology. Base dielectric layer 204 is formed on substrate 302 (e.g., on an isolation layer). Base dielectric layer 204 may be formed over and / or around CMOS 308, local interconnects 306, and wiring (not shown). Base dielectric layer 204 may include an electrically insulating material, such as silicon oxide.

[0045] FIG4A illustrates a cross-sectional view of the formation of a cell structure (e.g., cell structure 202) in a base dielectric layer 204 in a memory device structure 400 according to one or more embodiments of the present technology. Cell structure 202 can be formed in base dielectric layer 204. For example, cell structure 202 can be formed by removing portions of base dielectric layer 204 to form a cavity or base shape, depositing metal materials, dopants, and / or circuit components within the cavity, masking, patterning, or a combination thereof. In some embodiments, such as for DRAM, cell structure 202 can include capacitor-based circuitry.

[0046] FIG4B illustrates a cross-sectional view of the formation of an isolation region 432 for a thermal path in a memory device structure 430 according to one or more embodiments of the present technology. The isolation region 432 can be formed in the base dielectric layer 204, such as by removing or etching a targeted portion of the base dielectric layer 204. In practice, the isolation region 432 can correspond to a cavity or recess later occupied by the thermal path 206 of FIG2 . The isolation region 432 can be separated from the cell structure 202 of FIG4A along a lateral direction. In some embodiments (not shown), the isolation region 432 can be formed over a through-silicon via (TSV) or a thermal via. The thermal path's isolation region 432 can be isolated from areas designated for other circuit components, such as contacts, vias, and / or TSVs, in the base dielectric layer 204.

[0047] FIG4C illustrates a cross-sectional view of the formation of a thermal path (e.g., thermal path 206) in a memory device structure 460 according to one or more embodiments of the present technology. Thermal path 206 can be formed by filling or depositing a thermally conductive material in isolation region 432 of FIG4B in base dielectric layer 204. Thermal path 206 can be formed in base dielectric layer 204 using a highly thermally conductive and / or electrically non-conductive material, such as aluminum oxide, aluminum nitride, etc. In some embodiments, thermal path 206 can be formed by a spin-on coating process, a deposition process, a polishing process, or a combination thereof.

[0048] Figures 5A and 5B illustrate various embodiments of thermal path 206. Figure 5A illustrates a cross-sectional view of the formation of a thermal path 206a extending from base dielectric layer 204 and connected to substrate 302 in a memory device structure 500 according to one or more embodiments of the present technology. Thermal path 206 can extend from base dielectric layer 204 up to and / or into the isolation layer. For example, isolation region 432 in Figure 4B can have an additional extension that exposes a portion of substrate 302. The additional extension within the cavity can be comprised of thermally conductive and / or non-conductive material, thereby forming thermal path 206a having an extension extending toward and / or contacting substrate 302. In some embodiments, base dielectric layer 204 can be formed or re-deposited over thermal path 206, thereby surrounding a top portion of thermal path 206a.

[0049] FIG5B illustrates a cross-sectional view of the formation of a thermal path 206b through the base dielectric layer 204 and connected to the substrate 302 in a memory device structure 530 according to one or more embodiments of the present technology. The thermal path 206b may extend through a portion or the entire base dielectric layer 204. For example, the isolation region 432 in FIG4B may have an additional extension that exposes a portion of the substrate 302. The additional extension within the cavity may be filled with a thermally conductive and / or non-conductive material, thereby forming a thermal path 206b having an extension extending toward and / or contacting the substrate 302. In some embodiments, the base dielectric layer 204 may be formed or re-deposited above the thermal path 206b, further filled with a thermally conductive and / or non-conductive material. Thus, the thermal path 206b may have a second extension extending upward and through the base dielectric layer 204.

[0050] FIG5C illustrates a cross-sectional view of a stacked thermal path 206c in a memory device 560 according to one or more embodiments of the present technology. As an illustrative example, thermal path 206c may be continuously connected through memory device structures 562, 564, and 566. For example, memory device 560 may be formed from wafers or dies having thermal paths 206a and / or 206b stacked one on top of the other (e.g., wafer bonding or stacked die). The stacked wafers or stacked die may further include through-silicon vias (TSVs) or corresponding thermal extensions that directly contact vertically extending portions of thermal paths 206a and / or 206b. Thus, the resulting thermal path 206c may align and directly connect thermal paths 206a and / or 206b across multiple layers. During operation, thermal path 206 may provide a path for heat energy to flow between memory device structures 566, 564, and 562.

[0051] FIG6A illustrates a cross-sectional view of the formation of a through-hole 602 in a memory device structure 600 according to one or more embodiments of the present technology. Through-hole 602 may be formed on or after memory device structure 460 of FIG4C , memory device structure 500 of FIG5A , or memory device structure 530 of FIG5B . Through-hole 602 (such as a TSV or contact) may extend through substrate 302 and base dielectric layer 204 . As an illustrative example, through-hole 602 may separate thermal path 206 from cell structure 202 in base dielectric layer 204 . Through-hole 602 may be formed by removing or etching to form a cavity extending through base dielectric layer 204 and / or substrate 302 . The through-hole cavity may be filled with a barrier material, a seed metal material, a primary metal material (e.g., copper), or a combination thereof.

[0052] FIG6B illustrates a cross-sectional view of the formation of a redistribution layer (RDL) 604 within an EOL layer (606) of a memory device structure 650, according to one or more embodiments of the present technology. RDL 604 may include lateral electrical connections, such as traces, local vias, or a combination thereof. RDL 604 may connect to vias 602, cell structure 202, CMOS 308, local interconnects 306, or a combination thereof.

[0053] FIG7 illustrates a cross-sectional view of thermal paths 206c and 206d on memory devices 704 and 706 connected to a logic circuit 702 of an apparatus 700 (e.g., apparatus 100 of FIG1 ) according to one or more embodiments of the present technology. For illustrative purposes, FIG7 may depict a portion of a directly bonded semiconductor wafer or a corresponding stacked device having memory or data storage circuits (e.g., memory cells, such as for DRAM). For example, the depicted portions of memory devices 704 and 706 may correspond to memory array 150 of FIG1 . Logic circuit 702 may correspond to other circuits depicted in FIG1 , such as address command input circuit 105 of FIG1 , I / O circuit 160 of FIG1 , and / or the like.

[0054] Memory devices 704 and 706 may include thermal paths for managing heat within device 700, such as thermal path 206 in FIG. 2 , 206a in FIG. 5A , and / or 206b in FIG. 5B . Thermal paths 206c and 206d provide a thermally conductive path for heat to flow from logic circuit 702 to memory device 704 and out of memory device 706 . Once the fabrication process for memory devices 704 and 706 (as depicted in FIG. 3A through FIG. 6B ) is complete, memory devices 704 and 706 may be flipped (via, for example, a carrier wafer) and mounted above logic circuit 702 to create device 700 . This allows the active sides of memory devices 704 and 706 to face downward and closer to logic circuit 702 at the bottom of device 700 .

[0055] In some embodiments, thermal paths 206a and 206b are connected (as shown in FIG. 5C ) to provide a direct connection path (e.g., a thermal support or a path to a thermal support comprising thermally conductive and / or electrically insulating materials as described above) for heat dissipation from device 700. For illustrative purposes, the thermal path has a quadrilateral cross-sectional shape. However, it should be understood that the various embodiments described herein can be implemented in other configurations, such as to achieve any size and shape for a thermal path in a memory device structure.

[0056] FIG8A is a flow chart illustrating an exemplary method 800 for designing a thermal path for a memory device structure according to one or more embodiments of the present technology. As described above, the method 800 may determine the placement (e.g., size, shape, location, or the like) of a thermal path (e.g., thermal path 206 of FIG2-7 ) in a memory device structure.

[0057] At block 802, method 800 may include determining an operational metric of a device (e.g., device 100 of FIG. 1 and / or device 700 of FIG. 7 ). The operational metric may include bandwidth requirements, circuit capacity, operating speed, thermal displacement, footprint, or any device design preference or criteria. In some embodiments, the operational metric may be determined based on a circuit diagram or a requirement regarding the circuit diagram provided by another party or entity (e.g., a circuit designer or a customer).

[0058] At block 804, method 800 may include calculating parameters of the thermal path (e.g., location, size, shape, length, width, depth, and / or number) based on operational metrics of the device. The thermal path may be positioned within the memory device structure to provide a path for heat energy to dissipate from the memory structure. The method may include determining where to position the thermal path within the memory device structure. For example, the thermal path may be positioned within a base dielectric layer, an isolation layer, or across multiple layers within the memory device structure.

[0059] Method 800 may include calculating parameters (e.g., location and / or shape) of a thermal path based on a cell structure, via, socket, receptacle, solder location, hole, connector, or any feature in the memory device structure. For example, the manufacturing system may generate a layout for the thermal path that avoids placing the thermal path at, below, overlapping, and / or within a threshold distance from a via or cell structure in the memory device structure.

[0060] A machine learning or artificial intelligence (ML / AI) module can be configured to analyze operational metrics of a memory device and calculate parameters of one or more thermal paths to be added to the memory device structure to remove heat. The ML / AI learning module can be configured to analyze the operational metrics and calculate the thermal path parameters based on at least one ML / AI model trained on at least one dataset reflecting previously user-determined parameters of thermal paths based on the operational metrics. The ML / AI algorithms (and models) can be stored locally in a database and / or externally in a database (e.g., a cloud database and / or cloud server). Client devices (e.g., personal computers, smartphones, tablets, etc.) can be equipped to access these ML / AI algorithms and intelligently calculate the parameters of the thermal paths in the memory device structure based on at least one ML / AI model trained on historical thermal path parameters. For example, historical thermal path parameters can be collected to train an ML / AI model to automatically determine the location, size, shape, length, width, depth, and / or number of thermal paths based on the operational parameters of the memory device.

[0061] As described herein, an ML / AI model may refer to a predictive or statistical utility or program that can be used to determine a probability distribution over one or more character sequences, categories, objects, outcome sets, or events, and / or to predict a response value from one or more predictors. A model may be based on or incorporate one or more rule sets, machine learning, a neural network, or the like. The ML / AI model may process historical parameters of thermal paths in memory devices and other data stores (e.g., semiconductor standards, etc.) to analyze memory device structures and design thermal path locations and dimensions within the memory device structures. Based on a compilation of data from a memory device design database, external / internal portals, and other user data stores, at least one ML / AI model may be trained and subsequently deployed to automatically design a memory device having one (or more) thermal paths inserted into one or more layers of the memory device structure.

[0062] At block 806, method 800 may include calculating (using, for example, a computing system) the thermal conductivity of a layer in a memory device structure. The calculation may be based on simulations of layers with added thermal paths to calculate the thermal conductivity of the memory device. For example, by adding thermal paths to layers of the memory device structure, thermal conductivity may be improved and operating temperature may be reduced. Simulation results may indicate a predicted improvement in thermal conductivity or a change in device temperature by adding thermal paths to layers of the memory device structure.

[0063] At decision block 808, method 800 may include determining whether the thermal conductivity of the layer is below a threshold value (e.g., 200 W / m·K). If the estimated thermal conductivity of the layer is not below a predetermined acceptable threshold value, method 800 may include adjusting parameters of a thermal path interposed in the layer of the memory device structure, as illustrated by the feedback loop to block 804. If the thermal conductivity value of the layer is below the threshold value, then at block 810, method 800 enables the design for manufacturing.

[0064] Based on the approval, the device design can be used to manufacture a memory device having a thermal path within one or more layers of the memory device structure. For example, the device design can be provided to a memory device manufacturer. When the memory device is manufactured according to the approved design, the thermal path or material can be configured within one or more layers of the memory device structure according to the design.

[0065] FIG8B is a flow chart illustrating an exemplary method 850 for creating a thermal path in one or more layers of a memory device structure, according to one or more embodiments of the present technology. Method 850 may include adding a thermally conductive material during the FEOL layer fabrication stage. FEOL layers may include isolation layers interconnecting a CMOS structure (e.g., CMOS 308 of FIG3-7 ) and local wiring.

[0066] At block 852, method 850 may include forming a base dielectric layer (e.g., base dielectric layer 204 of Figures 2-7) on the isolation layer. The base dielectric layer may be formed to add thermally conductive material during the FEOL fabrication stage. At block 854, method 850 may include forming a cell structure (e.g., cell structure 202 of Figures 2-7) in the base dielectric layer.

[0067] At block 856, method 850 may include forming an isolation region for a thermal path in the base dielectric layer adjacent to the cell structure (e.g., isolation region 432 of FIG. 4B ). The thermal path region may be electrically isolated from regions of peripheral circuitry and regions of contacts, vias, and / or TSVs using the base dielectric layer, such as by retaining or forming vertical portions or walls around the thermal path portion.

[0068] At block 858, method 850 may include forming a thermal path (e.g., thermal path 206 of Figures 2-7) in the dielectric layer at the thermal path region by adding a thermally conductive, non-conductive material (such as aluminum oxide, aluminum nitride, etc.). The thermal path may be formed by a spin-on process containing the thermally conductive material as a filler in the base dielectric layer. In some embodiments, the thermal path is formed by a combination of processes such as physical vapor deposition (PVD), molybdenum (MO), or cut metal dielectric (CMD) to form a thermally conductive layer as a functional film and remove it by a polishing process. The manufacturing process may be completed by performing a back-end of line (BEOL) process to form the wiring of the memory device.

[0069] At block 860, method 850 may include aligning and bonding wafers and / or dies. For example, method 850 may include using the processes described above with respect to blocks 852 through 858 to fabricate one or more wafers / dies, such as a wafer including logic circuit 702 of FIG. 7 , one or more wafers or dies including memory devices 704 / 706 of FIG. 7 , or a combination thereof. The wafers or dies may be aligned, such as using a marker. When aligning the wafers or dies, the thermal paths 206 in the wafers or dies may be vertically stacked or aligned along a vertical line.

[0070] Aligned wafers or dies can be attached, such as by direct wafer-to-wafer bonding. For example, the wafers or dies can be placed one above the other or stacked so that the copper pads on the top and bottom pads are in direct contact with each other. The contacting copper pads can be directly bonded to each other (e.g., without adhesive or solder), such as using diffusion bonding, ultrasonic welding, or other similar direct bonding mechanisms.

[0071] FIG9 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. Any of the aforementioned apparatuses (e.g., memory devices) associated with the memory devices described above with respect to FIG1 through FIG8B may be incorporated into or implemented in a memory (e.g., a memory device 900) or any of a myriad of larger and / or more complex systems, a representative example of which is system 980 schematically shown in FIG9. System 980 may include memory device 900, a power supply 982, a driver 984, a processor 986, a placement mechanism 988, and / or other subsystems or components 990. Placement mechanism 988 may utilize ML / AI models to determine the location, size, shape, length, width, depth, and / or number of thermal paths to be added to the memory device structure based on operational metrics of the memory device (as described in FIG8A and FIG8B).

[0072] Memory device 900 may include features generally similar to those of the apparatus described above with respect to Figures 1 through 8B and, therefore, may include various features for executing a direct read request from a host device. The resulting system 980 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 980 may include, but are not limited to, handheld devices (e.g., cell phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 980 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communications network). The components of system 980 may also include remote devices and any of a variety of computer-readable media.

[0073] From the foregoing, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the present technology. Furthermore, certain aspects of the novel technology described in the context of specific embodiments may be combined or eliminated in other embodiments. Furthermore, although advantages associated with specific embodiments of the novel technology have been described in the context of those embodiments, other embodiments may also exhibit these advantages, and not all embodiments necessarily exhibit these advantages to fall within the scope of the present technology. Therefore, the present technology and related technologies may encompass other embodiments not explicitly shown or described herein.

[0074] In the embodiments illustrated above, the apparatus has been described in the context of DRAM devices. However, apparatus configured according to other embodiments of the present technology may include other types of suitable storage media in addition to or in place of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, and the like.

[0075] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, computing results, executing instructions, assembling, transferring, and / or manipulating data structures. The term data structure includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data such as computed or generated data, and program data. Furthermore, as used herein, the term "dynamic" describes procedures, functions, actions, or implementations that occur during the operation, use, or deployment of a corresponding device, system, or embodiment, as well as after or while running manufacturer or third-party firmware. Procedures, functions, actions, or implementations that occur dynamically may occur after or subsequent to design, manufacturing, and initial testing, setup, or configuration.

[0076] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the relevant art will appreciate that the present technology may have additional embodiments and may be practiced without several of the details of the embodiments described above with respect to Figures 1-9.

[0077] 100: Equipment 105: Command / address input circuit 110: Address decoder 115: Command decoder 120:Pulse input circuit 130: Internal clock circuit 140: Column decoder 145: Row Decoder 150:Memory array 155: Read / Write Amplifier 160: Input / Output (I / O) Circuit 170: Internal voltage generator circuit 200: Memory device structure 202: Cell structure 204: base dielectric layer 206: Thermal Path / Continuous Material 206a: Hot Path 206b: Hot path 206c: Hot Path 206d: Hot Path 300: Memory device structure 302:Substrate 304: Groove 306: Local interconnect 308: Complementary Metal Oxide Semiconductor (CMOS) 330: Memory device structure 360:Memory device structure 400: Memory device structure 430: Memory device structure 432:Isolated area 460:Memory device structure 500: Memory device structure 530: Memory device structure 560:Memory device 562:Memory device structure 564:Memory device structure 566:Memory device structure 600: Memory device structure 602:Through hole 604: Heavy cloth layer 606:EOL layer 650: Memory device structure 700: Equipment 702: Logic Circuit 704: Memory device 706: Memory device 800:Method 802: Block 804: Block 806: Block 808: Decision Block 810: Block 850: Method 852: Block 854: Block 856: Block 858: Block 860: Block 900: Memory device 980: System 982: Power Supply 984:Drive 986: Processor 988: Placement mechanism 990: Other subsystems or components

Claims

1. A memory device comprising: A semiconductor substrate; A memory cell is located above the semiconductor substrate; a dielectric material is formed on the semiconductor substrate. A thermal path is provided above the semiconductor substrate and separated from the memory cell in a lateral direction. The thermal path includes an electrically insulating material that is more thermally conductive than the dielectric material. The dielectric material surrounds at least a peripheral portion of the memory cell and the thermal path.

2. The device as requested in item 1, wherein the thermal path is configured to transfer thermal energy out of or through the device.

3. The device of claim 1, wherein the thermal path is electrically isolated from the memory cell using the semiconductor substrate.

4. The equipment as requested in item 1, wherein the electrical insulating material is aluminum oxide or aluminum nitride.

5. The apparatus of claim 1, wherein the thermal path includes a top portion, a bottom portion, or both exposed through the semiconductor substrate.

6. A memory device comprising: A semiconductor substrate portion; A dielectric layer is disposed above the semiconductor substrate portion; At least one cell structure disposed in the dielectric layer and configured to store charges representing stored data; and a thermal path located adjacent to the at least one cell structure and at least partially embedded in the dielectric layer, the thermal path comprising an electrically insulating material that is more thermally conductive than the dielectric material of the dielectric layer.

7. The memory device as claimed in claim 6, wherein the thermal path is configured to transfer heat out of or through the memory device.

8. The memory device of claim 6, wherein the thermal path is electrically isolated from the at least one cell structure using the dielectric layer.

9. The memory device of claim 6, wherein the electrical insulating material is aluminum oxide or aluminum nitride.

10. The memory device of claim 6, further comprising: An active circuit is disposed below the at least one cell structure and on or above the semiconductor substrate portion; and a through-silicon via (TSV) extends in a vertical direction and passes through the dielectric layer, the semiconductor substrate portion, or both.

11. The memory device as claimed in claim 6, further comprising: A logic device wafer includes logic circuitry configured to facilitate the storage, access, and maintenance of data stored in the memory device. The semiconductor substrate portion, the dielectric layer, the at least one cell structure, and the thermal path include a semiconductor storage device configured to store data. The semiconductor storage device is wafer-bonded to and above the logic device. The thermal path is configured to allow heat generated by the logic device to travel upwards and through the semiconductor storage device.

12. The memory device of claim 11, wherein the semiconductor storage device has a first thermal path and is directly attached to a first storage device of the logic device, the storage device further comprising: A second storage device having a second thermal path and directly wafer-bonded to and above the first storage device, wherein the first and second thermal paths are aligned along a vertical line.

13. The memory device as claimed in claim 6, wherein the memory device includes a dynamic random access memory (DRAM).

14. A method of forming a memory device, comprising: Provide a semiconductor substrate; At least one cell structure is formed on the semiconductor substrate, wherein the at least one cell structure is configured to store data. A dielectric layer is formed above the semiconductor substrate and surrounding the at least one cell structure; at least one isolation region is formed adjacent to the at least one cell structure by removing a portion of the dielectric layer; and a thermal path is formed in the dielectric layer at the at least one isolation region by adding an electrically insulating material to the at least one isolation region, wherein the electrically insulating material is more thermally conductive than the dielectric material of the dielectric layer.

15. The method of claim 14, wherein forming the thermal path comprises: spin-coating to deposit the electrically insulating material in the at least one isolation region of the dielectric layer.

16. The method of claim 14, wherein forming the thermal path comprises: a physical vapor deposition (PVD) process for depositing the electrical insulating material, a cleaved metal dielectric (CMD) process, or a combination thereof.

17. The method of claim 14, wherein the electrical insulating material is added during a front-end process (FEOL) layer manufacturing stage.

18. The method of claim 14, wherein the electrical insulating material provides the thermal path to transfer heat energy out or through the dielectric layer.

19. The method of claim 14, further comprising: An active circuit is formed or attached on the semiconductor substrate, wherein at least one cell structure is formed above the active circuit; and a thermal via or through-silicon via (TSV) is formed extending through the dielectric layer and into the semiconductor substrate, wherein the thermal via or the TSV is located between the at least one cell structure and the thermal path, wherein the thermal path is separated and electrically isolated from the thermal via or the TSV and the active circuit entity using the dielectric layer.

20. The method of claim 14, wherein forming the thermal path comprises: depositing aluminum oxide or aluminum nitride in the at least one isolation region.

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