Semiconductor device and forming method thereof

Abstract

A semiconductor device includes a substrate comprising a first device region and a second device region. A first type of device is located in the first device region, comprising a first nanostructure stack and a first gate stack, the first gate stack surrounding the first nanostructure stack, wherein each first nanostructure in the first nanostructure stack has a first height. A second type of device is located in the second device region, comprising a second nanostructure stack and a second gate stack, the second gate stack surrounding the second nanostructure stack, wherein each second nanostructure in the second nanostructure stack has a second height. The second height is different from the first height.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Semiconductor devices are used in a variety of electronic devices, such as personal computers, mobile phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature hereinafter may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, this disclosure may use spatially relative terms, such as "below," "under," "lower," "above," "upper," etc., to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0008] In some embodiments of nanostructured semiconductor devices, the thickness of the nanosheet (e.g., the thickness of the semiconductor layer providing the channel region of the element) can define the transistor's electrical performance. For example, n-type semiconductor devices, such as n-type field-effect transistors (NFETs), benefit from thinner sheet heights. For example, by providing a thinner sheet height in an n-type semiconductor device (e.g., an NFET), doping effects can be reduced, resulting in better channel resistance. When n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs) are located on the same support substrate and have semiconductor layers of the same thickness, it is not possible to provide optimized performance for NFETs and PFETs respectively for the semiconductor layer (e.g., the nanosheet) providing the channel region of the element. In some embodiments, the methods and structures described herein can provide tunable NFET and PFET performance with different thicknesses (e.g., different heights) for the semiconductor layer (e.g., the nanosheet) providing the channel region of the element. In some embodiments, by providing tunable NFET and PFET performance through varying thicknesses of semiconductor layers (e.g., nanosheets), the methods and structures described herein can lead to improved wafer acceptance testing (WAT) performance. In some embodiments, the methods and structures provided herein can use a one-step etching process to provide adjustable, differentiated thicknesses of the semiconductor layers for individual NFET and PFET elements, without relying on multiple patterning steps to individually etch the stack of NFET and PFET devices.

[0009] Embodiments are described below in a specific context, and the die includes a nanoFET. However, various embodiments may be applied to dies that include other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, etc.) that replace or are combined with nanoFETs.

[0010] Figure 1 is a three-dimensional view illustrating an example of a nano-FET (e.g., a nanoline FET, a nanosheet FET, etc.) according to some embodiments. The nano-FET includes a nanostructure 55 (e.g., a nanosheet, nanowire, etc.) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nano-FET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, which may protrude over and from adjacent isolation regions 68. Although the isolation region 68 is described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom of fin 66 is shown as being made of a single, continuous material with substrate 50, the bottom portion of fin 66 and / or substrate 50 may comprise a single material or multiple materials. In this document, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0011] The gate dielectric layer 100 is located above the top surface of the fin 66 and along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. Depending on the context, the source / drain region 92 may refer individually or collectively to either the source or the drain.

[0012] Figure 1 further illustrates the reference cross-sectional views used in the following figures. Section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Section B-B' is perpendicular to section A-A' and parallel to the longitudinal axis of the fin 66 of the nanoFET and in a direction, for example, between the epitaxial source / drain regions 92. Section C-C' is parallel to section A-A' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, the following figures refer to these reference cross-sections.

[0013] Some embodiments herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate patterns used in planar devices, such as planar FETs or FinFETs.

[0014] Figures 2 through 20C are cross-sectional views of intermediate stages in the fabrication of a nanoFET according to some embodiments. Figures 2 through 5, 6A, 13A, 14A, 15A, 16A, 16C, 16D, 16F, 16G, 16H, 17A, 18A, 19A, and 20A show the reference cross-section A-A' shown in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, 11B, 11C, 12B, 12D, 13B, 14B, 15B, 16B, 16E, 17B, 18B, 19B, 20B, and 21B show the reference section B-B' shown in Figure 1. Figures 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13C, 18C, 19C, and 20C show the reference section C-C' shown in Figure 1.

[0015] In Figure 2, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0016] In some embodiments, the substrate 50 includes two regions of different conductivity types. In some embodiments, the substrate 50 has an n-type region 50N and a p-type region 50P. In some embodiments, the n-type region 50N may provide a first conductivity type region, and the p-type region 50P may provide a second conductivity type region. The n-type region 50N may be used to form an n-type device, such as an NMOS transistor, such as an n-type nanoFET, and the p-type region 50P may be used to form a p-type device, such as a PMOS transistor, such as a p-type nanoFET. The n-type region 50N may be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active elements, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P may be disposed.

[0017] Further in Figure 2, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor layer 51A, a first semiconductor layer 51B, a first semiconductor layer 51C (collectively referred to as the first semiconductor layer 51) and a second semiconductor layer 53A, a second semiconductor layer 53B, a second semiconductor layer 53C (collectively referred to as the second semiconductor layer 53). For illustrative purposes and as discussed in more detail below, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. In this embodiment, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously.

[0018] Referring to Figure 2, for illustrative purposes, the multilayer stack 64 is shown as comprising three layers: a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53.

[0019] Each layer of the multilayer stack 64 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 can be formed of a first semiconductor material suitable for p-type nanoFETs, such as silicon germanium, and the second semiconductor layer 53 can be formed of a second semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbon, etc.

[0020] The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity to each other. In this way, the first semiconductor layer 51 can be removed without significantly removing the second semiconductor layer 53. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material.

[0021] In some embodiments, the first semiconductor layer 51 may be composed of a germanium-containing material such as silicon-germanium (SiGe). In one example, the germanium content of the silicon-germanium (SiGe) component of the first semiconductor layer 51 may be in the range of 15% to 40%. The second semiconductor layer 53 may be composed of a silicon-containing material of silicon (Si).

[0022] In some embodiments, the mixed-component interface layer 57 and the mixed-component interface layer 58 may be formed between the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the epitaxial deposition process for forming the first semiconductor layer 51 and the second semiconductor layer 53 also forms the mixed-component interface layer 57 and the mixed-component interface layer 58. More specifically, when the formation gas is switched in the epitaxial deposition formation sequence to form alternating first semiconductor layers 51 and second semiconductor layers 53, an epitaxially formed interface layer, such as the first mixed-component interface layer 57 and the second mixed-component interface layer 58, is generated. In some embodiments, the mixed-component interface layer 57 and the mixed-component interface layer 58 include elements from the first semiconductor layer 51 and the second semiconductor layer 53. In some examples, the mixed-component interface layer 57 and the mixed-component interface layer 58 are silicon-containing layers containing germanium from the first semiconductor layer 51.

[0023] As will be further described below with reference to Figures 11A to 12C, the mixed-component interface layer 57 and the mixed-component interface layer 58 can be doped to change the etching rate. More specifically, a dopant can be introduced into the source / drain region 92, and then the dopant can be diffused to the first mixed-component interface layer 57 and the second mixed-component interface layer 58 by thermal diffusion, for example, during an annealing process step. For example, the first mixed-component interface layer 57 can be present in the n-type region 50N, while the second mixed-component interface layer 58 can be present in the p-type region 50P. The etching process combining the components and dopant in the first mixed-component interface layer 57 can be selective to increase the etching rate of the first mixed-component interface layer 57 in the n-type region 50N relative to the second mixed-component interface layer 58 present in the p-type region 50P. For example, a portion of the mixed-component interface layer (e.g., the first mixed-component interface layer 57) within the n-type region 50N may be doped with an n-type dopant, and a portion of the mixed-component interface layer (e.g., the second mixed-component interface layer 58) within the p-type region 50P may be doped with a p-type dopant. In one example, the n-type dopant present in the mixed-component interface layer within the n-type region 50N may be selected from phosphorus, arsenic, antimony, and combinations thereof. In one example, the p-type dopant present in the mixed-component interface layer within the p-type region 50P may be selected from boron, boron fluoride, indium, and combinations thereof. The n-type and p-type dopants can diffuse from the first semiconductor layer 51 to the mixed-component interface layer.

[0024] In some other embodiments, the portion of the first semiconductor layer 51 existing in the n-type region may be doped with an n-type dopant, which diffuses to the interface between the first semiconductor layer 51 and the second semiconductor layer 53 to provide a first mixed-component interface layer 57 with n-type doping within the n-type region 50N. In some examples, the first mixed-component interface layer 57 formed in the n-type region 50N is a silicon-containing layer comprising 0.1% to 5% germanium (Ge) and 0.01% to 1% phosphorus (P).

[0025] In some other embodiments, a portion of the first semiconductor layer 51 existing in the p-type region may be doped with a p-type dopant, which diffuses to the interface between the first semiconductor layer 51 and the second semiconductor layer 53 to provide a p-type doped second mixed-component interface layer 58 within the p-type region 50P. In some examples, the second mixed-component interface layer 58 formed in the p-type region 50P is a silicon-containing layer comprising 0.01% to 5% germanium (Ge) and 0.01% to 1% boron (B).

[0026] The n-type dopant and p-type dopant can be introduced into the first semiconductor layer 51 by ion implantation, in-situ doping, or a combination thereof. The n-type and p-type regions can be processed separately using a photoresist mask or other mask (not shown separately). The photoresist mask can be formed using spin coating and can be patterned using acceptable lithography techniques. For example, to introduce the n-type dopant into the first semiconductor layer 51, a first mask can be applied to the p-type region 50P, and a stack of the first semiconductor layer 51 and the second semiconductor layer 53 can be formed in the n-type region 50N, wherein the n-type dopant can be introduced by in-situ doping during the deposition of the first semiconductor layer 51. After the stack of the first semiconductor layer 51 and the second semiconductor layer 53 is formed in the n-type region 50N, the first mask can be removed, for example, by oxygen ashing. Thereafter, a second mask can be formed over the n-type region 50N, and the p-type region 50P can be processed to provide the first semiconductor layer 51 having the p-type dopant. For example, after applying a second mask to the n-type region, a stack of a first semiconductor layer 51 and a second semiconductor layer 53 can be formed in the p-type region 50P, wherein in-situ doping can be used to introduce p-type dopant during the deposition of the first semiconductor layer 51. In some embodiments, an ion implantation process can be used to introduce n-type or p-type dopant instead of in-situ doping.

[0027] Although the mixed component interface layer can be formed by element diffusion from the interface between the first semiconductor layer 51 and the second semiconductor layer 53, in some embodiments, a deposition step separate from the deposition step of forming the first semiconductor layer 51 and the second semiconductor layer 53 can be used to form the first mixed component interface layer 57 and the second mixed component interface layer 58.

[0028] Referring now to Figure 4, according to some embodiments, fins 66 are formed in a substrate 50, and nanostructures 55 are formed in a multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. Forming nanostructures 55 by etching the multilayer stack 64 can also define first nanostructures 52A to 52F (collectively referred to as sacrificial nanostructures 52) from a first semiconductor layer 51 and second nanostructures 54A to 54F from a second semiconductor layer 53. Between the first nanostructures 52A to 52F and the second nanostructures 54A to 54F is a first mixed-component interface layer 57 and a second mixed-component interface layer 58. Second nanostructures 54A, 54B, and 54C provide first stacked nanostructures in a first conductivity type region (n-type region 50N). Second nanostructures 54D, 54E, and 54F provide second stacked nanostructures in a second conductivity type region (p-type region 50P). A first mixed-component interface layer 57 is present in the n-type region 50N, and a second mixed-component interface layer 58 is present in the p-type region 50P. The first nanostructure 52 and the second nanostructure 54 can also be collectively referred to as nanostructure 55.

[0029] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more lithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 66 and nanostructures 55. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers can be formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0030] For illustrative purposes, Figure 3 shows fins 66 in the n-type region 50N and p-type region 50P as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or thinner than that of the fins 66 in the p-type region 50P. Furthermore, while the fins 66 and nanostructures 55 are shown to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of the fins 66 and / or nanostructures 55 continuously increases in the direction toward the substrate 50. In such embodiments, the nanostructures 55 may have different widths.

[0031] In some embodiments, the first mixed-component interface layer 57 may be present at the interface of the stack of the first nanostructure 52 and the second nanostructure 54 in the n-type region 50N; while the second mixed-component interface layer 58 may be present at the interface of the stack of the first nanostructure 52 and the second nanostructure 54 in the p-type region 50P. The first mixed-component interface layer 57 and the second mixed-component interface layer 58 may each contain a large amount of silicon (Si) and a small amount of germanium (Ge) from the first nanostructure 52. For example, the germanium content in each of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 may be 5% or less. The first mixed-component interface layer 57 and the second mixed-component interface layer 58 may be formed by mixing deposition elements during the epitaxial deposition sequence for forming the multilayer stack 64 shown in Figure 2. In some embodiments, the mixing of different components of the first nanostructure 52 and the second nanostructure 54 may be provided by thermal diffusion during the annealing step to provide the first mixed-component interface layer 57 and the second mixed-component interface layer 58.

[0032] Furthermore, the first mixed-component interface layer 57 may include up to 1% of an n-type dopant, such as phosphorus (P). The n-type dopant may be introduced into the first mixed-component interface layer 57 via diffusion (e.g., thermal diffusion) from the subsequently formed source / drain regions 92, as described above with reference to Figures 11A through 11C. However, in some other embodiments, the n-type dopant may be introduced into the first mixed-component interface layer 57 via diffusion (e.g., thermal diffusion) from the first nanostructures 52D, 52E, 52F in the n-type region 50N. In one example, the n-type dopant may be provided by a phosphorus (P) dopant present in the first mixed-component interface layer 57, the amount of which ranges from 0.01% to 1%.

[0033] Furthermore, the second mixed-component interface layer 58 may include up to 1% of a p-type dopant, such as boron (B). The p-type dopant may be introduced into the second mixed-component interface layer 58 from the first nanostructures 52A, 52B, 52C in the p-type region 50P via diffusion (e.g., thermal diffusion). In one example, the n-type dopant may be provided by a boron (B) dopant present in the second mixed-component interface layer 58, wherein the amount of boron (B) dopant ranges from 0.01% to 1%.

[0034] In Figure 4, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitrides, or combinations thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed through any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed via an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed to cover the nanostructure 55 with an excess of insulating material. Although the insulating material is shown as a single layer, some embodiments may form multiple layers. For example, in some embodiments, a liner (not shown separately) may be formed first along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. Subsequently, a filling material can be formed on top of the pad, as discussed above.

[0035] The insulating material is then removed using a removal process to remove excess insulating material from the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof, may be used. The planarization process exposes the nanostructure 55 such that the top surfaces of the nanostructure 55 and the insulating material are horizontal after the planarization process is completed.

[0036] Then, the insulating material is recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 68 may be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as a material-selective etching process for the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructure 55). For example, it can be removed using an oxide such as dilute hydrofluoric acid (dHF).

[0037] The process described above with reference to Figures 2 through 4 is only one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid prior and / or subsequent ion implantation, although in-situ doping and implantation doping can be used together.

[0038] For illustrative purposes, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in different orders in the p-type region 50P and the n-type region 50N. However, the materials selected for the first semiconductor layer 51 and the second semiconductor layer 53 will have etch selectivity parameters used by the processes described herein.

[0039] In Figure 5, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The dummy gate layer 72 can be a conductive or non-conductive material, selected from amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicates, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity for the etch isolation region. The masking layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single masking layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0040] Figures 6A through 18C illustrate various additional steps in the manufacture of the embodiment device. Figures 7A, 8A, 9A, 10A, 11A, 12A, 12C, 13A, 13C, 14A, 15A, and 18C illustrate features in the n-type region 50N or p-type region 50P. In Figures 6A and 6B, the mask layer 74 (see Figure 5) can be patterned using acceptable photolithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate from adjacent dummy gates 76. The length direction of the dummy gate 76 is basically perpendicular to the length direction of the corresponding fin 66.

[0041] In Figures 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed above the structures shown in Figures 6A and 6B, respectively. Subsequently, the first spacer layer 80 and the second spacer layer 82 are patterned as spacers for forming self-aligned source / drain regions. In Figures 7A and 7B, the first spacer layer 80 is formed on the top surface of the STI region 68; and the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76 and dummy gate dielectric 71. The second spacer layer 82 is deposited above the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation or deposited through CVD, ALD, etc. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be formed by CVD, ALD, or similar techniques.

[0042] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation of lightly doped (LDD) source / drain regions (not shown separately) can be performed. In embodiments with different device types, similar to the implantation discussed above in Figure 4, a mask such as a photoresist can be formed over the n-type region 50N, while simultaneously exposing the p-type region 50P, and an appropriate type (e.g., p-type) impurity can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the p-type region 50P, while simultaneously exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. Lightly doped source / drain regions can have impurity concentrations ranging from about 1 × 10¹⁵ atoms / cm³ to about 1 × 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0043] Note that the annealing process described above for repairing injection damage can also cause elements from the first nanostructure 52 and the second nanostructure 54 to diffuse to the interface between the first nanostructure 52 and the second nanostructure 54, forming a first mixed component interface layer 57 and a second mixed component interface layer 58, as shown in Figure 16C.

[0044] In Figures 8A and 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source and drain regions, and to protect the sidewalls of the fins 66 and / or nanostructures 55 during subsequent processing.

[0045] The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or similar. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in Figure 8A. Thereafter, the second spacer 83 acts as a mask while the exposed portion of the first spacer layer 80 is etched to form the first spacer 81, as shown in Figure 8A.

[0046] As shown in Figure 8A, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. As shown in Figure 8B, in some embodiments, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the shield 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the first spacer layer 80. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the shield 78, the dummy gate 76, and the dummy gate dielectric 71.

[0047] It should be noted that the above disclosure provides a general description of the process for forming spacers and LDD regions. Other processes and steps may also be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacer 81 may be patterned before the deposition of the second spacer layer 82), additional spacers may be formed and removed, etc. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0048] In Figures 9A and 9B, according to some embodiments, a first groove 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. Next, an epitaxial source / drain region will be formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. As shown in Figure 9A, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed below the top surface of the STI region 68; or a similar step. The first groove 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). A first spacer 81, a second spacer 83, and a mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50 during the etching process for forming the first groove 86. Each layer of the nanostructure 55 and / or fin 66 can be etched using a single etching process or multiple etching processes. Timed etch processes can be used to stop etching the first groove 86 after it has reached the desired depth.

[0049] In Figures 10A and 10B, a portion of the sidewalls of each layer of a multilayer stack 64 formed of a first semiconductor material (e.g., a first nanostructure 52) is etched, this portion being exposed by a first recess 86 to form a sidewall recess 88 in the n-type region 50N and a sidewall recess 88 in the p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight in Figure 10B, the sidewalls can be concave or convex. An isotropic etching process, such as wet etching, can be used to etch the sidewalls. In embodiments where the first nanostructure 52 comprises, for example, SiGe, and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N and the p-type region 50P.

[0050] In Figures 11A to 11C, a first internal spacer 90 is formed in a sidewall recess 88. The first internal spacer 90 can be formed by depositing an internal spacer layer (not shown separately) on the structure shown in Figures 10A and 10B. The first internal spacer 90 serves as an isolation component between the subsequently formed source / drain region and the gate structure. As will be discussed in more detail below, the source / drain region will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with the corresponding gate structures.

[0051] The internal spacer layer can be deposited using a conformal deposition process, such as CVD, ALD, etc. The internal spacer layer may include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low k) material having a k value of less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer sidewall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54 in the n-type region 50N and flush with the sidewall of the first nanostructure 52 in the p-type region 50P, the outer sidewall of the first internal spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52.

[0052] Furthermore, although the outer wall of the first internal spacer 90 is shown as straight in Figure 11B, the outer wall of the first internal spacer 90 can be concave or convex. As an example, Figure 11C shows an embodiment in which the sidewall of the first nanostructure 52 is recessed, the outer wall of the first internal spacer 90 is recessed, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54 in the n-type region 50N. An embodiment in which the sidewall of the second nanostructure 54 is recessed, the outer wall of the first internal spacer 90 is recessed, and the first internal spacer 90 is recessed from the sidewall of the first nanostructure 52 in the p-type region 50P is also shown. The internal spacer layer can be etched by anisotropic etching processes (e.g., RIE, NBE, etc.). The first internal spacer 90 can be used to prevent the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, discussed below with reference to Figures 12A to 12C) from being damaged by subsequent etching processes (e.g., etching processes used to form gate structures).

[0053] In Figures 12A to 12C, epitaxial source / drain regions 92 are formed in the first recess 86. In some embodiments, the source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 50N and the p-type region 50P, thereby improving performance. As shown in Figure 12B, the epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between each pair of adjacent epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate of the subsequently formed nanoFET.

[0054] The epitaxial source / drain region 92 in the n-type region 50N (e.g., an NMOS region) can be formed by shielding the p-type region 50P (e.g., a PMOS region). The source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET.

[0055] In some examples, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55 and may have facets.

[0056] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by shielding the n-type region 50N (e.g., an NMOS region). The source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can include a material that applies compressive strain to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have facets.

[0057] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have an impurity concentration between about 1 × 10¹⁹ atoms / cm³ and about 1 × 10²¹ atoms / cm³. The n-type and / or p-type impurities used for the source / drain region may be any impurities discussed previously. In some embodiments, the epitaxial source / drain region 92 may be doped in situ during growth.

[0058] In some embodiments, an n-type dopant in the epitaxial source / drain region 92 of the n-type region 50N diffuses to a first mixed-component interface layer 57, which exists within a stack of nanostructures 55 between the first nanostructure 52 and the second nanostructure 54. For example, phosphors can be n-type dopants that diffuse from the epitaxial source / drain region 92 to the first mixed-component interface layer 57 present in the n-type region 50N, wherein the n-type dopant can increase the etch rate of the first mixed-component interface layer 57 compared to the etch rate of a second mixed-component interface layer 58 including p-type dopant. The diffusion of the n-type dopant can be achieved through thermal diffusion, which can be produced by any annealing step in the process.

[0059] In some embodiments, p-type dopant from the epitaxial source / drain region 92 in the p-type region 50P diffuses to a second mixed-component interface layer 58, which exists within a stack of nanostructures 55 between the first nanostructure 52 and the second nanostructure 54. For example, boron can be a p-type dopant that diffuses from the epitaxial source / drain region 92 to the second mixed-component interface layer 58 present in the p-type region 50P, wherein the p-type dopant can slow down the etching rate of the second mixed-component interface layer 58 compared to the etching rate of the first mixed-component interface layer 57, which includes an n-type dopant. The diffusion of the p-type dopant can be achieved through thermal diffusion, which can be generated by any annealing step in the process. The dopant from the source / drain region 92 also diffuses to the first nanostructure 52 and the second nanostructure 54.

[0060] The difference in etching rates between the first mixed component interface layer 57 and the second mixed component interface layer 58 allows for the simultaneous processing of two stacks of nanostructure 55, while providing different thicknesses for the nanostructures, ultimately providing channel regions for the devices in the n-type region 50N and the p-type region 50P.

[0061] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, as shown in Figure 12A. In other embodiments, as shown in Figure 12C, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed. In the embodiments shown in Figures 12A and 12C, a first spacer 81 may be formed onto the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewalls of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0062] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the first semiconductor material layer 92A.

[0063] Figure 12D illustrates an embodiment in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are recessed, and the outer sidewall of the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54. As shown in Figure 12D, the epitaxial source / drain region 92 may be formed to contact the first internal spacer 90 and may extend beyond the sidewalls of the second nanostructure 54 in the n-type region 50N.

[0064] In Figures 13A to 13C, a first interlayer dielectric (ILD) 96 is deposited over the structures shown in Figures 6A, 12B, and 12A, respectively (the fabrication process in Figures 7A to 12D does not change the cross-section shown in Figure 6A). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD.

[0065] The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed through any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the material covering the first ILD 96.

[0066] In Figures 14A to 14B, a planarization process such as CMP can be performed to make the top surface of the first ILD96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD96 are horizontal within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0067] In Figures 15A and 15B, the dummy gate 76 and mask 78 (if present) are removed in one or more etching steps to form a second recess 98. A portion of the dummy dielectric layer 70 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy dielectric layer 70 are removed via an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The nanostructure 55 serving as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 70 may be used as an etch stop layer when the dummy gate 76 is etched. The dummy dielectric layer 70 may then be removed after the dummy gate 76 has been removed.

[0068] In Figures 16A to 16H, the first nanostructure 52 is removed from the n-type region 50N and p-type region 50P extending the second groove 98. Figures 16A and 16B illustrate the removal of the first nanostructure 52 by performing an isotropic etching process, such as wet etching. In some embodiments, removing the first nanostructure 52 may include using an etchant with a material that selectively removes the first nanostructure 52 while the second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched. The first nanostructure 52 can be removed simultaneously from the first stack in the n-type region 50N and p-type region 50P without the need for a blocking mask and / or a mask to separate the processes applied to the n-type region 50N and p-type region 50P.

[0069] Figure 16C illustrates an embodiment of using a first mixed-component interface layer 57 and a second mixed-component interface layer 58 as etch stop layers to remove a first nanostructure 52. In Figure 16C, the layer including the first mixed-component interface layer 57 is designated as stack 50N', where the stack shown in Figure 16C corresponds to a stack having the first mixed-component interface layer 57 present in the n-type region 50N depicted in Figures 16A, 16B, and 16D. In Figure 16C, the layer including the second mixed-component interface layer 58 is designated as stack 50P', where the stack shown in Figure 16C corresponds to a stack having the second mixed-component interface layer 58 present in the n-type region 50N depicted in Figures 16A, 16B, and 16D.

[0070] Figure 16C illustrates the etching sequence of three stages. The initial stage 300 depicted in Figure 16C shows a stack 50N' depicted in an n-type region 50N and a stack 50P' depicted in a p-type region 50P. A portion of the stacks 50N' and 50P' depicted in Figure 16C includes two second nanostructures 54 having a first nanostructure 52 present between the two depicted second nanostructures 54. The stack 50N' in the n-type region 50N includes a first mixed-component interface layer 57 present at the interface between the first nanostructure 52 and the second nanostructure 54. The stack 50P' in the p-type region 50P includes a second mixed-component interface layer 58 present at the interface between the first nanostructure 52 and the second nanostructure 54. As described above, the first mixed-component interface layer 57 and the second mixed-component interface layer 58 may be formed of elements that diffuse (e.g., thermally diffuse) at least from the source / drain region 92. In some embodiments, the first mixed-component interface layer 57 is a silicon (Si) layer comprising germanium (Ge) in an amount ranging from 0.1% to 5%, and may also include an n-type dopant, such as phosphorus (P). In some embodiments, the second mixed-component interface layer 58 is a silicon (Si) layer comprising germanium (Ge) in an amount ranging from 0.1% to 5%, and may also include a p-type dopant, such as boron (B).

[0071] The first etching stage 310 shown in Figure 16C illustrates the removal of the first nanostructure 52 from the n-type region 50N and the p-type region 50P. In some embodiments, the first nanostructure 52 composed of silicon germanium (SiGe) containing 15% to 40% germanium can be selectively removed from the first mixed-component interface layer 57 of the aforementioned components, through an etching chemical comprising at least one of fluorine (F2) gas, hydrogen fluoride (HF) gas, and nitrogen trifluoride (NF3) gas, wherein the etching temperature is low. For example, the etching of the first nanostructure 52 having the first mixed-component interface layer 57 with the aforementioned components, using the aforementioned etching chemical, can have an etching temperature of 40°C or lower.

[0072] In some embodiments, the first nanostructure 52 composed of silicon germanium (SiGe) containing 15% to 40% germanium can be selectively removed from the second mixed component interface layer 58 of the aforementioned components. This removal can be achieved by using an etching chemical substance comprising at least one of fluorine (F2) gas, hydrogen fluoride (HF) gas, and nitrogen trifluoride (NF3) gas, wherein the etching temperature is low. For example, the etching of the first nanostructure 52 having the second mixed component interface layer 58 of the aforementioned components, using the aforementioned etching chemical substance, can have an etching temperature of 40°C or lower.

[0073] It should be noted that the same etching process used to remove the first nanostructure 52 during the first etching stage 310 can be applied simultaneously to the first stack 50N' and the second stack 50P' of the first nanostructure 52 and the second nanostructure 54 in the n-type region 50N and the p-type region 50P, without the need to use separate etching masks and / or masks to separately apply etchant to the n-type region 50N and the p-type region 50P. In some embodiments, the etching chemicals used to remove the first nanostructure 52 are selective for the first mixed component interface layer 57 and the second mixed component interface layer 58, the second nanostructure 54, the isolation region 68, and the substrate 50.

[0074] It is worth noting that in the first etching stage 310 of the process sequence shown in Figure 16C, the height (also referred to as thickness) of the second nanostructures 54A, 54B, and 54C stacked in the n-type region 50N is equal to the height (also referred to as thickness) of the second nanostructures 54D, 54E, and 54F stacked in the p-type region 50P, as shown in Figures 16A and 16B. Furthermore, in this stage of the process sequence, the first mixed-component interface layer 57 and the second mixed-component interface layer 58 serve as etch stop layers and are essentially not etched by the etching chemicals used to remove the first nanostructure 52. Therefore, the first mixed-component interface layer 57 and the second mixed-component interface layer 58 also have substantially the same height (also referred to as thickness) after the first etching stage 310.

[0075] Referring to Figures 16C to 16E, a second etching stage 320 can be applied to trim the height of the structure including the first nanostructure 52 and the first mixed-component interface layer 57 and the second mixed-component interface layer 58. The second etching stage 320 may be referred to as trimming etching. During the second etching stage, the etching rate of the first mixed-component interface layer 57 is increased due to the presence of the n-type dopant (e.g., phosphorus (P)) compared to the etching rate of the second mixed-component interface layer 58, which does not contain an n-type dopant. The second mixed-component interface layer 58 is p-type doped, for example, doped with boron (B). As described above, the n-type dopant present in the first mixed-component interface layer 57 diffuses from the source / drain region 92 along with the p-type dopant present in the second mixed-component interface layer 58. The source / drain region 92 in the n-type region 50N is doped with an n-type dopant, so the n-type dopant can be introduced (e.g., thermally diffused) into the stack 50N' including the first mixed-component interface layer 57 present in the n-type region 50N. The source / drain region 92 in the p-type region 50P is doped with a p-type dopant, so the p-type dopant can be introduced (e.g., thermally diffused) into the stack 50P' which includes a second mixed component interface layer 58 present in the p.

[0076] For example, the first mixed-component interface layer 57 is a silicon-containing layer comprising up to 5% germanium and up to 1% phosphorus (P); the second mixed-component interface layer 58 is a silicon-containing layer comprising up to 5% germanium and up to 1% boron (B). In some embodiments, phosphorus (P) increases the etching rate (also referred to as trimming rate) of the first mixed-component interface layer 57. For example, during the second etching stage 320, the etching rate of phosphorus (P)-doped silicon germanium (SiGe) is greater than the etching rate of undoped silicon germanium. Furthermore, during the second etching stage 320, the etching rate of undoped silicon germanium (SiGe) is greater than the etching rate of boron (B)-doped silicon germanium (SiGe). For example, the etching rate of the second mixed-component interface layer is reduced due to the presence of p-type dopants (e.g., boron (B)) compared to the etching rate of the first mixed-component interface layer 57, which does not contain p-type dopants.

[0077] Figures 21A and 21B illustrate how n-type and p-type dopants (e.g., phosphorus (P) and boron (B)) affect the etching rate of silicon-germanium using etching gases containing hydrogen and fluorine. Figure 21A is a graph of the activation energy of the chemical reaction induced by fluorine (fluorine migration) in silicon-germanium, e.g., the ease with which silicon-germanium is etched. Activation energy is the energy required for a system to undergo a chemical reaction. A higher activation energy means that the etchant material has less energy and requires more thermal energy to etch.

[0078] The lower the activation energy, the faster the etching rate. Curve 301 is the activation energy of phosphorus (P) doped silicon-germanium (SiGe) material. Curve 302 is the activation energy of undoped silicon-germanium (SiGe) material without n-type or p-type dopants. Curve 303 is the activation energy of boron (B) doped silicon-germanium (SiGe) material.

[0079] The activation energy of phosphorus-doped silicon germanium (SiGe) is lower than that of undoped silicon germanium (SiGe) with n-type or p-type dopants. For fluorine-containing etchants, the etching rate of phosphorus (P)-doped silicon germanium (SiGe) is greater than that of undoped silicon germanium (SiGe) with n-type or p-type dopants. The activation energy of boron-doped silicon germanium (SiGe) is greater than that of undoped silicon germanium with n-type or p-type dopants. For fluorine-containing etchants, the etching rate of boron (B)-doped silicon germanium is lower than that of undoped silicon germanium with n-type or p-type dopants.

[0080] Figure 21B is a graph showing the activation energy of chemical reactions induced by hydrogen in silicon-germanium, for example, the ease of etching silicon-germanium. Curve 401 is the activation energy of silicon-germanium (SiGe) material doped with phosphorus (P). Curve 402 is the activation energy of silicon-germanium (SiGe) material without n-type or p-type dopants. Curve 403 is the activation energy of silicon-germanium (SiGe) material doped with boron (B).

[0081] The activation energy of phosphorus-doped silicon germanium (SiGe) is lower than that of undoped silicon germanium (SiGe) with n-type or p-type dopants. For hydrogen-containing etchants, the etching rate of phosphorus-doped silicon germanium (SiGe) is greater than that of undoped silicon germanium (SiGe) with n-type or p-type dopants. The activation energy of boron-doped silicon germanium (SiGe) is greater than that of undoped silicon germanium with n-type or p-type dopants. For hydrogen-containing etchants, the etching rate of boron-doped silicon germanium (SiGe) is lower than that of undoped silicon germanium with n-type or p-type dopants.

[0082] In some embodiments, the second etching stage 320 (trimming etch) etches the first mixed-component interface layer 57 to a greater extent than the second component interface layer 58. This results in the first mixed-component interface layer 57 having a smaller height (also referred to as thickness) than the second mixed-component interface layer 58 after the second etching stage 320 (trimming etch). In some embodiments, the difference in etching rate between the first mixed-component interface layer 57 and the second mixed-component interface layer 58 can result in a height difference (also referred to as thickness) between the simultaneously etched first mixed-component interface layer 57 and the second mixed-component interface layer 58, which can range from 0.5 nm to 1.5 nm. In one example, the difference in etching rate between the first mixed-component interface layer 57 and the second mixed-component interface layer 58 can result in a height difference (also referred to as thickness) between the simultaneously etched first mixed-component interface layer 57 and the second mixed-component interface layer 58, which can range from 0.5 nm to 1.5 nm.

[0083] In some embodiments, the first mixed-component interface layer 57 is composed of silicon (Si), which includes up to 5% germanium (Ge) and up to 1% phosphorus (P); the second mixed-component interface layer 58 is composed of silicon (Si), which includes up to 5% germanium (Ge) and up to 1% boron (B). The etching chemicals of the second etching stage 320 may include ammonia (NH3) gas, and the temperature at the second etching stage 320 is applied at a higher temperature than that of the first etching stage 310. For example, the etching chemicals of the second etching stage 320 may include fluorine (F2) gas, hydrogen fluoride (HF) gas, nitrogen trifluoride (NF3) gas, and ammonia (NH3) gas. For example, the etching temperature used to selectively trim the height (also referred to as thickness) of the first mixed-component interface layer 57 relative to the second mixed-component interface layer 58 may be an etching temperature greater than 40°C.

[0084] It should be noted that the same etching process used to trim the first mixed-component interface layer 57 during the second etching stage 320 can be applied simultaneously to the first stack 50N' and the second stack 50P' of the second nanostructure 54 in the n-type region 50N, without the need to use separate etching masks and / or masks to separately apply etchant to the n-type region 50N and the p-type region 50P. In some embodiments, the etching chemicals used to selectively trim the first mixed-component interface layer 57 to the second mixed-component interface layer 58 can also be selective for the second nanostructure 54, the isolation region 68, and the substrate 50.

[0085] Figure 16F illustrates the stacking of the second nanostructure 54 and, after the second etching stage 320, the height and width dimensions of the remaining portions of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 in the n-type region 50N and the p-type region 50P. Figure 16F illustrates the different sheet heights between the remaining portions of the first mixed-component interface layer 57 and the second nanostructure 54 in the n-type region 50N, and between the remaining portions of the second mixed-component interface layer 58 and the nanostructure 54 in the p-type region 50P. Figure 16F shows that the sheet heights HN1, HN2, HN3 provided by the first mixed-component interface layer 57 and the second nanostructure 54 in the n-type region 50N are smaller than the sheet heights HP1, HP2, HP3 provided by the second mixed-component interface layer 58 and the second nanostructure 54 in the p-type region 50P. Figure 16F further illustrates that the sheet widths WN1, WN2, WN3 provided by the first mixed component interface layer 57 and the second nanostructure 54 in the n-type region 50N are equal to the sheet widths WP1, WP2, WP3 provided by the second mixed component interface layer 58 and the second nanostructure 54 in the p-type region 50P.

[0086] In one example, the wafer heights HN1, HN2, and HN3 provided by the first mixed-component interface layer 57 and the second nanostructure 54 in the n-type region 50N can be in the range of 3 nm to 8 nm. In one example, the wafer heights HP1, HP2, and HP3 provided by the second mixed-component interface layer 58 and the second nanostructure 54 in the p-type region 50P can be in the range of 3 nm to 8 nm. However, the wafer heights resulting from the differential etching process used to simultaneously etch the first mixed-component interface layer 57 and the second mixed-component interface layer 58 can vary, ranging from 0.3 nm to 1 nm. For example, when the wafer height difference is 1 nm, the wafer heights HN1, HN2, and HN3 of the first mixed-component interface layer 57 and the second nanostructure 54 in the n-type region 50N are equal to 4 nm, and the wafer heights HP1, HP2, and HP3 provided by the second mixed-component interface layer 58 and the second nanostructure 54 in the p-type region 50P are equal to approximately 5 nm. In some embodiments, the sheet widths WN1, WN2, WN3 provided by the first mixed component interface layer 57 and the second nanostructure 54 in the n-type region 50N are substantially equal to (e.g., within + / - 0.2 nm or less) the sheet widths WP1, WP2, WP3 provided by the second mixed component interface layer 58 and the second nanostructure 54 in the p-type region 50P.

[0087] Figure 16F also shows the vertical spacing dimensions SN1, SN2, SN3 separating the adjacent stacked structures of the second nanostructure 54 and the first mixed-component interface layer 57 in the n-type region 50N after the second etching stage 320, and the vertical spacing dimensions SP1, SP2, SP3 separating the adjacent stacked structures of the second nanostructure 54 and the second mixed-component interface layer 58 in the p-type region 50P. By allowing independent control of the vertical spacing in the n-type region 50N and the p-type region 50P, the methods and structures described herein can provide tunable NFET and PFET performance. In some embodiments, tunable NFET and PFET performance is provided through different vertical spacings of semiconductor layers (e.g., nanosheets), and the methods and structures described herein can have better wafer acceptance testing (WAT) performance.

[0088] Figure 16F shows that the vertical spacing dimensions SN1, SN2, SN3 separating the adjacent stacked structures of the second nanostructure 54 and the first mixed component interface layer 57 in the n-type region 50N are larger than the vertical spacing dimensions SP1, SP2, SP3 separating the adjacent stacked structures of the second nanostructure 54 and the second mixed component interface layer 58 in the p-type region 50P. For example, the vertical spacing dimensions SN1, SN2, SN3 separating the adjacent stacked structures of the second nanostructure 54 and the first mixed component interface layer 57 in the n-type region 50N can be in the range of 3 nm to 8 nm. For example, the vertical spacing dimensions SP1, SP2, SP3 separating the adjacent stacked structures of the second nanostructure 54 and the first mixed component interface layer 57 in the p-type region 50P can be in the range of 3 nm to 8 nm. However, the vertical spacing dimensions differ due to the differential etching process used to simultaneously etch the first mixed component interface layer 57 and the second mixed component interface layer 58. In some embodiments, the difference in vertical spacing dimensions can be in the range of 0.3 nm to 1 nm. For example, when the difference in vertical spacing size is 1 nm, the vertical spacing sizes SN1, SN2, and SN3 of the adjacent stacked structures of the second nanostructure 54 and the first mixed component interface layer 57 in the n-type region 50N are equal to 4 nm, and the vertical spacing sizes SP1, SP2, and SP3 of the adjacent stacked structures separating the second nanostructure 54 and the first mixed component interface layer 57 in the p-type region 50P can be equal to 3 nm.

[0089] Referring to Figure 16E, although there is a difference in the vertical spacing between the nanostructures in the p-type region 50P and the n-type region 50N, the critical dimensions CDN1, CDN2, CDN3 (channel lengths) of the second nanostructure 54 in the n-type region 50N are the same as the critical dimensions CDP1, CDP2, CDP3 (channel lengths) of the second nanostructure 54 in the p-type region 50P. For example, the critical dimensions CDN1, CDN2, CDN3 (channel lengths) of the second nanostructure 54 in the n-type region 50N can be from 10 nm to 20 nm, and the critical dimensions CDP1, CDP2, CDP3 (channel lengths) of the second nanostructure 54 in the n-type region 50N can be from 10 nm to 20 nm.

[0090] Figure 16E also shows that for each n-type region 50N and each p-type region 50P, a channel region is provided by a second nanostructure 54 and a trimmed first mixed-component interface layer 57 and a trimmed second mixed-component interface layer 58. During the trimming step described above, a portion of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 overlaps with the first internal spacer 90. The portions of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 that contact (overlap) with the first internal spacer 90 are protected from etching used to trim the channel height. The protected portions of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 retain their original height after the etching process described above. The original height of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 at the ends of the channel region and the thinned central portions of the first mixed-component interface layer 57 and the second mixed-component interface layer 58 create a channel region with a cross-section having an H-shaped geometry.

[0091] Figure 16G illustrates the total height of the stacks 50N' and 50P' of the remaining portions of the second nanostructure 54 with the first mixed-component interface layer 57 and the second mixed-component interface layer 58 after the second etching stage 320, for each n-type region 50N and each p-type region 50p. The total height TN1 of the stack in the n-type regions is equal to the total height TP1 of the stack in the p-type regions. The total height TN1 and the total height TP1 are the dimensions from the upper surface of the isolation region 68 to the upper surface of the second nanostructure 54 providing the top sheet for the stack. In one example, the total height TN1 of the stack in the n-type region 50N can be in the range of 40 nm to 60 nm, and the total height TP1 of the stack in the p-type region 50P can be in the range of 40 nm to 60 nm.

[0092] In the embodiment shown in Figure 16G, each stack 50N' and stack 50P' includes three vertically stacked second nanostructures 54. In some embodiments, although the total heights TP1 and TP2 to the top sheet are the same for each stack 50N' and stack 50P' in the n-type region 50N and the p-type region 50P, the distance from the middle and lower second nanostructures 54 to the isolation region 68 in the n-type region 50N is less than the distance from the middle and lower second nanostructures 54 to the isolation region 68 in the p-type region 50P.

[0093] The total height TN2 and total height TP2 of the intermediate second nanostructure 54 are measured from the upper surface of the isolation region 68. In one example, the total height TN2 of the intermediate second nanostructure 54 in the n-type region 50N ranges from 25 nm to 40 nm. In another example, the total height TP2 of the intermediate second nanostructure 54 in the p-type region 50P ranges from 25 nm to 40 nm. However, the difference between the total height TN2 of the intermediate second nanostructure 54 in the n-type region 50N and the total height TP2 of the intermediate second nanostructure 54 in the p-type region 50P can be in the range of 0.3 nm to 0.5 nm.

[0094] The total height TN3 and total height TP3 of the lower second nanostructure 54 are also measured from the upper surface of the isolation region. In one example, the total height TN3 of the lower second nanostructure 54 in the n-type region 50N ranges from 10 nm to 20 nm. In one example, the total height TP3 of the lower second nanostructure 54 in the p-type region 50P ranges from 10 nm to 20 nm. However, the difference between the total height TN3 of the lower second nanostructure 54 in the n-type region 50N and the total height TP3 of the lower second nanostructure 54 in the p-type region 50P can be in the range of 0.3 nm to 0.5 nm.

[0095] Figure 16H illustrates an embodiment of sheet end rounding occurring at the edge of the second nanostructure 54 during an etching process for removing the first nanostructure 52 and trimming the first mixed-component interface layer 57. As shown in Figure 16H, the second nanostructure 54 in the stack 50N' of the n-type region 50N has more rounded corners than the second nanostructure 54 in the stack 50P' of the p-type region 50P. As shown in Figure 16H, the second nanostructure 54 in the p-type region 50P has more square corners than the second nanostructure 54 in the n-type region 50N. For the second nanostructure 54 in the n-type region 50N, corner trimming dimensions RN1T and RN1B can be applied up to 2 nm (measured from the original corner). For the second nanostructure in the p-type region 50P, corner trimming dimensions RP1T and RP1B can be applied up to 1 nm (measured from the original corner).

[0096] It should be noted that the embodiments depicted in Figures 16A to 16H are provided for illustrative purposes only and are not intended to limit this disclosure to the examples depicted in Figures 16A to 16H. For example, the stack depicted in Figures 16A to 16H includes only three nanostructures. This disclosure is not limited to the number of nanostructures in the stack.

[0097] In Figures 17A and 17B, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second groove 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. In the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, as well as on the top surface, sidewalls, and bottom surface of the second nanostructures 54E, 54C, and 54D. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0098] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structures of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0099] Gate electrodes 102 are deposited above gate dielectric layer 100 and fill the remaining portion of second groove 98. Gate electrode 102 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102 is shown in Figures 17A and 17B, gate electrode 102 may include any number of substrates, any number of work function adjustment layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited in n-type region 50N, between adjacent nanostructures in second nanostructures 54B and 54C, and between second nanostructure 54A and substrate 50, and in p-type region 50P, may be deposited between adjacent nanostructures in second nanostructures 54E and 54F, and between second nanostructure 54D and substrate 50.

[0100] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material. Similarly, the formation of the gate electrode 102 can be performed simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed through different processes, such that the gate dielectric layer 100 in each region can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 can be formed through different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0101] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102, which are located above the top surface of the first ILD 96. The remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 thus form an alternative gate structure for the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0102] In Figures 18A to 18C, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) can be recessed such that the recess is formed directly on the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. The subsequently formed gate contact (e.g., gate contact 114, discussed below with reference to Figures 20A to 20C) penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0103] As further shown in Figures 18A to 18C, the second ILD 106 is deposited over the first ILD 96 and over the gate shield 104. In some embodiments, the second ILD 106 is a flowable film formed via FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0104] In Figures 19A to 19C, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third groove 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third groove 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, etc.). In some embodiments, a first etching process can be used to etch through the second ILD 106 and the first ILD 96; a second etching process can be used to etch through the gate mask 104; and then a third etching process can be used to etch through the CESL 94 to form the third groove 108. A mask, such as photoresist, can be formed and patterned over the second ILD 106 to shield a portion of the second ILD 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch; therefore, the third groove 108 may extend into the epitaxial source / drain region 92 and / or gate structure. The bottom of the third groove 108 may be flush with the substrate (e.g., at the same level as the substrate, or at the same distance) or below (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or gate structure. Although Figure 19B shows the third groove 108 exposing the epitaxial source / drain region 92 and gate structure in the same cross-section, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts. In some embodiments, the silicate region 110 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) to form a silicate or germanide region over the exposed portion of the epitaxial source / drain region 92, wherein the metal is, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, and then performing a thermal annealing process to form the silicate region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicate region 110 is referred to as a silicate region, it can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicate and germanide). In an embodiment, the silicate region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0105] Next, in Figures 20A to 20C, contacts 112 and 114 (also referred to as contact plugs) are formed in the third groove 108. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive components (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0106] Figures 20A to 20C illustrate a semiconductor device including a substrate 50, the substrate 50 including a first device region (e.g., an n-type region 50N) and a second device region (e.g., a p-type region 50P). In some embodiments, a first type of device (e.g., an n-type device) is present in the first device region. In some embodiments, the first type of device includes a first nanostructure stack and a first gate stack (gate electrode 102, gate dielectric 100) surrounding each first nanostructure. The first nanostructure may be provided by second nanostructures 54A, 54B, 54C present in the n-type region 50N. In some embodiments, each first nanostructure of the first nanostructure stack has a first height HN1, HN2, HN3. In some embodiments, a second type of device (e.g., a p-type device) in the second device region (e.g., the p-type region 50P) includes a second nanostructure stack and a second gate stack (gate electrode 102, gate dielectric 100) surrounding each first nanostructure. The second nanostructure stack is provided by second nanostructures 54D, 54E, and 54F present in the p-type region 50P. In some embodiments, each second nanostructure in the second nanostructure stack has a second height HP1, HP2, and HP3. The second heights HP1, HP2, and HP3 are different from the first heights HN1, HN2, and HN3. For example, the second heights HP1, HP2, and HP3 may be greater than the first heights HN1, HN2, and HN3. In some embodiments, the first spacings SN1, SN2, and SN3 between adjacent stacked nanostructures in the second nanostructure stacks 54A, 54B, and 54C are greater than the second spacings SP1, SP2, and SP3 between adjacent stacked nanostructures 54D, 54E, and 54F in the second nanostructure stack. In some embodiments, each first nanostructure in the first nanostructure stack (provided by second nanostructures 54A, 54B, 54C) has a first width WN1, WN2, WN3, and each second nanostructure in the second nanostructure stack (provided by second nanostructures 54D, 54E, 54F) has a second width WP1, WP2, WP3, and the first width is equal to the second width.

[0107] The size difference of the nanostructures in the p-type region 50P and the n-type region 50N can be provided by a first mixed-component interface layer 57 and a second mixed-component interface layer 58 with different etch rates. As described above, the n-type dopant present in the first mixed-component interface layer 57 increases the etch rate of the first mixed-component interface layer 57 relative to the second mixed-component interface layer 58 which does not contain n-type dopant. In some embodiments, the second nanostructures 54a, 54b, 54c, 54d, 54e, and 54f can be referred to as the core of the nanostructure, and the first mixed-component interface layer 57 and the second mixed-component interface layer 58 can be referred to as surface layers, existing on the core of the nanostructure.

[0108] The embodiments can achieve the following advantages. For example, the methods and structures described herein can provide a simple process for providing nanosheet stacks with different nanosheet heights. More specifically, nanosheet stacks with different nanosheet heights can be formed simultaneously using a single-step etching process without requiring additional patterning processes to individually process individual nanosheet stacks to provide different nanosheet heights. The methods and structures provided herein can provide adjustable nanosheet heights within a single nanosheet stack. The methods and structures provided herein can provide a larger process view for wafer acceptance test (WAT) control.

[0109] In some embodiments, a semiconductor device is described, including a substrate comprising a first device region and a second device region; a first type device is located in the first device region, the first type device including a first nanostructure stack and a first gate stack, the first gate stack surrounding the first nanostructure stack, wherein the first nanostructure has a first total height, and each first nanostructure in the first nanostructure stack has a first height; a second type device is located in the second device region, the second type device including a second nanostructure stack and a second gate stack, the second gate stack surrounding the second nanostructure stack, wherein the second nanostructure stack has a second total height, and each second nanostructure in the second nanostructure stack has a second height, the first total height and the second total height are equal, and the second height is different from the first height. In some embodiments, the first type device has a first source / drain region of n-type conductivity at opposite ends of each first nanostructure of the first nanostructure stack, and the second type device has a second source / drain region of p-type conductivity at opposite ends of each second nanostructure of the second nanostructure stack. In some embodiments, the second height is higher than the first height. In some embodiments, a first spacing between adjacent nanostructure stacks in a first nanostructure stack is greater than a second spacing between adjacent nanostructure stacks in a second nanostructure stack. In some embodiments, each first nanostructure in the first nanostructure stack has a first width, and each second nanostructure in the second nanostructure stack has a second width, wherein the first width is equal to the second width. In some embodiments, a first curvature of a first sidewall of each first nanostructure in the first nanostructure stack is greater than a second curvature of a second sidewall of each first nanostructure in the second nanostructure stack.

[0110] In some embodiments, a semiconductor device is described, including a substrate comprising a first device region and a second device region; a first type device located in the first device region, the first type device including a first nanostructure stack and a first gate stack, the first gate stack surrounding the first nanostructure stack, wherein each first nanostructure of the first nanostructure stack includes a first core of a first semiconductor element and a first conductivity type dopant, a second semiconductor element and a first surface layer of the first semiconductor element, wherein the first nanostructure stack has a first total height and the first core and the first surface layer have a first combined thickness; a second type device located in the second device region, the second type device including a second nanostructure stack and a second gate stack, the second gate stack surrounding the second nanostructure stack, wherein each second nanostructure of the second nanostructure stack includes a second core of a first semiconductor element and a second conductivity type dopant, a second semiconductor element and a second surface layer of the first semiconductor element, wherein the second nanostructure stack has a second total height and the second core and the second surface layer have a second combined thickness, wherein the first total height is equal to the second total height and the second combined thickness is different from the first combined thickness. In some embodiments, a first-type device has a first source / drain region of n-type conductivity at opposite ends of each first nanostructure in a first nanostructure stack, and a second-type device has a second source / drain region of p-type conductivity at opposite ends of each second nanostructure in a second nanostructure stack. In some embodiments, a first semiconductor element comprises silicon, and a second semiconductor element comprises germanium. In some embodiments, a second composite thickness is greater than a first composite thickness, and a first core has a thickness equal to that of a second core. In some embodiments, a first spacing between adjacent nanostructure stacks in a first nanostructure stack is greater than a second spacing between adjacent nanostructure stacks in a second nanostructure stack, wherein each first nanostructure in a first nanostructure stack has a first width, and each second nanostructure in a second nanostructure stack has a second width, the first width being equal to the second width. In some embodiments, a first conductivity type dopant is an n-type dopant, and a second conductivity type dopant is a p-type dopant. In some embodiments, an n-type dopant is phosphorus, and a p-type dopant is boron.

[0111] In some other embodiments, the method of forming a semiconductor device includes the following steps: forming a first stack of a first semiconductor layer and a second semiconductor layer in a first region of a substrate, and forming a second stack of the first semiconductor layer and the second semiconductor layer in a second region of the substrate, the second semiconductor layer of the first stack including a first conductivity type dopant, the second semiconductor layer of the second stack including a second conductivity type dopant, wherein a mixed component interface layer exists between each of the first semiconductor layer and each of the second semiconductor layer in the first and second stacks. Removing the first semiconductor layer by selectively etching at least the mixed component interface layer in the first and second stacks. Etching the mixed component interface layer in the first and second stacks, wherein the first conductivity type dopant in the mixed component interface layer in the first stack increases the etching rate of the mixed component interface layer in the first stack compared to the mixed component interface layer in the second stack. Forming a first gate stack on the first stack and forming a second gate stack on the second stack.

[0112] In some embodiments, after etching the mixed-component interface layer of the first stack and the second stack, a first remaining portion of the mixed-component interface layer in the first stack and the second semiconductor layer provide a first height, and after etching the mixed-component interface layer of the first stack and the second stack, a second remaining portion of the mixed-component interface layer in the second stack and the second semiconductor layer provide a second height, wherein the second height is greater than the first height. In some embodiments, the first conductivity type dopant in the silicon-containing material of the second semiconductor layer in the first stack is an n-type dopant, and the second conductivity type dopant in the silicon-containing material of the second semiconductor layer in the second stack is a p-type dopant. In some embodiments, the n-type dopant is phosphorus, and the p-type dopant is boron. In some embodiments, the mixed-component interface layer in the first stack includes a first conductivity type dopant, silicon, and up to 5% germanium, and the mixed-component interface layer in the second stack includes a second conductivity type dopant, silicon, and up to 5% germanium. In some embodiments, the removal of the first semiconductor layer by selective etching of at least the mixed-component interface layer in the first and second stacks includes an etching chemical selected from the group consisting of F2, HF, NF3, and combinations thereof, wherein the etching temperature is below 40°C. In some embodiments, etching of the mixed-component interface layer in the first and second stacks includes an etching chemical comprising ammonia (NH3), wherein the etching temperature is above 40°C.

[0113] The foregoing has summarized the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a three-dimensional view illustrating an example of a nanostructure field-effect transistor (nano-FET) according to some embodiments. Figures 2, 3, 4, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 13A, 13B, 13C, 14A, 14B, 15A Figures 15B, 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H, 17A, 17B, 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, and 20C are cross-sectional views of intermediate stages in the fabrication of nanoFETs according to some embodiments. Figure 21A is a diagram of the activation energy of the chemical reaction induced by fluorine in silicon-germanium according to some embodiments. Figure 21B is a diagram of the activation energy of the chemical reaction induced by hydrogen in silicon-germanium. [Biomaterial Storage]

[0115] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device, comprising: A substrate, including a first device region and a second device region; A first type device, located in the first device region, the first type device includes a first nanostructure stack and a first gate stack, the first gate stack surrounding the first nanostructure stack, wherein the first nanostructure has a first total height, and each first nanostructure in the first nanostructure stack has a first height, wherein each first nanostructure includes a first semiconductor layer and a first mixed component interface layer, the first mixed component interface layer having a first thickness; and a second type device, located in the second device region, the second type device includes a second nanostructure stack and a second gate stack, the second gate stack surrounding the second nanostructure stack, wherein the second nanostructure stack has a second total height, and each second nanostructure in the second nanostructure stack has a second height, the first total height and the second total height being equal, and the second height being different from the first height, wherein each second nanostructure includes a second semiconductor layer and a second mixed component interface layer, the second mixed component interface layer having a second thickness, the second thickness being greater than the first thickness.

2. The semiconductor device as claimed in claim 1, wherein a first spacing between adjacent nanostructure stacks in the first nanostructure stack is greater than a second spacing between adjacent nanostructure stacks in the second nanostructure stack.

3. The semiconductor device as claimed in claim 1, wherein each first nanostructure in the first nanostructure stack has a first width, and each second nanostructure in the second nanostructure stack has a second width, the first width being equal to the second width.

4. The semiconductor device as claimed in claim 1, wherein a first curvature of a first sidewall of each first nanostructure in the first nanostructure stack is greater than a second curvature of a second sidewall of each first nanostructure in the second nanostructure stack.

5. A semiconductor device, comprising: A substrate, including a first device region and a second device region; a first type device located in the first device region, the first type device including a first nanostructure stack and a first gate stack, the first gate stack surrounding the first nanostructure stack, wherein each first nanostructure of the first nanostructure stack includes a first core of a first semiconductor element and a first conductivity type dopant, a second semiconductor element and a first surface layer of the first semiconductor element, wherein the first nanostructure stack has a first total height, and the first core and the first surface layer have a first combined thickness, the first surface layer having a first thickness; and a second type device located in the second device region, the second type... The device includes a second nanostructure stack and a second gate stack surrounding the second nanostructure stack. Each second nanostructure in the second nanostructure stack includes a second core of the first semiconductor element and a second conductivity type dopant, the second semiconductor element, and a second surface layer of the first semiconductor element. The second nanostructure stack has a second total height, and the second core and the second surface layer have a second combined thickness. The first total height is equal to the second total height, and the second combined thickness is different from the first combined thickness. The second surface layer has a second thickness that is greater than the first thickness.

6. The semiconductor device as claimed in claim 5, wherein the first type device has a first source / drain region of n-type conductivity at opposite ends of each first nanostructure in the first nanostructure stack, and the second type device has a second source / drain region of p-type conductivity at opposite ends of each second nanostructure in the second nanostructure stack.

7. The semiconductor device as claimed in claim 5, wherein the second assembly thickness is greater than the first assembly thickness, and the first core has a thickness equal to that of the second core.

8. The semiconductor device of claim 5, wherein a first spacing between adjacent nanostructure stacks in the first nanostructure stack is greater than a second spacing between adjacent nanostructure stacks in the second nanostructure stack, wherein each first nanostructure in the first nanostructure stack has a first width, and each second nanostructure in the second nanostructure stack has a second width, the first width being equal to the second width.

9. A method of forming a semiconductor device, comprising: A first stack of a first semiconductor layer and a second semiconductor layer is formed in a first region of a substrate, and a second stack of the first semiconductor layer and the second semiconductor layer is formed in a second region of the substrate. The second semiconductor layer of the first stack includes a first conductivity type dopant, and the second semiconductor layer of the second stack includes a second conductivity type dopant. A mixed component interface layer exists between each of the first semiconductor layer and each of the second semiconductor layer in the first stack and the second stack. The first semiconductor layer is removed by selective etching of the mixed component interface layer in the first stack and the second stack. The mixed component interface layer in the first stack and the second stack is etched, wherein the first conductivity type dopant in the mixed component interface layer in the first stack increases the etch rate of the mixed component interface layer in the first stack compared to the mixed component interface layer in the second stack, such that a first thickness of the mixed component interface layer in the first stack is less than a second thickness of the mixed component interface layer in the second stack. A first gate stack is formed on the first stack, and a second gate stack is formed on the second stack.

10. The method of claim 9, wherein after etching the mixed component interface layer of the first stack and the second stack, a first remaining portion of the mixed component interface layer in the first stack and the second semiconductor layer provide a first height, and after etching the mixed component interface layer of the first stack and the second stack, a second remaining portion of the mixed component interface layer in the second stack and the second semiconductor layer provide a second height, and wherein the second height is greater than the first height.

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