Semiconductor device and method of forming the same

Abstract

The semiconductor device of this invention includes a first semiconductor substrate, a dielectric material, a first interconnect structure, and a first bonding structure. The first semiconductor substrate has a first inclined sidewall. The dielectric material is located above the first semiconductor substrate and has a sidewall, a second inclined sidewall, and a transition point between the sidewall and the second inclined sidewall. The first interconnect structure is located above the first semiconductor substrate and is at least laterally surrounded by the dielectric material. The first bonding structure is located above the first interconnect structure and is at least laterally surrounded by the dielectric material.

Description

Prior Technology

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various components, such as transistors, diodes, resistors, and capacitors. To a large extent, this improvement in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Technological advancements in integrated circuit (IC) design have produced generation after generation of ICs, each with smaller and more complex circuit designs than the previous one. Continued efforts are being made to develop new mechanisms for semiconductor structures that improve electrical performance. Simple Explanation of the Diagram

[0002] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1A to 1E illustrate various cross-sectional views of methods for forming a semiconductor device according to some embodiments. Figures 2A to 2C illustrate various cross-sectional views of methods for forming semiconductor structures according to some embodiments. Figure 3 illustrates a cross-sectional view of a semiconductor device according to some embodiments. Figures 4A and 4B illustrate various cross-sectional views of methods for forming a semiconductor device according to some embodiments. Figure 5 illustrates a cross-sectional view of a semiconductor device according to some embodiments. Figures 6A to 6E illustrate various cross-sectional views of methods for forming a semiconductor device according to some embodiments. Figure 7 illustrates a cross-sectional view of a semiconductor device according to some embodiments. Figure 8 illustrates a flowchart of a method for forming a semiconductor device according to some embodiments. Implementation

[0003] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "overlapping," "upper," and similar terms may be used herein to describe the relationship between one element or feature and another element or feature as shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0005] Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and similar operations. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0006] Figures 1A to 1E illustrate various cross-sectional views of methods for forming a semiconductor device according to some embodiments.

[0007] Referring to FIG1A, a semiconductor substrate 1100 is provided. The semiconductor substrate 1100 includes a plurality of grain regions 110-1, 110-2 and a plurality of dicing regions 110D located between the grain regions 110-1, 110-2. The grain regions 110-1, 110-2 may be separated by the dicing regions 110D, and subsequent dicing processes are performed in the dicing regions 110D. For example, the grain regions 110-1, 110-2 are diced to form individual semiconductor grains 110. Each semiconductor die 110 may be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), a combination thereof (e.g., a system-on-a-chip (SoC) die), or a similar device.

[0008] In some embodiments, each semiconductor die 110 includes a first semiconductor substrate 112, a first device 114 formed in / on the first semiconductor substrate 112, a first interconnect structure 116 formed on the first semiconductor substrate 112 and electrically coupled to the first device 114, and a first bonding structure 118 formed on the first interconnect structure 116 and electrically coupled to the first interconnect structure 116. The first semiconductor substrate 112 may be an active layer of a doped or undoped silicon substrate or a semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 112 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide; or combinations thereof. Other suitable substrates, such as multilayer substrates or gradient substrates, may be used.

[0009] The first semiconductor substrate 112 may include a front side 112a and a back side 112b opposite to the front side 112a. For example, a first device 114 is formed on the front side 112a of the first semiconductor substrate 112. The first device 114 may include active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, inductors, etc.), combinations thereof, or similar devices. It should be noted that the number and type of the first devices 114 may differ from those shown.

[0010] Referring again to FIG1A, a first interconnect structure 116 may be formed on the front side 112a of a first semiconductor substrate 112 and may be electrically coupled to a first device 114 to form an integrated circuit. The first interconnect structure 116 may be disposed in a first dielectric layer 1161 and include a first metallization pattern 1162. The material of the first dielectric layer 1161 may include oxides (e.g., silicon oxide or aluminum oxide), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), similar materials, or combinations thereof. Each first metallization pattern 1162 may include conductive pads, conductive lines, conductive vias, combinations thereof, and / or similar materials. The first metallization pattern 1162 may also be referred to as metal layer 0 (M0), metal layer 1 (M1), metal layer 2 (M2), metal layer 3 (M3)... metal layer x (Mx), and via layers 0 (V0), 1 (V1), 2 (V2), 3 (V3)... via (x-1)(V(x-1)) inserted between two adjacent metal layers. Each first metallization pattern 1162 may be formed of a conductive material, such as copper, cobalt, aluminum, gold, combinations thereof, or similar materials. It should be noted that the first dielectric layer 1161 and the first metallization pattern 1162 may have different configurations than those shown.

[0011] In some embodiments, a first bonding structure 118 may be disposed in a first bonding dielectric layer 1181 and include a first bonding member 1182. The first bonding dielectric layer 1181 may be formed of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, and / or the like. The first bonding member 1182 may be formed of a conductive material, such as copper, aluminum, or the like. Each first bonding member 1182 may be a conductive pad, a conductive via, a combination thereof, etc. In some embodiments, the first bonding member 1182 is electrically connected to a first metallization pattern 1162 of the first interconnect structure 116. It should be noted that the first bonding dielectric layer 1181 and the first bonding member 1182 may have different configurations than those shown. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), grinding, etching, combinations thereof, or similar processes) is performed such that the top surfaces (1181t and 1182t) of the first bonding dielectric layer 1181 and the first bonding member 1182 are substantially flush (or coplanar) within the range of process variations.

[0012] Referring again to FIG1A, each first semiconductor die 110 includes a functional region 110A and a sealing ring region 110S surrounding the functional region 110A. For example, the sealing ring region 110S is located between the functional region 110A and the dicing region 110D, while the dicing region 110D is located between two adjacent die regions 110-1 and 110-2. In some embodiments, the first device 114, the first metallization pattern 1162, and the first bonding member 1182 are located within the functional region 110A. In some embodiments, the first bonding dielectric layer 1181 and the first dielectric layer 1161 both span the functional region 110A, the sealing ring region 110S, and the dicing region 110D.

[0013] In some embodiments, one or more sealing rings 117 may be formed in the first dielectric layer 1161 and within the sealing ring region 110S. For example, the sealing rings 117 are disposed in the peripheral region of each first semiconductor die 110. In some embodiments, each sealing ring 117 is configured to surround a first metallization pattern 1162 in the functional region 110A. The sealing ring 117 may include conductive vias and conductive pads, which are vertically stacked and interconnected by the conductive vias, wherein the conductive pads of the sealing ring 117 may be at the same level as the conductive pads of the first metallization pattern 1162, and the conductive vias of the sealing ring 117 may be at the same level as the conductive vias of the first metallization pattern 1162. Each first semiconductor die 110 may (or may not) include any metallization pattern and / or conductive features outside the sealing ring 117. It should be noted that the sealing ring 117 may have a different configuration than that shown.

[0014] Referring again to FIG1A, the first bonding structure 118 may include an additional bonding member 1182D, which is embedded in the first bonding dielectric layer 1181 and formed above the sealing ring 117 within the sealing ring region 110S. The additional bonding member 1182D may be formed at the same level as the first bonding member 1182. In some embodiments, the additional bonding member 1182D is electrically and spatially isolated from the sealing ring 117 at least through the first bonding dielectric layer 1181. In an alternative embodiment, the additional bonding member 1182D is physically connected to the underlying sealing ring 117. In some embodiments, the additional bonding member 1182D is a dummy bonding member and is electrically floating in each of the first semiconductor dies 110. For example, the presence of the additional bonding member 1182D helps to increase pattern uniformity and metal density, thereby facilitating subsequent bonding processes. Alternatively, the additional bonding member 1182D may be omitted, and a conductive feature may not be formed directly above the sealing ring 117.

[0015] In some embodiments, the cut region 110D may include a plurality of virtual conductive patterns 1162D therein. The virtual conductive patterns 1162D include non-functional conductive features such as virtual conductive pads, virtual conductive lines, virtual conductive vias, combinations thereof, and / or similar features. Each virtual conductive pattern 1162D may be formed of a conductive material such as copper, cobalt, aluminum, gold, combinations thereof, or similar features. The virtual conductive patterns 1162D may be formed simultaneously with the first metallization pattern 1162 and formed in the first dielectric layer 1161. Here, when an element is described as "substantially at the same level," the element is formed at substantially the same height in the same layer, or has the same position embedded in the same layer. In some embodiments, elements substantially at the same level are formed from the same material using the same process steps. In some embodiments, the tops of elements substantially at the same level are substantially coplanar. For example, the virtual conductive pattern 1162D is substantially at the same level as the first metallization pattern 1162. Specifically, the surface (e.g., top surface) of the virtual conductive pattern 1162D is substantially coplanar with the surface (e.g., top surface) of the first metallization pattern 1162 of the first interconnect structure 116. In some embodiments, the virtual conductive pattern 1162D is a virtual pattern and electrically floating. For example, the presence of the virtual conductive pattern 1162D helps to increase pattern uniformity and metal density, thereby facilitating subsequent bonding processes. Alternatively, the virtual conductive pattern 1162D may be omitted, and conductive features are not formed in the cut region 110D. It should be noted that the virtual conductive pattern 1162D can have any suitable number and configuration.

[0016] In some embodiments, the diced region 110D includes a first portion 110D1 and a second portion 110D2, with the first portion 110D1 disposed between the first semiconductor substrate 112 and the second portion 110D2. The second portion 110D2 may be metal-free (e.g., dummy conductive pattern 1162D, first bonding member 1182, first metallization pattern 1162, and sealing ring 117), while the first portion 110D1 includes conductive elements (e.g., dummy conductive pattern 1162D). For example, the second portion 110D2 may consist only of dielectric material (e.g., first bonding dielectric layer 1181 and first dielectric layer 1161), and the first portion 110D1 may include both dielectric material (e.g., first dielectric layer 1161) and conductive material (e.g., dummy conductive pattern 1162D). The thickness of the second portion 110D2 may be less than the thickness of the first portion 110D1. For example, the ratio of the thickness of the second portion 110D2 to the thickness of the first portion 110D1 may be less than 0.3. In one embodiment, the thickness of the second portion 110D2 is in the range of 2 μm to 6 μm, and the thickness of the first portion 110D1 is in the range of 12 μm to 16 μm. In some embodiments, the topmost virtual conductive pattern 1162D adjacent to the second portion 110D2 may be substantially at the same level as the first metallization pattern 1162 (e.g., metal 15 (M15) layer). For example, the virtual conductive pattern 1162D from bottom to top may be substantially at the same level as metal 0 (M0) layer, metal 1 (M1) layer... metal 14 (M14) layer and metal 15 (M15) layer, respectively. However, this disclosure is not limited thereto.

[0017] Referring to FIG1B, a plasma dicing process is performed on a semiconductor substrate 1100 to form a trench 110T in a dicing region 110D. In one embodiment, a mask layer M is formed on the semiconductor substrate 1100. The mask layer M is a patterned hard mask layer, a patterned photoresist layer, or the like. The mask layer M exposes the dicing region 110D. For example, a portion of the first bonding dielectric layer 1181 in the dicing region 110D is exposed. The plasma dicing process is then performed to remove dielectric material (e.g., the first bonding dielectric layer 1181 and the first dielectric layer 1161) in a second portion 110D2 of the dicing region 110D. In some embodiments, since the second portion 110D2 of the dicing region 110D does not contain metal, it is suitable to completely remove the dielectric material in the second portion 110D2 using a plasma dicing process. The plasma dicing process may include using a plasma source with a power between about 1500 W and about 4500 W and lasting for 60 seconds to 600 seconds. In some embodiments, the plasma cutting process includes fluorocarbon gas (CxFy), helium (He), argon (Ar), or a combination thereof. The trench 110T may extend through the first bonding dielectric layer 1181 and the first dielectric layer 1161 in the second portion 110D2 of the cutting region 110D. In some embodiments, the trench 110T terminates at the top of the virtual conductive pattern 1162D in the first portion 110D1 of the cutting region 110D. The trench 110T may not penetrate the first portion 110D1 of the cutting region 110D. For example, the trench 110T is defined by the sidewall 1181W of the first bonding dielectric layer 1181, the sidewall 1161W1 of the first dielectric layer 1161 in the second portion 110D2, and the surface of the first dielectric layer 1161. For example, the surface of the first dielectric layer 1161 lies between opposing surfaces of the first dielectric layer 1161. The sidewalls 1181W of the first bonding dielectric layer 1181 and the sidewalls 1161W1 of the first dielectric layer 1161 are continuous and have no transition points between them. The sidewalls 1181W of the first bonding dielectric layer 1181 and the sidewalls 1161W1 of the first dielectric layer 1161 may be substantially perpendicular to each other. Therefore, the trench 110T may have a substantially constant width W1 from top to bottom. In some embodiments, the trench 110T is formed as a ring surrounding the respective grain regions 110-1 and 110-2. For example, the grain regions 110-1 and 110-2 are surrounded by the trench 110T.

[0018] Referring to FIG1C, a laser process is performed on a semiconductor substrate 1100 to form a groove 110G in a diced region 110D. The laser process removes dielectric material (e.g., a first dielectric layer 1161) and conductive material (e.g., a dummy conductive pattern 1162D) from a first portion 110D1 of the diced region 110D. The laser process can further remove a first semiconductor substrate 112 from the diced region 110D. The laser process is also referred to as a laser grooving process. In some embodiments, the laser process power is between about 0.5 W and about 2 W, the laser frequency is between about 1000 kHz and about 3000 kHz, and the feed rate (e.g., movement speed) is between about 500 mm / s and about 1000 mm / s. The groove 110G can extend through the first dielectric layer 1161 in the first portion 110D1 of the diced region 110D and further into the first semiconductor substrate 112. The groove 110G has a depth 110GT. In some embodiments, the groove 110G stops at a first depth of the first semiconductor substrate 112. The groove 110G may not completely penetrate the first semiconductor substrate 112. For example, the groove 110G is defined by the sidewall 1161W2 of the first dielectric layer 1161 in the first portion 110D1, the sidewall 112W of the first semiconductor substrate 112, and the surface 112S of the first semiconductor substrate 112. The surface 112S of the first semiconductor substrate 112 is located between the front side 112a and the back side 112b. The sidewall 1161W2 of the first dielectric layer 1161 and the sidewall 112W of the first semiconductor substrate 112 are continuous and have no turning points between them. The sidewall 1161W2 of the first dielectric layer 1161 and the sidewall 112W of the first semiconductor substrate 112 are inclined at an angle θ. The angle θ may be in the range of 75 degrees to 85 degrees. In some embodiments, the groove 110G communicates with the trench 110T, and the groove 110G is formed as a ring surrounding the corresponding grain regions 110-1 and 110-2. For example, the grain regions 110-1 and 110-2 are surrounded by the trench 110T and the groove 110G.

[0019] In some embodiments, the top width W2T of the groove 110G is not greater than the width W1 of the trench 110T to prevent the sidewalls 1181W and 1161W1 of the first bonding dielectric layer 1181 and the first dielectric layer 1161 from being damaged by the laser process. For example, the top width W2T of the groove 110G is smaller than the width W1 of the trench 110T. In other words, from a top view, the groove 110G is located inside the trench 110T. In other embodiments, the top width W2T of the groove 110G is substantially equal to the width W1 of the trench 110T. In some embodiments, the laser process removes a portion of the first semiconductor substrate 112. However, this disclosure is not limited thereto. In other embodiments, the laser process may stop at the front side 112a of the first semiconductor substrate 112, removing only the first dielectric layer 1161 in the first portion 110D1 of the cut region 110D.

[0020] In some embodiments, due to the differences between plasma dicing and laser dicing processes, the sidewalls / surfaces of different regions of the first semiconductor die 110 may have different roughnesses. For example, sidewalls 1181W and 1161W1 formed by plasma dicing are smoother than sidewalls 1161W2 and 112W formed by laser dicing. For example, the surface roughness of sidewalls 1161W2 and 112W is greater than that of sidewalls 1181W and 1161W1.

[0021] Referring to FIG1D, an additional laser process is performed on semiconductor substrate 1100 to enlarge groove 110G into groove 110G'. In some embodiments, the additional laser process is performed at a power of about 0.5 W to about 2 W, a laser frequency of about 2000 kHz to about 5000 kHz, and a feed rate (e.g., movement speed) of about 800 mm / s to about 1000 mm / s. The additional laser process further removes a portion of the first dielectric layer 1161 in the second portion 110D2 and a portion of the first semiconductor substrate 112 in the dicing region 110D. In some embodiments, groove 110G' stops at a second depth in the first semiconductor substrate 112, which is greater than the first depth. Groove 110G' may not completely penetrate the first semiconductor substrate 112. For example, groove 110G' is defined by the sidewalls 1161W2' of the first dielectric layer 1161, the sidewalls 112W' of the first semiconductor substrate 112, and the surface 112S' of the first semiconductor substrate 112. The surface 112S' of the first semiconductor substrate 112 is located between the front side 112a and the back side 112b. For example, the sidewalls 1161W2' of the first dielectric layer 1161 and the sidewalls 112W' of the first semiconductor substrate 112 are continuous and have no transition point. For example, the sidewalls 1161W2' of the first dielectric layer 1161 and the sidewalls 112W' of the first semiconductor substrate 112 are inclined at an angle θ'. The angle θ' can be in the range of 70 degrees to 85 degrees. In some embodiments, the groove 110G' communicates with the trench 110T, and the groove 110G' is formed as a ring surrounding the corresponding grain regions 110-1 and 110-2. For example, the grain regions 110-1 and 110-2 are surrounded by the trench 110T and the groove 110G'.

[0022] In some embodiments, as shown in Figures 1C and 1D, the top width W2T' of the groove 110G' is greater than the top width W2T of the groove 110G, and the depth 110GT' of the groove 110G' is greater than the depth 110GT of the groove 110G. Therefore, the groove 110G is expanded into the groove 110G' through an additional laser process. In some embodiments, the top width W2T' of the groove 110G' is not greater than the width W1 of the trench 110T to prevent the sidewalls 1181W and 1161W1 of the first bonding dielectric layer 1181 and the first dielectric layer 1161 from being damaged by the additional laser process. For example, the top width W2T' of the groove 110G' is less than the width W1 of the trench 110T. In other words, from a top view, the groove 110G' is disposed inside the trench 110T. However, this disclosure is not limited thereto. In other embodiments, the top width W2T' of the groove 110G' is substantially equal to the width W1 of the trench 110T.

[0023] In some embodiments, the additional laser process not only enlarges the groove 110G but also modifies the surface of the sidewall 1161W2 of the first dielectric layer 1161. As mentioned above, the surface roughness of the sidewall formed by the laser process may be greater than that of the sidewall formed by the plasma cutting process. In some embodiments, the sidewalls 1161W2 and 112W can be further modified by the additional laser process to reduce surface roughness. For example, the sidewall 1161W2' of the first dielectric layer 1161 modified by the additional laser process is smoother than the sidewall 1161W2 of the first dielectric layer 1161 formed by the laser process, which is suitable for subsequent formation of an insulating encapsulation. In other embodiments, the enlargement process of the groove 110G and the surface modification process of the groove 110G can be performed separately; in other words, the surface modification process is performed after the enlargement process. In some embodiments, the trench 110T and the groove 110G' are connected and can be collectively referred to as a recess.

[0024] Referring to FIG1E, individual first semiconductor dies 110 are formed. In some embodiments, a thinning process is performed to remove a portion of the first semiconductor substrate 112, thereby separating the first semiconductor dies 110 from each other. For example, a backside polishing process such as CMP is performed from the back side 112b of the first semiconductor substrate 112 to reduce the thickness of the first semiconductor substrate 112. In some embodiments, the polishing process stops when the recess is exposed, thereby separating the semiconductor substrate 1100 into a plurality of individual first semiconductor dies 110.

[0025] In some embodiments, the first semiconductor die 110 includes a first semiconductor substrate 112 and a dielectric material DM on the first semiconductor substrate 112. A first device 114, a first interconnect structure 116, and a first bonding structure 118 formed in / on the first semiconductor substrate 112 are surrounded at least laterally by the dielectric material DM. In some embodiments, the dielectric material DM includes a first dielectric portion DM1 and a second dielectric portion DM2, the first dielectric portion DM1 being disposed between the first semiconductor substrate 112 and the second dielectric portion DM2. The first dielectric portion DM1 includes a portion of a first dielectric layer 1161, and the second dielectric portion DM2 includes a portion of the first dielectric layer 1161 and the bonding structure 118. In some embodiments, the first dielectric portion DM1 includes an inclined sidewall 1161W2', and the second dielectric portion DM2 includes a vertical sidewall 1161W1 of the first dielectric layer 1161 and a vertical sidewall 1181W of the first bonding dielectric layer 1181. An inclined sidewall 1161W2' is disposed between the vertical sidewall 1161W1 and the inclined sidewall 112W'. Here, the term "vertical sidewall" also includes the meaning of "substantially vertical sidewall". In some embodiments, the sidewall 1161W2' of the first dielectric layer 1161 is continuous with the sidewall 112W' of the first semiconductor substrate 112, and there is no turning point between them. As shown in FIG1E, the angle θ1 formed by the surface (e.g., bottom surface) of the first dielectric layer 1161 and the inclined sidewall 1161W2' of the first dielectric layer 1161 may be substantially equal to the angle θ2 formed by the surface (e.g., bottom surface) of the first semiconductor substrate 112 and the inclined sidewall 112W' of the first semiconductor substrate 112. Angle θ1 is, for example, substantially equal to the angle θ' in FIG1D.

[0026] In some embodiments, the vertical sidewall 1161W1 is located inside and separate from the inclined sidewall 1161W2'. For example, a surface 1161S (e.g., a horizontal surface) of the first dielectric layer 1161 exposes and connects the inclined sidewall 1161W2' and the vertical sidewall 1161W1. Therefore, in a cross-sectional view, the dielectric material DM (also the first semiconductor die 110) may have a stepped sidewall STP1. In some embodiments, as shown in FIG1E, the second dielectric portion DM2 may have a substantially constant width DM2W, and the first dielectric portion DM1 may have a width DM1W greater than the width DM2W. The width DM1W of the first dielectric portion DM1 may decrease as the first dielectric portion DM1 approaches the second dielectric portion DM2. For example, the width DM1W of the first dielectric portion DM1 at the interface between the first dielectric portion DM1 and the second dielectric portion DM2 is smaller than the width DM2W of the second dielectric portion DM2. In some embodiments, a transition point TP is formed between the first dielectric portion DM1 and the second dielectric portion DM2.

[0027] In some cases where plasma cutting processes are used, a metal-free cut area is required, which makes it difficult to control the metallization and / or planarization topology. Conversely, in some embodiments, the cutting process is performed by combining plasma cutting and laser processes (e.g., laser grooving), thus avoiding the need for a metal-free cut area. Specifically, the cut area may include a metal-free portion (e.g., a second portion 110D2) and a metal-containing portion (e.g., a first portion 110D1), with the plasma cutting process used to remove the metal-free portion and the laser process used to remove the metal-containing portion. Furthermore, by avoiding a metal-free cut area, the area of ​​the cut area may be reduced. For example, in some embodiments, the area of ​​the cut area is reduced compared to some cases where plasma cutting processes are used.

[0028] Figures 2A to 2C illustrate various cross-sectional views of methods for forming semiconductor structures according to some embodiments.

[0029] Referring to FIG2A, a semiconductor substrate 1200 is provided. The semiconductor substrate 1200 may include a second semiconductor substrate 122, a second interconnect structure 126 formed on the second semiconductor substrate 122, a second bonding structure 128 formed on the second interconnect structure 126, and a via 125 in the second semiconductor substrate 122 and extending into the second interconnect structure 126. The second semiconductor substrate 122 may be a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The material of the second semiconductor substrate 122 is similar to the material of the first semiconductor substrate 112 discussed in FIG1A, and therefore a detailed description is omitted here. The second semiconductor substrate 122 may be doped or undoped. In some embodiments, the semiconductor substrate 1200 does not contain active / passive devices, and the second semiconductor substrate 122 does not include formed devices on its front side 122a. In some embodiments, active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.) are formed on the front side 122a of the second semiconductor substrate 122.

[0030] A second interconnect structure 126 may be formed on the front side 122a of a second semiconductor substrate 122. The second interconnect structure 126 may be disposed in one or more second dielectric layers 1261 and include a second metallization pattern 1262. The second dielectric layer 1261 and the second metallization pattern 1262 may be similar to the first dielectric layer 1161 and the first metallization pattern 1162 described in FIG. 1A, respectively, and therefore detailed descriptions are omitted here. A second bonding structure 128 may be formed on and electrically connected to the second interconnect structure 126. For example, the second bonding structure 128 may be disposed in one or more second bonding dielectric layers 1281 and include a second bonding member 1282. The second bonding member 1282 may be electrically connected to the second metallization pattern 1262. The second bonding dielectric layer 1281 and the second bonding member 1282 may be similar to the first bonding dielectric layer 1181 and the first bonding member 1182 described in FIG. 1A, respectively, and therefore detailed descriptions are omitted here. In some embodiments, a planarization process (e.g., CMP process, polishing process, etching process, combinations thereof, or the like) is performed such that the top surfaces (1281t and 1282t) of the second bonding dielectric layer 1281 and the second bonding member 1282 are substantially flat (or coplanar) within the range of process variations.

[0031] Referring again to FIG2A, the second bonding structure 128 may include an additional bonding member 1282D embedded in the second bonding dielectric layer 1281. The additional bonding member 1282D may be formed at the same layer as the second bonding member 1282. In some embodiments, the additional bonding member 1282D is a dummy bonding member and is electrically isolated from the second bonding member 1282. The additional bonding member 1282D may be electrically floated in the semiconductor substrate 1200. In some embodiments, the additional bonding member 1282D is subsequently bonded to an additional bonding member 1182D of the first semiconductor die 110. The via 125 may be formed in the second semiconductor substrate 122 by depositing one or more diffusion barrier layers or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., tungsten, titanium, aluminum, copper, any combination thereof, and / or the like) into trenches in the second semiconductor substrate 122. For example, each via 125 includes a first end 125a that is physically and electrically connected to one of the second metallization patterns 1262 and a second end 125b opposite to the first end 125a, wherein the second end 125b may be embedded in the second semiconductor substrate 122 at this stage.

[0032] Referring again to FIG2A and FIG1E, a first semiconductor die 110 may be bonded to a semiconductor substrate 1200. It should be noted that although only a single first semiconductor die 110 is shown, any number of first semiconductor dies 110 may be bonded to the semiconductor substrate 1200. In some embodiments, the first semiconductor die 110 and the semiconductor substrate 1200 are directly bonded face-to-face via dielectric-to-dielectric bonding and metal-to-metal bonding, such that the front side (not shown) of the first semiconductor die 110 is bonded to the front side (not shown) of the semiconductor substrate 1200. For example, a first bonding dielectric layer 1181 may be fused to a second bonding dielectric layer 1281 via dielectric-to-dielectric bonding, and a dielectric-to-dielectric (e.g., oxide-to-oxide) bonding may be formed therebetween. A first bonding member 1182 may be bonded to a second bonding member 1282 via metal-to-metal bonding, and a metal-to-metal (e.g., copper-to-copper) bonding may be formed therebetween. In some embodiments, a dielectric-to-metal (e.g., oxide-to-copper; not shown separately) bonding may be formed at the bonding interface between the first semiconductor die 110 and the semiconductor substrate 1200. In some embodiments, the bonding interface is substantially flat and planar. In some embodiments, the first and second bonding members (1182 and 1282) are directly connected in a one-to-one correspondence after the bonding process. In some embodiments, additional bonding members (1182D and 1282D) may be directly connected in a one-to-one correspondence.

[0033] Referring to FIG2B, an insulating encapsulation 132 may be formed on a semiconductor substrate 1200 to encapsulate a first semiconductor die 110. In some embodiments, the insulating encapsulation 132 is formed of an oxide (e.g., silicon dioxide) or the like, and the insulating encapsulation 132 is formed by a deposition process (e.g., a chemical vapor deposition (CVD) process) or a similar process. For example, the insulating encapsulation 132 is a CVD oxide. In alternative embodiments, the insulating encapsulation 132 is formed of a molding material or compound and may be formed by compression molding, transfer molding, or similar methods. The molding material comprises a polymer material and may optionally comprise a filler, wherein the filler may be silicon dioxide particles or the like, and the polymer material may be an epoxy resin or the like. For example, an insulating material is formed on the top surface 1241t of the second bonding dielectric layer 1241 of the semiconductor substrate 1200, and the first semiconductor die 110 may be embedded in or covered by the insulating material. Optionally, a planarization process (e.g., CMP, polishing, etching, combinations thereof, or similar processes) can be performed on the insulating material to planarize the insulating material and the top surface 132t of the first semiconductor die 110. In an alternative embodiment, the planarization process may remove a portion of the first semiconductor substrate 112 at the back side 112b. In some embodiments, the back side 112b of the first semiconductor die 110 is exposed by planarization of the insulating encapsulation 132, such that the surfaces (e.g., 112b and 132t) of the first semiconductor die 110 and the insulating encapsulation 132 are substantially coplanar (or coplanar) within a range of process variations.

[0034] In some embodiments, the insulating encapsulation 132 extends along the outer surface of the first semiconductor die 110. For example, the sidewalls 1181W of the first bonding dielectric layer 1181, the sidewalls 1161W1, 1161W2' of the first dielectric layer 1161, the surface 1161S (e.g., a horizontal surface) of the first dielectric layer 1161, and the sidewalls 112W' of the first semiconductor substrate 112 are in direct contact with the insulating encapsulation 132. As described above, the sidewalls 1181W, 1161W1 formed by a plasma dicing process and the sidewalls 1161W2', 112W' formed by a laser process and further modified by an additional laser process can have the desired surface roughness. Therefore, the dielectric material DM can provide a surface suitable for forming (e.g., depositing) the insulating encapsulation 132 on the first semiconductor die 110. Accordingly, crack formation in the insulating encapsulation 132 can be prevented, and the reliability of the resulting semiconductor structure can be improved.

[0035] Referring again to FIG2B, a thinning process (e.g., polishing, CMP, etching, a combination thereof, or similar processes) can be performed on the back side of the semiconductor substrate 1200. For example, the back side 122b of the second semiconductor substrate 122 is thinned until at least a portion of the second end 125b of the via 125 is tangibly exposed. In some embodiments, the thinning process is performed after the insulating encapsulation 132 is formed. Since the via 125 penetrates the second semiconductor substrate 122, the via 125 may also be referred to as a substrate through-hole (TSV).

[0036] Referring to Figures 2C and 2B, a plurality of conductive terminals 142 may be formed on the back side 122b of the second semiconductor substrate 122 and electrically connected to vias 125. The conductive terminals 142 may be controlled-collapse wafer interconnect (C4) bumps, ball grid array (BGA) connectors, solder balls, metal pillars, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG), or the like. The conductive terminals 142 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive terminals 142 are formed by forming solder material and performing a reflow process on the solder material to form the desired bump shape. In some embodiments, a corresponding conductive terminal 142 includes a pillar portion (e.g., a copper pillar) and a cap portion formed on the pillar portion, wherein the pillar portion has substantially vertical sidewalls, and the cap portion has a bump profile.

[0037] In some embodiments, before forming the conductive terminal 142, a conductive pad 140 is formed on the second end 125b of the via 125 and the back side 122b of the second semiconductor substrate 122. The conductive terminal 142 may rest on the conductive pad 140 and be electrically connected to the via 125 through the conductive pad 140. In some embodiments, the conductive pad 140 is an under-bump metallization (UBM) pad. In an alternative embodiment (not shown), a redistribution structure is formed on the back side 122b of the second semiconductor substrate 122 before forming the conductive terminal 142, and then the conductive terminal 142 is formed on the redistribution structure such that the conductive terminal 142 is electrically connected to the via 125 through the redistribution structure.

[0038] Referring again to FIG2C and FIG2B, a dicing process can be selectively performed along a dicing line (not shown) to form a single semiconductor structure 10. For example, the semiconductor structure 10 includes a second semiconductor die 120 formed by dicing a semiconductor substrate 1200, a first semiconductor die 110 on the second semiconductor die 120, and an insulating encapsulation 132. After the dicing process, the sidewalls 132W of the insulating encapsulation 132 may be substantially flush with the sidewalls 120W of the second semiconductor die 120.

[0039] In some embodiments, the vertical sidewall 1161W1 is located inside and physically separated from the inclined sidewall 1161W2'. However, this disclosure is not limited thereto. In alternative embodiments, as shown in FIG3, the vertical sidewall 1161W1 and the inclined sidewall 1161W2' are physically connected. In these embodiments, the second dielectric portion DM2 may have a substantially constant width DM2W, and the width DM1W of the first dielectric portion DM1 may decrease as the first dielectric portion DM1 approaches the second dielectric portion DM2. For example, at the interface between the first dielectric portion DM1 and the second dielectric portion DM2, the width DM1W of the first dielectric portion DM1 is substantially equal to the width DM2W of the second dielectric portion DM2. For example, a transition point TP is formed between the first dielectric portion DM1 and the second dielectric portion DM2.

[0040] In some embodiments, a transition point TP is formed between the first dielectric portion DM1 and the second dielectric portion DM2. However, this disclosure is not limited thereto.

[0041] Figures 4A and 4B are schematic cross-sectional views of various stages in a method for forming a semiconductor device according to some embodiments.

[0042] Referring to FIG4A and FIG1C, an additional laser process is performed on the semiconductor substrate 1100 of FIG1C to form a groove 110G'. In some embodiments, the additional laser process is performed on the surfaces of both the trench 110T and the groove 110G. For example, the additional laser process removes the first bonding dielectric layer 1181 and the first dielectric layer 1161 surrounding the trench 110T, and the first dielectric layer 1161 and the first semiconductor substrate 112 surrounding the groove 110G. For example, the width W3 of the groove 110G' is greater than the width W1 of the trench 110T (as shown in FIG1B). In some embodiments, the additional laser process is performed at a power of about 0.5 W to about 2 W, a laser frequency of about 2000 kHz to about 5000 kHz, and a feed rate (e.g., movement speed) of about 800 mm / s to about 1000 mm / s. The groove 110G' may not completely penetrate the first semiconductor substrate 112. For example, the groove 110G' is defined by the sidewalls 1181W' of the first bonding dielectric layer 1181, the sidewalls 1161W3 of the first dielectric layer 1161, the sidewalls 112W' of the first semiconductor substrate 112, and the surface 112S' of the first semiconductor substrate 112. The surface 112S' of the first semiconductor substrate 112 is located between the front side 112a and the back side 112b. For example, the sidewalls 1161W3 of the first dielectric layer 1161 and the sidewalls 112W' of the first semiconductor substrate 112 are continuous and there is no turning point between them. For example, the sidewalls 1181W', 1161W3 of the first dielectric layer 1161 and the sidewalls 112W' of the first semiconductor substrate 112 are continuous and inclined at an angle θ'. The angle θ' can be in the range of 70 degrees to 85 degrees. In some embodiments, the groove 110G' is formed as a ring surrounding the corresponding grain regions 110-1, 110-2. In the illustrated embodiment, inclined sidewalls 1181W' and 1161W3 may be configured in the sealing ring region 110S. For example, the lateral distance between the inclined sidewalls 1181W' and 1161W3 and the sealing ring 117 is at least 10 μm. However, this disclosure is not limited thereto.

[0043] In some embodiments, the first dielectric layer 1161 in the first portion 110D1 of the cut region 110D is removed not only by the laser process described in FIG. 1C, but also by an additional laser process described in FIG. 4A. Similarly, the first bonding dielectric layer 1181 and the first dielectric layer 1161 in the second portion 110D2 of the cut region 110D are removed not only by the plasma cutting process described in FIG. 1B, but also by an additional laser process described in FIG. 4A. In other words, the sidewalls of the first bonding dielectric layer 1181 and the first dielectric layer 1161 are further modified by an additional laser process to achieve the desired surface roughness. For example, the sidewall 1181W' formed by the additional laser process is smoother than the sidewall 1181W formed by the plasma dicing process (as shown in FIG1B), and the sidewall 1161W3 of the first dielectric layer 1161 formed by the additional laser process is smoother than the sidewall 1161W1 formed by the plasma dicing process (as shown in FIG1B) and the sidewall 1161W2 formed by the laser process (as shown in FIG1C).

[0044] Referring to FIG4B, individual first semiconductor dies 110 are formed. For example, a thinning process is performed. This thinning process is similar to the process described in FIG1E. In some embodiments, as shown in FIG4B, the dielectric material DM has inclined sidewalls (including sidewalls 1181W' and 1161W3) that extend continuously between opposite surfaces of the dielectric material DM without any inflection points. That is, the sidewalls of the second dielectric portion DM2 and the sidewalls of the first dielectric portion DM1 are solidly connected without any inflection points between them. Furthermore, the inclined sidewalls of the dielectric material DM (including sidewalls 1181W' and 1161W3) are continuous with the inclined sidewall 112W' of the first semiconductor substrate 112 without any inflection points between them. As shown in Figure 4B, the angle θ1 formed between the surface (e.g., bottom surface) of the first dielectric layer 1161 and the inclined sidewall 1161W3 of the first dielectric layer 1161 may be substantially equal to the angle θ2 formed between the surface (e.g., bottom surface) of the first semiconductor substrate 112 and the inclined sidewall 112W' of the first semiconductor substrate 112. Angle θ1 is substantially equal to angle θ' in Figure 4A, for example.

[0045] In some embodiments, the width DM2W of the second dielectric portion DM2 may increase as the second dielectric portion DM2 approaches the first dielectric portion DM1, and the width DM1W of the first dielectric portion DM1 may decrease as the first dielectric portion DM1 approaches the second dielectric portion DM2. For example, at the interface between the first dielectric portion DM1 and the second dielectric portion DM2, the width DM1W of the first dielectric portion DM1 is substantially equal to the width DM2W of the second dielectric portion DM2.

[0046] The first semiconductor die 110 of Figure 4B is then bonded to the second semiconductor die 120 and encapsulated by an insulating encapsulator 132 to form the semiconductor structure 10 of Figure 5. The formation of the semiconductor structure 10 is similar to the process described in Figures 2A to 2C, and therefore a detailed description is omitted here. The difference is that the insulating encapsulator 132 may contact the continuous inclined sidewalls (including sidewalls 1181W' and 1161W3) of the first semiconductor die 110.

[0047] In the above embodiments, the different configurations of the dielectric material DM and the first semiconductor substrate 112 in Figures 1E, 3 and 4B may be achieved by using a laser beam splicing process, a defocusing process or a similar process.

[0048] Figures 6A to 6E illustrate various cross-sectional views of methods for forming a semiconductor device according to some embodiments.

[0049] Referring to FIG6A and FIG1B, a plasma dicing process is performed on a semiconductor substrate 1100 to form a trench 110T in a dicing region 110D. The plasma dicing process and the trench 110T are similar to those described in FIG1B, and therefore a detailed description is omitted here. In some embodiments, the trench 110T is defined by the sidewalls 1181W of the first bonding dielectric layer 1181, the sidewalls 1161W1 of the first dielectric layer 1161 in the second portion 110D2, and the surface of the first dielectric layer 1161.

[0050] Then, a thinning process is performed to remove a portion of the first semiconductor substrate 112, thereby reducing the thickness of the first semiconductor substrate 112. For example, a backside polishing process such as CMP is performed from the back side 112b of the first semiconductor substrate 112 to reduce the desired thickness of the first semiconductor substrate 112. The thinning process does not remove the entire first semiconductor substrate 112 in the cut region 110D, and the thickness of the remaining first semiconductor substrate 112 after the thinning process in FIG. 6A is less than the thickness of the first semiconductor substrate 112 in FIG. 1B.

[0051] Referring to Figure 6B, after the thinning process, a laser process is performed on the semiconductor substrate 1100 to form a groove 110G in the dicing region 110D. The laser process removes dielectric material (e.g., a first dielectric layer 1161) and conductive material (e.g., a virtual conductive pattern 1162D) from the first portion 110D1 of the dicing region 110D, as well as the first semiconductor substrate 112 in the dicing region 110D. The laser process is also referred to as a laser grooving process. In some embodiments, the energy density of the laser process is in the range of about 400 mJ / cm² to about 5000 mJ / cm², and the EPA (energy per unit area) of the wafer is in the range of about 5000 mJ / cm² to about 40,000 mJ / cm². For a dicing length of about 300 mm and a feed rate of about 1000 mm / s, the process time is about 0.3 seconds. The laser process is similar to that described in Figure 1C, therefore a detailed description is omitted here.

[0052] In some embodiments, the groove 110G is defined by the inclined sidewall 1161W2 of the first dielectric layer 1161, the inclined sidewall 112W of the first semiconductor substrate 112, and the surface 112S of the first semiconductor substrate 112.

[0053] Referring to FIG6C, a sawing process can be performed on the semiconductor substrate 1100 to completely separate the grain regions 110-1 and 110-2, thereby forming individual first semiconductor grains 110. The sawing process can be performed through respective trenches 110T in the cutting line region 110L and the recesses 110G below them. In some embodiments, the sawing process is a mechanical process using a saw blade placed in the respective trenches 110T and the recesses 110G below them to saw through the remaining first semiconductor substrate 112. Other sawing processes can be used in other embodiments.

[0054] After the sawing process, each separated first semiconductor die 110 may include a first semiconductor substrate 112 and a dielectric material DM on the first semiconductor substrate 112. In a cross-sectional view, the sidewalls of the first semiconductor die 110 may have a stepped profile. The first semiconductor substrate 112 and the dielectric material DM may each have stepped sidewalls STP1 and STP2, respectively. The stepped sidewall STP1 of the dielectric material DM is connected to the stepped sidewall STP2. For example, the sidewalls of the first semiconductor substrate 112 include an inclined sidewall 112W1 formed by a laser process and a vertical sidewall 112W2 formed by a sawing process, and the surface 112S of the first semiconductor substrate 112 is exposed and connected to the inclined sidewall 112W1 and the vertical sidewall 112W2. The sidewalls of the dielectric material DM may include vertical sidewalls 1181W and 1161W1 formed by a plasma dicing process and inclined sidewalls 1161W2 formed by a laser process, and the surface 1161S (e.g., a horizontal surface) of the first dielectric layer 1161 exposes and connects the inclined sidewalls 1161W2' and the vertical sidewalls 1161W1. Due to the differences in plasma dicing / laser / sawing processes, the surfaces of different regions of the first semiconductor die 110 may have different roughnesses. For example, the sidewalls 1181W and 1161W1 formed by the plasma dicing process may be smoother than the sidewalls 1161W2 and 112W1 formed by the laser process, and the sidewalls 1161W2 and 112W1 may be smoother than the sidewall 112W2 of the first semiconductor substrate 112 formed by the sawing process.

[0055] Referring to FIG6D, the first semiconductor die 110 is bonded to the semiconductor substrate 1200. The bonding of the first semiconductor die 110 and the semiconductor substrate 1200 is similar to that described in FIG2A, therefore a detailed description is omitted here.

[0056] An encapsulation layer 134 may then be formed on the semiconductor substrate 1200 to encapsulate the first semiconductor die 110. In some embodiments, the encapsulation layer 134 is formed of spin-coated glass (SOG), liquid oxide, polymer (e.g., polyimide), or the like, and is formed by a coating process (e.g., spin coating), a dispensing process, or a similar process. The encapsulation layer 134 may have sloping sidewalls, and the width of the encapsulation layer 134 increases as it approaches the interface between the first semiconductor die 110 and the semiconductor substrate 1200. The encapsulation layer 134 may cover the sidewalls 1181W, 1161W1, and 1161W2 of the dielectric material DM, and further cover a portion of the sidewall 112W of the first semiconductor substrate 112. For example, the encapsulation layer 134 covers a portion of the vertical sidewall 112W2 and all of the sloping sidewall 112W1. However, this disclosure is not limited thereto. The sealing layer 134 may expose all or a portion of the inclined sidewalls 112W1 and / or the vertical sidewalls 112W2. In some embodiments, the sealing layer 134 surrounds and directly contacts the dielectric material DM. However, this disclosure is not limited thereto. In alternative embodiments, all of the sidewalls 112W of the first semiconductor substrate 112 and a portion of the sidewalls 1161W2 of the dielectric material DM may be exposed by the sealing layer 134. In alternative embodiments, prior to forming the sealing layer 134, additional laser processes similar to those described in FIG1D may be performed on the sidewalls of the dielectric material DM (e.g., sidewalls 1161W2 of the dielectric material DM) to reduce the surface roughness of the dielectric material DM sidewalls. In other words, the sidewalls of the dielectric material DM may be further modified to have the surface roughness required for forming the sealing layer 134, as required.

[0057] Referring to FIG6E, an insulating encapsulation 132 may be formed on a semiconductor substrate 1200 to encapsulate a first semiconductor die 110 and a sealing layer 134. The insulating encapsulation 132 is made of a different material than the sealing layer 134, and an interface is formed between the insulating encapsulation 132 and the sealing layer 134. In some embodiments, the insulating encapsulation 132 is formed of an oxide (e.g., silicon oxide) or the like, and the insulating encapsulation 132 is formed by a deposition process (e.g., a chemical vapor deposition (CVD) process) or a similar process. For example, the insulating encapsulation 132 is a CVD oxide, while the sealing layer 134 is SOG. Subsequently, a conductive pad 140 and a conductive terminal 142 are formed. A dicing process may be selectively performed along a dicing line (not shown) to form individual semiconductor structures 10. For example, the semiconductor structure 10 includes a first semiconductor die 110, a second semiconductor die 120 formed by dicing a semiconductor substrate 1200, an insulating encapsulation 132 on the second semiconductor die 120, and a sealing layer 134 between the insulating encapsulation 132 and the first semiconductor die 110. The methods and materials for forming the insulating encapsulation 132, the conductive pad 140, and the conductive terminal 142, as well as the dicing process, are similar to those described in Figures 2B and 2C, and therefore detailed descriptions are omitted here.

[0058] In some embodiments, as shown in FIG6E, the inclined sidewall 112W1 and the vertical sidewall 112W2 are connected via a surface 112S of the first semiconductor substrate 112. However, this disclosure is not limited thereto. In an alternative embodiment, as shown in FIG7, the inclined sidewall 112W1 and the vertical sidewall 112W2 are directly connected.

[0059] As described above, the sidewalls 1161W2 of the dielectric material DM formed by laser processing may have a large surface roughness. In some embodiments, a sealing layer 134 suitable for forming the surface of the insulating encapsulation 132 may be formed on the dielectric material DM, so the insulating encapsulation 132 can be easily formed on the sealing layer 134. Therefore, crack formation in the insulating encapsulation 132 is prevented, and the reliability of the resulting semiconductor structure is improved.

[0060] Figure 8 illustrates a flowchart of a method for forming a semiconductor device according to some embodiments. Although the method is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated sequence or actions. Therefore, in some embodiments, actions may be performed in a different sequence than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other unillustrated actions or events may be included.

[0061] In action 802, a first semiconductor substrate is provided having a plurality of grain regions and diced regions located between the grain regions, wherein the diced regions include the semiconductor substrate, dielectric material on the semiconductor substrate, and a plurality of dummy conductive patterns at least laterally surrounded by the dielectric material. Figures 1A and 6A illustrate views corresponding to some embodiments of action 802.

[0062] In action 804, a plasma cutting process is performed on the cutting area to form a groove. Figures 1B and 6A illustrate views corresponding to some embodiments of action 804.

[0063] In action 806, a laser process is performed on the cutting area to form a groove communicating with the trench. Figures 1C and 6B illustrate views corresponding to some embodiments of action 806.

[0064] According to some embodiments of this disclosure, a semiconductor device includes a first semiconductor substrate, a dielectric material, a first interconnect structure, and a first bonding structure. The first semiconductor substrate has a first inclined sidewall. The dielectric material is located above the first semiconductor substrate and has a sidewall, a second inclined sidewall, and a transition point located between the sidewall and the second inclined sidewall. The first interconnect structure is located above the first semiconductor substrate and is at least laterally surrounded by the dielectric material. The first bonding structure is located above the first interconnect structure and is at least laterally surrounded by the dielectric material.

[0065] According to some embodiments of this disclosure, a semiconductor device includes a first die. The first die includes a first semiconductor substrate, a dielectric material, a first interconnect structure, and a first bonding structure. The dielectric material is located above the first semiconductor substrate. The first interconnect structure is located above the first semiconductor substrate and is at least laterally surrounded by the dielectric material. The first bonding structure is located above the first interconnect structure and is at least laterally surrounded by the dielectric material, wherein the first semiconductor substrate includes a first stepped sidewall.

[0066] According to some embodiments of this disclosure, a method for forming a semiconductor device includes the following steps: A first semiconductor substrate is provided, the first semiconductor substrate having a plurality of grain regions and diced regions located between the grain regions, wherein the diced regions include a semiconductor substrate, a dielectric material located on the semiconductor substrate, and a plurality of dummy conductive patterns at least laterally surrounded by the dielectric material. A plasma dicing process is performed in the diced regions to form trenches. A laser process is performed in the diced regions to form recesses communicating with the trenches.

[0067]

[0068] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0069] 10: Semiconductor Structure 110, 120: Semiconductor grains 110-1, 110-2: Grain regions 110A: Functional Area 110D: Cutting Area 110D1, 110D2: Partial 110G: Groove 110GT: Depth 110L: Cutting line area 110S: Sealing ring area 110T: Groove 112, 122, 1100, 1200: Semiconductor substrate 112a, 122a: Anterior side 112b, 122b: Dorsal side 112S, 1241t, 132t, 1161S, 1281t, 1282t: Surface 112W, 112W', 112W1, 112W2, 120W, 132W, 1161W1, 1161W2, 1161W2', 1161W3, 1181W: Sidewall 114, 214: Device 116, 126: Interconnection Structure 117: Sealing ring 118, 128: Joint structure 125: Through hole 125a, 125b: End 132: Insulating Encapsulation 134: Sealing layer 140: Conductive pad 142: Conductive terminal 1161, 1261: Dielectric layer 1162, 1262: Metallized patterns 1162D: Virtual Conductive Pattern 1181, 1241, 1281: Bonding dielectric layer 1182, 1182D, 1282D, 1282: Connecting parts DM: Dielectric material DM1, DM2: Dielectric components DM1W, DM2W, W1, W3, W2T: Width STP1, STP2: Stepped lateral walls TP: Turning Point θ, θ', θ1, θ2: Angles

Claims

1. A semiconductor device, comprising: A first semiconductor substrate having a first inclined sidewall; A dielectric material, located above the first semiconductor substrate and having a vertical sidewall, a second inclined sidewall, and a transition point between the vertical sidewall and the second inclined sidewall, the second inclined sidewall being located between the vertical sidewall and the first semiconductor substrate, and the vertical sidewall and the second inclined sidewall being physically connected; a first interconnect structure, located above the first semiconductor substrate and at least laterally surrounded by the dielectric material; and a first bonding structure, located above the first interconnect structure and at least laterally surrounded by the dielectric material.

2. The semiconductor device of claim 1, wherein the second inclined sidewall is located between the vertical sidewall and the first inclined sidewall.

3. The semiconductor device of claim 1, wherein the first inclined sidewall and the second inclined sidewall are continuously connected and there is no turning point between the first inclined sidewall and the second inclined sidewall.

4. The semiconductor device of claim 1, wherein the first semiconductor substrate further includes a vertical sidewall, and the first inclined sidewall is located between the vertical sidewall and the second inclined sidewall of the first semiconductor substrate.

5. The semiconductor device of claim 1, further comprising a first packaging material that encapsulates the first semiconductor substrate and the dielectric material.

6. A semiconductor device, comprising: A first die includes: a first semiconductor substrate; a dielectric material located above the first semiconductor substrate; a first interconnect structure located above the first semiconductor substrate and at least laterally surrounded by the dielectric material; and a first bonding structure located above the first interconnect structure and at least laterally surrounded by the dielectric material, wherein the first semiconductor substrate includes a first stepped sidewall, the dielectric material has a vertical sidewall and an inclined sidewall, the inclined sidewall being located between the vertical sidewall and the first semiconductor substrate, and the vertical sidewall and the inclined sidewall being substantially connected.

7. The semiconductor device of claim 6, wherein the first stepped sidewall of the first semiconductor substrate includes a vertical sidewall, an inclined sidewall, and a horizontal surface located between the vertical sidewall and the inclined sidewall of the first semiconductor substrate, and the inclined sidewall of the first semiconductor substrate is located between the vertical sidewall of the first semiconductor substrate and the inclined sidewall of the dielectric material.

8. A method of forming a semiconductor device, comprising: A first semiconductor substrate is provided, the first semiconductor substrate having a plurality of grain regions and a diced region located between the grain regions, wherein the diced region includes a semiconductor substrate, a dielectric material located on the semiconductor substrate, and a plurality of virtual conductive patterns at least laterally surrounded by the dielectric material; A plasma cutting process is performed in the cutting area to form a groove; And performing a laser process in the dicing area to form a groove communicating with the trench, wherein the dielectric material has a vertical sidewall and an inclined sidewall, the inclined sidewall being located between the vertical sidewall and the first semiconductor substrate, and the vertical sidewall and the inclined sidewall being physically connected.

9. The method of claim 8, wherein the plasma cutting process removes a first portion of the dielectric material that does not contain the virtual conductive pattern, and the laser process removes a second portion of the dielectric material and the virtual conductive pattern located in the second portion of the dielectric material.

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