Ethercat device and network communication method

Abstract

An EtherCAT device includes a communication circuit and a wake-up circuit. The wake-up circuit is configured to determine a condition for transmitting data to an EtherCAT master node. The wake-up circuit is configured to generate a wake-up packet based on such a condition. The communication circuit can be configured to receive EtherCAT frames originating from the EtherCAT master node. The communication circuit can be configured to populate the EtherCAT frames with data to be transmitted to the EtherCAT master node. The communication circuit can be configured to transmit the EtherCAT frames to the EtherCAT master node.

Description

Technical Field

[0001] The present invention relates to electronic communications, and more particularly to an Ethernet for Control Automation Technology (EtherCAT) controller. Prior Art

[0002] EtherCAT is a real-time industrial Ethernet technology originally developed by Beckhoff Automation. The EtherCAT protocol is disclosed in the International Electrotechnical Commission (IEC) standard IEC 61158. EtherCAT can be used in various suitable applications, such as automation, testing, and measurement.

[0003] An EtherCAT master node can transmit frames that can pass through every other node in the network (e.g., slave nodes, auxiliary nodes, or secondary nodes). Each EtherCAT slave node can read the data addressed to it located in the frame and insert its own data into the frame as the frame moves downstream. The frame may be delayed only by the hardware transmission latency. If the last slave node in a segment detects an open port, it uses the full duplex feature of Ethernet technology to send the information back to the master node.

[0004] The EtherCAT master node may be the only node in a network segment allowed to generate new EtherCAT frames. All other nodes may only forward the frames downstream and add their own data together. This concept can prevent unexpected delays.

[0005] The EtherCAT master node can use a standard Ethernet media access controller (MAC). This allows the implementation of the EtherCAT master node on any hardware platform with an available Ethernet port, regardless of the real-time operating system or application software used. The EtherCAT slave node can use an EtherCAT slave controller to process frames in real time. The EtherCAT slave controller can be implemented entirely in hardware, making the network performance predictable and independent of the implementation of individual slave devices. The interface of the EtherCAT master node or slave node can include a single Ethernet port.

[0006] An EtherCAT node can embed its payload in a standard Ethernet frame. The frame is identified by an identifier (0x88A4) in the EtherType field.

[0007] An EtherCAT controller such as a MAC or an EtherCAT slave controller can include a direct memory access (DMA) controller to perform data transfer between the device and the network. Each EtherCAT slave node can write its data to the corresponding position in the frame and read all the data addressed to it as the frame moves through the node. Thus, the frame returned to the main device has been correctly classified.

[0008] The inventors of the specific example of the present invention have found that current EtherCAT networks and slave controllers do not support low power mode, remote power management, cable diagnostics, or clock daisy-chaining. In such a network, there is no mechanism for placing a node in a low power mode (e.g., sleep mode) and then waking up such a node. Specifically, such a node in a lower power mode cannot be remotely awakened by other nodes using remote power management. Furthermore, in such a network, there is no mechanism for diagnosing whether network interference or cable problems have degraded the signal performance. And, in such a network, there is no mechanism for effectively implementing a daisy-chain configuration of nodes in terms of clock signals. The inventors of the specific example of the present invention have found solutions to one or more of these disadvantages of current EtherCAT implementations. Summary of the Invention

[0009] A specific example of the present invention includes a device. This device may include an EtherCAT device in an EtherCAT network. The EtherCAT network may include an EtherCAT master node. The EtherCAT device may include a communication circuit and a wake-up circuit. The wake-up circuit may be configured to determine a condition for the EtherCAT device to transmit data to the EtherCAT master node. The wake-up circuit may be further configured to generate a wake-up packet based on the determination of the condition for the EtherCAT device to transmit data to the EtherCAT master node. The wake-up circuit may be further configured to transmit the wake-up packet to the EtherCAT network via a network interface card (NIC). The communication circuit may be configured to receive an EtherCAT frame from the EtherCAT network. The EtherCAT frame may originate from the EtherCAT master node. The communication circuit may be configured to populate the EtherCAT frame with data to be transmitted to the EtherCAT master node. The communication circuit may be configured to transmit the EtherCAT frame to the EtherCAT master node towards the EtherCAT network.

[0010] A specific example of the present invention may include an EtherCAT master node of an EtherCAT network. This EtherCAT master node may include a controller circuit, which is configured to determine whether to place a plurality of slave nodes in the EtherCAT network in a sleep mode. The controller circuit may be further configured to issue a signal with a sleep flag based on the determination to place the slave nodes in the sleep mode. The sleep flag of the signal may include a value indicating the slave nodes to enter the sleep mode. The controller circuit may be further configured to issue another signal with a sleep flag based on the determination not to place the slave nodes in the sleep mode. The sleep flag of the other signal may include a value indicating the slave nodes not to enter the sleep mode.

[0011] Specific examples of the present invention may include an EtherCAT device configured to be included in an EtherCAT network. The EtherCAT network may include an EtherCAT master node. The EtherCAT device may include a processor configured to operate in a sleep mode and a normal operation mode. The EtherCAT device may include a NIC including a circuit configured to receive input EtherCAT packets initially sent by the EtherCAT master node from the EtherCAT network. The NIC may further include a circuit configured to parse the input EtherCAT packets, determine whether a given input EtherCAT packet is a wake-on-LAN (WoL) packet, generate a wake-up signal to the processor based on the determination that the given input EtherCAT packet is a WoL packet, and forward the given input EtherCAT packet to another node in the EtherCAT network when the processor is in the sleep mode.

[0012] Specific examples of the present invention may include an EtherCAT device. The EtherCAT device may include a node for an EtherCAT network. The EtherCAT device may include: a clock circuit; a clock input terminal configured to receive an input clock signal; a clock output terminal configured to transmit an output clock signal; and a control logic configured to determine whether to operate the EtherCAT device in a clock generation mode or in a clock transmission mode. In the clock generation mode, the clock circuit is configured to drive an oscillator to generate the input clock signal. In the clock transmission mode, the clock circuit may be configured to receive the input clock signal from another node in the EtherCAT network. The control logic may further be configured to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based on the input clock signal.

[0013] Specific examples of the present invention include an EtherCAT device. The EtherCAT device may include a node in an EtherCAT network. The EtherCAT device may include a data input port configured to receive a signal representing data. The signal may represent a logical value. The EtherCAT device may include a degradation calculation circuit configured to read the data into an array of slices and determine the distance between the position of a slice and the position of a reference slice. The slice may contain the input data. The degradation calculation circuit may be further configured to determine an error based on the distance and determine a signal quality index based on the error.

[0014] Specific examples of the present invention include a method of performing the configuration operations described in any of the above specific examples. Brief Description of the Drawings

[0015] FIGS. 1A and 1B are schematic diagrams of an example network of specific examples of the present invention. FIG. 2 is a more detailed schematic diagram of a network of specific examples of the present invention, including a portion of a slave node configured to wake up a master node. FIG. 3 is a more detailed schematic diagram of a network of specific examples of the present invention, including a portion of a master node configured to wake up a slave node using a flag in network traffic. FIG. 4 is a more detailed schematic diagram of a network of specific examples of the present invention, including a portion of a slave node configured to perform network wake-up (WoL) in hardware. FIG. 5 is a more detailed schematic diagram of a node such as a master node and a slave node of specific examples of the present invention, including a portion of a node for evaluating signal integrity. FIG. 6 is a more detailed schematic diagram of a node of specific examples of the present invention, including a portion of a node configured to selectively operate based on a clock signal generated by the node or based on a clock signal received from other nodes. FIG. 7 is a schematic diagram of a method for a slave node to wake up a master node in specific examples of the present invention. FIG. 8 is a schematic diagram of a method for a master node to be woken up by a slave node in specific examples of the present invention. FIG. 9 is a schematic diagram of a method for a master node to wake up a slave node using a flag in network traffic in specific examples of the present invention. FIG. 10 is a schematic diagram of a method for a slave node to be woken up by a master node using a flag in network traffic in specific examples of the present invention. FIG. 11 is a schematic diagram of a method for a master node to wake up a slave node using a WoL packet in specific examples of the present invention. FIG. 12A to FIG. 12F are schematic diagrams of a method for a slave node to be awakened by a master node using a WoL packet in a specific example of the present invention. FIG. 13 is a schematic diagram of a method for a node to execute a clock signal daisy chain in a specific example of the present invention. FIG. 14 is a schematic diagram of a method for a node to execute an assessment of the quality of a received signal in a specific example of the present invention. Embodiment

[0016] The following EtherCAT devices and EtherCAT master nodes in specific examples can be configured in an EtherCAT network. The circuits of the EtherCAT devices and EtherCAT master nodes can be implemented using digital logic, analog circuits, digital circuits, instructions executed by a processor, or any suitable combination thereof.

[0017] A specific example of the present invention includes a device. This device can include an EtherCAT device in an EtherCAT network. The EtherCAT network can include an EtherCAT master node. The EtherCAT device can include a communication circuit and a wake-up circuit. The wake-up circuit can be configured to determine a condition for the EtherCAT device to transmit data to the EtherCAT master node. The condition can include, for example, user input, temperature change, or any other suitable condition. The wake-up circuit can be further configured to generate a wake-up packet based on the determination of the condition for the EtherCAT device to transmit data to the EtherCAT master node. The wake-up packet can include a programmed address as the destination address. The destination address can be unique to the wake-up signal. For example, the destination address of the wake-up packet can be different from the destination address of a normal EtherCAT frame, but can still correspond to the master node. For example, this can be a predetermined string of values, followed by one or more repetitions of the destination address. The packet can include a broadcast packet or a magic packet. The wake-up circuit can be further configured to transmit the wake-up packet to the EtherCAT network via a network interface card (NIC). The communication circuit can be configured to receive an EtherCAT frame from the EtherCAT network. The EtherCAT frame can originate from the EtherCAT master node. The communication circuit can be configured to populate the EtherCAT frame with data to be transmitted to the EtherCAT master node. The communication circuit can be configured to transmit the EtherCAT frame to the EtherCAT master node towards the EtherCAT network.

[0018] Specific examples of the present invention may include an EtherCAT master node of an EtherCAT network. This EtherCAT master node may be the EtherCAT master node described in any of the above specific examples. The EtherCAT master node may include a controller circuit configured to determine whether to place an auxiliary node in the EtherCAT network in a sleep mode. In the sleep mode, power to one or more parts of the electronic device may be cut off, for example, disconnecting the power supply or turning off the electronic device, gating the clock, or operating the electronic device in a manner that reduces power consumption but still provides power.

[0019] The sleep mode is based on any suitable criteria, input, or condition, such as user input, no activity on the network 120 for a period of time, no activity for the processor 112 for a period of time, or a request from the master node 102.

[0020] The auxiliary node may include a slave node. The controller circuit may be further configured to issue a signal with a sleep flag according to the determination to place the auxiliary node in the sleep mode. The sleep flag of the signal may include a value indicating that the auxiliary node enters the sleep mode. The controller circuit may be further configured to issue another signal with a sleep flag according to the determination not to place the auxiliary node in the sleep mode. The sleep flag of the other signal may include a value indicating that the auxiliary node does not enter the sleep mode. In combination with any of the above specific examples, the sleep flag of the other signal further indicates waking up the auxiliary node from the sleep mode.

[0021] Specific examples of the present invention may include an EtherCAT device configured to be included in an EtherCAT network. The EtherCAT network may include an EtherCAT master node. This EtherCAT device may include a processor configured to operate in a sleep mode and a normal operation mode. The EtherCAT device may include a NIC, which includes a circuit and is configured to receive an input EtherCAT packet initially sent by the EtherCAT master node from the EtherCAT network. The NIC may further include a circuit configured to parse the input EtherCAT packet, determine whether a given input EtherCAT packet is a Wake-on-LAN (WoL) packet when the processor is in the sleep mode, generate a wake-up signal to the processor according to the determination that the given input EtherCAT packet is a WoL packet, and forward the given input EtherCAT packet to another node in the EtherCAT network.

[0022] In combination with any of the above specific examples, the NIC may include a circuit that is further configured to determine that a given input EtherCAT packet is a WoL packet by determining that the given input EtherCAT packet is a broadcast packet. In combination with any of the above specific examples, the NIC may further include a circuit that is configured to determine that a given input EtherCAT packet is a WoL packet by determining that the given input EtherCAT packet includes a predetermined value within a load range.

[0023] In combination with any of the above specific examples, the NIC may include a circuit that is further configured to determine that a given input EtherCAT packet is a WoL packet by determining that the given input EtherCAT packet includes the address of an EtherCAT device.

[0024] In combination with any of the above specific examples, the NIC may include a circuit that is further configured to determine that a given input EtherCAT packet is a WoL packet by determining that the given input EtherCAT packet includes the address of another EtherCAT device.

[0025] In combination with any of the above specific examples, the NIC may include a circuit that is further configured to determine that a given input EtherCAT packet is a WoL packet by determining that the given input EtherCAT packet includes the address of an EtherCAT master node.

[0026] Specific examples of the present invention may include EtherCAT devices. Such EtherCAT devices may include nodes used in an EtherCAT network. Such EtherCAT devices may include: a clock circuit; a clock input terminal configured to receive an input clock signal; a clock output terminal configured to transmit an output clock signal; and control logic configured to determine whether to operate the EtherCAT device in a clock generation mode or a clock transmission mode. In the clock generation mode, the clock circuit is configured to drive an oscillator to generate the input clock signal. In the clock transmission mode, the clock circuit may be configured to receive the input clock signal from another node in the EtherCAT network. The control logic may be further configured to control the clock circuit to output the output clock signal for subsequent nodes in the EtherCAT network based on the input clock signal.

[0027] Combined with any of the above specific examples, the clock circuit may include a clock regeneration circuit configured to receive an input clock signal and generate an output clock signal based on the input clock signal, and the output clock signal is configured to alternate between a first voltage level and a second voltage level supplied to the clock regeneration circuit. Combined with any of the above specific examples, the clock circuit may include a first clock regeneration circuit configured to receive an input clock signal and generate a first output. The clock circuit may include a second clock regeneration circuit configured to receive the input clock signal and generate a second output. Combined with any of the above specific examples, the control logic is configured to output an output clock signal based on the first output of the first clock regeneration circuit or the second output of the second clock regeneration circuit according to whether the EtherCAT device is in the clock transmission mode or the clock generation mode.

[0028] Combined with any of the above specific examples, the clock circuit may include a crystal driver configured to provide a signal to the oscillator in the clock generation mode to drive the oscillator to generate an input clock signal. Combined with any of the above specific examples, the clock circuit is further configured to route the input clock signal to the input terminal of the crystal driver in the clock generation mode.

[0029] Specific examples of the present invention include an EtherCAT device. This EtherCAT device may include nodes used in an EtherCAT network. This EtherCAT device may include a data input port configured to receive a signal representing data. The signal may represent a logical value. The EtherCAT device may include a degradation calculation circuit configured to read data into a bit-slice array and determine the distance between the position of a bit-slice and the position of a reference bit-slice. The bit-slice may contain the input data. The degradation calculation circuit may be further configured to determine an error based on the distance and determine a signal quality index based on the error.

[0030] FIG. 1A and 1B are diagrams of an example network 120 of specific examples of the present invention. The network 120 may be an EtherCAT network. The network 120 may be implemented in any suitable environment (e.g., in a factory, a test and verification system, or an automotive or other vehicle). Each node may be implemented by a computer, a laptop, a smart sensor, a server, a controller, a microcontroller, or any other suitable electronic device.

[0031] For example, network 120 may include a node configured to operate as the primary node 102. Network 120 may include one or more other auxiliary nodes configured to operate as slave nodes 104. Although two instances of slave nodes 104 (nodes 104A and 104B) are illustrated in the example of FIG. 1, network 120 may include any suitable number of slave nodes 104.

[0032] The primary node 102 and the slave nodes 104 may be connected in any suitable manner. The primary node 102 and the slave nodes 104 may be connected using a network connection that follows the EtherCAT protocol modified by the teachings of the present invention. The primary node 102 and the slave nodes 104 may be connected in a daisy-chain manner or in any other suitable topology for network communication. The data communication ports in the primary node 102 and the slave nodes 104 are represented by data output (DO) and data input (DI) ports. The DO and DI ports may be implemented in any suitable manner (e.g., by a PHY Ethernet port). Although illustrated in a daisy-chain configuration in FIG. 1, the representation of the communication between the primary node 102 and the slave nodes 104 shown in FIG. 1 may be considered logical, and the primary node 102 and the slave nodes 104 may be connected to each other in any physical manner. The DI and DO ports may be used to transmit EtherCAT data between the primary node 102 and the slave nodes 104.

[0033] Furthermore, in one embodiment, the primary node 102 and the slave nodes 104 may be connected to each other in a daisy-chain manner with respect to a shared clock. Each of the primary node 102 and the slave nodes 104 may include a CLKIN port to receive a clock signal. Each of the primary node 102 and the slave nodes 104 may include a CLKOUT port through which the clock signal may be transmitted from a node to another node. For example, the primary node 102 may include a CLKOUT port connected to the CLKIN port of the slave node 104A. The slave node 104A may in turn include a CLKOUT port connected to the CLKIN port of the slave node 104B. As discussed further in detail below, the clock signal may be generated by the primary node 102.

[0034] Each of the primary node 102 and the slave nodes 104 may include a processor 112 interconnectedly coupled to a respective memory 114, represented as processors 112A, 112B, 112C and memories 114A, 114B, and 114C, respectively. The memory 114 may include instructions that, when loaded and executed by the respective processors 112, may configure the respective nodes to perform one or more operations described in the present invention.

[0035] In one embodiment, the master node 102 may include controller circuitry, such as an EtherCAT master circuit (EMC) 108. The EMC 108 can be implemented in any suitable manner (e.g., by analog circuitry, digital circuitry, instructions for execution by a processor 112A, or any suitable combination thereof). The EMC 108 may be configured to control EtherCAT data and clock operations of the network 120, e.g., generate EtherCAT frames, transmit the frames to the slave nodes 104, generate clock signals, transmit the clock signals to the slave nodes 104, wake up the slave nodes 104, and receive and process wake-up signals from the slave nodes 104.

[0036] In one embodiment, the slave node 104 may include EtherCAT slave circuits (ESCs) 106, denoted as ESCs 106A and 106B respectively. The ESC 106 can be implemented in any suitable manner (e.g., by analog circuitry, digital circuitry, instructions for execution by a processor, or any suitable combination thereof). The ESC 106 may be configured to control EtherCAT data and clock operations on behalf of the individual slave node 104, e.g., read and parse signals such as EtherCAT frames, transmit signals and EtherCAT frames to other slave nodes 104, receive clock signals, transmit clock signals to other slave nodes 104, wake itself up according to internal wake-up conditions, and generate wake-up signals for the master node 102.

[0037] As described above, in one embodiment, a given node in the network 120 may include a CLKIN port for receiving a clock signal from the next node above in the daisy-chain topology. In another embodiment, a given node in the network 120 may include a CLKOUT port for transmitting a clock signal (whether generated by the device or received via the CLKIN port of the given node) to the next node below in the daisy-chain topology. The CLKOUT and CLKIN ports can thus be configured to receive and forward clock signals.

[0038] Furthermore, in yet another specific example, a given node in network 120 may include a crystal input (XI) port. A given node in network 120 may include a crystal output (XO) port. The XI and XO ports can be used to connect the given node to an oscillator, crystal, resonant element, or other source for generating a clock signal for the given node. For example, the primary node 102 may be configured to connect to the crystal 110 via its XO and XI ports. The primary node 102 may utilize the crystal 110 to generate a clock signal and then transmit the clock signal to the slave node 104 via the CLKOUT port of the primary node 102.

[0039] In one specific example, if a given node (e.g., the slave node 104) does not generate a clock signal, then the XI or XO ports may not be used. In another specific example, the CLKIN port and the XI port may be the same port. The XI port may be reused as the CLKIN port and vice versa. Thus, in the example of FIG. 1, the primary node 102 may connect to the crystal 110 via its XO and XI / CLKIN ports. The EMC 108 may be configured to obtain a clock signal from the crystal 110. The EMC 108 may be configured to adjust or divide the clock signal received from the crystal 110 and provide the resulting clock signal on its CLKOUT port to the slave node 104A. The slave node 104A may be configured to receive the clock signal via its XI / CLKIN port and use the clock signal for synchronous operation relative to other components of the network 120. The slave node 104A may be configured to transmit the clock signal to the slave node 104B via its CLKOUT port, however, the XO port of the slave node 104A is not used or implemented within the slave node 104A. The slave node 104B may be configured to receive the clock signal via its XI / CLKIN port and use the clock signal for synchronous operation relative to other components of the network 120. The XO port of the slave node 104B may not be used or implemented within the slave node 104B. The slave node 104B may transmit the clock signal to other slave nodes (not shown in the figure).

[0040] The primary node 102 may include an application 118 configured to execute on the processor 112A. The application 118 may be implemented by any suitable software executing on the primary node 102. The slave node 104 may include a similar application (not shown in the figure). The application 118 may include, for example, firmware, user-level software, automation software, or any other suitable software. The application 118 may have information to provide to the slave node 104 or be able to use information to be provided by the slave node 104. To share or obtain such information, the application 118 may communicate with the slave node 104 via the EMC 108. The EMC 108 may be configured to receive commands for such communication from the processor 112A.

[0041] The primary node 102 may issue an EtherCAT frame to the slave node 104. The EtherCAT frame may include a request or command for the slave node to fill data into the EtherCAT frame from the slave node 104. This may constitute a poll of the slave node 104 by the primary node 102. In the slave node 104, the ESC 106 may be configured to monitor EtherCAT frames from the primary node 102 or other slave nodes 104 originating from the primary node 102. In one embodiment, the ESC 106 may be configured to monitor such EtherCAT frames independently of the processor 112. For example, once the ESC 106 is set to the listening mode to monitor EtherCAT frames, the ESC 106 may be configured to monitor the DI for EtherCAT frames and output the EtherCAT frames via its DO port without additional commands from the processor 112. In another embodiment, the ESC 106 may be configured to fill data into the EtherCAT frames and transmit these EtherCAT frames via its DO port without additional commands from the processor 112. Such data filling may be performed by a memory operation such as a DMA operation on the memory 114 according to the content of the received EtherCAT frame indicating that the slave node 104 provides specific information. In other cases, the ESC 106 may forward the EtherCAT frame to the processor 112 and the software executing thereon, or send other notifications to the processor 112 and the software executing thereon to provide information for the EtherCAT frame before transmitting the EtherCAT frame to other slave nodes 104. In some embodiments, the operation of the ESC 106 can be performed in hardware.

[0042] An EtherCAT frame can return from the slave node 104 at the end of the daisy chain to the master node 102. The EtherCAT frame can contain information requested by the slave node 104.

[0043] The master node 102 and the slave node 104 can be configured to operate in one or more sleep, power-off, or power-reduced or operating modes. In such various sleep modes, power can be cut off from one or more parts of the electronic device. In different sleep modes, power can be cut off from different parts of the electronic device. Cutting off the power of the electronic device can include disconnecting the power supply or turning off the electronic device, gating the clock, or operating the electronic device in a manner that reduces power consumption but still provides power.

[0044] The master node 102 and the slave node 104 can be configured to enter the sleep mode according to any suitable criteria, inputs, or conditions. For example, the master node 102 and the slave node 104 can be configured to enter the sleep mode according to user input, no activity on the network 120 for a period of time, no activity for the processor 112 for a period of time, or a request from the master node 102.

[0045] In one embodiment, the EMC 108 or the ESC 106 can be configured to monitor a wake-up signal in hardware to exit the sleep mode. The wake-up signal can be generated by other EMCs 108 or ESC 106 and transmitted through the network 120. After receiving the wake-up signal, the EMC 108 or the ESC 106 can be configured to wake up the respective processor 112, wake up other peripheral devices of the respective node, and forward the wake-up signal to another node on the daisy chain. The EMC 108 or the ESC 106 can be configured to send a wake-up signal to other nodes on the daisy chain to enable such nodes to correctly receive and process EtherCAT frames.

[0046] In one embodiment, the EMC 108 and the ESC 106 can be configured to determine whether the signal strength of the input data on their respective DI ports has sufficient strength for proper communication. The EMC 108 and the ESC 106 can be configured to perform such an operation by evaluating the voltage levels of different data received via the DI ports. If the quality of the signal strength is insufficient, the EMC 108 and the ESC 106 can be configured to take any appropriate corrective measures, such as warning the user, sending a request to the sender of the EtherCAT frame to retransmit the data, or resetting the network 120.

[0047] Figure 1B illustrates an example configuration of nodes in various devices within an example network and within a larger network or system that includes such an example network. For example, system 100 may include multiple instances of network 120.

[0048] In one example, a given master node 102 that is linked to one or more slave nodes 104 in a daisy chain fashion may be located on a single device. In Figure 1B, this may be represented as a single instance of network 120. A given network 120 in Figure 1B may be implemented where each node is a different component on the same semiconductor die, wafer, printed circuit board (PCB), or other platform. As shown in Figure 1B, system 100, as a collection of systems, electronic devices, or smaller networks, may include multiple instances of device 120. System 100 itself may be considered a network. The nodes within each instance of network 120 may be connected together in a daisy chain fashion with respect to a clock signal.

[0049] In one example, instances of network 120 may be connected in a daisy chain fashion with respect to a clock signal. In another example, instances of network 120 may not be connected in a daisy chain fashion with respect to a clock signal. Within a given instance of network 120, a node may be a master node or a slave node.

[0050] For example, network 120A may include master node 102A, which provides a clock signal to subsequent slave nodes 104B and 104C in a daisy chain fashion. Data may be returned to master node 102A. This relationship is reflected in Figure 1A.

[0051] Network 120B may include a first node that can provide a clock signal to subsequent slave nodes 104E and 104F in a daisy chain fashion. In one example, the first node may be an instance of a master node (e.g., master node 102B). In another example, the first node may be an instance of a slave node (e.g., slave node 104D). In such an example, although slave node 104D may not be considered to be fully implemented as a master node, slave node 104D can still provide a clock signal to other slave nodes 104E and 104F in a daisy chain fashion in the same manner as a master node provides a clock signal.

[0052] Similarly, network 120C may include a first node that can provide a clock signal to subsequent slave nodes 104H and 104I in a daisy-chain manner. In one embodiment, the first node may be an instance of a master node (e.g., master node 102C). In another embodiment, the first node may be an instance of a slave node (e.g., slave node 104G). In such an embodiment, although slave node 104G may not be considered to be fully implemented as a master node, slave node 104G can still provide a clock signal to other slave nodes 104H and 104I in a daisy-chain manner in the same way as a master node provides a clock signal.

[0053] In one embodiment, each instance of networks 120B and 120C may generate its own clock signal and transmit the clock signal between its nodes. In another embodiment, each instance of networks 120B and 120C may receive a clock signal and transmit the clock signal between its nodes. In another embodiment, networks 120B and 120C may receive a clock signal from network 120A in parallel. In yet another embodiment, networks 120B and 120C can receive a clock signal from network 120A in a daisy-chain manner.

[0054] For example, network 120B may receive a clock signal from network 120A. In one embodiment, the clock signal may include a clock signal originating from master node 102A, which is provided to slave node 104B and network 120B in parallel. In another embodiment, the clock signal may include a clock signal from the end of the daisy-chain of network 120A (e.g., slave node 104C).

[0055] In another example, network 120C may receive a clock signal from network 120A. In one embodiment, the clock signal may include a clock signal originating from master node 102A, which is provided to slave node 104B and network 120C in parallel.

[0056] In yet another example, network 120C may receive a clock signal from network 120B. In one embodiment, the clock signal may include a clock signal from the end of the daisy-chain of network 120B (e.g., slave node F).

[0057] In various embodiments, each instance of network 120 can generate its own clock, use the clock of network 100 in parallel, or otherwise obtain a clock signal without reference to other instances of network 120. Further, in various embodiments, when connected together in a daisy chain, instances of network 120 can operate in a manner similar to the internal components within a single instance of network 120 with respect to sharing a clock signal between a primary node and a subordinate node.

[0058] FIG. 2 is a more detailed illustration of network 120 of an embodiment of the present invention, including a portion configured to wake up primary node 102 by subordinate node 104.

[0059] As described above, primary node 102 can include application 118. Application 118 can be configured to stop network traffic on network 120. Such a stop can be based on, for example, a timer expiration with no new traffic, user input, or any other suitable input or condition. The primary node 102 can be placed in a sleep mode by any such input or condition.

[0060] When primary node 102 is in the sleep mode, one or more components of primary node 102 can be configured to monitor a wake-up signal. As shown in FIG. 2, such a wake-up signal can originate from, for example, a user of primary node 102, a component within primary node 102, or subordinate node 104. For example, EMC 108 can include a network interface card (NIC) 214 configured to monitor a wake-up signal received from subordinate node 104.

[0061] In contrast, the slave node 104 can be in a normal operation mode or a sleep mode. The slave node 104 can be in the sleep mode, in which parts inside it are turned off except for the components used to monitor the wake-up condition. Such conditions can include, for example, user input, temperature change, or any other suitable conditions. Whether the slave node 104 is in the normal operation mode or in the sleep mode, a given slave node 104 can determine that a condition has occurred for which the network 120 should be woken up. The slave node 104 may not be able to establish or generate new EtherCAT frames, and such a function may be reserved for the master node 102. However, the master node 102 may be in the sleep mode. Thus, in one specific example, the slave node 104 can be configured to wake up the master node 102 so that the master node 102 will start polling again or send out new EtherCAT frames. When the slave node 104 that wakes up the master node 102 receives an EtherCAT frame, the slave node 104 can fill the EtherCAT frame with the information that prompted the slave node 104 to wake up the master node 102.

[0062] To wake up the master node 102, based on the determination of the condition for the slave node 104 to send data to the master node 102, the slave node 104 can generate any suitable signal. The signal can include a wake-up packet that contains a destination address matching the address programmed in the NIC 214. The destination address can be specific to the wake-up signal. For example, the destination address of the wake-up signal can be different from the destination address of a normal EtherCAT frame but can still correspond to the master node 102. The NIC 214 can distinguish the wake-up signal from normal traffic by such a specific destination address. The signal can include a magic packet used in the Ethernet network. The magic packet can be a broadcast frame that includes a payload with a specified string of values. For example, this can be a predetermined string of values followed by one or more repetitions of the destination address. The signal can include a broadcast packet, where, in contrast to a packet intended for a specific destination, the NIC 214 wakes up when the nature of the signal is a broadcast packet.

[0063] The slave node 104 may include any suitable mechanism for generating a wake-up signal. Additionally, the slave node 104 may include any suitable mechanism for generating normal traffic. For example, the slave node 104 may include a wake-up circuit (e.g., wake-up circuit 204). The slave node 104 may include a telecommunications circuit (e.g., communication circuit 202). The wake-up circuit 204 and the communication circuit 202 may be implemented within, for example, the ESC 106. The wake-up circuit 204 and the communication circuit 202 may be implemented by analog circuits, digital circuits, instructions for execution by a processor, or any suitable combination thereof. The wake-up circuit 204 may be configured to determine conditions under which the slave node 104 is to transmit data to other nodes (e.g., the master node 102). For example, the wake-up circuit 204 may be configured to determine the wake-up conditions of the slave node 104 and the network 120. To determine the wake-up conditions, the wake-up circuit 204 may receive inputs from any appropriate source where the slave node 104 is to wake up or where there is a condition for the slave node 104 to report data, alerts, or information to other parts of the network 120. For example, the slave node 104 may include or may be communicatively coupled to a sensor 208, a user interface (UI) 210, or a timer 212. The sensor 208 may record network, device, or environmental conditions that other elements of the network 120 are to be notified of. The UI 210 may record user inputs for explicitly or implicitly waking up multiple parts of the network 120. The timer 212 may alert the wake-up circuit 204 to wake up multiple parts of the network 120, for example, according to periodicity.

[0064] The communication circuit 202 may be configured to issue normal traffic on behalf of the slave node 104, such as filling of EtherCAT frames. For example, after receiving an EtherCAT frame on the DI, the application 206 of the slave node 104 may immediately provide an input to fill the EtherCAT frame. Such a filled EtherCAT frame may be issued as normal traffic via the DO of the slave node 104.

[0065] The slave node 104 may include any suitable mechanism for determining whether to issue normal traffic or a wake-up signal. For example, the slave node 104 may include a multiplexer 205, which is configured to selectively issue the output of normal traffic from the communication circuit 202 or the wake-up signal from the wake-up circuit 204. The multiplexer 205 may be controlled by, for example, the wake-up circuit 204. The wake-up circuit 204 may be configured to issue a wake-up enable signal to the multiplexer 205. When the wake-up enable signal is set to an active level, the wake-up enable signal may cause the multiplexer 205 to issue the output from the wake-up circuit 204. Otherwise, by default, the multiplexer 205 may issue the output from the communication circuit 202.

[0066] The master node 102 can be configured to receive a wake-up signal or normal traffic from the slave node 104 via the DI. When the master node 102 is in the sleep mode, the normal traffic received at the master node 102 can be ignored. When the master node 102 is in the normal operation mode, the wake-up signal received at the master node 102 can be ignored.

[0067] After receiving the wake-up signal, the master node 102 can be configured to immediately generate a new EtherCAT frame to poll the slave node 104. To generate a new EtherCAT frame, various parts of the master node 102 can be awakened from the sleep mode. For example, after detecting a wake-up signal from the slave node 104, the NIC 214 can generate an interrupt or other suitable wake-up signal to the application 118 or the processor 112. Thereafter, the master node 102 can be configured to generate an EtherCAT frame and transmit it to the slave node 104.

[0068] Thereafter, the communication circuit 202 can be configured to receive an EtherCAT frame from the now-awakened master node 102 on the DI. The communication circuit 202 can be configured to fill the EtherCAT frame with data to be transmitted to the master node 102. The data can include data requested by the master node 102 via the EtherCAT frame, data recorded by the slave node 104, alerts, or any other suitable information. The communication circuit 202 can be configured to then transmit the filled EtherCAT frame back to the master node 102 via the network 120.

[0069] In one embodiment, the slave node 104 can be configured to issue a wake-up signal under any condition where the slave node 104 determines that the slave node 104 wants to share information with other components of the network 120.

[0070] FIG. 3 is a more detailed illustration of the network 120 of an embodiment of the present invention, including a portion of the master node 102 configured to use a flag in the network traffic to wake up the slave node 104.

[0071] The master node 102 can be configured to wake up the slave node 104 to ensure that the slave node 104 can receive and process EtherCAT frames. The master node 102 can be configured to wake itself up or determine whether to wake up the slave node.

[0072] As described above, the master node 102 may be configured to stop network traffic on the network 120. Such a stop may be based on, for example, the expiration of a timer without new traffic, user input, or any other suitable input or condition. The master node 102 may be placed in a sleep mode by any such input or condition. Additionally, the master node 102 may be configured to place the slave node 104 in a sleep mode based on any such input or condition.

[0073] When the slave node 104 is in the sleep mode, one or more components of the slave node 104 may be configured to monitor for wake-up signals. As shown in FIG. 3, such wake-up signals may originate from, for example, a user of the slave node 104, components within the slave node 104, or the master node 102. For example, the ESC 106 may include a NIC 302 configured to monitor for wake-up signals received from the master node 102. The NIC 302 may be further configured to monitor input EtherCAT packets from the network 120 initially sent by the master node 102.

[0074] The master node 102, in turn, may be in a normal operating mode or a sleep mode. The master node 102 may be in the sleep mode, in which case it shuts down some of its internal parts except for the components used to monitor for wake-up conditions. Such conditions may include, for example, user input, temperature changes, or any other suitable condition. Whether the master node 102 is in the normal operating mode or the sleep mode, the master node 102 may determine that a condition has occurred where the network 120 (specifically, the slave node 104) should be awakened. The slave node 104 may not be able to respond to EtherCAT frames while in the sleep mode. Thus, in one embodiment, the master node 102 may be configured to wake up the slave node 104 so that the slave node 104 can start responding to polls and received EtherCAT frames again.

[0075] To wake up the slave node 104 or put the slave node 104 into the sleep mode, the master node 102 can generate any suitable signal. In a specific example, traffic or packets with a specific flag such as SleepFlag can be used to wake up the slave node or put the slave node 104 into the sleep mode. Such traffic or packets can be implemented in an EtherCAT frame. SleepFlag can include a bit, a flag, information, or other data of the packet. If SleepFlag is not activated in the packet transmitted from the master node 102, the slave node 104 that receives the packet can wake up while being in the sleep mode. If the slave node is in the normal operation mode, the flag set to be not activated can be ignored. In any case, if SleepFlag is set to be not activated, the slave node 104 that receives the packet may not enter or remain in the sleep mode. By default, SleepFlag can be not activated. If SleepFlag is activated, the slave node 104 that receives the packet can enter the sleep mode if it is not already in the sleep mode. If the slave node 104 that receives the packet is already in the sleep mode, the packet can be ignored or simply forwarded. In any case, the slave node 104 that receives traffic with SleepFlag set to any setting can also forward the traffic to other slave nodes 104.

[0076] The master node 102 can include any suitable mechanism for generating a wake-up signal with SleepFlag set or cleared in the packet. For example, the master node 102 can include a wake-up circuit 322 or a communication circuit 320. The wake-up circuit 322 and the communication circuit 320 can be implemented, for example, within the EMC 108. The wake-up circuit 322 and the communication circuit 320 can be implemented by an analog circuit, a digital circuit, instructions for execution by a processor, or any suitable combination thereof. The wake-up circuit 322 can be configured to determine the wake-up conditions of the master node 102 and the network 120. The wake-up circuit 322 can receive inputs from any suitable source from which the master node 102 or other components of the network 120 are to wake up. For example, the master node 102 can include or can be communicatively coupled to a sensor 324, a UI 326, or a timer 328. The sensor 324 can record the network, device, or environmental conditions under which the network 120 (e.g., the master node 102 and the slave node 104) is to wake up and the slave node 104 is to start reporting. The UI 326 can record user inputs for explicitly or implicitly waking up multiple parts of the network 120. The timer 328 can remind the wake-up circuit 322 to wake up multiple parts of the network 120, for example, according to periodicity.

[0077] The EMC 108 can be configured to use the communication circuit 320 to send normal traffic with a SleepFlag set to inactive. For example, the application 118 can provide an input or command to fill the EtherCAT frame. When the slave node 104 wakes up, such an EtherCAT frame can be sent as normal traffic after receiving the EtherCAT frame on the DI or after generating the EtherCAT frame. The EtherCAT frame can be sent by the communication circuit 320.

[0078] Furthermore, after notifying or determining to send an EtherCAT frame to the slave node 104, the EMC 108 can be configured to immediately send a signal with a SleepFlag set to inactive to the slave node 104. This can be performed by the wake-up circuit 322.

[0079] When notifying or determining to put the slave node 104 into the sleep mode, the EMC 108 can be configured to immediately send a signal with a SleepFlag set to active. This can be performed by the wake-up circuit 322. The signal can include an EtherCAT frame or any other suitable signal and can be generated by any suitable part of the EMC 108.

[0080] The slave node 104 can be configured to receive a signal from the master node 102 via the DI. The slave node 104 can be configured to receive a signal including the SleepFlag from the master node 102. If the SleepFlag is set to active and the slave node 104 is already in the sleep mode, the SleepFlag can be ignored and the signal can be transmitted to another slave node. If the SleepFlag is set to active and the slave node 104 is not in the sleep mode, the slave node 104 can set various parts of the slave node 104 to the power-saving mode or turn them off. The signal can be transmitted to another slave node. If the SleepFlag is set to inactive and the slave node 104 has woken up, the signal can be ignored and the signal can be transmitted to another slave node. If the SleepFlag is set to inactive and the slave node 104 has not woken up, various parts of the slave node 104 can be woken up, and the signal can be ignored and the signal can be transmitted to another slave node.

[0081] Any suitable part of the slave node 104 can handle wake-up or sleep operations according to the state of the SleepFlag. For example, when the NIC 302 detects the state of the SleepFlag that requires a wake-up or sleep change of the slave node 104, it can immediately transfer the state of the SleepFlag to the application 206, the processor 112, or the power controller 306. The NIC 302 can transfer the SleepFlag to the application 206. The NIC 302 can first wake up the application 206, or the application 206 can operate in a limited manner on the parts of the slave node 104 that are still operating during the sleep mode. The application 206 can transfer wake-up instructions, sleep instructions, interrupt requests, or any other suitable signals to the processor 112 and the power controller 306. The power controller 306 can be implemented by an analog circuit, a digital circuit, instructions for execution by the processor, or any suitable combination thereof. The power controller 306 can be configured to wake up or put the various peripheral devices 304 of the slave node 104 into the sleep state. The peripheral devices 304 can include, for example, a memory controller, a video controller, an input / output device, a counter, a timer, a function generator, an encryption block, or any other suitable electronic device or part thereof. The processor 112 can be configured to wake up or put the various components (e.g., processing cores) inside it into the sleep state. Although in the sleep mode, some peripheral devices 304 can remain operating, while other peripheral devices 304 or the processor 112 enter the sleep mode. For example, during the sleep mode, the motor controller can continuously operate the electromechanical motor without additional input from the processor 112.

[0082] FIG. 4 is a more detailed illustration of the network 120 of a specific example of the present invention, including a part of the slave node 104 configured to perform network wake-up (WoL) in hardware. In FIG. 4, the main node 102 can be implemented in a similar manner as shown in FIG. 3. In FIG. 4, the wake-up circuit 322 or the communication circuit can issue a signal without the SleepFlag component. The signal can include a packet. The packet can be implemented within an EtherCAT frame.

[0083] In a specific example, a packet can include a packet having a specific address. When received by the slave node 104, the slave node 104 can identify the packet as a wake-up packet based on the address. The address may not be unique to a particular instance of the slave node 104, such that after forwarding the packet to another instance of the slave node, the other slave node can also identify the address as indicating that the packet is a wake-up packet. Thus, the packet can be a wake-up packet for the slave node 104, and its address is not unique to the slave node 104, or otherwise identifies the actual address used by the slave node 104. The address can be, for example, the address of the master node 102. When received by the slave node 104, the packet can be understood as a wake-up packet.

[0084] In another specific example, the packet can include a WoL packet, which can be specifically configured to be recognized by the WoL circuit. The WoL packet can include a magic packet. The magic packet can include a broadcast frame. The magic packet can include a specific sequence of values within a given portion of the frame. For example, the magic packet can include a value of 255 in its payload, followed by a specific number of repetitions of the target address, e.g., 16 repetitions. When received by the slave node 104, the packet can be identified as a WoL-packet-based identification of the specific sequence of values. The WoL packet can be configured as a wake-up packet for the slave node 104. When received by the slave node 104, the packet can be understood as a wake-up packet. Thus, the NIC 302 can be configured to determine that the packet is a WoL packet by determining that the wake-up packet includes a predetermined value in its payload.

[0085] In yet another specific example, the packet can be a broadcast packet such as a broadcast frame. The broadcast frame can be an EtherCAT frame. When the slave node 104 receives the packet, the packet can be identified as a broadcast frame and, based on its status as a broadcast frame, be used as a wake-up packet for the slave node 104. When the slave node 104 receives the packet, the packet can be regarded as a wake-up packet. Thus, the NIC 302 can be configured to determine that the packet is a WoL packet by determining that the wake-up packet is a broadcast packet.

[0086] In yet another specific example, the packet can be a frame such as an EtherCAT frame that is addressed to a specific instance of the slave node 104 identified by the address of the slave node 104. When the slave node 104 receives the packet, the packet can be regarded as a wake-up packet. Thus, the NIC 302 can be configured to determine that the packet is a WoL packet by determining that the wake-up packet contains the address of the slave node 104.

[0087] In another specific example, the packet can be a frame such as an EtherCAT frame, which is addressed to a specific instance of the slave node 104 identified by the address of another slave node 104 or the master node 102. When the slave node 104 receives the packet, the packet can be regarded as a wake-up packet. Therefore, the NIC 302 can be configured to determine that the packet is a WoL packet by determining that the wake-up packet contains the address of another specific EtherCAT device different from the slave node 104. Specifically, the NIC 302 can be configured to determine that the packet is a WoL packet by determining that the wake-up packet contains the address of the master node 102.

[0088] For any such wake-up packet, the identification of the wake-up packet, the alert of other parts of the slave node 104, and the forwarding of the wake-up packet to other slave nodes can be processed in hardware. For example, these can be processed in the NIC 302 (especially in the WoL circuit 402 within the NIC 302). The WoL circuit 402 can be implemented by any suitable combination of analog and digital circuits. The WoL circuit 402 can be configured to parse the input packet when other parts of the slave node 104 (such as the processor 112) are in the sleep mode. The WoL circuit 402 can forward the received packet to other nodes in the daisy chain. The WoL circuit 402 can be configured to determine whether a given input packet is a WoL packet. After identifying the input packet as a wake-up packet, the WoL circuit 402 can be configured to immediately generate a wake-up signal such as a WoL signal to any other suitable part of the slave node 104 to start waking up the slave node 104 from the sleep mode. Such a wake-up signal can be transmitted to, for example, the processor 112 or the power controller 306. The NIC 302 can be configured to forward the packet to another node in the network 120.

[0089] For example, the WoL circuit 402 can detect the wake-up packet. In response, the WoL circuit 402 can send a WoL signal to the power controller 306. After receiving the WoL signal, the power controller 306 can immediately start the rest of the slave node 104. This can include, for example, the processor 112.

[0090] FIG. 5 is a more detailed illustration of nodes such as main node 102 and subordinate node 104 of a specific example of the present invention, including a portion of the node for evaluating signal integrity. In the example of FIG. 5, a more detailed illustration of ESC 106 in subordinate node 104 is illustrated, including degradation circuit 502. However, degradation circuit 502 can also be implemented in EMC 108 within main node 102. Degradation circuit 502 can be implemented by an analog circuit, a digital circuit, instructions for execution by a processor, or any suitable combination thereof.

[0091] Degradation circuit 502 can be configured to determine the signal strength of an input channel, data, or line on the DI port of subordinate node 104. The data input on the DI port can include one of any suitable different logic values. For example, the EtherCAT signal on the DI port may have three different logic values: -1, 0, and +1. These three logic values can actually be transmitted in network 120 at any suitable voltage (e.g., -5V, 0V, and +5V). However, due to interference, component degradation, transmission line degradation, or any other error source, the voltages used to actually transmit and receive the logic values may not be -5V, 0V, and +5V, but values that vary therewith. Degradation circuit 502 can be configured to evaluate how much deviation has occurred between the ideal transmission voltage and the actual received voltage regarding these logic values.

[0092] Degradation circuit 502 can include a demodulator, an analog-to-digital converter (ADC), and a digital signal processor (DSP) 504. Degradation circuit 502 can be configured to sample the input from the DI port and generate a data set, wherein the input signal has been normalized within a given range (e.g., from -128 to 128). Each unit within the range can be referred to as a slice. The slices can be represented by an array. In this data set, the ideal -1 logic received value will be represented by slice -128, the ideal 0 logic received value will be represented by slice 0, and the ideal +1 logic received value will be represented by slice 128.

[0093] The degradation circuit 502 can be configured to determine how far a given input received via DI and represented in a data bit slice is from an expected value. This can be achieved by evaluating the distance between the measured bit slice and bit slices -128 and +128. Bit slice -128 can represent an ideal measurement of the logical value -1. Bit slice +128 can represent an ideal measurement value of the logical value +1. Bit slice 0 can represent an ideal measurement of the logical value 0. Measurements represented by bit slices between -128 and -65 can be considered as the logical value -1. Measurements represented by bit slices between -64 and +64 can be considered as the logical value 0. Measurements represented by bit slices between +65 and +128 can be considered as the logical value +1. Bit slice -64 can represent that the logical value -1 has degraded sufficiently to be considered as a value of the logical value 0, or conversely, the logical value 0 has degraded sufficiently to be considered as a value of the logical value -1. Bit slice +64 can represent that the logical value +1 has degraded sufficiently to be considered as a value of the logical value 0, or conversely, the logical value 0 has degraded sufficiently to be considered as a value of the logical value +1. When a given received value has an unknown logical value, the degradation circuit 502 can be configured to determine the expected logical value based on the proximity to the ideal bit slices. When the signal degrades and further drifts away from bit slices -128 and +128, the degradation circuit 502 can be configured to identify such a situation before, for example, the logical value +1 degrades below bit slice +64, the logical value 0 degrades above bit slice +64 or below bit slice -64, or the logical value -1 degrades above bit slice -64. Thus, the degradation circuit 502 can be configured to determine the distance between the position of a given bit slice (i.e., the data input) and the position of a reference bit slice. The reference bit slice can include, for example, bit slices -128 and +128.

[0094] If the measured bit slice is less than or equal to 64 positions away from bit slice -128, the logical value -1 can be detected. Such a position can be evaluated in absolute terms. In an ideal situation, the logical value -1 would be received in bit slice -128, where it is 64 positions away from bit slice -64. The actual distance between the measured bit slice and bit slice -128 can be used as a measure of the error in the transmission of the logical value -1. Once the logical value -1 is equal to or greater than bit slice -64, the internal data may be useless because the logical value may be uncertain or appear as the logical 0 instead of the logical -1.

[0095] If the measured bit slice is more than 64 positions away from both bit slices -128 and +128, then the logical value 0 can be detected. In an ideal situation, the logical value 0 is received in bit slice 0, where it is 128 positions away from bit slice -128 and bit slice +128. The actual distance between the measured bit slice and bit slice 0 can be used as a measure of the error in the transmission of the logical value 0. Once the logical value 0 is equal to or less than bit slice -64 or equal to or greater than bit slice +64, the internal data may be useless because the logical value may be uncertain or appear as logical -1 or 1 instead of logical 0.

[0096] If the measured bit slice is less than or equal to 64 positions away from bit slice +128, then the logical value +1 can be detected. In an ideal situation, the logical value +1 is received in bit slice +128, where it is 64 positions away from bit slice +64. The actual distance between the measured bit slice and bit slice +128 can be used as a measure of the error in the transmission of the logical value +1. Once the logical value +1 is equal to or less than bit slice +64, the internal data may be useless because the logical value may be uncertain or appear as logical 0 instead of logical +1.

[0097] The error of the measured input data can be calculated by any suitable mechanism and added to other measurement results. For example, the degradation circuit 502 can include a mean-squared-error (MSE) circuit 506. The MSE circuit 506 can be implemented by an analog circuit, a digital circuit, instructions for execution by a processor, or any suitable combination thereof. The MSE circuit 506 can be configured to measure the distances between the bit slices of the signal under test and bit slices -128, 0, and +128, determine the expected logical value (if not known in advance), and calculate the error represented by the distances. The MSE circuit 506 can be configured to, for example, use the quantization of the distances between the bit slices of the signal under test and bit slices -128, 0, and +128 over a period of time (e.g., 500 microseconds). The mean-squared-error calculation can be performed. The determined error can be mapped to one of a set of discrete error conditions in a look-up table (LUT) 508. The result of mapping the error to the LUT 508 can be stored in a memory (e.g., error register 510) or provided to the user of the system 120. Thus, the degradation circuit 502 can be configured to determine the error based on the calculated distances.

[0098] The discrete error conditions defined in the LUT 508 can describe the relative degree of error conditions (e.g., the condition of no error) as the logical -1 exceeding the acceptable range, the logical 0 exceeding the acceptable range, or the logical +1 exceeding the acceptable range. The acceptable range can be, for example, between the position of the bit slice of the ideal logical value and the midpoint between the position of the bit slice of the ideal logical value and the bit slice -64 or +64. For example, the acceptable range of logical -1 can be between bit slice -128 and bit slice -96. If the measurement of logical -1 is greater than bit slice -96 and close to bit slice -64, it may cause an error condition for logical -1. The acceptable range of logical 0 can be between bit slice -32 and bit slice +32. If the measurement of logical 0 is greater than bit slice +32 or less than bit slice -32, it may cause an error condition for logical 0. The acceptable range of logical +1 can be between bit slice +96 and bit slice +128. If the measurement of logical +1 is less than bit slice +96, it may cause an error condition for logical +1.

[0099] The system 120 can use the error determined by the LUT 508 as an indicator of the signal quality index in any suitable manner. The error itself can be used as the signal quality index, or the error can be converted into a qualitative measure of the signal quality index. Any appropriate corrective action can be taken, for example, re - issuing the data or alerting the user.

[0100] FIG. 6 is a more detailed illustration of a node of an embodiment of the present invention, including a portion of a node configured to selectively operate based on a clock signal generated by the node or based on a clock signal received from another node in the daisy chain. FIG. 6 can provide a more detailed illustration of the ESC 106 in the slave node 104 or a more detailed illustration of the EMC 108 in the master node 102. The node 102 / 104 can include a clock circuit 602.

[0101] The clock circuit 602 can be configured to selectively determine whether a given node implementing the clock circuit 602 internally uses a clock signal generated by the node or a clock signal received from another node in the daisy chain at the node. In addition, the clock circuit 602 can be configured to route the connections within the node to use a clock signal generated by the node or a clock signal received from another node in the daisy chain at the node. The clock circuit 602 can include a clock input terminal configured to receive an input clock signal, such as XI / CLKIN. The clock circuit 602 can include a clock output terminal configured to transmit an output clock signal, such as CLKOUT.

[0102] The clock circuit 602 may include control logic 604, which may be implemented by any suitable combination of analog circuits, digital circuits, and instructions for execution by a processor. The control logic 604 may determine the setting of nodes 102 / 104 to determine whether to use the clock signal generated by nodes 102 / 104 or the clock signal received from another node in the daisy chain at nodes 102 / 104. Such determination can be made in any suitable manner (e.g., a numerical value in a memory or register). When nodes 102 / 104 generate a clock signal, it can be said that nodes 102 / 104 operate in a clock generation mode. The clock signal can be generated in any suitable manner, e.g., by using an internal oscillator, an oscillator circuit, or a crystal oscillator (not shown in the figure) connected to nodes 102 / 104. When nodes 102 / 104 receive a clock signal from another node in the daisy chain and operate nodes 102 / 104 using the clock signal, it can be said that nodes 102 / 104 operate in a clock transmission mode. Therefore, the control logic 604 can operate various components of the clock circuit 602 according to whether nodes 102 / 104 are configured to operate in a clock generation mode or in a clock transmission mode.

[0103] In many intended applications of the specific example of the present invention, the clock signal used inside the clock circuit 602 may have different voltages in the clock generation mode and in the clock transmission mode. For example, in the clock generation mode, where the clock circuit 602 is configured to generate a clock signal by, for example, applying an excitation voltage to an external crystal 110 (not shown in the figure), and then receiving the generated clock signal via XI / CLKIN, the clock signal generated in this way may be within a relatively low voltage range, e.g., 3.3 volts. In the clock transmission mode, where the clock circuit 602 is configured to transmit the received clock signal from another node to the rest of the daisy chain, the received clock signal may be within a relatively high voltage range, e.g., 5 volts.

[0104] The clock circuit 602 may include one or more clock regeneration circuits, which may be implemented in any suitable manner. Such a clock regeneration circuit may be configured to receive an input clock signal and generate an output clock signal based on the input clock signal. The output clock signal may alternate between voltage levels defined by the clock circuit 602 as a clock signal. Thus, given a noisy input clock signal, the clock circuit 602 may be configured to regenerate a clock signal with reduced noise before it is passed to subsequent nodes in the network 120. The clock circuit 602 may include any suitable number of clock regeneration circuits. The clock circuit 602 may include different clock regeneration circuits according to different voltage ranges that may be required to be used in the clock circuit 602. For example, the clock regeneration circuits of the clock circuit 602 may include a VDDL buffer 608 and a VDDH buffer 606.

[0105] The VDDL buffer 608 may be configured to emit a logic value "1" equal to the voltage of its voltage source VDDL in response to a positive signal on its input when it is enabled, and to emit a logic value "0" at, for example, zero voltage when it is disabled or in response to a low or negative signal on its input. The VDDL buffer 608 may be used to process an input clock signal in a relatively low voltage range from the XI / CLKIN input terminal. Similarly, the VDDH buffer 606 may be configured to emit a logic "1" equal to the voltage of its power supply VDDH when it is enabled, and to emit a logic value "0" at, for example, zero voltage when it is disabled or in response to a low or negative signal on its input. The VDDH buffer 606 may be used to process an input clock signal in a relatively high voltage range from the XI / CLKIN input terminal. The buffers 606, 608 may be enabled or disabled by control signals from the control logic 604. The VDDL buffer 608 and the VDDH buffer 606 may each be connected to the CLKIN / XI input terminal of the node. The VDDL buffer 608 and the VDDH buffer 606 may each be configured to remove noise, jitter, or otherwise clean up the clock signal generated by the crystal or received by the node from another node via the CLKIN / XI input terminal. The VDDL buffer 608 and the VDDH buffer 606 may each be configured to do so by regenerating the clock signal.

[0106] In one particular example, only one of the VDDH buffer 606 and the VDDL buffer 608 can be enabled at a time. Thus, the output clock signal of the clock circuit 602 may be based on the output of the buffer that is enabled among the VDDH buffer 606 and the VDDL buffer 608.

[0107] The outputs of buffers 606 and 608 can be within the range defined by the power supplies supplied to the individual buffers 606 and 608. Thus, in order to standardize the output level of the output clock signal via CLKOUT to the next node in the daisy chain, clock circuit 602 can include one or more level converter circuits such that the output from any enabled buffer among the individual buffers 606 and 608 can be standardized in both the clock generation mode and the clock transmission mode. For example, level converter circuit 614 can receive the outputs of buffers 606 and 608. Level converter circuit 614 can be configured to amplify its non-zero input to match a specified level. The specified level can be, for example, the voltage level for the output clock signal. Furthermore, clock circuit 602 can include output driver 616, which is configured to receive the output of level converter circuit 614 and provide the output clock signal to CLKOUT. Since processing is performed by level converter circuit 614 to ensure that the output clock signal is within an appropriate range and does not alternate between several voltage levels, the output clock signal can thus alternate between the voltage levels supplied to VDDH buffer 606 in the clock transmission mode or between the voltage levels supplied to VDDL buffer 608 in the clock generation mode.

[0108] The outputs of VDDH buffer 606 and VDDL buffer 608 can be used as internal references for use in clock circuit 602 or generally in slave node 104. The internal reference can be a clock signal. The internal reference can be obtained from the node connecting the outputs of VDDH buffer 606 and VDDL buffer 608, or from the output of level converter circuit 614 or output driver 616 (not shown in the figure).

[0109] Clock circuit 602 can include crystal driver 610, which is implemented by, for example, an inverting operational amplifier. Crystal driver 610 can be enabled or disabled by a control signal (not shown in the figure) from control logic 604. Crystal driver 610 can be configured to receive an input from the CLKIN / XI input terminal and drive the output to a crystal (not shown) connected to the XO output terminal. Although called a "crystal" driver, crystal driver 610 can include any suitable circuit to drive the operation of an oscillator to generate the input clock signal for clock circuit 602 as described below. Thus, crystal driver 610 can receive an input clock signal at its input. Furthermore, crystal driver 610 can thus be configured to provide a signal to the oscillator to drive the oscillator to generate the input clock signal.

[0110] In the clock generation mode, the control logic 604 may issue a low control signal SELCLKDRV. SELCLKDRV may disable the VDDH buffer 606 and, through the inverter 612, enable the VDDL buffer 608. The voltage generated by the crystal driver 610 may drive the crystal and generate a clock signal, which is then received on CLKIN / XI. The clock signal may be routed back to the crystal driver 610, which may continue to drive the crystal to generate the clock signal. At the same time, the VDDH buffer 606 may be disabled and thus not provide an output. Furthermore, at the same time, the VDDL buffer 608 may be enabled, thus reproducing the clock signal received from the crystal on CLKIN / XI. The VDDL buffer 608 may reproduce the clock signal as a value between VDDL and ground. The reproduced clock signal may be sent out on the CLKOUT output and may be used internally within the node as needed. Thus, the clock circuit 602 may cooperate with a crystal or oscillator to generate the input clock signal itself.

[0111] In the clock transmission mode, the control logic 604 may issue SELCLKDRV as a high logic signal. SELCLKDRV may enable the VDDH buffer 606 and, through the inverter 612, disable the VDDL buffer 608. A clock signal from another node may be received on CLKIN / XI. The VDDL buffer 608 may be disabled and thus not provide an output. Furthermore, the VDDH buffer 606 may be enabled, thus reproducing the clock signal received from another node on CLKIN / XI. The VDDH buffer 606 may reproduce the clock signal as a value between VDDH and ground. The regenerated clock signal may be sent out on the CLKOUT output after level conversion by the level converter circuit 614 and driving by the output driver 616, respectively, and may be used internally within the node as needed. Thus, the clock circuit 602 may receive an input clock signal from another node in the network 120.

[0112] In either mode, the clock circuit 602 may be configured to provide the output of the VDDH buffer 606 or the VDDL buffer 608 as a reference for use within the node and, after level conversion by the level converter circuit 614 and driving by the output driver 616, respectively, provide such an output as an output clock signal to a subsequent node in the network 120.

[0113] FIG. 7 is a diagram of method 700 for a slave node to wake up a master node according to an embodiment of the present invention. Method 700 may be performed by any suitable component (e.g., the components shown in FIGS. 1-6). Specifically, method 700 may be performed by an instance of ESC 106. Method 700 can be implemented in, for example, hardware or software. Method 700 may include fewer or more steps than those shown in FIG. 7. Method 700 may start from any suitable step (e.g., step 705). Method 700 may repeat steps, omit steps, perform steps in parallel, or perform steps recursively. Method 700 may optionally repeat or terminate.

[0114] In step 705, the slave node 104 may issue normal traffic. Such normal traffic may include filling EtherCAT frames received for requesting data and transmitting messages to other nodes.

[0115] In step 710, the slave node 104 may observe or determine a condition to wake up the master node 102. For example, the slave node 104 may have data to share with the master node 102 or other slave nodes 104. To transmit such data, the slave node 104 may need to fill EtherCAT frames, however, the master node 102 may be responsible for generating EtherCAT frames and may be in a sleep mode. Therefore, in step 710, the slave node 104 may determine whether there is a condition to wake up the master node 102, and if so, method 700 may proceed to step 715. Otherwise, method 700 may return to step 705.

[0116] In step 715, the slave node 104 may enable a wake-up signal on its output hardware. The wake-up signal may be issued as traffic. The wake-up signal may be transmitted to other slave nodes and ultimately reach the master node 102. The slave node 104 may issue the wake-up signal because the slave node 104 may not know the sleep state of the master node 102. Method 700 may return to step 705.

[0117] FIG. 8 is a diagram of method 800 for a master node to be woken up by a slave node according to an embodiment of the present invention.

[0118] Method 800 can be performed by any suitable component (e.g., the components shown in FIGS. 1-6). Specifically, method 800 can be performed by an instance of the EMC 108 in the primary node 102. Method 800 can be performed in hardware or software, for example. Method 800 can include fewer or more steps than those shown in FIG. 8. Method 800 can start from any suitable step (e.g., step 805). Method 800 can repeat steps, omit steps, perform steps in parallel, or perform steps recursively. Method 800 can optionally repeat or terminate.

[0119] In step 805, the primary node 102 can send out normal traffic. In step 810, it can be determined whether the primary node 102 has encountered a sleep condition for itself alone or generally for the network 120. If so, then method 800 can proceed to step 815; otherwise, method 800 can return to step 805.

[0120] In step 815, the primary node 102 can enter a sleep mode. Additionally, the primary node 102 can send a signal to the slave node 104 to enter a sleep mode. The sleep mode can be partial, where the slave node 104 observes a wake-up condition or performs other operations in the sleep mode.

[0121] In step 820, it can be determined whether the primary node 102 has received a wake-up packet from one or more slave nodes 104. If so, then method 800 can proceed to step 830. Otherwise, method 800 can proceed to step 825.

[0122] In step 825, it can be determined whether the primary node 102 itself has observed a wake-up condition. If so, then method 800 can proceed to step 830. Otherwise, method 800 can return to step 820.

[0123] In step 830, the primary node 102 can wake up its processor and other internal parts. The primary node 102 can send a wake-up signal to the slave node 104 and generate an EtherCAT frame. The EtherCAT frame can contain a wake-up signal. Method 800 can return to step 805.

[0124] FIG. 9 is a diagram of a method 900 for a primary node to wake up a slave node using a flag in network traffic according to a specific example of the present invention.

[0125] Method 900 can be performed by any suitable component (e.g., the components shown in FIGS. 1 to 6). Specifically, method 900 can be performed by an instance of the EMC 108. Method 900 can be performed in hardware or software, for example. Method 900 can include fewer or more steps than those shown in FIG. 9. Method 900 can start from any suitable step (e.g., step 905). Method 900 can repeat steps, omit steps, perform steps in parallel, or perform steps recursively. Method 900 can optionally repeat or terminate.

[0126] In step 905, the primary node 102 can emit traffic with a cleared sleep flag. The cleared sleep flag can indicate to the receiver (the subordinate node 104) to operate in the normal operating mode. In step 910, it can be determined whether a sleep condition has occurred, where the subordinate node 104 is to operate in the sleep mode. If so, then method 900 can proceed to step 915. Otherwise, method 900 can return to step 905.

[0127] In step 915, the primary node 102 can emit traffic (including packets or signals) with a set sleep flag. Receiving this traffic by the subordinate node 104 can cause the subordinate node 104 to enter the sleep mode. Subsequent traffic (if any) will be emitted with the same set sleep flag.

[0128] In step 920, it can be determined whether the primary node 102 is to wake up the subordinate node 104. If not, then method 900 can return to step 915. During the repetition of step 915, it may not be necessary to transmit subsequent traffic with a set sleep flag again. If the primary node 102 is to wake up the subordinate node, then method 900 can return to step 905, where traffic with a cleared sleep flag can be emitted.

[0129] FIG. 10 is an illustration of a method 1000 for a subordinate node to be woken up by a flag in network traffic used by a primary node according to a specific example of the present invention.

[0130] Method 1000 can be performed by any suitable component (e.g., the components shown in FIGS. 1-6). Specifically, method 1000 can be performed by an instance of ESC 106 in slave node 104. Method 1000 can be performed in hardware or software, for example. Method 1000 can include fewer or more steps than shown in FIG. 10. Method 1000 can start from any suitable step (e.g., step 1005). Method 1000 can repeat steps, omit steps, perform steps in parallel, or perform steps recursively. Method 1000 can optionally repeat or terminate.

[0131] In step 1005, slave node 104 can normally send out traffic in response to and forwarding EtherCAT packets. In step 1010, it can be determined whether slave node 104 is to enter the sleep mode. This determination can be made by observing the input or conditions of slave node 104. If slave node 104 is to enter the sleep mode, then method 1000 can proceed to step 1020. Otherwise, method 1000 can proceed to step 1015. In step 1015, it can be determined whether a packet with a set sleep mode flag has been received from another node (from master node 102). If so, then method 1000 can proceed to step 1020. Otherwise, method 1000 can return to step 1005.

[0132] In step 1020, slave node 104 can enter the sleep mode. In step 1025, it can be determined whether traffic with a cleared sleep flag has been received. If so, then method 1000 can proceed to step 1035. Otherwise, method 1000 can proceed to step 1030. In step 1030, it can be determined whether a local wake-up condition has been observed. If so, then method 1000 can proceed to step 1035. Otherwise, method 1000 can return to step 1025.

[0133] In step 1035, slave node 104 can wake up its processor and other components and enter the normal operation mode. Method 1000 can return to step 1005.

[0134] FIG. 11 is a diagram of method 1100 for a master node to wake up a slave node using a WoL packet according to a specific example of the present invention.

[0135] Method 1100 can be executed by any suitable component (e.g., the components shown in FIGS. 1 to 6). Specifically, method 1100 can be executed by an instance of the EMC 108 in the primary node 102. Method 1100 can be executed in hardware or software, for example. Method 1100 can include fewer or more steps than those shown in FIG. 11. Method 1100 can start from any suitable step (e.g., step 1105). Method 1100 can repeat steps, omit steps, execute steps in parallel, or execute steps recursively. Method 1100 can optionally repeat or terminate.

[0136] In step 1105, the primary node 102 can send normal traffic to the subordinate node 104 as needed. However, there may be a long time between traffic, such that the subordinate node 104 can be in a dormant node. In step 1110, it can be determined whether to wake up the subordinate node 104. If so, method 1100 can proceed to step 1115. Otherwise, method 1100 can return to step 1105. In step 1115, a WoL packet can be sent to the subordinate node 104. Method 1100 can return to step 1105.

[0137] FIGS. 12A to 12F are diagrams of method 1200 for a subordinate node to be woken up by a primary node using a WoL packet in a specific example of the present invention.

[0138] Method 1200 can be executed by any suitable component (e.g., the components shown in FIGS. 1 to 6). Specifically, method 1200 can be executed by an instance of the ESC 106 in the subordinate node 104. Method 1200 can be executed in hardware or software, for example. Method 1200 can include fewer or more steps than those shown in FIG. 12. Method 1200 can start from any suitable step (e.g., step 1205). Method 1200 can repeat steps, omit steps, execute steps in parallel, or execute steps recursively. Method 1200 can optionally repeat or terminate.

[0139] In FIG. 12A, in step 1205, the subordinate node 104 can normally send traffic. In step 1210, it can be determined whether the subordinate node 104 is to enter the sleep mode. If so, method 1200 can proceed to step 1215, otherwise return to step 1205.

[0140] In step 1215, the slave node 104 can enter the sleep mode. In step 1220A, it can be determined whether a WoL packet has arrived. Step 1220A can be implemented in any suitable manner. FIGS. 12B to 12F illustrate exemplary implementations of step 1220A within the scope of the same steps performed in other ways in method 1200. For example, in FIG. 12B, in step 1220B, if the received packet is a broadcast packet, it can be determined that the WoL packet has arrived. In FIG. 12C, in step 1220C, if the received packet contains a predetermined value, it can be determined that the WoL packet has arrived. In FIG. 12D, in step 1220D, if the received packet contains the address of the device, it can be determined that the WoL packet has arrived. In FIG. 12E, in step 1220E, if the received packet contains the address of another different device, it can be determined that the WoL packet has arrived. In FIG. 12F, in step 1220F, if the received packet includes the address of the master node, it can be determined that the WoL packet has arrived.

[0141] If it has been determined that the WoL packet has arrived by any one of steps 1220A to F, then method 1200 can proceed to step 1230. Otherwise, method 1200 can proceed to step 1225. In step 1225, it can be determined whether a local wake-up condition has been observed at the slave node. If so, then method 1200 can proceed to step 1230. Otherwise, method 1200 can return to step 1220.

[0142] In step 1230, the processor of the slave node 104 together with other parts of the slave node 104 can be awakened. The normal operation mode can be entered, and method 1200 can return to step 1205.

[0143] FIG. 13 is a diagram of method 1300 for a node to execute a clock signal daisy chain according to an embodiment of the present invention.

[0144] Method 1300 can be executed by any suitable component (e.g., the components shown in FIGS. 1 to 6). Specifically, method 1300 can be executed by an instance of the clock circuit 602 in the respective ESC 106 or EMC 108 within the slave node 104 or the master node 102. Method 1300 can be executed in, for example, hardware or software. Method 1300 can include fewer or more steps than those shown in FIG. 13. Method 1300 can start from any suitable step (e.g., step 1305). Method 1300 can repeat steps, omit steps, execute steps in parallel, or execute steps recursively. Method 1300 can optionally repeat or terminate.

[0145] In step 1305, the clock setting of the node can be determined, for example, by reading a value from a register. The clock setting can determine whether to use a local oscillator, crystal, or other clock pulse source, or whether to use a clock pulse source from another node.

[0146] In step 1310, in response to the determination in step 1305, it can be determined whether to use a local crystal as the clock signal. If so, method 1300 can proceed to step 1315. Otherwise, method 1300 can proceed to step 1335.

[0147] In step 1315, a control signal can be issued to enable a crystal driver such as driver 610 and a first clock regeneration circuit such as VDDL buffer 608. The control signal can disable a second clock regeneration circuit such as VDDH buffer 606. The control signal can be issued by control logic 604. In step 1320, the clock input for the node can be routed to crystal driver 610 and the first clock regeneration circuit. In step 1325, the output of the crystal driver can be routed to the input of the crystal. The output of the crystal can be routed to the clock input of the node. In step 1330, the output of the first clock regeneration circuit can be routed to the clock output of the next node in the daisy chain and used as the internal clock reference for the node.

[0148] In step 1335, a control signal can be issued to disable the first clock regeneration circuit. The control signal can enable the second clock regeneration circuit. The control signal can be issued by control logic 604. In step 1340, the clock input of the node can be routed to the second clock regeneration circuit. In step 1345, the output of the second clock regeneration circuit can be routed to the clock output of the next node in the daisy chain and used as the internal clock reference for the node.

[0149] FIG. 14 is a diagram of method 1400 for a node to perform an assessment of the quality of a received signal according to an embodiment of the present invention.

[0150] Method 1400 can be performed by any suitable component (e.g., the components shown in FIGS. 1-6). Specifically, method 1400 can be performed by an example of the degradation circuit 502 in the ESC 106 or the EMC 108. Method 1400 can be performed in hardware or software, for example. Method 1400 can include fewer or more steps than those shown in FIG. 14. Method 1400 can start from any suitable step (e.g., step 1405). Method 1400 can repeat steps, omit steps, perform steps in parallel, or perform steps recursively. Method 1400 can optionally repeat or terminate.

[0151] In step 1405, data input to the node can be read. The data can be one of a plurality of logical values, e.g., -1, 0, and +1. In step 1410, the input can be demodulated, converted to the digital domain, and processed into bit slices, where the input value at each time point can appear in one of the bit slices within the defined range of the bit slices. In step 1415, the difference between the bit slice of the input at each time point and other reference bit slices can be determined. The reference bit slices can be, for example, bit slices representing ideal values corresponding to logical values. In step 1420, the differences can be used to identify the expected logical value of the input data. In step 1425, those differences and the expected logical values can be used to determine the quantization of the error at a given time point of the input. In step 1430, in view of such previous quantization of the error at previous time points, the quantization of the error at the given time point can be used to determine the mean square error. In step 1435, using the determined error, the SQI characteristics of the data can be queried within various ranges of the look-up table. According to the SQI characteristics, if the quality of the received input data is poor enough, an alarm can be issued or corrective measures can be taken.

[0152] Although the exemplary embodiments have been described above, other variations and embodiments can be made in accordance with the present invention without departing from the spirit and scope of these embodiments.

[0153] This application claims the priority of Indian Provisional Patent Application Serial No. 201911043952 filed on October 30, 2019, the entire content of which is incorporated herein by reference.

[0154] 100: (Network) System / Network 102: (Main) Node 102A: (Main) Node 102B: (Main) Node 102C: (Main) Node 104: (Slave) Node 104A: (Slave) Node 104B: (Slave) Node 104C: (Slave) Node 104D: (Slave) Node 104E: (Slave) Node 104F: (Slave) Node 104G: (Slave) Node 104H: (Slave) Node 104I: (Slave) Node 106: EtherCAT Slave Circuit (ESC) 106A: EtherCAT Slave Circuit (ESC) 106B: EtherCAT Slave Circuit (ESC) 108: EtherCAT Master Circuit (EMC) 110: Crystal 112: Processor 112A: Processor 112B: Processor 112C: Processor 114: Memory 114A: Memory 114B: Memory 114C: Memory 118: Application 120: Network / (Network) Device / (Network) System 120A: Network 120B: Network 120C: Network 202: Communication Circuit 204: Wake-up Circuit 205: Multiplexer 206: Application 208: Sensor 210: User Interface (UI) 212: Timer 214: Network Interface Card (NIC) 302: Network Interface Card (NIC) 304: Peripheral Device 306: Power Controller 320: Communication Circuit 322: Wake-up Circuit 324: Sensor 326: User Interface (UI) 328: Timer 402: Wake-on-LAN (WoL) Circuit 502: Degradation Circuit 504: Demodulator / Analog-to-Digital Converter (ADC) / Digital Signal Processor (DSP) 506: Mean Squared Error (MSE) Circuit 508: Look-Up Table (LUT) 510: Error Register 602: Clock Circuit 604: Control Logic 606: (VDDH) Buffer 608: (VDDL) Buffer 610: (Crystal) Driver 612: Inverter 614: Level Converter Circuit 616: Output Driver 700: (Slave Node Wakes up Master Node) Method 705, 710, 715: (Method) Steps 800: (Master Node is Woken up by Slave Node) Method 805, 810, 815, 820, 825, 830: (Method) Steps 900: (Master Node Wakes up Slave Node) Method 905, 910, 915, 920: (Method) Steps 1000: (Slave Node is Woken up by Master Node) Method 1005, 1010, 1015, 1020, 1025, 1030, 1035: Method (Steps) 1100: (Master Node Wakes up Slave Node) Method 1105, 1110, 1115: (Method) Steps 1200: (Slave Node is Woken up by Master Node) Method 1205, 1210, 1215, 1220A, 1220B, 1220C, 1220D, 1220E, 1220F, 1225, 1230: (Method) Steps 1300: (Execute Clock Signal Daisy Chain) Method 1305, 1310, 1315, 1320, 1325, 1330, 1335, 1340, 1345: (Method) steps 1400: (Signal quality assessment) method 1405, 1410, 1415, 1420, 1425, 1430, 1435: (Method) steps CLKIN: Clock signal input (port) CLKOUT: Clock signal output (port) DI: Data input (port) DO: Data output (port) SELCLKDRV: (Clock generation / transmission) control signal XI: Crystal input (port) XO: Crystal output (port)

Claims

1. An EtherCAT device used as a node in an EtherCAT network, the EtherCAT device comprising: A clock circuit; A clock input terminal is used to receive an input clock signal; A clock output terminal is used to transmit an output clock signal; The system also includes control logic for: determining whether the EtherCAT device is operating in a clock generation mode or a clock transmission mode, wherein: in the clock generation mode, the clock circuit drives an oscillator to generate the input clock signal; and in the clock transmission mode, the clock circuit receives the input clock signal from another node in the EtherCAT network; and controlling the clock circuit to transmit the output clock signal at its clock output terminal for use by a subsequent node in the EtherCAT network, the output clock signal being based on the input clock signal.

2. The EtherCAT device as described in request item 1, wherein, The clock circuit includes at least one clock regeneration circuit for receiving the input clock signal and generating the output clock signal from the input clock signal, the output clock signal alternating between a first voltage level and a second voltage level supplied to the at least one clock regeneration circuit.

3. The EtherCAT device as described in request item 1, wherein, The clock circuit includes a first clock regeneration circuit for receiving the input clock signal and generating a first output; the clock circuit includes a second clock regeneration circuit for receiving the input clock signal and generating a second output; and the control logic is used to output the output clock signal at the clock output terminal based on the first output of the first clock regeneration circuit or the second output of the second clock regeneration circuit, depending on whether the EtherCAT device is in the clock generation mode or the clock transmission mode.

4. The EtherCAT device as described in request item 1, wherein, The clock circuit includes a crystal driver for providing a signal to the oscillator in the clock generation mode to drive the oscillator to generate the input clock signal; and the clock circuit for routing the input clock signal to one of the input terminals of the crystal driver in the clock generation mode.

5. A network communication method, comprising: Receive an input clock signal via a clock input terminal; A clock signal is transmitted via a clock output terminal; Based on the input clock signal, the method outputs the output clock signal for use by a subsequent node in an EtherCAT network; and determines whether to operate an EtherCAT device in the EtherCAT network in a clock generation mode or a clock transmission mode, wherein: in the clock generation mode, the method includes driving an oscillator to generate the input clock signal; and in the clock transmission mode, the method includes receiving the input clock signal from another node in the EtherCAT network.

6. An EtherCAT device, comprising: A data input port is used to receive a signal representing data, which represents one of a plurality of possible discrete logic values; And a degradation calculation circuit for: reading, demodulating, and converting the received signal into a digital domain representation; processing the digital domain representation into bit slices, wherein the value of the signal received at an individual time point is represented in an individual bit slice of the bit slices; determining the difference between the individual bit slices and a reference bit slice; in response to the determined difference, identifying an expected discrete logic value of the received signal; in response to the identified discrete logic value and the determined difference, determining the quantization of an error at an individual time point; and in response to the determined quantization of the error, determining a signal quality index (SQI).

7. The EtherCAT device as described in request item 6, wherein, This degradation calculation circuit is used to normalize the representation of the bit field within a given range.

8. The EtherCAT device as described in request item 6, wherein, This degradation calculation circuit is used to determine the quantification of the error at individual time points using mean square error calculation.

9. The EtherCAT device as described in request item 6, wherein, The degradation calculation circuit uses the quantization of the determined error to determine the SQI characteristics of the data.

10. The EtherCAT device as described in claim 9, wherein, The degradation calculation circuit determines the SQI characteristics of the data from a lookup table.

11. The EtherCAT device as described in request item 9, wherein, If the quality of the received data is sufficiently poor based on these SQI characteristics, the degradation calculation circuit provides an alarm or a correction measure.

12. A network communication method, comprising: Receive a signal representing data, which represents one of a plurality of possible discrete logic values; The received signal is read, demodulated, and converted into a digital domain representation; the digital domain representation is processed into bit slices, wherein the value of the signal received at an individual time point is represented in individual bit slices of these bit slices; the difference between these individual bit slices and a reference bit slice is determined; in response to the determined difference, an expected discrete logic value of the received signal is identified; in response to the identified discrete logic value and the determined difference, the quantization of an error at an individual time point is determined; and in response to the determined quantization of the error, a signal quality index (SQI) is determined.

13. The network communication method of claim 12 includes normalizing the representation of the bit field within a given range.

14. The network communication method as described in request item 12 includes using mean square error calculation to determine the quantification of the error at individual time points.

15. The network communication method of claim 12 includes using the quantization of the determined error to determine the SQI characteristics of the data.

16. The network communication method of claim 15 includes determining the SQI characteristics of the data from a lookup table.

17. The network communication method of request item 15 includes providing an alarm or a corrective measure if the quality of the received data is sufficiently poor based on the SQI characteristics.

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