Semiconductor device

Abstract

The semiconductor device of the present invention includes: a gallium oxide crystal substrate having a recess extending substantially perpendicularly to a (001) surface in a region other than the outer edge; a first electrode layer disposed in contact with the (001) surface of the gallium oxide crystal substrate; and a second electrode layer disposed in contact with a surface opposite to the (001) surface of the gallium oxide crystal substrate.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Prior Technology

[0002] Patent document 1 discloses a semiconductor device.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-141004

[0004] As a next-generation switching element capable of achieving high voltage withstand, low loss, and high heat resistance, semiconductor devices using gallium oxide (Ga2O3) with a large band gap have attracted much attention and are expected to be applied to power semiconductor devices such as inverters. Patent Document 1 discloses a technique for miniaturizing semiconductor devices with a gallium oxide substrate while suppressing the interference of crystal defects on the diode interface. Summary of the Invention

[0005] In an embodiment of the present invention, a semiconductor device is provided, comprising: a gallium oxide crystal substrate having a recess extending substantially perpendicularly to a (001) surface in a region other than the outer edge; a first electrode layer disposed in contact with the (001) surface of the gallium oxide crystal substrate; and a second electrode layer disposed in contact with a surface opposite to the (001) surface of the gallium oxide crystal substrate.

[0006] Furthermore, the above summary of the invention does not encompass all features of the invention. Any combination of these features may also constitute the invention. Simple Explanation of the Diagram

[0007] Figure 1 is a diagram simulating the appearance of the anode side of the semiconductor device of Embodiment 1. Figure 2 is a schematic cross-sectional view of the semiconductor device of Example 1. Figure 3 is a diagram of the appearance of the anode side of the semiconductor device in Example 2. Figure 4 is a schematic cross-sectional view of the semiconductor device of Example 2. Figure 5 is a schematic cross-sectional view of the semiconductor device of Example 3. Figure 6 is a diagram that mimics the appearance of a wafer used in the manufacture of existing semiconductor devices. Figure 7 is a diagram that mimics the appearance of the anode side of a conventional semiconductor device. Figure 8 is a schematic diagram of a cross-section of a prior art semiconductor device. Figure 9 is a microscope image of a cut gallium oxide crystal substrate in an existing example. Implementation

[0008] The present invention is described below through embodiments, and these embodiments are not intended to limit the scope of the invention as described in the appendix.

[0009] Furthermore, not all of the feature combinations described in the embodiments of the invention are necessary for the solution of the invention.

[0010] Furthermore, the semiconductor device of the present invention is conceived to be of a size visible to the naked eye. Therefore, the wave motion of electrons, which plays a crucial role in the semiconductor device, is sufficiently extended within the semiconductor device. Electrons are reflected on the inner side of the semiconductor substrate, i.e., the inner surface of the semiconductor substrate. The wave motion of electrons extends to the outer side of the semiconductor substrate, i.e., the outer surface of the semiconductor substrate.

[0011] In describing embodiments of the invention, sometimes the crystal planes of the semiconductor crystal substrate are used. Even in such cases, in the actual manufactured semiconductor crystal substrate, some or all of it may not be composed solely of strictly defined crystal planes. This is because sometimes an offset angle is intentionally set to improve productivity, thereby forming a plane that deviates slightly from the ideal plane. In addition, due to limited processing precision, it is sometimes inherently difficult to obtain an ideal crystal plane.

[0012] For example, even if a part of a semiconductor crystal substrate is processed to obtain the (100) surface of the semiconductor crystal substrate, it is not necessarily true that only an ideal flat plane will appear. Due to the formation of unevenness, sometimes a surface other than the (100) surface will appear at the processed part.

[0013] Therefore, even if the embodiment of the invention is described using the crystal plane of a semiconductor substrate, the crystal plane is sometimes merely ideal.

[0014] This also applies to the crystal axis of a semiconductor crystal substrate.

[0015] Furthermore, the accompanying drawings used in the following description are schematic, and the dimensional relationships and ratios of the elements in the drawings may not necessarily match those in reality. Additionally, the dimensional relationships and ratios of elements may not be consistent across multiple drawings.

[0016] Figure 1 schematically shows the appearance of the semiconductor device 100 according to Embodiment 1 of the present invention as viewed from the anode side. Figure 2 schematically shows a cross-section of the semiconductor device 100 according to Embodiment 1 of the present invention along AA shown in Figure 1. Unless otherwise stated, the external structure of the semiconductor device 100 shown in Figure 1 may be bilaterally symmetrical or vertically symmetrical. The cross-sectional structure of the semiconductor device 100 shown in Figure 2 is bilaterally symmetrical.

[0017] This symmetry also applies to Embodiments 2, 3, and the prior art embodiments shown below.

[0018] The semiconductor device 100 includes: a gallium oxide crystal substrate 200 having a recess 700 extending substantially perpendicularly to the (001) surface in a region other than the outer edge; a first electrode layer 310 disposed in contact with the (001) surface of the gallium oxide crystal substrate 200; and a second electrode layer 410 disposed in contact with the opposite surface of the (001) surface of the gallium oxide crystal substrate 200.

[0019] The semiconductor device 100 has an electrode layer 310 that serves as a positive electrode for electrical connection with the outside and an electrode layer 410 that serves as a negative electrode.

[0020] Semiconductor device 100 corresponds to the semiconductor device described in the summary section of this invention. Gallium oxide crystal substrate 200 corresponds to the gallium oxide crystal substrate described in the embodiments in the overview section of the invention. Electrode layer 310 corresponds to the first electrode layer described in the summary section of the invention. Electrode layer 410 corresponds to the second electrode layer described in the summary section of this invention.

[0021] The recess can be formed by a recess extending along the

[0100] direction of the gallium oxide crystal substrate.

[0022] Furthermore, the recess may be formed by a recess extending along the

[0010] direction of the gallium oxide crystal substrate.

[0023] As described above, the gallium oxide crystal substrate 200 has recesses 700 extending substantially perpendicular to the (001) plane. As shown in FIG1, the bottom surface 205 of the recesses 700 can be seen from the anode side. As shown in FIG1, in the recesses 700, two extend along the

[0100] direction of the gallium oxide crystal substrate 200, two extend along the

[0010] direction of the gallium oxide crystal substrate 200, and these recesses are intersected and connected to each other at four locations.

[0024] Therefore, in the case of Embodiment 1 where the depth of the recess 700 is the same, as shown in FIG1, when viewed from the anode side, the bottom surface 205 of the recess becomes a shape similar to the # mark.

[0025] The depth of the recess can be approximately 60% to 95% of the thickness of the gallium oxide crystal substrate in the

[0001] direction.

[0026] As shown in Figure 2, the depth of the recess 700 is approximately 60% of the thickness of the gallium oxide crystal substrate in the

[0001] direction. During manufacturing, the depth of the recess 700 can be increased to approximately 95% of the thickness of the gallium oxide crystal substrate in the

[0001] direction.

[0027] Gallium oxide crystal substrates can be composed of N-type conductive gallium oxide crystal substrates.

[0028] Example 1: The gallium oxide crystal substrate 200 has a β-type crystal structure and N-type conductivity.

[0029] Furthermore, the gallium oxide crystal substrate can be formed from two or more N-type conductive gallium oxide crystal substrates with different electrical conductivities.

[0030] In Example 1, the gallium oxide crystal substrate 200 is composed of two N-type gallium oxide crystal substrates with different electrical conductivities. The N-type N-gallium oxide crystal substrate 211 with low conductivity and the electrode layer 310 are chemically bonded at their interface and in contact with each other. The N-type N+gallium oxide crystal substrate 220 with high conductivity and the electrode layer 410 are chemically bonded at their interface and in contact with each other.

[0031] The N-type gallium oxide crystal substrates 210 and 211, which have low conductivity, originally formed a single crystal substrate and thus have the same conductivity, but are separated from each other by providing the recess 700. Although not shown in Figure 2, the gallium oxide crystal substrate located on the anode side at the left end is the numbered N-gallium oxide crystal substrate 210. This is also true for Embodiments 2 and 3.

[0032] When the gallium oxide crystal substrate is composed of two or more N-type conductive gallium oxide crystal substrates with different conductivity, all (001) surfaces appearing at the bottom of the recess can be composed of (001) surfaces of gallium oxide crystal substrates that are not in contact with the first electrode layer.

[0033] The gallium oxide crystal substrate 200 is formed of N-type N-gallium oxide crystal substrates 210 and 211 and N+gallium oxide crystal substrate 220 with different conductivity, and all (001) surfaces exposed in the bottom of the recess 700 are N+gallium oxide crystal substrates 220 that are not in contact with the electrode layer 310 (for example, the (001) surface appearing at the bottom of the recess 700 is the bottom surface 205 of the recess shown in FIG1).

[0034] The first electrode layer or the second electrode layer may be composed of two or more metal layers with different constituent elements.

[0035] At least one of the first electrode layers or the second electrode layer is composed of any one of titanium, nickel, silver and gold, or has any one of titanium, nickel, silver and gold, or a combination of these layers.

[0036] This is because by making the electrode layer this structure, an ohmic connection can be easily formed between the gallium oxide single crystal and the electrode layer.

[0037] At least one of the first electrode layer or the second electrode layer is a layer composed of any one of nickel, aluminum, gold and titanium, or a layer composed of any combination of nickel, aluminum, gold and titanium, or a combination thereof.

[0038] This is because by making the electrode layer this structure, a Schottky barrier can be easily formed between the gallium oxide single crystal and the electrode layer.

[0039] The electrode layer 310 is connected via a process that allows it to be chemically coupled to the N-type gallium oxide crystal substrate 200. Sputtering is typically used for such a process. Depending on the sputtering process conditions and post-processing conditions, a Schottky barrier or an ohmic connection can be formed between the electrode portion 310 and the N-type gallium oxide crystal substrate 200.

[0040] As an example, the thickness of the electrode portion 310 is several hundred nm.

[0041] The electrode layer 310 can be formed by electron beam evaporation. This is because it avoids plasma damage to the gallium oxide crystal substrate 200 that may occur when using sputtering.

[0042] In Embodiment 1 of the present invention, a process for forming a Schottky barrier between the electrode layer 310 and the N-type gallium oxide crystal substrate 200 was used. In Embodiment 1, nickel metal was used as the sputtering material.

[0043] Similarly, the electrode layer 410 is connected via a process that allows it to be chemically coupled to the N-type gallium oxide crystal substrate 200. Sputtering is typically used for such a process. Depending on the sputtering process conditions and post-processing conditions, a Schottky barrier or an ohmic connection can be formed between the electrode layer 410 and the N-type gallium oxide crystal substrate 200.

[0044] As an example, the electrode portion 410 has a thickness of several hundred nm.

[0045] In Embodiment 1 of the present invention, a process is used to form an ohmic connection between the electrode layer 410 and the N-type gallium oxide crystal substrate 200.

[0046] In Example 1, titanium metal was used as the sputtering material.

[0047] Gallium oxide crystal substrate 200 is manufactured by processing an N-type gallium oxide crystal substrate, which has a generally circular wafer shape when viewed from the direction in which the electrode layer 310 or the electrode layer 410 is formed.

[0048] For ease of explanation, a conventional semiconductor device 150 will be described here. FIG6 shows an example of the appearance of a gallium oxide wafer 500 used in the manufacture of the conventional semiconductor device 150 after the electrode layer 310 composed of a metal film has been formed and before cutting. The double-dotted line in FIG6 is an imaginary line serving as a dividing line reference.

[0049] Figure 7 schematically shows the appearance of a conventional semiconductor device 150 manufactured by dicing a gallium oxide wafer 500, viewed from the anode side. Figure 8 is a cross-section schematically showing the conventional semiconductor device 150 along line AA of Figure 7. As shown in Figure 8, crystal defects 600, indicated by ×, are easily generated on and near the side of the semiconductor device 150 that appears through dicing.

[0050] Figure 9 shows a micrograph of an example of a crack appearing in the area enclosed by the dashed circle. This crack sometimes occurs, for example, during cutting. Although the cutting-induced crack shown in Figure 9 appears to extend about 30 μm from the side of the gallium oxide crystal substrate in the

[0010] direction, it is easy to imagine the existence of fine, long cutting-induced cracks, etc., that are not shown in this micrograph. Even such fine, long cutting-induced cracks can reliably affect the electrical characteristics of semiconductor devices.

[0051] Therefore, as an example of a problem, when the gallium oxide crystal substrate constituting a semiconductor device is formed by dicing gallium oxide wafers, it is necessary to minimize the cracks and crystal defects remaining in the gallium oxide crystal substrate. This problem is particularly concerning for gallium oxide crystals, which are more brittle than other semiconductor materials such as silicon. It should be noted that since semiconductor device manufacturing processes can take various forms, the causes of cracks and crystal defects remaining in the gallium oxide crystal substrate are not limited to the dicing of gallium oxide wafers.

[0052] Figure 6 illustrates a layout with five semiconductor devices 150. The substrate thickness is approximately 0.6 mm. Several representative methods are known for manufacturing N-type gallium oxide crystal substrates. Gallium oxide crystal substrates 250 composed of multiple layers with different electrical conductivity can also be obtained. Detailed descriptions of these manufacturing methods are omitted here.

[0053] The gallium oxide crystal substrate 250 is composed of an N-gallium oxide crystal substrate 260 with low conductivity and an N+gallium oxide crystal substrate 270 with high conductivity.

[0054] For example, the approximate active donor concentrations of the silicon-doped N-gallium oxide crystal substrate 260 and N+gallium oxide crystal substrate 270 are 2 × 10¹⁶ cm⁻³ and 1 × 10¹⁹ cm⁻³, respectively. The thickness of the N-gallium oxide crystal substrate 260 is approximately 10 μm. The thickness of the N+gallium oxide crystal substrate 270 is approximately 600 μm.

[0055] For example, the area of ​​the electrode portion 310 formed on the wafer of the N-type gallium oxide crystal substrate 250 cut from the wafer state by cutting is 4×4 mm2.

[0056] Similarly, in Embodiments 1, 2, and 3 of the present invention, the thickness of each crystal substrate, the impurity concentration, and the area of ​​the electrode portion are also the same.

[0057] In Embodiment 1 of the present invention, unlike the prior art described above, as stated above, a recess 700 is provided in the gallium oxide crystal substrate 200 before dicing the gallium oxide wafer. The principle of the recess 700 is the same as that of the dry or wet etching process used in the manufacturing of silicon semiconductor devices.

[0058] Dry etching is superior to wet etching in order to improve processing accuracy, but it will increase the process cost.

[0059] As an example, in a dry etching process, boron trichloride (BCl3) gas is used for etching. The etching rate of gallium oxide single crystals varies greatly depending on factors such as ICP (Inductively Coupled Plasma) power, process pressure, gas flow rate, bias power, and the equipment used. The etching rate differs when using reactive gases other than boron trichloride.

[0060] As an example, when using an ICP dry etching apparatus, let's assume the ICP power is 200W, the processing pressure is 600Pa, the argon (Ar) gas flow rate is 30sccm, and the chlorine (Cl2) gas flow rate is 30sccm. In this case, the etching rate of gallium oxide single crystal is approximately 2nm / s. Alternatively, by changing the ICP power and other process conditions, the etching rate of gallium oxide single crystal can be set to approximately 300nm.

[0061] As an example, in the case of a wet etching process, hydrofluoric acid (HF) is used for etching.

[0062] As an example, when using 45% by mass hydrofluoric acid at room temperature, the etching rate of the (001) facet of a gallium oxide single crystal is approximately 60 nm / h. The etching rate increases with increasing hydrofluoric acid concentration or temperature.

[0063] As an example, the width of the recess 700 shown in Figure 2 in the gallium oxide crystal substrate 200 is approximately 40 μm.

[0064] As an example, the depth of the recess 700 shown in Figure 2 in the gallium oxide crystal substrate 200 is approximately 12 μm.

[0065] As an example, the recess 700 shown in FIG2, which is provided in the gallium oxide crystal substrate 200, is set to be about 50 μm away from the peripheral portion of the gallium oxide crystal substrate 200.

[0066] Due to limited processing precision, the shape of the recess 700 within the semiconductor device 100 is not necessarily uniform, nor is it necessarily composed of an ideal flat plane.

[0067] As an example, in the appearance of the semiconductor device 100 shown in Figure 1, the bottom surface 205 of the recess 700 appears to be straight when viewed from the anode side, but in reality it may sometimes be curved. Therefore, when viewed from the anode side, the shape of the bottom surface 205 of the recess 700 may not be straight.

[0068] As an example, the cross-section of the recess 700 in the semiconductor device 100 shown in Figure 2 is not necessarily straight. This is also true for embodiments 2 and 3 of the present invention.

[0069] Regardless of whether a dry etching process or a wet etching process is chosen, the recesses 700 shown in Example 1 act as a protective barrier against the diffusion of crystal defects. Therefore, crystal defects 600 and 610 (indicated by ×) are easily generated on and near the sides of the semiconductor device 100 formed by cutting, but crystal defects are difficult to generate in the area sandwiched between the electrode layers 310 and 410, which are crucial to the operation of the semiconductor device 100. Therefore, the manufacturing yield can be improved in the semiconductor device manufacturing process. Furthermore, the manufacturing cost of the semiconductor device can be reduced.

[0070] Furthermore, it can be assumed that if the semiconductor device 100 operates, crystal defects become more likely to grow as it heats up. Therefore, it is also conceivable that crystal defects caused by dicing grow during the operation of the semiconductor device 100.

[0071] However, by providing the recess 700, the growth of cracks around the gallium oxide crystal substrate, which could lead to semiconductor device malfunction, can be easily prevented. This preventative effect is particularly effective when the semiconductor device 100 is used as a power semiconductor, as heat generation increases.

[0072] Furthermore, the

[0100] axis and

[0001] axis of the gallium oxide crystal form an angle of 103.7° instead of 90°. The difference between 90° and 103.7° is 13.7°. Therefore, it is sometimes difficult to provide a recess 700 that extends at 90° relative to the surface of the gallium oxide crystal substrate 200 (001).

[0073] The recess can be a recess that extends along the

[0100] direction of gallium oxide.

[0074] Sometimes, semiconductor devices 100 are manufactured by cutting them from a wafer. In this case, by providing a recess 700 extending in the

[0100] direction in the gallium oxide crystal substrate 200, the growth of crystal defects in a specific direction can be easily suppressed. That is, it is possible to easily suppress the growth of crystal defects generated at the periphery of the semiconductor device 100 due to cutting in the

[0010] direction or the opposite direction. Furthermore, it is possible to easily suppress the effect of causing semiconductor device failure.

[0075] Similarly, the recess can be a recess that extends along the

[0010] direction of gallium oxide.

[0076] Sometimes, semiconductor devices 100 are manufactured by cutting them from a wafer. In this case, by providing a recess 700 extending in the

[0010] direction in the gallium oxide crystal substrate 200, the growth of crystal defects in a specific direction can be easily suppressed. That is, it is possible to easily suppress the growth of crystal defects generated at the periphery of the semiconductor device 100 due to cutting in the

[0100] direction or the opposite direction. Furthermore, it is possible to easily suppress the effect of causing semiconductor device failure.

[0077] The depth of the recess can be approximately 60% to 95% of the thickness of the gallium oxide in the

[0001] direction.

[0078] In Example 1, the recess 700 is provided in the N+ gallium oxide crystal substrate 220. Therefore, it is possible to easily suppress the generation and growth of crystal defects in the N- gallium oxide crystal substrate 211. Crystal defects present in the N- gallium oxide crystal substrate 211 lead to an increase in the so-called leakage current of the semiconductor device 100. Therefore, by making the depth of the recess 700 approximately 60% to 95% or more of the thickness of gallium oxide in the

[0001] direction, and by ensuring that the crystal defects on and near the side of the semiconductor substrate generated by cutting are uniformly distributed in the depth direction, a new effect can be achieved that makes it easier to reduce the leakage current to less than 50%.

[0079] In the case of manufacturing by cutting semiconductor substrates from wafers, most of the crystal defects generated around the semiconductor substrate by cutting are widely distributed in the thickness direction of gallium oxide in the

[0001] direction. By making the depth of the recess 700 approximately 60% to 95% of the thickness of gallium oxide in the

[0001] direction, the total amount of crystal defects generated by cutting can be reduced to less than half, and it is expected that the impact on electrical properties can be reduced to less than 50%.

[0080] In addition, regarding the (100), (010), and (001) planes of gallium oxide crystals, the (100) plane is the easiest to cleave, followed by the (001) plane.

[0081] Therefore, as described above, by providing a recess 700 extending approximately perpendicular to the (001) plane in the

[0100] and

[0010] directions from the view of the electrode layer in the gallium oxide crystal substrate 200, the generation and growth of crystal defects can be suppressed to the greatest extent.

[0082] On the other hand, since the recess 700 increases the area occupied by the semiconductor device 100 in the gallium oxide wafer, in addition to the process cost of setting the recess, the productivity decreases. Furthermore, because gallium oxide crystals are inherently more brittle than other semiconductor materials such as silicon, setting the recess 700 itself presents a challenge. However, according to the effects produced by the present invention, a significant increase in the final yield of the semiconductor device is expected to lead to an increase in productivity. In addition, a significant increase in the characteristic yield of the final semiconductor device is expected to further improve productivity.

[0083] As in Example 1, the gallium oxide crystal substrate can have N-type conductivity. Because the technology for manufacturing gallium oxide wafer substrates with N-type conductivity is being developed, it is relatively easy to obtain wafer substrates with optimized thickness and impurity concentration in order to suppress the heat generation of semiconductor devices as much as possible.

[0084] Furthermore, the effects of the present invention are further amplified if a wafer substrate that minimizes heat generation, a cause of crystal defect growth, is used.

[0085] Furthermore, as in Example 1, the gallium oxide crystal substrate can have two or more N-type conductors, each with a different conductivity.

[0086] This is because, compared to the case where the conductivity is only 1, a further optimized gallium oxide wafer substrate can be obtained in order to suppress the heat generation of the semiconductor device as much as possible.

[0087] In this invention, the electrodes are configured such that the characteristics of the semiconductor device are largely dominated by the first electrode layer and the gallium oxide crystal substrate in contact with it. When the gallium oxide crystal substrate has two or more N-type conductivity with different conductivity, all (001) surfaces appearing at the bottom of the recess can be formed by the (001) surfaces of the gallium oxide crystal substrate that are not in contact with the first electrode layer.

[0088] Example 1 is one such example. Because the recess 700 is disposed in the N+ gallium oxide crystal substrate 220, it is assumed that crystal defects present in the N+ gallium oxide crystal substrate 220 have almost no effect on device operation. This is because, by forming a Schottky barrier between the first electrode layer 310 and the gallium oxide crystal substrate 200 in contact with it, the semiconductor device 100 uses the first electrode layer 310 as the anode to exhibit the characteristics of a Schottky diode.

[0089] In a semiconductor device, a recess extending substantially perpendicularly to the (100) surface may be provided separately from the outer edge of a gallium oxide crystal substrate on the (100) surface where the recess is provided.

[0090] Figure 3 schematically shows the appearance of the semiconductor device 101 according to a second exemplary embodiment of the present invention, viewed from the anode side. Figure 4 schematically shows a cross-section of the semiconductor device 101 according to Embodiment 2 of the present invention along AA shown in Figure 3.

[0091] In the semiconductor device 101 shown in Figures 3 and 4, a recess 710 extending substantially perpendicularly to the (100) surface is provided separately from the outer edge of the gallium oxide crystal substrate 201 on the (100) surface where the recess 700 is provided.

[0092] As an example, the (001) surface appearing at the bottom of the recess 710 is the bottom surface 206 of the recess shown in FIG. 3. The semiconductor device 101 differs from the semiconductor device 100 of Embodiment 1 in that a shallow recess 710 is added on the electrode layer side of the N-gallium oxide crystal substrate. Because the recess 710 is provided at the outer edge of the gallium oxide crystal substrate 201, the recess 710 is not directly involved in suppressing the growth of crystal defects as described above.

[0093] This recess 710 is used for cutting markings due to the design of the cutting process. With such markings, transparent gallium oxide crystals can be cut reliably, and the suppression of crystal defect growth becomes easier.

[0094] The recessed portion 710, which serves as a marker, is designed using the same principles as the dry etching or wet etching processes used in silicon semiconductor devices. Dry etching is superior to wet etching for improving processing accuracy. On the other hand, wet etching is less expensive than dry etching.

[0095] In the design of the cutting process, it is sometimes desirable to perform multiple cuts along the same cutting line to suppress the formation of crystallization defects caused by the cutting process. For this purpose, sometimes a wide but shallow cut is performed first, followed by a narrow but deep cut.

[0096] In Example 2, as a result of this cutting, a shallow recess 710 is added to the outer edge of the N-gallium oxide crystal substrate 210 on the electrode layer 310 side. This cutting process itself suppresses the generation of crystal defects caused by the cutting process, so it becomes a very effective process when the recess 700, which cannot be sufficiently deep as a barrier layer against crystal defects, is not possible.

[0097] As an example, the width of the recess 710 shown in FIG4, which is provided on the outer edge of the gallium oxide crystal substrate 201, is approximately 20 μm.

[0098] As an example, the depth of the recess 710 shown in FIG. 4, which is provided on the outer edge of the gallium oxide crystal substrate 201, is approximately 2 μm. In Embodiment 2, the outer edge of the gallium oxide crystal substrate 201 is also the outer edge of the gallium oxide crystal substrate 210.

[0099] As described above, at least one of the first electrode layer or the second electrode layer may include two or more metal layers with different constituent elements.

[0100] Figure 5 schematically shows a cross-section of a semiconductor device 102 according to a third exemplary embodiment of the present invention. Embodiment 3 differs from Embodiments 1 and 2 in that the anode and cathode are each composed of three metal layers.

[0101] As an example, the thickness of each metal layer is several hundred nm.

[0102] Specifically, metal layers 350, 370, and 460 are nickel, metal layer 360 is aluminum, metal layer 450 is titanium, and metal layer 470 is silver.

[0103] Therefore, at least one of the first electrode layer composed of metal layers 350, 360 and 370 or the second electrode layer composed of metal layers 450, 460 and 470 is composed of two or more metal layers with different constituent elements.

[0104] By adopting this structure, the design freedom is increased compared to the case with only one metal layer. Therefore, the thickness and sequence of multiple electrode layers can be appropriately adjusted, making it easier to perform optimal designs related to heat and stress. Specifically, it is possible to optimize the heat generated and its distribution during the operation of the semiconductor device 102, as well as the stress distribution inside the gallium oxide crystal substrate 202 caused by the expansion and contraction of the semiconductor device 102 due to heat and piezoelectric effects. This results in more reliable suppression of the growth of crystal defects accompanying the operation of the semiconductor device 102. This is because the growth mechanism of crystal defects inside the gallium oxide crystal substrate is closely related to the stress distribution inside the gallium oxide crystal substrate.

[0105] (Appendix 1) A semiconductor device, comprising: A gallium oxide crystal substrate having recesses extending substantially perpendicularly to the (001) plane in regions other than the outer edge; A first electrode layer is disposed in contact with the (001) surface of the gallium oxide crystal substrate; and The second electrode layer is disposed in contact with the side opposite to the (001) surface of the gallium oxide crystal substrate.

[0106] (Appendix 2) According to the semiconductor device described in Appendix 1, wherein: The recess is formed by a recess extending along the

[0100] direction of the gallium oxide crystal substrate.

[0107] (Appendix 3) According to the semiconductor device described in Appendix 1, wherein: The recess is formed by a recess extending along the

[0010] direction of the gallium oxide crystal substrate.

[0108] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein: The depth of the recess is approximately 60% to 95% of the thickness of the gallium oxide crystal substrate in the

[0001] direction.

[0109] (Appendix 5) According to the semiconductor device described in Appendix 4, wherein: The gallium oxide crystal substrate is composed of a gallium oxide crystal substrate with N-type conductivity.

[0110] (Appendix 6) According to the semiconductor device described in Appendix 1, wherein: The gallium oxide crystal substrate is composed of two or more gallium oxide crystal substrates with different electrical conductivities and N-type conductivity.

[0111] (Appendix 7) According to the semiconductor device described in Appendix 6, wherein: All (001) surfaces appearing at the bottom of the recess are formed by (001) surfaces of a gallium oxide crystal substrate that are not in contact with the first electrode layer.

[0112] (Appendix 8) According to the semiconductor device described in Appendix 1, wherein: At least one of the first electrode layer or the second electrode layer is composed of two or more metal layers with different constituent elements.

[0113] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, wherein: The outer edge of the gallium oxide crystal substrate having the recessed (100) surface has a recess that extends substantially perpendicularly to the (100) surface, other than the recessed (100) surface.

[0114] As described above, although the present invention has been illustrated with embodiments 1 to 3, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or modifications can be made to the content of the above embodiments. It is clear from the claims that such modified or modified implementations are also included within the technical scope of the present invention.

[0115] It should be noted that the order of operation of the apparatus, process, or device shown in the request, specification, and drawings may be performed in any order unless explicitly stated as "before" or similar. The results of the above processing are used for subsequent processing of the actions of the request, specification, and device. Even if "firstly" or "next" is used, it does not mean that they must be performed in that order.

[0116] 100: Semiconductor devices 101: Semiconductor Devices 102: Semiconductor Devices 150: Semiconductor devices 200: Gallium oxide crystal substrate 201: Gallium oxide crystal matrix 202: Gallium oxide crystal matrix 205: Bottom surface of the concave part 206: Bottom of concave part 210: N-gallium oxide crystal matrix 211: N-gallium oxide crystal matrix 220: N+ gallium oxide crystal substrate 250: Gallium oxide crystal substrate 260: N-gallium oxide crystal substrate 270: N+ gallium oxide crystal substrate 310: Electrode layer 350: Metal layer 360: Metal Layer 370: Metal layer 410: Electrode layer 450: Metal layer 460: Metal layer 470: Metal layer 500: Gallium oxide wafer 600: Crystal Defect 610: Crystal defects 700: concave part 710: concave part

[0117] none

Claims

1. A semiconductor device, comprising: A gallium oxide crystal substrate having a recess extending substantially perpendicularly to a (001) surface in a region other than its outer edge, wherein the depth of the recess is approximately 60% to 95% of the thickness of the gallium oxide crystal substrate in the [001] direction; a first electrode layer disposed in contact with the (001) surface of the gallium oxide crystal substrate; and a second electrode layer disposed in contact with a surface opposite to the (001) surface of the gallium oxide crystal substrate.

2. The semiconductor device according to claim 1, wherein, The recess is formed by a recess extending along the [100] direction of the gallium oxide crystal substrate.

3. The semiconductor device according to claim 1, wherein, The recess is formed by a recess extending along the [010] direction of the gallium oxide crystal substrate.

4. The semiconductor device according to claim 1, wherein, The gallium oxide crystal substrate is composed of a gallium oxide crystal substrate with N-type conductivity.

5. The semiconductor device according to claim 1, wherein, The gallium oxide crystal substrate is composed of two or more gallium oxide crystal substrates with different electrical conductivities and N-type conductivity.

6. The semiconductor device according to claim 5, wherein, All (001) surfaces appearing at the bottom of the recess are formed by (001) surfaces of a gallium oxide crystal substrate that are not in contact with the first electrode layer.

7. The semiconductor device according to claim 1, wherein, At least one of the first electrode layer or the second electrode layer is composed of two or more metal layers with different constituent elements.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The outer edge of the gallium oxide crystal substrate having the recessed (100) surface has a recess that extends substantially perpendicularly to the (100) surface, other than the recessed (100) surface.

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