Method of forming advanced memory device, advanced memory array, and semiconductor processing system

Abstract

This technology includes methods and systems for forming advanced memory structures, and the resulting apparatus. The method includes forming a dielectric material layer over one or more features: a first sidewall, a second sidewall, and a bottom wall, wherein the first sidewall and the second sidewall are spaced apart, and the bottom wall is disposed between the first sidewall and the second sidewall. The method includes directly depositing a pad material on the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall. The method includes removing at least a portion of the pad material from the bottom wall. The method includes selectively depositing a conductive material on the remaining portion of the pad material.

Description

[Technical Field]

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 438,146, filed February 9, 2024, entitled “METAL SIGNAL OR POWERLINE SEPARATION THROUGH SELECTIVE DEPOSITION IN ADVANCED MEMORY DEVICES”, the entire contents of which are incorporated herein by reference.

[0002] This disclosure generally describes designs for advanced memory devices, such as 4F2 dynamic random access memory (DRAM) arrays, 6F2 DRAM arrays, 3D DRAM, 3D NAND, junctionless SONOS memory, floating cell memory, oxide semiconductor memory, ferroelectric memory, and other devices with high aspect ratio characteristics. More specifically, this disclosure describes advanced memory arrays with low signal or power line resistivity. [Previous Technology]

[0003] With the advancement of computing technology, computing devices are becoming smaller and have increased processing power. This necessitates increased storage and memory to meet the device's programming and computational needs. Reducing the size of devices with increased storage capacity is achieved by increasing the number of storage cells with smaller geometries.

[0004] Dynamic Random Access Memory (DRAM) architectures continue to shrink over time. For example, the one-transistor, one-capacitor (1T-1C) DRAM cell architecture has been successfully reduced from an 8F2 size to a 6F2 size (where F-series minimum feature size). Further design changes from 6F2 to 4F2 could help further improve area density. As devices continue to shrink, improvements in device resistivity are desired. However, advanced designs often exhibit high aspect ratios, making it difficult to etch and deposit conductive materials without damaging the device. Therefore, there is a need in industry to improve one or more features of advanced memory devices. [Summary of the Invention]

[0005] This technology generally relates to methods of forming advanced memory devices. The method includes forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall of one or more features, wherein the first sidewall and the second sidewall are spaced apart, and the bottom wall is disposed between the first sidewall and the second sidewall. The method includes directly depositing a pad material on the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall. The method includes removing at least a portion of the pad material from the bottom wall. The method includes selectively depositing a conductive material on the remaining portion of the pad material.

[0006] In embodiments, the pad material is conformally deposited on the first and second sidewalls. Furthermore, in embodiments, the pad is deposited by atomic layer deposition, chemical vapor deposition, or a combination thereof. In other embodiments, the conductive material is deposited using selective atomic layer deposition, selective chemical vapor deposition, or a combination thereof. Additionally or alternatively, the conductive material is deposited only above the pad material. Embodiments include depositing the pad material, etching the pad material, and depositing the conductive material without vacuum disruption. Further embodiments include recessed pad material. Furthermore, in embodiments, the conductive material is recessed together with the pad material, or the conductive material is selectively deposited after the recessed pad material. In embodiments, the method includes filling one or more features with a sacrificial material after depositing the pad material. Furthermore, in embodiments, the etching of the pad material is performed before filling one or more features. In other embodiments, the pad material and the sacrificial material are recessed simultaneously or sequentially.

[0007] In further embodiments, the gasket material includes titanium nitride, titanium silicon nitride, titanium aluminum aluminum aluminum aluminum nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicon nitride, titanium, ruthenium, tungsten, molybdenum, tantalum nitride, tungsten nitride, tungsten silicon nitride, tungsten carbonitride, tungsten silicon nitride, niobium nitride, titanium aluminum aluminum nitride, titanium silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, lanthanum nitride, or combinations thereof. In further embodiments, the conductive material comprises titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicon nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum nitride, titanium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, nickel silicon nitride, cobalt silicon nitride, iridium oxide, ruthenium oxide, or combinations thereof, and combinations thereof. In embodiments, the conductive material comprises molybdenum, tungsten, or combinations thereof, and wherein molybdenum and / or tungsten are selectively deposited by contacting a pad material with one or more molybdenum and / or tungsten precursors. Furthermore, in embodiments, one or more molybdenum precursors comprise molybdenum chloride, molybdenum oxychloride, molybdenum-based organometallic compounds, or combinations thereof, and / or one or more tungsten precursors comprise tungsten chloride.

[0008] This technology also generally relates to advanced memory arrays. The array includes a feature having a first sidewall opposite to a second sidewall and a bottom wall. The array includes a dielectric material layer formed over the first sidewall, second sidewall, and bottom wall. The array includes a pad formed over the dielectric material layer on the first sidewall, second sidewall, and bottom wall. The array includes a conductive material formed over the pad on the first and second sidewalls, wherein the bottom wall typically does not contain conductive material, and wherein the conductive material formed over the pad on the first sidewall is electrically isolated from the conductive material formed over the pad on the second sidewall. The array includes a conductive material formed of molybdenum, ruthenium, tungsten, titanium nitride, titanium, or combinations thereof, and a pad formed of titanium nitride, titanium silicon nitride, amorphous silicon, polycrystalline silicon, molybdenum nitride, molybdenum silicon, or combinations thereof.

[0009] This technology also generally relates to semiconductor processing systems. The system includes a system controller configured to form a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall in a first processing chamber. The system includes a system controller configured to deposit a pad material over the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall in a second processing chamber. The system includes a system controller configured to etch the pad material from the bottom wall in a third processing chamber and selectively deposit a conductive material over the pad material in the second processing chamber or a fourth processing chamber. In embodiments, the second, third, and optionally fourth processing chambers are contained within a cluster tool having a shared vacuum environment. Furthermore, in embodiments, the system includes additional processing chambers containing one or more oxide removal systems.

[0010] This technology offers several advantages over conventional systems and techniques. For example, the process and system allow the use of materials that are difficult to etch in high aspect ratio features such as word lines. Additionally, by allowing the separation of high resistivity word line materials, the process and system can significantly improve gate resistivity. These and other embodiments, along with many of their advantages and features, are described in more detail below in conjunction with the accompanying drawings.

Implementation Method

[0029] Historically, DRAM chip bit density has increased by approximately 25% between nodes. However, for recent generations, the trend of increasing bit density between nodes has slowed to around 20%, primarily due to the challenges of scaling cell area. Modern DRAM cell design architectures are based on a 6F2 geometry, where "F" represents the minimum feature size for a given technology node. The switch from 6F2 to 4F2 cell architectures can result in a 33% increase in bit density at the same technology node. Furthermore, 4F2 DRAM is significantly less difficult to pattern than 6F2. This is at least partly due to the fact that in the 4F2 DRAM scheme, capacitors and bit lines are located at both ends of the vertical cell transistor, rather than being tightly packed on the same side as in 6F2 DRAM.

[0030] However, advanced memory structures, including vertical cell structures such as 4F2DRAM, 6F2DRAM, 3D NAND, 3D DRAM, junctionless SONOS memory, floating cell memory, oxide semiconductor memory, ferroelectric memory, and other devices with high aspect ratios, come with their own challenges. For example, such advanced memory cells exhibit high aspect ratios with small critical dimensions, making directional etching difficult, especially without damaging the surrounding sidewalls. For example, it is desirable to utilize conductive materials in advanced memory devices, such as those used to form signal or electric lines, which can also be in sheet form. However, conductive materials (such as molybdenum, ruthenium, tungsten, titanium, and the like) are difficult to etch, especially when placed in high aspect ratio structures. The etching difficulty is further exacerbated when the device requires almost no change in the physical and chemical properties of the conductive material. This is problematic because when forming metallic signals or electric lines, the deposited material must be separated to isolate adjacent cells, which requires bottom stamping using high-bias reactive ion etching. Furthermore, this problem is exacerbated in advanced memory structures because the aspect ratio of features increases from 25:1 to 30:1 after the deposition of metallic signal or power line material. Therefore, existing processes fail to provide a method for forming electrically isolated conductive signal or power lines (such as word lines or bit lines) nearby without damaging the conductive material formed on the device sidewalls.

[0031] This technology overcomes these and other problems by depositing a conformal pad material over the feature and etching the bottom of the pad material before introducing conductive signal or power line material. That is, by carefully selecting the pad material and conductive material, a pad material with favorable etching properties can be used, thereby reducing the difficulty of the under-stamping process. Furthermore, careful selection of the conductive material allows the growth of the conductive material to occur only above the under-stamped pad material, thus limiting the growth of the conductive material to the portion of the feature on which the pad is formed. In addition, the pad material can be deposited at a thickness less than 50% of the required thickness of the conductive material. Therefore, the difficulty of etching and the possibility of sidewall damage can be further reduced, as under-stamping etching can occur when the feature exhibits a much lower aspect ratio (such as less than 30:1, less than 20:1, less than 15:1, or even less than 10:1) and a larger critical dimension. Therefore, this technology provides the ability to form metallic signals or power lines in advanced memory structures using conductive materials without etching the conductive material.

[0032] Although the remainder of this disclosure will conventionally identify specific deposition and etching processes for forming vertical cell access array transistors (VCAATs) such as 4F2DRAM devices, it will be readily understood that the system and methods are equally applicable to other memory devices, including 6F2DRAM arrays, 3D NAND, and / or 3D DRAM devices, junctionless SONOS memory, floating cell memory, oxide semiconductor memory, ferroelectric memory, and other devices with high aspect ratio characteristics, their orientation, and the processes used to form such devices. Therefore, the technology should not be considered as limited to use with such specific devices or individual systems. Before describing additional variations and modifications to this device according to embodiments of the present technology, this disclosure will discuss possible semiconductor devices that may utilize one or more components using one or more word lines according to embodiments of the present technology.

[0033] Figure 1A shows a top plan view of a multi-chamber processing system 100 that may be specifically configured to implement some embodiments of the present technology or to operate accordingly. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on separate substrates (such as any number of semiconductor substrates) for forming semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer loading gates 110 and 112 (although dual loading gates may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading gates 110 and 112 may include a heating device 113 and may be attached to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. Processing chambers 122 and 124 may be attached to buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108, and may facilitate transfer between robots 126 and 128. Platforms 102 and 104 may have access to both the transfer chamber and the buffer chamber, or the platforms may be selectively isolated from or sealed to allow different operating pressures to be maintained between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, such as those for orientation or measurement operations.

[0034] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any means or combination of means configured to perform the operations described below. Thus, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, can perform the operations described with respect to the method according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps during the fabrication of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform several substrate processing operations, which may include dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0035] Figures 1B and 1C show a top view and a perspective view of a conventional 4F2 memory array 150. The memory array 150 may include a plurality of word lines 152 arranged in a first layer above a substrate. The word lines 152 may be conductive traces for selecting memory cells in the memory array 150. The memory array 150 may also include a plurality of bit lines 154 arranged in a second layer above a substrate. The plurality of bit lines may be conductive traces for selecting memory cells in the memory array 150. Activating one of the plurality of bit lines 154 and one of the plurality of word lines 152 can select an individual cell in the memory array 150. The first layer and the second layer may include different metal layers formed at different times during the manufacturing process. For example, the first layer having word lines 152 may be formed on the second layer having bit lines 154 such that the two layers do not intersect.

[0036] A plurality of vertical memory cells may be arranged above the intersection of a plurality of word lines 152 and a plurality of bit lines 154. Each of the plurality of vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or a vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar, or any other substrate discussed in more detail below. This silicon channel may be formed by etching the substrate. Each of the plurality of vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may be operated by storing charge on the vertical capacitor 156 to indicate the saved memory state. However, although Figures 1B and 1C show an arrangement of vertical transistors and capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" can be within approximately 10° of orthogonality, such as less than or about 7.5°, such as less than or about 5°, such as less than or about 2.5°, such as less than or about 1°, or any range or value between them, and "generally" can be used to similarly vary "vertical," "horizontal," and the like), it should be understood that other orientations are contemplated for use in this art. For example, in an embodiment, capacitors and vertical transistors may be spaced alternately in rows, such that these rows are offset by half the distance between the vertical transistors. That is, in an embodiment, the first row of memory cells may be regularly spaced in a first direction, and the second row of memory cells may also be regularly spaced in a first direction, but the second row of memory cells may be offset from the first row of memory cells, such as being approximately mid-aligned between the vertical transistors and capacitors in the first row. Compared to the square patterns shown in Figures 1B and 1C, this pattern may be referred to as a "honeycomb" or "hexagonal pattern." Therefore, it should be understood that any suitable orientation may be used in this technique.

[0037] Characterizing the size of the unit cell region 166 of this conventional 4F2 memory array is useful for comparison with a simple memory array described below. For example, the capacitor-occupied region 158 can be defined as a circular region around each vertical capacitor 156. The capacitor-occupied region 158 may include a horizontal cross-sectional region of capacitors extending outward until this cross-sectional region contacts the capacitor regions from adjacent memory cells. Assume that the word line pitch 162 of the plurality of word lines 152 and the bit line pitch 164 of the plurality of bit lines 154 can be defined as 2F. This results in a total cross-sectional area of ​​4F2 for the unit cell region 166.

[0038] Figure 2 illustrates exemplary operations in method 200 according to some embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formation, but such operations are not critical to the technology or may be performed by alternative methods that would be readily understood. Furthermore, although the method may be described as a vertical formation method, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0039] Method 200 may include additional operations prior to the operations listed above. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The prior processing operations may be performed in a chamber in which method 200 is performed, or the processing prior to delivering the substrate to a semiconductor processing chamber in which method 200 is performed may be performed in one or more other processing chambers. In any case, method 200 may, as appropriate, include a processing area of ​​delivering the semiconductor substrate to a semiconductor processing chamber (such as processing chamber 100 described above, or other chambers that may include components as described above). The substrate may be deposited on a substrate support / transfer platform, which may be a base, such as substrate support 104, and may be placed in a processing area of ​​a chamber, such as the processing area of ​​processing chamber 120 described above. Method 200 describes operations schematically illustrated in the figures, and the description of these operations will be described in conjunction with the operations of method 200. It will be understood that the diagrams show only partial schematics, and the semiconductor substrate may include additional components of any size or configuration as shown in the diagrams, as well as alternative components, that can still benefit from the present technology.

[0040] Method 200 may or may not involve optional operations for forming a semiconductor structure to specific manufacturing operations. It will be understood that method 200 can be performed on any number of semiconductor structures 300 shown in the figure, including exemplary structures on which selectively deposited materials can be formed. Semiconductor structures formed from substrate materials (which can be any number of materials) are shown in Figure 3A, such as silicon or silicon-containing materials, germanium, silicon-germanium (SiGe), silicon on insulator (SOI), silicon-germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, other substrate materials, and substrate wafers or substrates made of one or more materials that can be overlaid on the substrate during semiconductor processing.

[0041] Furthermore, although various deposition and filling processes will be described, it should be understood that, in embodiments, the semiconductor structure may be moved to and transported between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or the like. Therefore, unless specifically stated otherwise, it should be understood that any one or more of the above methods may be utilized as known in the art. Similarly, the semiconductor structure can be moved to and transported between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, or one or more of the like, as well as other etching processes known in the art.

[0042] In embodiments, the substrate may include a bulk substrate on an insulator wafer, an epitaxially grown substrate, silicon, silicon-germanium (SiGe), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, and / or gallium arsenide, as well as any one or more substrate materials discussed above. As used herein, the term "semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or a combination of semiconductor materials used to form the semiconductor structure. For example, the semiconductor layer may comprise one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon-germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which the substrate can be formed are described herein, any material that can be used as a substrate falls within the spirit and scope of this disclosure on which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed.

[0043] In embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor produced during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a larger hole concentration compared to the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0044] As shown in Figure 3A, in an embodiment, a structure 300 containing two or more electrical isolation channels 302 is provided, with features 303 formed between the electrical isolation channels. This structure may be shallow trench isolation. The two or more electrical isolation channels 302 may be formed from any one or more substrate materials discussed herein and have a dielectric material 304 formed thereon. In an embodiment, suitable dielectric materials may include one or more gate oxides, one or more high dielectric constant materials, and stacks or combinations thereof. In an embodiment, dielectric material 304 may include one or more layers of gate oxides, SiO-SiN-SiO stacks, SiO-polysilicon-SiO stacks, high dielectric constant materials, or combinations thereof. As shown, dielectric material 304 may be formed over the opposing first and second sidewalls 310 of the feature and on the bottom wall 311.

[0045] Figure 3A illustrates the deposition of a pad material 306 over the dielectric material 304 contained on the first and second sidewalls and the bottom wall at operation 201. In an embodiment, the pad material may be formed directly over the dielectric material 304. In an embodiment, the pad material may be one or more materials suitable for initiating or seeding selective growth of one or more conductive materials and exhibiting good etching properties. Furthermore, the pad material 306 is selected to meet the resistivity and operating function requirements of the device without the pad being completely consumed during the deposition of the conductive material. In an embodiment, the pad material may include titanium nitride, titanium silicon nitride, titanium aluminide, titanium aluminum nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicon nitride, titanium, ruthenium, tungsten, molybdenum, tantalum nitride, tungsten nitride, tungsten silicon nitride, tungsten carbonitride, tungsten silicon nitride, niobium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, lanthanum nitride, or combinations thereof. Advantageously, the pads according to this technology can be deposited using one or more non-selective processes (also known as conformal deposition processes, such as ALD) or other processes known in the art. Furthermore, as will be discussed in more detail below, this type of pad material also exhibits excellent etch selectivity compared to the surrounding structure. In any case, in embodiments, the pad material may include titanium nitride, titanium silicon nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicon nitride, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, lanthanum nitride, or combinations thereof. In other embodiments, the pad material may include titanium nitride, titanium silicon nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicon nitride, or combinations thereof. Furthermore, in the embodiments, the gasket comprises titanium nitride, titanium silicon nitride, amorphous silicon, polycrystalline silicon, molybdenum nitride, molybdenum silicon, or a combination thereof.

[0046] Nevertheless, in embodiments, the pad material can be deposited at operation 201 at a thickness greater than that of a conventional seed layer, while still maintaining a critical dimension significantly larger than after the formation of metallic signals or power lines. That is, it may be advantageous to deposit a slightly thicker pad material in the event of any damage during the under-stamping process, while also maintaining a sufficiently small thickness to allow for a low aspect ratio and a large critical dimension. Thus, in embodiments, the pad material can be deposited to a thickness greater than or about 0.5 nm, such as greater than or about 0.75 nm, greater than or about 1 nm, greater than or about 1.25 nm, greater than or about 1.5 nm, greater than or about 1.75 nm, greater than or about 2 nm, greater than or about 2.25 nm, greater than or about 2.5 nm, greater than or about 2.75 nm, such as greater than or about 3 nm, or such as less than or about 4 nm, less than or about 3.5 nm, less than or about 3 nm, less than or about 2.5 nm, less than or about 2 nm, or any range or value between these. However, it should be understood that in the embodiments, the liner may not be present in the finished device, as the liner may be partially or completely replaced by a conductive material to allow for selective deposition of the conductive material.

[0047] Regardless of the deposition method chosen, the structure shown in Figure 3A, measured by the width between adjacent pad material layers, can have an aspect ratio of less than or about 30:1, such as less than or about 25:1, such as less than or about 20:1, such as less than or about 19:1, less than or about 18:1, less than or about 17:1, less than or about 16:1, less than or about 15:1, less than or about 14:1, less than or about 13:1, less than or about 12:1, less than or about 1:1, such as less than or about 10:1, or any range or value between these. Therefore, compared to structures with metallic signals or electric field lines formed above the pads, the structure shown in Figure 3A can have advantageous critical dimensions (e.g., feature width) and a reduced aspect ratio. Thus, such a structure allows for a more efficient etching process with reduced damage.

[0048] That is, the intermediate structure may have a critical dimension CD between adjacent sidewalls greater than or about 4 nm, such as greater than or about 5 nm, such as greater than or about 6 nm, such as greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, greater than or about 11 nm, greater than or about 12 nm, greater than or about 13 nm, greater than or about 14 nm, greater than or about 15 nm, greater than or about 16 nm, such as greater than or about 17 nm, such as greater than or about 18 nm, such as greater than or about 19 nm, such as greater than or about 20 nm, such as greater than or about 22 nm, such as greater than or about 24 nm, such as greater than or about 26 nm, such as greater than or about 28 nm, such as at most about 30 nm, or such as less than or about 30 nm, less than or about 28 nm, less than or about 26 nm, less than or about 24 nm, less than or about 22 nm, less than or about 20 nm, less than or about 18 nm, less than or about 16 nm, less than or about 14 nm. nm, less than or about 12 nm, less than or about 10 nm, or any range or value in between. CD can also be used to measure the width of a unit cell, such as to determine the aspect ratio of a feature before depositing conductive material.

[0049] Therefore, as shown in Figure 3B, at operation 202, the pad material can be bottom-etched, also known as "bottom stamping". Surprisingly, by bottom-etching the pad material 306 before depositing the conductive material, this process can leave very little residue or damage after the bottom etching process. Furthermore, the etching chemistry of the pad material can be easily customized to be selective for the pad material. In embodiments, bottom etching may include directional etching processes, such as reactive ion etching, and other etching methods as known in the art. Nevertheless, as shown, at least a portion of the top portion and the pad disposed on the bottom wall is removed, while the pad portion is retained on the sidewall 310. That is, as shown, in embodiments, the bottom etching operation may remove some or all of the pad, i.e., typically all pads disposed in the central critical size region are removed, while portions of the pad disposed both on the bottom and adjacent to the sidewall are retained. In any case, in embodiments, it should be understood that discrete portions of the pad may remain on the bottom wall after deposition.

[0050] In an embodiment, an optional protective film may be applied over the pad material prior to bottom etching to further protect the pad material. In this embodiment, the protective film may include silicon, silicon oxide, silicon nitride, carbon, titanium, titanium nitride, tungsten nitride, aluminum oxide, or the like, and may be removed after bottom etching. In an embodiment, the pad material may alternatively be deposited at a thickness greater than necessary to minimize the impact of any damage during etching. Furthermore, because the pad material serves as a selective deposition surface for the conductive material, a small amount of damage may have little impact on the final structure, as the conductive material will grow over the pad material as long as it is present.

[0051] Following the bottom etching at operation 202, at optional operation 203, the semiconductor structure 300 may undergo one or more cleaning operations, such as oxide removal, oxide conversion operations, and / or etching of exposed surfaces of the pad material that may have been altered by the air or under-punch operations. One or more cleaning operations may be used to remove any oxides formed during the under-punch operations or to convert oxides back to the pad material (e.g., TiO to TiN).

[0052] However, it should be understood that in the embodiments, cleaning operations may not be necessary. For example, in the embodiments, operations 201, 202, and / or 204 can be performed in the same cluster tool without disrupting the vacuum environment. Furthermore, in the embodiments, one or more conductive materials can be formed from precursors of etched oxides, thereby eliminating the need for separate cleaning operations. For example, as will be discussed in more detail below, the conductive precursor can etch all or part of the pad material, replacing damaged or exposed surfaces of the pad material without intermediate cleaning operations, or even completely removing the pad material and replacing it with the target conductive material.

[0053] Regardless of whether a cleaning operation is performed, at operation 204, one or more conductive materials 308 may be selectively deposited over the pad material 306, as shown in Figure 3C. As shown, in embodiments, one or more conductive materials may be formed directly on the pad material 306. Furthermore, in embodiments, little or no conductive material may be formed over the exposed dielectric material on the bottom wall. For example, as discussed above, by carefully selecting the pad material and the conductive material, the conductive material may be selectively deposited on the pad material without growing on any exposed material other than the pad material. Therefore, since the pad material has already undergone bottom etching, the conductive material may be selectively deposited along the sidewalls, thereby maintaining the separation between adjacent conductive material layers 308 without the need to etch the conductive material. In other words, in embodiments of the present technology, the conductive material may be a metallic signal or power line, such as word line and / or bit line material in the embodiments, which may be formed only on the surface of the pad material even without etching the conductive material. As discussed above, in embodiments, conductive material 308 may partially or completely remove and / or replace pad material 306. Regardless, the critical dimension after deposition of conductive material 308 decreases from the previous critical dimension before deposition of conductive material, as shown by CD2 in Figure 3C. Therefore, in embodiments, the thickness of the pad material and conductive material (which may be all or substantially all of the conductive material after deposition) is greater than or about 1 nm, such as greater than or about 2 nm, greater than or about 3 nm, greater than or about 3.5 nm, greater than or about 4 nm, greater than or about 4.5 nm, greater than or about 5 nm, greater than or about 5.5 nm, greater than or about 6 nm, greater than or about 6.5 nm, such as greater than or about 7 nm, such as less than or about 14 nm, less than or about 12 nm, less than or about 10 nm, or any range or value between these.

[0054] In embodiments, the conductive material may include any one or more conductive materials, which may also have conductivity that allows selective growth over a selected pad material. In embodiments, the conductive material may include titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicon nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum aluminum aluminum aluminum nitride, titanium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, nickel silicon nitride, cobalt silicon nitride, iridium oxide, ruthenium oxide, or combinations thereof, and combinations thereof. In embodiments, the conductive material may include one or more metals, such as titanium nitride, molybdenum nitride, molybdenum silicon, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum nitride, titanium silicon, titanium silicon nitride, tantalum silicon, tantalum silicon nitride, ruthenium titanium nitride, nickel silicon, cobalt silicon, iridium oxide, ruthenium oxide, or combinations thereof, and combinations thereof. Furthermore, in embodiments, the conductive material may include titanium nitride, molybdenum nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum nitride, or combinations thereof, and combinations thereof. In other embodiments, the conductive material may include titanium nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tungsten nitride, or combinations thereof, and combinations thereof. In embodiments, the conductive material differs from the padding material. Furthermore, in the embodiments, the conductive material comprises molybdenum, ruthenium, tungsten, titanium nitride, titanium, or combinations thereof.

[0055] In embodiments, the conductive material may be selectively deposited using one or more processes known in the art, such as ALD or CVD processes. That is, the selected conductive precursor may flow alone or co-flow with one or more carrier gases and / or inert gases into the chamber after bottom etching, thereby contacting the etched pad material. For example, when molybdenum is used as the conductive material, suitable precursors may include molybdenum chloride, molybdenum oxychloride, molybdenum-based organometallic compounds, or combinations thereof. However, it should be understood that other precursors may be used depending on the selected conductive material.

[0056] Furthermore, as discussed above, the precursor can be selected to etch natural oxides formed on the pad material, potentially eliminating the need for optional cleaning operations. For example, when molybdenum is used as the conductive material, a molybdenum chloride precursor can be introduced, which selectively etches natural oxides formed on the pad material. After etching any oxides present on the pad, molybdenum chloride will selectively deposit on the pad material. As another example, when tungsten is used as the conductive material, a tungsten chloride precursor can be introduced, which selectively etches natural oxides formed on the pad material. After etching any oxides present on the pad, tungsten chloride will selectively deposit on the pad material. Thus, the precursor material can be selected to reduce the need for one or more cleaning operations.

[0057] Deposition can be carried out at temperatures greater than or about 200°C, such as greater than or about 210°C, such as greater than or about 220°C, such as greater than or about 230°C, such as greater than or about 240°C, such as greater than or about 250°C, such as greater than or about 260°C, such as greater than or about 270°C, such as greater than or about 280°C, such as greater than or about 290°C, such as greater than or about 300°C, such as greater than or about 310°C, such as greater than or about 320°C, such as greater than or about 330°C, such as greater than or about 340°C, such as greater than or about 350°C, such as greater than or about 360°C, such as greater than or about 370°C. Temperatures, such as greater than or about 380°C, such as greater than or about 390°C, such as greater than or about 400°C, such as greater than or about 410°C, such as greater than or about 420°C, such as greater than or about 430°C, such as greater than or about 440°C, such as greater than or about 450°C, such as greater than or about 460°C, such as greater than or about 470°C, such as greater than or about 480°C, such as greater than or about 490°C, such as greater than or about 500°C, such as greater than or about 510°C, such as greater than or about 520°C, such as greater than or about 530°C, such as greater than or about 540°C, such as greater than or about 550°C, or any range or value between these. Furthermore, it should be understood that temperature or other chamber process conditions may be selected based on the chosen precursor and / or desired conductive material.

[0058] Furthermore, in embodiments, the conductive material can be deposited at a chamber pressure greater than or about 50 millitors, such as greater than or about 500 millitors, such as greater than or about 1 tor, such as greater than or about 5 tor, such as greater than or about 10 tor, such as greater than or about 15 tor, such as greater than or about 20 tor, such as greater than or about 25 tor, such as greater than or about 30 tor, such as greater than or about 35 tor, such as greater than or about 40 tor, such as greater than or about 45 tor, such as greater than or about 50 tor, such as greater than or about 7 5 pallets, such as greater than or about 100 pallets, such as greater than or about 150 pallets, such as greater than or about 200 pallets, such as greater than or about 250 pallets, such as greater than or about 300 pallets, such as greater than or about 350 pallets, such as greater than or about 400 pallets, such as greater than or about 450 pallets, such as greater than or about 500 pallets, such as greater than or about 550 pallets, such as greater than or about 600 pallets, such as greater than or about 650 pallets, such as greater than or about 700 pallets, up to about 760 pallets, or any range or value in between.

[0059] Regardless of the process conditions used, as shown in Figure 3D, in the embodiments, the pad material and / or conductive material are etched back to the desired gate length. However, one or more methods can be used to perform such etching without requiring the etching of the conductive material, without departing from the process discussed herein that allows the conductive material to be formed on the feature sidewalls rather than on the feature bottomwalls. Figures 4 and 6 illustrate the process steps for forming such gate lengths, which can be discussed in conjunction with Figures 5A to 5B and Figures 7A to 7C. However, it should be understood that other methods can still be used to form the semiconductor structure discussed herein. That is, although Figures 3C and 3D show deposition prior to the gate length recess, it should be clear that the pad material can be recessed prior to the deposition of the conductive material.

[0060] Figure 4 illustrates exemplary operations in method 400 according to some embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 400 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formations, but these operations are not critical to the technology or may be performed by alternative methods that would be readily understood. Furthermore, although the method may describe a vertical formation method, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0061] In embodiments, operations 401 and 402 may be performed according to any one or more of the embodiments discussed above regarding operations 201 and 202. However, as shown in Figure 5A, at operation 403, sacrificial material 312 may be filled into the feature. Although not illustrated, it should be understood that in embodiments, conductive material 308 may be formed over pad material 306 prior to operation 404. In embodiments, the sacrificial material may be any one or more materials having etch selectivity for oxide material 304.

[0062] Nevertheless, Figure 5B illustrates operation 404, in which the sacrificial material and pad material (and conductive material, if present) are recessed to a desired depth based on the target gate length. Although a single-step etching process is shown, in which the sacrificial material and pad material are etched simultaneously, it should be understood that multi-step operations are also contemplated herein. That is, in this embodiment, the sacrificial material may initially be recessed to the desired depth, and subsequently the pad material is recessed. Furthermore, although not illustrated, it should be understood that in embodiments, etch-back and / or chemical mechanical polishing operations may be performed to remove the sacrificial material and pad material from the top surface of the semiconductor structure before the sacrificial material and pad material are recessed. The recessing operation can be performed by any etching process known in the art.

[0063] After the recessed sacrificial material and pad material (and conductive material, if present), the remaining sacrificial material can be removed at operation 405, and the semiconductor structure can re-enter the process flow discussed above with respect to Figure 3C and operations 203 and 204. However, as discussed above, in embodiments, conductive material may have already been formed on top of the pad material before the introduction of the sacrificial material.

[0064] Figure 6 illustrates exemplary operations in method 500 according to some embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 500 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, numerous operations are described to provide a broader range of structure formations, but these operations are not critical to the technology or may be performed by alternative methods that would be readily understood. Furthermore, although the method may describe a vertical formation method, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0065] In an embodiment, operation 501 may be performed according to any one or more of the embodiments discussed above regarding operation 201. However, as shown in Figure 7A, at operation 502, sacrificial material 312 may be filled into the feature. Figure 7B shows the etch-back and / or chemical mechanical polishing portion of operation 503, wherein pad material 306 and sacrificial material 312 are polished from the top surface 314 of the semiconductor structure.

[0066] Nevertheless, Figure 7C illustrates the recess at operation 503, where the sacrificial material and the pad material are recessed to the desired depth based on the target gate length. Although a single-step etching process is shown, in which the sacrificial material and the pad material are etched simultaneously, it should be understood that multi-step operations are also contemplated herein. That is, in this embodiment, the sacrificial material may initially be recessed to the desired depth, and then the pad material is recessed. The recess operation can be performed by any etching process known in the art.

[0067] After the recessed sacrificial material and pad material (and conductive material, if present), the remaining sacrificial material can be removed at operation 504, and the semiconductor structure can re-enter the process flow discussed above with respect to Figures 3B and 3C and operations 202 to 204. That is, according to any one or more of the embodiments discussed above, the pad material may undergo under-punching, optional cleaning, and selective growth of conductive material at operation 505.

[0068] It should be understood that the specific steps shown in the figures provide a particular method for forming a 4F2DRAM array according to various embodiments, but are also suitable for other advanced memory structures as discussed herein. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Furthermore, the individual steps shown in the figures may include multiple sub-steps, which may be adapted to be performed in various sequences of the individual steps. In addition, additional steps may be added or removed depending on the specific application. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0069] As used herein, the terms “about” or “approximately” or “substantially” may be interpreted as within the scope expected by a person of ordinary skill in the art in view of this specification.

[0070] In the foregoing description, several specific details have been set forth for purposes of explanation in order to provide a thorough understanding of the various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and apparatuses are illustrated in block diagram form.

[0071] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the above description of the various embodiments is intended to provide enabling disclosure for implementing at least one embodiment. It should be understood that various changes to the function and arrangement of the apparatus can be made without departing from the spirit and scope of some embodiments set forth in the appended claims.

[0072] Specific details are set forth in the foregoing description to provide a thorough understanding of this disclosure. However, it will be understood that embodiments may be practiced without such specific details. For example, circuits, systems, networks, processes, and other components may be illustrated as components in the form of block diagrams so as not to obscure the embodiments with unnecessary details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be illustrated without unnecessary details in order to avoid obscuring the embodiments.

[0073] Furthermore, it is noted that an independent embodiment may be described as a process, depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. Although a flowchart may describe operations as a continuous process, many operations may be executed in parallel or concurrently. Furthermore, the order of operations may be rearranged. A process may terminate when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, function, program, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0074] The term "computer-readable media" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent any combination of a program, function, subroutine, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment may be coupled to another code segment or hardware circuit by transmitting and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be transmitted, forwarded, or sent by any suitable means, including memory sharing, message passing, symbol passing, network transmission, etc.

[0075] Furthermore, embodiments may be implemented using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, code or code fragments for performing necessary tasks may be stored in a machine-readable medium. The processor may perform the necessary tasks.

[0076] In the above description, features are described with reference to specific embodiments thereof, but it should be understood that not all embodiments are limited thereto. Various features and styles of some embodiments may be used individually or in combination. In addition, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are therefore considered illustrative rather than restrictive.

[0077] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, the methods may be performed in a different order than described. It should also be understood that the methods described above may be executed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or logic circuit) designed with an instruction set to perform the methods. Such machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be executed by a combination of hardware and software. [Simplified Explanation of the Diagram]

[0011] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the drawings.

[0012] Figure 1A illustrates a top plan view of an exemplary processing chamber according to an embodiment of the present technology.

[0013] Figure 1B shows a top view of a conventional 4F2 memory array.

[0014] Figure 1C shows a perspective view of a conventional 4F2 memory array.

[0015] Figure 2 illustrates a selected operation in a forming method according to an embodiment of the present technology.

[0016] Figure 3A illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0017] Figure 3B illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0018] Figure 3C illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0019] Figure 3D illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0020] Figure 4 illustrates a selected operation in a forming method according to an embodiment of the present technology.

[0021] Figure 5A illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0022] Figure 5B illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0023] Figure 6 illustrates a selected operation in a forming method according to an embodiment of the present technology.

[0024] Figure 7A illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0025] Figure 7B illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0026] Figure 7C illustrates a schematic diagram of a semiconductor structure according to an embodiment of the present technology.

[0027] Several diagrams are included as illustrations. It will be understood that the diagrams are for illustrative purposes and are not considered to be to scale unless specifically mentioned as such. Furthermore, as illustrations, the diagrams are provided to aid understanding and may not include all appearances or information compared to the actual representation, and may include exaggerated material for illustrative purposes.

[0028] In the accompanying drawings, similar parts and / or features may have the same device symbol. Additionally, parts of the same type may be distinguished by a device symbol followed by a letter distinguishing them from each other. If only a first device symbol is used in this specification, the description applies to any of the similar parts having the same first device symbol, regardless of the letter.

Claims

1. A method of forming an advanced memory device, comprising the steps of: forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall of one or more features, wherein the first sidewall and the second sidewall are spaced apart, and the bottom wall is disposed between the first sidewall and the second sidewall; directly depositing a pad material on the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall; removing at least a portion of the pad material from the bottom wall; and selectively depositing a conductive material on a remaining portion of the pad material.

2. The method as described in claim 1, wherein the padding material is deposited conformally on the first sidewall and the second sidewall.

3. The method as described in claim 1, wherein the padding material is deposited by an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof.

4. The method as described in claim 1, wherein the conductive material is deposited using a selective atomic layer deposition process, a selective chemical vapor deposition process, or a combination thereof.

5. The method as described in claim 1, wherein the conductive material is deposited only on top of the pad material.

6. The method as described in claim 1, wherein the deposition of the pad material, the removal of the portion of the pad material, and the deposition of the conductive material are performed without a vacuum disruption.

7. The method as described in claim 1 further includes the step of: recessing the padding material.

8. The method as described in claim 7, wherein the conductive material is recessed together with the pad material, or selectively deposited on the remaining portion of the pad material after the pad material is recessed.

9. The method as described in claim 1 further comprises the step of filling the one or more features with a sacrificial material after depositing the padding material.

10. The method as described in claim 9, wherein the padding material is recessed before the one or more features are filled.

11. The method as described in claim 9, wherein the padding material and the sacrificial material are recessed simultaneously or sequentially.

12. The method as claimed in claim 1, wherein the gasket material comprises titanium nitride, titanium silicon nitride, titanium aluminide, titanium aluminum nitride, polycrystalline silicon, amorphous silicon, molybdenum nitride, molybdenum silicon nitride, titanium, ruthenium, tungsten, molybdenum, tantalum nitride, tungsten nitride, tungsten silicon nitride, tungsten carbonitride, tungsten silicon nitride, niobium nitride, titanium aluminum nitride, titanium silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, lanthanum nitride, or a combination thereof.

13. The method as claimed in claim 1, wherein the conductive material comprises titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicon nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminum aluminum aluminum aluminum nitride, titanium silicon nitride, titanium silicon nitride, tantalum silicon nitride, tantalum silicon nitride, ruthenium titanium nitride, nickel silicon nitride, cobalt silicon nitride, iridium oxide, ruthenium oxide, or a combination thereof.

14. The method of claim 13, wherein the conductive material comprises molybdenum, tungsten, or a combination thereof, and wherein the molybdenum and / or tungsten is selectively deposited by contacting the pad material with one or more molybdenum and / or tungsten precursors.

15. The method as described in claim 14, wherein the one or more molybdenum precursors comprise molybdenum chloride, molybdenum oxychloride, a molybdenum-based organometallic compound, or a combination thereof, and / or the one or more tungsten precursors comprise tungsten chloride.

16. An advanced memory array comprising: a feature having a first sidewall opposite a second sidewall and a bottom wall; a dielectric material layer formed over the first sidewall, the second sidewall, and the bottom wall; a pad formed over the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall; and a conductive material formed over the pad on the first sidewall and the second sidewall, wherein the bottom wall is generally free of the conductive material, and wherein the conductive material formed over the pad on the first sidewall is electrically isolated from the conductive material formed over the pad on the second sidewall; wherein the conductive material comprises molybdenum, ruthenium, tungsten, titanium nitride, titanium, or a combination thereof, and the pad comprises titanium nitride, titanium silicon nitride, amorphous silicon, polycrystalline silicon, molybdenum nitride, molybdenum silicon, or a combination thereof.

17. The array as described in claim 16, wherein the aspect ratio of the feature having a width measured from the pad is less than or about 20:

1.

18. A semiconductor processing system comprising: a system controller configured to form a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall in a first processing chamber; deposit a pad material over the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall in a second processing chamber; etch the pad material from the bottom wall in a third processing chamber; and selectively deposit a conductive material over the pad material in the second processing chamber or a fourth processing chamber.

19. The semiconductor processing system as claimed in claim 18, wherein the second processing chamber, the third processing chamber, and the optional fourth processing chamber are contained within a cluster of tools having a shared vacuum environment.

20. The semiconductor processing system as claimed in claim 18 further includes an additional processing chamber containing one or more oxide removal systems.

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