Semiconductor device and manufacturing method thereof

Abstract

This invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device may include: a substrate; a first compound semiconductor layer disposed on the substrate; a second compound semiconductor layer disposed on the first compound semiconductor layer; a source electrode disposed on the second compound semiconductor layer and in contact with the first compound semiconductor layer; a drain electrode disposed on the second compound semiconductor layer spaced apart from the source electrode and in contact with the first compound semiconductor layer; a gate electrode disposed on the upper surface of the second compound semiconductor layer between the source electrode and the drain electrode; an insulating layer disposed on the second compound semiconductor layer and the gate electrode; and a spacer disposed on the side of at least one of the source electrode and the drain electrode, extending for a length defined along a first extending direction, and in contact with the second compound semiconductor layer and the insulating layer.

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device capable of suppressing leakage current and a method for manufacturing the same. Prior Technology

[0002] Recently, compared with existing silicon transistors, gallium nitride transistors can perform high-speed switching operations, thus having the advantages of being suitable not only for ultra-high-speed signal processing, but also for high-voltage environments due to the high voltage withstand characteristics of the raw materials themselves.

[0003] In particular, the use of gallium nitride to utilize the two-dimensional electron gas generated at the heterojunction interface can improve electron mobility, making it suitable for high-speed signal transmission, and therefore has attracted much attention from the industry.

[0004] However, in order to minimize size and achieve high frequency and improved output, high electron mobility transistors require a reduction in gate length and the spacing between the gate and drain, which increases leakage current and makes it difficult to manufacture the desired output and frequency.

[0005] Existing technical documents

[0006] Patent documents

[0007] (Patent Document 0001) Korean Patent Publication No. 10-2017-0048126 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] One embodiment of the disclosed invention provides a semiconductor device and a method thereof that can modify the structure of the source electrode and drain electrode to suppress leakage current flowing on the surface of the compound semiconductor layer.

[0010] Furthermore, one embodiment of the disclosed invention provides a semiconductor device and a method for manufacturing the same, which reduces the size of transistors and enables the performance of high-power and high-frequency products.

[0011] Technical means to solve the problem

[0012] A semiconductor element according to one embodiment of the disclosed invention may include: a substrate; a first compound semiconductor layer disposed on the substrate; a second compound semiconductor layer disposed on the first compound semiconductor layer; a source electrode disposed on the second compound semiconductor layer and in contact with the first compound semiconductor layer; a drain electrode disposed on the second compound semiconductor layer spaced apart from the source electrode and in contact with the first compound semiconductor layer; a gate electrode disposed in the upper surface of the second compound semiconductor layer between the source electrode and the drain electrode; an insulating layer disposed on the second compound semiconductor layer and the gate electrode; and a spacer disposed on at least one side of the source electrode and the drain electrode and extending for a length defined along a first extending direction, in contact with the second compound semiconductor layer and the insulating layer.

[0013] The spacer can insulate at least one of the source electrode and the drain electrode from the leakage current path disposed at the junction interface of the second compound semiconductor layer and the insulating layer.

[0014] The spacer can extend from the upper end of the insulating layer through the junction boundary between the second compound semiconductor layer and the insulating layer.

[0015] The first compound semiconductor layer may further include a plurality of wells respectively disposed below the source electrode and the drain electrode. The wells may extend along a second extending direction such that their area is larger than the area of ​​the source electrode and the spacer bonded to the first compound semiconductor layer, or the area of ​​the drain electrode and the spacer bonded to the first compound semiconductor layer.

[0016] A method for fabricating a semiconductor device according to one embodiment of the disclosed invention may include: a step of forming a first compound semiconductor layer on a substrate; a step of forming a second compound semiconductor layer on the first compound semiconductor layer; a step of forming an insulating layer on the second compound semiconductor layer; a step of forming a plurality of trenches penetrating the second compound semiconductor layer and the insulating layer at a predetermined location on the substrate; a step of forming a spacer on at least one sidewall of the plurality of trenches; and a step of forming a source electrode and a drain electrode on each inner side of the plurality of trenches, wherein the spacer may be disposed on at least one sidewall of the source electrode and the drain electrode, extends along a predetermined length in a first extending direction, and contacts the second compound semiconductor layer and the insulating layer.

[0017] The spacer can extend from the upper end of the insulating layer through the junction boundary between the second compound semiconductor layer and the insulating layer.

[0018] The present invention may further include the step of setting a plurality of traps at a predetermined location in the first compound semiconductor layer, wherein the traps may extend along a second extension direction, be set with a predetermined area, and the area is greater than the area where the source electrode and the spacer are bonded to the first compound semiconductor layer, or the area where the drain electrode and the spacer are bonded to the first compound semiconductor layer.

[0019] Compared with the efficacy of previous technologies

[0020] According to one embodiment of the disclosed invention, a semiconductor device and its fabrication method can be provided that modify the structure of the source electrode and drain electrode to suppress leakage current flowing on the surface of the compound semiconductor layer.

[0021] Furthermore, according to one embodiment of the disclosed invention, a semiconductor device and its manufacturing method can be provided that can reduce the size of transistors and achieve the performance of high-power and high-frequency products. Simple Explanation of the Diagram

[0022] Figure 1 is a cross-sectional view of a semiconductor element according to an embodiment of the present invention.

[0023] Figure 2 is a diagram showing A in Figure 1 in detail.

[0024] Figures 3a and 3b are diagrams illustrating a semiconductor element according to another embodiment of the present invention.

[0025] Figures 4a to 4e are diagrams illustrating a method for fabricating a semiconductor element according to an embodiment of the present invention.

[0026] Figures 5a to 5d are diagrams illustrating a method for fabricating a semiconductor element according to another embodiment of the present invention. Implementation

[0027] Throughout this specification, the same reference numerals denote the same structural elements. This specification does not describe all elements of the embodiments, but rather omits general content within the technical field to which the disclosed invention pertains or content repeated between embodiments. Terms such as "part, module, component, block" as used in this specification can be implemented in software or hardware, and according to embodiments, multiple "parts, modules, components, blocks" can also be embodied as a single structural element, or a "part, module, component, block" can include multiple structural elements.

[0028] Throughout the instruction manual, when it is stated that a part is "connected" to other parts, this includes not only direct connections but also indirect connections, including connections via wireless communication networks.

[0029] Furthermore, when it is stated that a part "includes" a certain structural element, unless there is a particularly contrary statement, it means that other structural elements may also be included, rather than other structural elements being removed.

[0030] In the full text of the instruction manual, when it is stated that a component is located "on" other components, this includes not only the case where the component is connected to other components, but also the case where there are other components between the two components.

[0031] The terms "first" and "second" are used to distinguish one structural element from another, and the structural element is not limited by the aforementioned terms.

[0032] Singular expressions include plural expressions unless there is an explicit exception in the context.

[0033] In each step, the identification number is used for ease of explanation. The identification number does not indicate the order of the steps. Unless a specific order is explicitly stated in the context, the steps can be performed in a different order than that described above.

[0034] The working principle and embodiments of the disclosed invention will be described below with reference to the accompanying drawings.

[0035] Figure 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. Figure 2 is a detailed view of section A of Figure 1.

[0036] Referring to Figures 1 and 2, a semiconductor element according to an embodiment of the present invention may include: a substrate 110; a first compound semiconductor layer 120 disposed on the substrate 110; a second compound semiconductor layer 130 disposed on the first compound semiconductor layer 120; a source electrode 210 disposed on the second compound semiconductor layer 130 and in contact with the first compound semiconductor layer 120; a drain electrode 220 disposed on the second compound semiconductor layer 130 spaced apart from the source electrode 210 and in contact with the first compound semiconductor layer 120; a gate electrode 150 disposed on the upper surface of the second compound semiconductor layer 130 between the source electrode 210 and the drain electrode 220; an insulating layer 160 disposed on the second compound semiconductor layer 130 and the gate electrode 150; and a spacer 230 disposed on at least one side of the source electrode 210 and the drain electrode 220, extending for a length set along a first extending direction (vertical direction), and in contact with the second compound semiconductor layer 130 and the insulating layer 160.

[0037] The substrate 110 may contain sapphire (AL2O3), gallium nitride (GaN), silicon (Si), silicon carbide (SiC), etc.

[0038] The first compound semiconductor layer 120 serves as a buffer layer and may contain gallium nitride (GaN). The first compound semiconductor layer 120 can be provided with a thickness set on the substrate 110.

[0039] The second compound semiconductor layer 130 serves as a barrier layer and may contain aluminum gallium nitride (AlGaN). The second compound semiconductor layer 130 can be configured with a thickness that is set to that of the first compound semiconductor layer 120.

[0040] By means of the heterojunction between the first compound semiconductor layer 120 and the second compound semiconductor layer 130, the first compound semiconductor layer 120 can form the channel region 140 by the two-dimensional electron gas (2DEG) generated at the upper end of the first compound semiconductor layer 120.

[0041] The source electrode 210 may contain a conductive material and may be disposed at a predetermined location on the first compound semiconductor layer 120. A portion of the area of ​​the source electrode 210 may be bonded to the second compound semiconductor layer 130.

[0042] The drain electrode 220 may contain a conductive material and is spaced apart from the source electrode 210, and is disposed at a predetermined position on the first compound semiconductor layer 120. A portion of the area of ​​the drain electrode 220 may be bonded to the second compound semiconductor layer 130.

[0043] Depending on the transistor design, the areas where the source electrode 210 and the drain electrode 220 are bonded to the second compound semiconductor layer 130 may be the same or different.

[0044] The gate electrode 150 may contain a conductive material and may be disposed on the upper surface of the second compound semiconductor layer 130 between the source electrode 210 and the drain electrode 220.

[0045] The insulating layer 160 can serve as a protective layer covering the second compound semiconductor layer 130 and the gate electrode 150. The insulating layer 160 can be provided with a thickness set on the second compound semiconductor layer 130 and the gate electrode 150.

[0046] Semiconductor devices including substrate 110, first compound semiconductor layer 120, second compound semiconductor layer 130, source electrode 210, drain electrode 220, gate electrode 150 and insulating layer 160 need to move two-dimensional electron gas only to channel region 140 when the device is in operation. However, the two-dimensional electron gas will move at the boundary between the second compound semiconductor layer 130 and the insulating layer 160 and generate leakage current path 250, which can cause problems such as semiconductor device failure and difficulty in threshold voltage control.

[0047] To address this problem, in one embodiment of the present invention, a spacer 230 comprising an insulating film may be formed in the portion of the semiconductor element that is in contact with one side of the source electrode 210 or one side of the drain electrode 220.

[0048] The spacer 230 can be formed to contact one side of the source electrode 210 or one side of the drain electrode 220, and to contact one side of the second compound semiconductor layer 130 and one side of the insulating layer 160. Furthermore, the spacer 230 can be configured to be located in the region including the boundary between the second compound semiconductor layer 130 and the insulating layer 160 (the location of the leakage current path 250).

[0049] The semiconductor device can form a spacer 230 between the first region where the active electrode 210 or drain electrode 220 is formed and the second region where the second compound semiconductor layer 130 and the insulating layer 160 are formed, thereby blocking the leakage current path 250 that may occur at the junction boundary between the second compound semiconductor layer 130 and the insulating layer 160, and allowing the two-dimensional electron gas to move only toward the channel region 140 when the device is driven.

[0050] Furthermore, the spacer 230 can insulate at least one of the source electrode 210 and the drain electrode 220 from the leakage current path 250, which occurs at the junction boundary between the second compound semiconductor layer 130 and the insulating layer 160. The spacer 230 can extend along the inner sidewall of the trench 170 that penetrates the second compound semiconductor layer 130 and the insulating layer 160. The spacer 230 can also extend along at least one side of the source electrode 210 and the drain electrode 220. For example, the spacer 230 can be disposed on at least one side of the source electrode 210 and the drain electrode 220, and can be disposed on a side adjacent to the gate electrode 150. Alternatively, the spacer 230 can be disposed on both sides of at least one of the source electrode 210 and the drain electrode 220. The spacer 230 can comprise at least one of silicon oxide, silicon nitride (SiN), and oxides combined with them.

[0051] At this time, the spacer 230 can extend with a set thickness or length, such that at least one of the source electrode 210 and the drain electrode 220 is insulated from the junction interface of the second compound semiconductor layer 130 and the insulating layer 160.

[0052] A spacer 230 may be provided on one side of the source electrode 210 near the gate electrode 150, on one side of the drain electrode 220 near the gate electrode 150, or on both sides of the source electrode 210 and the gate electrode 150. In this way, the semiconductor device can prevent the generation of a leakage current path 250 that may occur at the junction interface between the second compound semiconductor layer 130 and the insulating layer 160.

[0053] The spacer 230 can extend from the upper end of the insulating layer 160 through the junction of the second compound semiconductor layer 130 and the insulating layer 160, and is formed in such a way that the leakage current path 250 does not come into contact with at least one of the source electrode 210 and the drain electrode 220. That is, preferably, the length of the spacer 230 in the first extension direction, i.e., the vertical direction, is set such that the junction of the second compound semiconductor layer 130 and the insulating layer 160 does not come into contact with at least one of the source electrode 210 and the drain electrode 220.

[0054] In one embodiment of the present invention, a semiconductor element may have a spacer 230 disposed on at least one side of the source electrode 210 and the drain electrode 220 to suppress leakage current flowing to the leakage current path 250.

[0055] Figures 3a and 3b are diagrams illustrating a semiconductor element according to another embodiment of the present invention. For convenience, the substrate 110 is omitted in Figures 3a and 3b.

[0056] Referring to Figures 3a and 3b, in another embodiment of the present invention, in order to improve the ohmic contact between the source electrode 210 and the drain electrode 220 and the first compound semiconductor layer 120, a well 180 can be formed within the first compound semiconductor layer 120. The area of ​​the well 180 can be the area in contact with the source electrode 210 and the drain electrode 220 and the first compound semiconductor layer 120. An etching process and a vapor deposition process are performed in the area where the well 180 is formed, and the source electrode (210 in Figure 1), the drain electrode 220, and the spacer 230 are formed. During the etching process, in the etching step used to form the spacer 230, the depth of the transition moment can be greater than a preset depth, so that the well 180 and the spacer 230 come into contact.

[0057] In this case, as shown in "X" in Figure 3a, the spacer 230 can be formed with a length that penetrates the channel region 140 and contacts the first compound semiconductor layer 120. If the spacer 230 is formed in this structure, when the device is in operation, a portion of the channel region 140 in the semiconductor device, which serves as a two-dimensional electron gas movement path, is blocked by the spacer 230, which acts as an insulating material, preventing electron movement and current flow, thereby rendering the semiconductor device inoperable.

[0058] Therefore, in another embodiment of the present invention, a trap 180 may be formed at the lower part of at least one of the source electrode (210 in FIG. 1) and the drain electrode 220, with an area larger than the area of ​​the lower surface of the source electrode (210 in FIG. 1) and the spacer 230, or the area of ​​the lower surface of the drain electrode 220 and the spacer 230.

[0059] For example, the area of ​​the well 180 can be larger than the area of ​​the source electrode (210 in FIG. 1) and the lower surface of the spacer 230 disposed in the trench 170, or the area of ​​the drain electrode 220 and the lower surface of the spacer 230 disposed in the trench 170.

[0060] The well 180 can be formed using N+ ion implantation, and multiple wells 180 can be provided in the first compound semiconductor layer 120. The wells 180 can extend along a second extension direction (horizontal direction) and be provided with a predetermined area.

[0061] In one embodiment of the present invention, a semiconductor element may have a spacer 230 disposed on at least one side of the source electrode 210 and the drain electrode 220 to prevent the two-dimensional electron gas from moving toward the leakage current path 250.

[0062] In another embodiment of the present invention, the semiconductor element may include a well 180 in at least one of the source electrode (210 in FIG. 1) or drain electrode 220. When the spacer 230 is in contact with the well 180 through the channel region 140, the well 180 may be provided with an area larger than the area of ​​the lower surface of the source electrode (210 in FIG. 1) and the spacer 230, or the lower surface of the drain electrode 220 and the spacer 230, which are in contact with the well 180. This allows for smoother movement of the two-dimensional electron gas flowing from the source electrode (210 in FIG. 1) through the channel region 140 to the drain electrode 220, thereby enabling the semiconductor element to operate.

[0063] Hereinafter, the method for manufacturing the semiconductor element of the present invention will be described with reference to FIGS. 4a to 5d.

[0064] Figures 4a to 4e are diagrams illustrating a method for fabricating a semiconductor element according to an embodiment of the present invention. Figures 4c to 4e are diagrams showing the process with reference to part B of Figure 4b.

[0065] A method for fabricating a semiconductor element according to an embodiment of the present invention may be as follows: a first compound semiconductor layer 120, a second compound semiconductor layer 130, a gate electrode 150 and an insulating layer 160 are sequentially formed on a substrate 110; a plurality of trenches 170 are formed through the second compound semiconductor layer 130 and the insulating layer 160 to a predetermined depth; an insulating film 200 is formed in the insulating layer 160 and the trenches 170; and the insulating film 200 is etched along the arrow directions in Figures 4c and 4d to form spacers 230 on the sidewalls of the trenches 170; after a conductive material is vapor-deposited or deposited on the insulating layer 160, the trenches 170 and the spacers 230, a pattern is formed according to a predetermined pattern to form a source electrode 210 and a drain electrode 220.

[0066] First, referring to FIG4a, a first compound semiconductor layer 120, a second compound semiconductor layer 130, a gate electrode 150, and an insulating layer 160 can be sequentially formed on the substrate 110. Their fabrication process is a well-known technique, therefore, detailed description is omitted.

[0067] Then, referring to FIG4b, a plurality of trenches 170 can be formed to a predetermined depth by penetrating the second compound semiconductor layer 130 and the insulating layer 160. The fabrication process of the trenches 170 is a well-known technique, therefore, detailed description is omitted.

[0068] Then, referring to FIG4c, an insulating material comprising at least one of silicon oxide, silicon nitride, and oxides combined therewith can be vapor-deposited on the front surface of substrate 110 to form insulating film 200 in insulating layer 160 and trench 170.

[0069] Then, referring to FIG4d, if anisotropic (arrow direction) etching is performed on the insulating film 200 stacked on the insulating layer 160 and the trench 170, the insulating film 200 formed on the upper part of the insulating layer 160 is etched, and the insulating film 200 is retained only on the sidewall of the trench 170, thereby forming the spacer 230. Alternatively, the front surface of the substrate 110 is etched, and after the insulating film 200 is etched back, the second compound semiconductor layer 130 is etched, thereby forming the spacer 230 in a structure that contacts the second compound semiconductor layer 130 and the insulating layer 160. Moreover, the spacer 230 can be formed with a length from the upper end of the insulating layer 160 through the bonding boundary surface of the second compound semiconductor layer 130 and the insulating layer 160.

[0070] Then, referring to FIG4e, conductive materials can be vapor-deposited or deposited on the insulating layer 160, trench 170, and spacer 230 to form the source electrode 210 and drain electrode 220. The source electrode 210 and drain electrode 220 can be formed by filling the interior of the trench 170, and their lower ends can be electrically connected to the channel region 140. Furthermore, spacers 230 can be formed on each side of the source electrode 210 and drain electrode 220, i.e., on the side of the trench 170, thereby insulating them from the junction boundary between the second compound semiconductor layer 130 and the insulating layer 160. This suppresses leakage current at the junction boundary between the second compound semiconductor layer 130 and the insulating layer 160.

[0071] Figures 5a to 5d are diagrams illustrating a method for fabricating a semiconductor element according to another embodiment of the present invention. For convenience, the substrate is omitted in Figures 5a to 5d to illustrate the method for fabricating a semiconductor element according to another embodiment of the present invention.

[0072] The structure of a semiconductor element according to another embodiment of the present invention may include a first compound semiconductor layer 120 disposed on a substrate (not shown), a second compound semiconductor layer 130 disposed on the first compound semiconductor layer 120, a gate electrode 150 disposed on the second compound semiconductor layer 130, an insulating layer 160 disposed on the second compound semiconductor layer 130, a plurality of wells 180 disposed at predetermined positions on the first compound semiconductor layer 120, a plurality of trenches 170 disposed on the upper part of each of the plurality of wells 180, a spacer 230 disposed on at least one sidewall of the plurality of trenches 170, and a source electrode 210 and a drain electrode 220 disposed on the inner side of each of the plurality of trenches 170.

[0073] A method for fabricating a semiconductor element according to another embodiment of the present invention will be described with reference to Figures 5a to 5d.

[0074] As shown in Figure 5a, a first compound semiconductor layer 120, a second compound semiconductor layer 130, a gate electrode 150 and an insulating layer 160 are sequentially formed on a substrate (not shown). After photoresist PR is applied to the insulating layer 160, a patterning process including a mask exposure process is performed.

[0075] At this point, as shown in Figure 5a, the area used to form the well 180 through the patterning process is exposed. Then, in the direction of the arrow, the well 180 is formed using N+ ion implantation. Multiple wells 180 can be provided in the first compound semiconductor layer 120. The wells 180 can extend along the second extension direction (horizontal direction) and be provided with a predetermined area.

[0076] The area of ​​the well 180 can be larger than the area of ​​the lower surface of the source electrode 210 and the spacer 230 in the trench 170, which is configured with a preset value, or the area of ​​the lower surface of the drain electrode 220 and the spacer 230 in the trench 170.

[0077] Then, referring to FIG5b, an insulating material comprising at least one of silicon oxide, silicon nitride (SiN), and oxides combining the thereof can be deposited on the front surface of the substrate (not shown) to form an insulating film 200 in the insulating layer 160 and the trench 170. At this time, the insulating film 200 is formed in the well 180.

[0078] That is, if the ion implantation process is completed in FIG. 5a, processes are performed to remove the photoresist PR and the second compound semiconductor layer 130, insulating layer 160, residues, etc. remaining in the trench 170, and the channel region 140 exposed through the trench 170 is etched and exposed to the well 180. After that, an insulating film 200 formation process can be performed to form an insulating film 200 in the well 180.

[0079] Then, referring to FIG5c, the insulating film 200 stacked on the insulating layer 160 and the trench 170 is etched to form a spacer 230 on the sidewall of the trench 170. The spacer 230 may be etched in an over-etching manner during the etching of the second compound semiconductor layer 130 to etch a portion of the first compound semiconductor layer 120, that is, a portion of the upper end of the well 180, and may be formed to a length that contacts the well 180.

[0080] Then, referring to FIG5d, the source electrode 210 and the drain electrode 220 can be formed by vapor deposition or plating of a conductive material. The source electrode 210 and the drain electrode 220 can be formed by filling the interior of the trench 170, and can be electrically connected to the channel region 140 through the well 180. Furthermore, the source electrode 210 and the drain electrode 220 can be insulated from the junction interface of the second compound semiconductor layer 130 and the insulating layer 160 by means of spacers 230. Thus, leakage current generated at the junction interface of the second compound semiconductor layer 130 and the insulating layer 160 can be suppressed, and the source electrode 210 and the drain electrode 220 can be electrically connected through the well 180 and the channel region 140, thereby enabling electron movement.

[0081] According to the present invention, the structure of the source electrode and the drain electrode can be modified to suppress leakage current flowing at the boundary between the second compound semiconductor layer and the insulating layer.

[0082] Furthermore, according to the present invention, the size of transistors can be reduced, and the performance of high-power and high-frequency products can be achieved.

[0083] As described above, the disclosed embodiments have been illustrated with reference to the accompanying drawings. Those skilled in the art will understand that the invention can be implemented in forms different from the disclosed embodiments without altering the technical concept or essential features of the invention. The disclosed embodiments are merely illustrative and should not be interpreted in a restrictive manner.

[0084] 110:Substrate 120: First compound semiconductor layer 130: Second compound semiconductor layer 140: Passage Area 150: Gate electrode 160: Insulation layer 170: Trench 180: Trap 200: Insulating film 210: Source electrode 220: Drain electrode 230: Spacing 250: Leakage current path

Claims

1. A semiconductor element, comprising: substrate; A first compound semiconductor layer is disposed on the substrate; A second compound semiconductor layer is disposed on the first compound semiconductor layer; A source electrode is disposed in the second compound semiconductor layer and in contact with the first compound semiconductor layer; a drain electrode is disposed in the second compound semiconductor layer, spaced apart from the source electrode, and in contact with the first compound semiconductor layer; a gate electrode is disposed directly on the upper surface of the second compound semiconductor layer and located between the source electrode and the drain electrode; an insulating layer is disposed on the second compound semiconductor layer and the gate electrode; and a spacer is disposed on the side of at least one of the source electrode and the drain electrode and extends for a length set along a first extending direction, in contact with the second compound semiconductor layer and the insulating layer; wherein a channel region of two-dimensional electron gas is formed between the first compound semiconductor layer and the second compound semiconductor layer; wherein the depth of the spacer in the first extending direction is less than the depth of at least one of the source electrode and the drain electrode in the first extending direction.

2. The semiconductor element as claimed in claim 1, wherein, The spacer insulates at least one of the source electrode and the drain electrode from the leakage current path disposed at the junction interface of the second compound semiconductor layer and the insulating layer.

3. The semiconductor element as claimed in claim 1, wherein, The spacer extends from the top of the insulating layer through the junction of the second compound semiconductor layer and the insulating layer.

4. The semiconductor element as claimed in claim 1, wherein, The first compound semiconductor layer also includes a plurality of wells respectively disposed at the lower part of the source electrode and the drain electrode. The wells extend along a second extending direction such that their area is larger than the area of ​​the source electrode and the spacer bonded to the first compound semiconductor layer, or the area of ​​the drain electrode and the spacer bonded to the first compound semiconductor layer.

5. A method for manufacturing a semiconductor device, comprising: The step of forming a first compound semiconductor layer on a substrate; The step of forming a second compound semiconductor layer on the first compound semiconductor layer; The steps include: forming a gate electrode directly on the upper surface of the second compound semiconductor layer; forming an insulating layer on the second compound semiconductor layer and the gate electrode; forming a plurality of trenches penetrating the second compound semiconductor layer and the insulating layer, and penetrating the upper surface of the first compound semiconductor layer, at a predetermined location on the substrate; forming a spacer on at least one sidewall of the plurality of trenches; and forming a source electrode and a drain electrode on each inner side of the plurality of trenches, wherein the spacer is disposed on the side of at least one of the source electrode and the drain electrode, extends along a predetermined length in a first extending direction, and contacts the second compound semiconductor layer and the insulating layer; wherein a channel region of two-dimensional electron gas is formed between the first compound semiconductor layer and the second compound semiconductor layer; wherein the depth of the spacer in the first extending direction is less than the depth of at least one of the source electrode and the drain electrode in the first extending direction.

6. A method for manufacturing a semiconductor device as described in claim 5, wherein, The spacer extends from the top of the insulating layer through the junction of the second compound semiconductor layer and the insulating layer.

7. A method for manufacturing a semiconductor device as described in claim 5, wherein, It also includes the step of setting a plurality of traps at a predetermined location on the first compound semiconductor layer, the traps extending along a second extension direction and set with a predetermined area, and the area being larger than the area where the source electrode and the spacer are bonded to the first compound semiconductor layer, or the area where the drain electrode and the spacer are bonded to the first compound semiconductor layer.

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