Method of forming layout plan of integrated circuit device, processing device for forming layout plan of integrated circuit device, and non-transitory computer-readable medium

Abstract

An embodiment of the method for forming an integrated circuit (IC) device layout plan includes obtaining a layout of a plurality of digital circuit cells in a layout plan region; obtaining an initial layout of one or more thermal sensing resistor cells in a plurality of metallization layer subsets and a plurality of via layer subsets of the layout plan; obtaining a routing plan based on clock tree synthesis and the initial layout of one or more thermal sensing resistor cells; performing thermal analysis based on the layout and routing plan of the plurality of digital circuit cells to identify one or more regions of interest in the layout plan region; and obtaining a fine layout of one or more thermal sensing resistor cells on one or more regions of interest, respectively.

Description

[Technical Field]

[0001] Priority Claims and Cross-References

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 698,187, filed September 24, 2024, the entire contents of which are hereby incorporated by reference. [Previous Technology]

[0003] The semiconductor industry is experiencing rapid growth due to the continuous improvement in the integration density of various components (e.g., optoelectronic devices, electrical components, or the like). In some applications, the miniaturization of semiconductor devices (also known as integrated circuit (IC) devices), due to their high power density, leads to higher requirements for thermal management and heat dissipation efficiency. In some cases, the thermal management of IC devices may rely on measuring the temperature of one or more areas of interest within the IC device, corresponding to circuit blocks that may be heat sources, temperature-sensitive circuit blocks, and / or circuit blocks that can be configured based on their measured temperatures.

Implementation Method

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "consisting of." In this disclosure, the phrase "one of A, B, C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not imply that one comes from A, one from B, and one from C, unless otherwise stated.

[0009] According to one or more embodiments of this disclosure, the design flow of the thermal sensing resistor is integrated into the design flow of the digital region of an integrated circuit (IC) device (i.e., the digital design flow). In some embodiments, the digital region of the IC device corresponds to a region including digital circuit blocks. In some embodiments, compared to the analog region of the IC device, which includes analog circuit blocks or mixed-mode circuit blocks, the components in the digital region are manufactured with higher density, lower operating voltage, lower dynamic voltage, and faster operating speed.

[0010] In some embodiments, according to one or more embodiments of the present disclosure, a digital design flow integrating a thermal sensing resistor design flow includes: obtaining a layout of a plurality of digital circuit cells in a digital region; obtaining an initial layout of thermal sensing resistor cells (representing thermal sensing resistors) on the digital region in a subset of a plurality of metallization layers and a subset of a plurality of via layers in the layout plan; obtaining a routing plan based on clock tree synthesis and the initial layout of one or more thermal sensing resistor cells; performing thermal analysis based on the layout and routing plan of the plurality of digital circuit cells to identify regions of interest (e.g., heat sources) in the digital region; and obtaining a fine layout of the thermal sensing resistor cells such that the thermal sensing resistor cells are located above the regions of interest. In some embodiments, the thermal sensing resistor according to the present application does not have an inherent junction voltage and can be placed close to the region of interest where the temperature needs to be measured (e.g., in a metallization layer directly above a heat source). Therefore, the measurement accuracy based on the thermal sensing resistor according to the present application is improved. In some embodiments, the thermal sensing resistor according to the present application is designed based on a design flow integrated into the digital design flow and manufactured based on (and integrated into) a back-end process (BEOL). Therefore, the production cost and design overhead of the thermal sensing resistor according to this application are reduced.

[0011] FIG1A is a block diagram of a semiconductor device 100, which conforms to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 corresponds to an integrated circuit device or a portion thereof.

[0012] As shown in FIG1A, the semiconductor device 100 includes (among others) at least one circuit macro 110. In some embodiments, the circuit macro 110 corresponds to a set of semiconductor elements configured as memory, a controller, one or more logic gates, or similar elements. The circuit macro 110 includes (among others) one or more circuit cells, such as circuit cells 112, 114, and 116. In some embodiments, each of the circuit cells 112, 114, and 116 includes a layout pattern representing transistors formed based on one or more active regions extending along a first direction (e.g., the X direction) and one or more gate structures extending along a second direction (e.g., the Y direction). In some embodiments, each of the circuit cells 112, 114, and 116 has corresponding cell heights H1, H2, and H3, measurable along the second direction.

[0013] In some embodiments, each of circuit cells 112, 114, and 116 includes a layout pattern representing a respective conductive circuit in one or more metallization layers electrically connected to various transistors indicated by each of circuit cells 112, 114, and 116. In some embodiments, semiconductor device 100 defines a plurality of power rail regions extending along a first direction, configured to deliver a first supply voltage (e.g., VDD) or a second supply voltage (e.g., VSS or ground). In some embodiments, a circuit cell includes a first side extending along a power rail region and a second side extending along another power rail region. In some embodiments, a circuit cell without any other power rail region between the first and second sides is sometimes referred to as having a standard cell height. In some embodiments, for a more compact design based on certain process nodes, a circuit cell with a standard cell height includes up to four metallization regions (in addition to the power rail regions) extending along the first direction in the lowest metallization layer (also referred to as the MO layer) above the transistor. In some embodiments, any one of the cell heights H1, H2, and H3 has a standard cell height (e.g., 1H cell), two standard cell heights (e.g., 2H cell), or three standard cell heights (e.g., 3H cell). In some embodiments, the cells in the circuit macro 110 correspond to multiple standard cell heights or less than one standard cell height (e.g., 1 / 2H cell).

[0014] FIG1B is a simplified plan view of a semiconductor device (e.g., semiconductor device 100), consistent with some embodiments. In a non-limiting embodiment of FIG1B, the plan view of semiconductor device 100 includes multiple regions, such as a first digital region 132, a second digital region 134, and an analog region 136. In some embodiments, most of the circuit blocks and elements in the first digital region 132 and the second digital region 134, configured on the substrate and in the metallization layer of semiconductor device 100, are designed based on circuit cells and component cells automatically selected and placed by an electronic design automation (EDA) system. In some embodiments, most of the circuit blocks and elements in the analog region 136 are customized based on the layout and dimensions adjusted and specified by an analog circuit designer by operating an EDA system. In some embodiments, the circuit blocks and elements in the first digital region 132 and the second digital region 134 will be manufactured with higher density, lower operating voltage, lower dynamic voltage, and faster operating speed; while the circuit blocks and elements in the analog region 136 will be manufactured with lower density, higher operating voltage, higher dynamic voltage, and slower operating speed.

[0015] FIG2 is a cross-sectional view of a semiconductor device (e.g., semiconductor device 100) according to some embodiments. In some embodiments, the cross-sectional view is a simplified cross-sectional view, and many features are simplified or not shown.

[0016] The semiconductor device 100 in FIG2 includes a substrate 210, an active region 212, and a gate structure 214 at least partially formed in the substrate 210. In this example, the semiconductor device 100 includes a metal-drain / source (MD) structure 222 coupled to the active region 212. In this example, the semiconductor device 100 includes a via-drain / source (VD) structure connected to the MD structure 222 and a via-gate (VG) structure connected to the gate structure 214, with a VD / VG layer (relative to the Z direction) located above the substrate 210. In some embodiments, the semiconductor device 100 further includes a plurality of metallization layers (e.g., M0, M1, M2, ..., Mn-1 and Mn layers) and a plurality of via layers (e.g., V0, V1, V2, ..., Vn-2 and Vn-1 layers) above the VD / VG layer and the substrate 210 (n is a positive integer). In some embodiments, the number of metallization layers above the substrate 210 ranges from 8 to 14. In some embodiments, the Vn-1 layer represents a via structure between and connecting conductive lines in the Mn-1 layer and the Mn layer. In some embodiments, the M0 layer represents a first metallization layer above the substrate 210. In some embodiments, the plurality of metallization layers and the plurality of via layers comprise conductive materials, including copper, aluminum, gold, tungsten, combinations thereof, or the like.

[0017] The semiconductor device 100 in FIG2, as a non-limiting example, further includes conductive structures disposed beneath the substrate 210. For example, the semiconductor device 100 further includes back metallization layers BMO and BM1 and back via layers BVD and BVO. In this example, the BVD layer represents a back via structure connecting the back conductive lines in the active region 212 and the BMO layer; while the BVO layer represents a back via structure connecting the back conductive lines in the BMO and BM1 layers. In some embodiments, the BMO layer represents a first metallization layer beneath the substrate 210. In this example, there are two back metallization layers and corresponding via layers. In some embodiments, the number of back metallization layers beneath the substrate 210 ranges from 2 to 6. In some embodiments, some or all of the back conductive structures (e.g., back metallization layers BMO and BM1 and back via layers BVD and BVO) are at least partially embedded in the substrate 210. In some embodiments, the back metallization layers BMO and BM1, and the back via layers BVD and BV0, comprise conductive materials, including copper, aluminum, gold, tungsten, combinations thereof, or the like. In some other embodiments, the semiconductor device does not include any back conductive structure.

[0018] In some embodiments, the semiconductor device 100 includes one or more redistribution layers and conductive pad structures (not shown in FIG. 2) disposed on the one or more redistribution layers. In some embodiments, the semiconductor device 100 further includes conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder ball bumps, or the like, not shown in FIG. 2) disposed on the conductive pad structures. In some embodiments, the semiconductor device 100 further includes one or more back redistribution layers and back conductive pad structures (not shown in FIG. 2) disposed below the one or more back redistribution layers. In some embodiments, the semiconductor device 100 further includes back conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder ball bumps, or the like, not shown in FIG. 2) disposed below the back conductive pad structures.

[0019] FIG3 is a circuit diagram of temperature sensor 300, which conforms to some embodiments. In some embodiments, the circuit diagram in FIG3 is a simplified circuit diagram of temperature sensor 300, and includes other elements that are not fully depicted or omitted in FIG3 in some embodiments.

[0020] Temperature sensor 300 includes two current sources 312 and 314, two resistors 322 and 324, and two thermal sensing resistors 326 and 328. In FIG. 3, thermal sensing resistor 326 includes a terminal electrically coupled to current source 312 and another terminal electrically coupled to resistor 322 at node 332; while resistor 324 includes a terminal electrically coupled to current source 314 and another terminal electrically coupled to thermal sensing resistor 328 at node 334. Furthermore, resistor 322 includes a terminal electrically coupled to node 332 and another terminal electrically coupled to ground reference node 336; while thermal sensing resistor 328 includes a terminal electrically coupled to node 334 and another terminal electrically coupled to ground reference node 336. In some embodiments, thermal sensing resistors 326 and 328 are configured such that their resistance values ​​vary with the temperature of the region of interest (e.g., a heat source in an integrated circuit device). In some embodiments, resistors 322 and 324 are configured such that their resistance values ​​do not change as much with the temperature of the region of interest as thermal sensing resistors 326 and 328.

[0021] In some embodiments, current source 312 is a drive circuit connected to power supply node 338, configured to output drive current to thermal sensing resistor 326 and resistor 322; while current source 314 is another drive circuit connected to power supply node 338, configured to output another drive current to resistor 324 and thermal sensing resistor 328. In some embodiments, voltage detection circuitry (not shown in FIG. 3) is electrically coupled to nodes 332 and 334 and configured to convert the voltage difference between nodes 332 and 334 into a digital form of measured voltage difference. In some embodiments, the measured voltage difference also varies with the temperature of the region of interest, and therefore represents the measured temperature of the region of interest.

[0022] In some embodiments, the voltage detection circuitry includes an analog-to-digital converter based on a sigma-delta architecture, a dual-slope architecture, or a flash memory architecture. In some embodiments, the temperature sensor 300 is formed in the digital or analog region of the integrated circuit device. In some embodiments, the corresponding voltage detection circuitry is formed in the analog region, the digital region, or partly in the analog region and partly in the digital region of the integrated circuit device.

[0023] The temperature sensor 300 in Figure 3 is based on a differential signal architecture. In some embodiments, the temperature sensor is based on a single-ended architecture. For example, in a single-ended architecture, the voltage level of node 332 is used to measure the temperature reflected by the thermal sensing resistor 326, while the current source 314, resistor 324, and thermal sensing resistor 328 are omitted.

[0024] FIG4A is a simplified plan view 400A of a semiconductor device, showing two regions of interest as a non-limiting example, consistent with some embodiments. In some embodiments, the semiconductor device corresponds to the semiconductor device 100 in FIG1B and includes a first digital region 132, a second digital region 134, and an analog region 136. In FIG4A, the temperature of region 412 in the first digital region 132 and the temperature of region 414 in the second digital region 134 are measured and used for the operation of the semiconductor device 100. Therefore, regions 412 and 414 are also referred to as regions of interest in this disclosure. For example, in some embodiments, regions 412 and 414 correspond to the processor cores of a central processing unit (CPU) or a graphics processing unit (GPU) that operate based on a high-frequency (e.g., greater than 1 gigahertz, GHz) clock signal and generate a large amount of heat during operation. In some embodiments, to prevent damage or errors caused by overheating, the operation of the processor cores is throttled or selectively paused based on the temperature of regions 412 and / or 414.

[0025] In some embodiments, to measure the temperature of regions 412 and 414, a thermal sensing resistor (e.g., thermal sensing resistor 326 or 328 in FIG. 3) is implemented at location 422 of analog region 136 based on a vertical bipolar junction transistor (BJT). In some embodiments, given the junction voltage of the BJT (e.g., about 0.7 volts), the corresponding drive circuitry (e.g., current sources 312 and 314 in FIG. 3) needs to be coupled to a power supply node (e.g., power supply node 328 in FIG. 3) carrying a supply voltage much higher than 0.7 volts (e.g., 1.2 volts). Furthermore, given that location 422 of the BJT is in analog region 136, the corresponding drive circuitry may be placed at location 424 of analog region 136. Therefore, the design flow of the thermal sensing resistor (i.e., the BJT) at location 422 and the corresponding drive circuitry at location 424 will be based on an analog design flow, where most components and layouts are custom-designed by design engineers rather than on a cell-based automated process.

[0026] FIG4B is a simplified plan view 400B of a semiconductor device, showing two regions of interest as a non-limiting example, consistent with some embodiments. In some embodiments, the semiconductor device also corresponds to the semiconductor device 100 in FIG1B and includes a first digital region 132, a second digital region 134, and an analog region 136. In FIG4B, similar to the case described above for FIG4A, the temperature of region 412 in the first digital region 132 and the temperature of region 414 in the second digital region 134 are measured and used for the operation of the semiconductor device 100.

[0027] In some embodiments, to measure the temperature of regions 412 and 414, a thermal sensing resistor (e.g., thermal sensing resistor 326 or 328 in FIG. 3) is implemented based on a resistor formed in a subset of multiple metallization layers planned in the layout of the semiconductor device 100. In some embodiments, such a thermal sensing resistor is configured in a digital region (e.g., locations 432 and 442) above regions 412 and 414. Compared to location 422 of the BJT-based thermal sensing resistor in FIG. 4A, the thermal sensing resistor based on the conductive structure of the metallization layer is placed above a circuit block that is a heat source in the region of interest (e.g., regions 412 and 414). Therefore, the design flow of the thermal sensing resistor implemented in the metallization layer will be based on a digital design flow, where most of the components and layout are automated on a cell-based basis. In some embodiments, the drive circuit is placed at a location in the analog region (e.g., location 434 in analog region 136), outside the digital region of the thermal sensing resistor (e.g., location 432 in the first digital region 132), and supplies a voltage range of 1.0 to 1.8 volts. Furthermore, the thermal sensing resistor based on the conductive structure of the metallization layer does not have an inherent junction voltage, which sets a minimum requirement for the supply voltage of the corresponding drive circuit. Therefore, in some embodiments, the drive circuit is placed at the same location in the digital region 136 as the thermal sensing resistor (e.g., at position 444 in the second digital region 134), with the thermal sensing resistor located at position 442 in the second digital region 134, and the supply voltage range being 0.55 to 0.75 volts.

[0028] FIG5 is a cross-sectional view of a semiconductor device 500 having a thermal sensing resistor 510 formed in a metallization layer, consistent with some embodiments. In some embodiments, the cross-sectional view is a simplified cross-sectional view, and many features are simplified or not depicted.

[0029] In FIG5, the semiconductor device 500 includes a substrate 502 and a digital region 504, the digital region 504 including a digital circuit block and designed based on a digital design flow and a set of design rules applicable to the digital circuit block. In some embodiments, the digital circuit block includes one or more inverters, buffers, NAND gates, NOR gates, memory cells, multiplexers, combinations thereof, or similar elements.

[0030] The thermal sensing resistor 510 is located in a subset of a plurality of metallization layers (e.g., metallization layers Mx and Mx+1) and a subset of a plurality of via layers (e.g., via layers Vx and Vx+1) of the semiconductor device 500 (x is a positive integer). In some embodiments, the subset of the plurality of metallization layers in the layout plan corresponds to conductive lines formed during the BEOL process. In some embodiments, the subset of the plurality of metallization layers in the layout plan corresponds to one or more of the fourth, fifth, or sixth metallization layers (e.g., M3, M4, and / or M5) above the digital circuit block formed in the substrate 502. In some embodiments, the thermal sensing resistor 510 corresponds to conductive lines having a width of 20 nanometers (nm) to 36 nm. In some embodiments, the two terminals of the thermal sensing resistor 510 have conductive paths with lengths ranging from 10 micrometers (µm) to 50 µm. In some embodiments, the thermal sensing resistor 510 corresponds to a resistance value having a resistance value of 10 kiloohms (kΩ) to 50 kΩ.

[0031] In the non-limiting example of FIG. 5, the thermal sensing resistor 510 is formed based on conductive lines in the Mx metallization layer and the Mx+1 metallization layer, and via structures in the via layer Vx. In this non-limiting example, the thermal sensing resistor 510 further includes two terminals formed based on two via structures 512 and 514 in the via layer Vx+1. In some embodiments, x corresponds to 3, 4, or 5.

[0032] In some embodiments, the semiconductor device 500 further includes one or more conductive circuits 522 and 524 in one or more metallization layers (e.g., in the My metallization layer, where y ranges from 8 to 14) located above the thermal sensing resistor 510 for coupling the terminals of the thermal sensing resistor 510 (e.g., via structure 512 or via structure 514) to the corresponding driving circuit.

[0033] FIG6A is a layout diagram of a first thermal sensing resistor unit example 600A, which conforms to some embodiments. In some embodiments, the thermal sensing resistor (e.g., thermal sensing resistor 500 in FIG5 or thermal sensing resistor 326 or thermal sensing resistor 328 in FIG3) is formed based on the layout pattern specified in the first thermal sensing resistor unit example 600A.

[0034] Example 600A of the first thermal sensing resistor unit in FIG. 6A includes a first plurality of conductive lines (layout pattern 612) in a metallization layer (e.g., the Mx metallization layer in FIG. 5) along a first direction (e.g., the X direction); a second plurality of conductive lines (layout pattern 614) in another metallization layer (e.g., the Mx+1 metallization layer in FIG. 5) along a second direction (e.g., the Y direction); and a plurality of via structures (layout pattern 616) in a via layer (e.g., the Vx via layer in FIG. 5). In FIG. 6A, a first portion of the layout pattern 614 is located in region 614a at one end of the unit, and a second portion of the layout pattern 614 is located in region 614b at the other end of the unit.

[0035] In some embodiments, a plurality of via structures (indicated by layout pattern 616) are configured to connect a first plurality of conductive lines (indicated by layout pattern 612) and a second plurality of conductive lines (indicated by layout pattern 614) to form a first conductive strip extending back and forth along a first direction. Example 600A of the first thermal sensing resistor unit in FIG. 6A further includes layout pattern 618 indicating via structures at both ends of the conductive strip that serve as terminals of the resulting thermal sensing resistor in another via layer (e.g., the Vx+1 via layer in FIG. 5).

[0036] FIG6B is a layout diagram of a second thermal sensing resistor unit example 600B, which conforms to some embodiments. In some embodiments, the thermal sensing resistor (e.g., thermal sensing resistor 500 in FIG5 or thermal sensing resistor 326 or thermal sensing resistor 328 in FIG3) is formed based on the layout pattern specified in the second thermal sensing resistor unit example 600B.

[0037] Example 600B of the second thermal sensing resistor unit in FIG. 6B includes a first plurality of conductive lines (layout pattern 622) in a metallization layer (e.g., the Mx metallization layer in FIG. 5) along a first direction (e.g., the X direction); a second plurality of conductive lines (layout pattern 624) in another metallization layer (e.g., the Mx+1 metallization layer in FIG. 5) along a second direction (e.g., the Y direction); and a plurality of via structures (layout pattern 626) in a via layer (e.g., the Vx via layer in FIG. 5). In FIG. 6B, layout pattern 622 is uniformly distributed along the second direction, and layout pattern 624 is uniformly distributed along the first direction.

[0038] In some embodiments, a plurality of via structures (indicated by layout pattern 626) are configured to connect a first plurality of conductive lines (indicated by layout pattern 622) and a second plurality of conductive lines (indicated by layout pattern 624) to form a conductive mesh. Example 600B of the second thermal sensing resistor unit in FIG. 6B further includes layout pattern 628 indicating via structures at the two corners of the conductive mesh serving as terminals of the resulting thermal sensing resistor in another via layer (e.g., the Vx+1 via layer in FIG. 5).

[0039] FIG6C is a layout diagram of a third thermal sensing resistor unit example 600C, which conforms to some embodiments. In some embodiments, the thermal sensing resistor (e.g., thermal sensing resistor 500 in FIG5 or thermal sensing resistor 326 or thermal sensing resistor 328 in FIG3) is formed based on the layout pattern specified in the third thermal sensing resistor unit example 600C.

[0040] Example 600C of the third thermal sensing resistor unit in FIG. 6C includes a first plurality of conductive lines (layout pattern 632) in a metallization layer (e.g., the Mx metallization layer in FIG. 5) along a first direction (e.g., the X direction); a second plurality of conductive lines (layout pattern 634) in another metallization layer (e.g., the Mx+1 metallization layer in FIG. 5) along a second direction (e.g., the Y direction); and a plurality of via structures (layout pattern 636) in a via layer (e.g., the Vx via layer in FIG. 5). In FIG. 6C, layout pattern 634 includes a layout pattern on the left side of the unit (relative to the first direction) and another layout pattern on the right side of the unit (relative to the first direction); layout pattern 632 is uniformly distributed along the second direction.

[0041] In some embodiments, a plurality of via structures (indicated by layout pattern 636) are configured to connect a first plurality of conductive lines (indicated by layout pattern 632) and a second plurality of conductive lines (indicated by layout pattern 634) to form a conductive elevator-shaped mesh. Example 600C of the third thermal sensing resistor unit in FIG. 6C further includes layout pattern 638 indicating via structures at the two corners of the conductive elevator-shaped mesh serving as terminals of the resulting thermal sensing resistor in another via layer (e.g., the Vx+1 via layer in FIG. 5).

[0042] FIG6D is a layout diagram of a fourth thermal sensing resistor unit example 600D, which conforms to some embodiments. In some embodiments, the thermal sensing resistor (e.g., thermal sensing resistor 500 in FIG5 or thermal sensing resistor 326 or thermal sensing resistor 328 in FIG3) is formed based on the layout pattern specified in the fourth thermal sensing resistor unit example 600D.

[0043] Example 600D of the fourth thermal sensing resistor unit in FIG. 6D includes a first plurality of conductive lines (layout pattern 642) in a metallization layer (e.g., the Mx metallization layer in FIG. 5) along a first direction (e.g., the X direction); a second plurality of conductive lines (layout pattern 644) in another metallization layer (e.g., the Mx+1 metallization layer in FIG. 5) along a second direction (e.g., the Y direction); and a plurality of via structures (layout pattern 646) in a via layer (e.g., the Vx via layer in FIG. 5). In FIG. 6D, layout pattern 642 is distributed across the first and second directions, and layout pattern 644 is also distributed across the first and second directions.

[0044] In some embodiments, a plurality of via structures (indicated by layout pattern 646) are configured to connect a first plurality of conductive lines (indicated by layout pattern 642) and a second plurality of conductive lines (indicated by layout pattern 644) to form a second conductive strip extending in a zigzag manner along a diagonal direction different from the first and second directions. Example 600D of the fourth thermal sensing resistor unit in FIG. 6D further includes a layout pattern 648 indicating via structures at both ends of the conductive strip serving as terminals of the resulting thermal sensing resistor in another via layer (e.g., the Vx+1 via layer in FIG. 5).

[0045] FIG6E is a layout diagram of a fifth thermal sensing resistor unit example 600E, which conforms to some embodiments. In some embodiments, the thermal sensing resistor (e.g., thermal sensing resistor 500 in FIG5 or thermal sensing resistor 326 or thermal sensing resistor 328 in FIG3) is formed based on the layout pattern specified in the fifth thermal sensing resistor unit example 600E.

[0046] Example 600E of the fifth thermal sensing resistor cell in FIG. 6E includes a first plurality of conductive lines (layout pattern 652) in a metallization layer (e.g., the Mx metallization layer in FIG. 5) along a first direction (e.g., the X direction); a second plurality of conductive lines (layout pattern 654) in another metallization layer (e.g., the Mx+1 metallization layer in FIG. 5) along a second direction (e.g., the Y direction); and a plurality of via structures (layout pattern 656) in a via layer (e.g., the Vx via layer in FIG. 5). In FIG. 6E, layout pattern 654 includes a longer layout pattern on both sides of the cell (relative to the first direction) and a shorter layout pattern distributed across the first and second directions. Furthermore, layout pattern 652 includes a longer layout pattern uniformly distributed along the second direction and a shorter layout pattern at the corner of the cell.

[0047] In some embodiments, a plurality of via structures (indicated by layout pattern 656) are configured to connect a first plurality of conductive lines (indicated by layout pattern 652) and a second plurality of conductive lines (indicated by layout pattern 654) to form a modified trapezoidal grid with branches (based on conductive lines indicated by the shorter layout pattern in layout pattern 656). The fifth thermal sensing resistor unit example 600E in FIG. 6E further includes a layout pattern 658 indicating via structures at the two corners of the modified trapezoidal grid serving as terminals of the resulting thermal sensing resistor in another via layer (e.g., the Vx+1 via layer in FIG. 5).

[0048] Figure 7 is a process flow diagram of at least a portion of the IC design flow 700 for the digital region of a semiconductor device, conforming to some embodiments. In some embodiments, the thermal sensing resistor design described herein is implemented as part of the digital region IC design flow 700 (i.e., the digital design flow). The IC design flow 700 utilizes one or more EDA tools to generate, optimize, and / or verify the IC design prior to IC fabrication. In some embodiments, the EDA tool is one or more sets of executable instructions in an EDA system (e.g., the EDA system discussed with reference to Figure 9), executed by a processor or controller or a programmed computer to perform the indicated function. In at least one embodiment, the IC design flow 700 is executed by the design room of the IC manufacturing system discussed herein with reference to Figure 10.

[0049] In step 710, based on the IC design (e.g., a hardware description or functional description of a set of digital circuit blocks), the EDA system obtains the layout of multiple digital circuit cells in the IC layout planning area. In some embodiments, the digital circuit cell includes cell information indicating the size, shape, and position of various components therein, as well as one or more terminals (i.e., also referred to as "pins" in some applications) of the corresponding cell. In some embodiments, candidate cells are stored in a cell library 715, which is a database that records cell information related to candidate cells. In some embodiments, once a circuit cell is selected and placed in the layout plan of the IC device, subsequent steps of the IC design flow 700 interact with the circuit cell through the terminals of the cell without changing or interfering with the components in the cell. In some embodiments, the EDA system obtains the layout of multiple digital circuit cells by generating a layout, receiving a layout from another EDA system, or receiving a layout from a memory storing layouts previously generated by an EDA system or other EDA systems.

[0050] In step 720, the EDA system obtains an initial layout of one or more thermal sensing resistor cells. In some embodiments, the one or more thermal sensing resistor cells are located on a subset of a plurality of metallization layers and a subset of a plurality of via layers in the layout plan, and are located above a region of the layout plan. In some embodiments, candidate thermal sensing resistor cells are stored in cell library 715. In some embodiments, candidate thermal sensing resistor cells are formed based on one or more example combinations of Figures 6A to 6E. In some embodiments, the initial layout may be based on the location of circuit blocks configured to perform a specific function (e.g., a processing core of a CPU or GPU). In some embodiments, step 720 includes or is integrated into a virtual reservation setting step for the initial layout of a heat dissipation unit (e.g., a chimney columnar structure unit). In some embodiments, the EDA system obtains the layout of one or more thermal sensing resistor cells by generating a layout, receiving a layout from another EDA system, or receiving a layout from memory storing layouts previously generated by an EDA system or other EDA systems.

[0051] In step 730, the EDA system performs clock tree synthesis (CTS) to minimize skew and / or delays that may exist due to the placement of circuit elements in the layout plan. In some embodiments, CTS includes optimization processes to ensure that signals are transmitted and / or arrive at the appropriate timing. For example, during CTS, a layout pattern indicating one or more via structures is inserted into the layout plan to increase and / or remove time margins (signal arrival timing) to achieve the desired timing.

[0052] In step 740, the EDA system, based on the clock tree synthesis result of step 730 and the initial layout of one or more thermal sensing resistor units in step 720, obtains a routing plan indicating conductive paths for connecting the pins of multiple digital circuit units through multiple metallization layers and multiple via layers. In some embodiments, the generation of the routing plan is also referred to as a routing process, which is performed to ensure that the interconnects or networks of the routing meet a set of constraints. For example, step 740 includes a global routing process, track assignment, and detailed routing process. In the global routing process, routing resources for interconnects or networks are assigned. For example, the routing area is divided into multiple sub-regions, the pins of the laid-out circuit elements are mapped to the sub-regions, and the network is constructed as a set of physically routable sub-regions for interconnects. During track assignment, the EDA system assigns interconnects or networks to the corresponding conductive layers of the layout plan. In the detailed routing process, the EDA system routes interconnects or networks within the assigned conductive layers and within the global routing resources. For example, detailed physical interconnections are generated within the corresponding set of sub-regions defined in global routing and within the conductive layers defined in track assignment. In some embodiments, the EDA system obtains a routing plan by generating a routing plan, receiving a routing plan from another EDA system, or receiving a routing plan from memory storing routing plans previously generated by the EDA system or other EDA systems.

[0053] In step 750, the EDA system performs thermal analysis based on the layout and routing plans of multiple digital circuit units to identify one or more areas of interest (e.g., heat sources) within the layout plan area. In some embodiments, the thermal analysis is based on the required operation and power simulation of the circuit blocks corresponding to the multiple digital circuit units, and the signal flow based on the routing plan.

[0054] As a result of step 750, in some cases, the circuit designer may want to measure one or more regions of interest that do not perfectly correspond to the initial layout of the thermal sensing resistor cells. In step 760, the EDA system obtains a fine layout of one or more thermal sensing resistor cells such that the one or more thermal sensing resistor cells are respectively located on one or more regions of interest in the layout planning area. In some embodiments, step 750 includes or is integrated into an insertion step for inserting a heat dissipation unit (e.g., a chimney column structure unit). In some embodiments, the one or more thermal sensing resistors indicated by the one or more thermal sensing resistor cells also serve as heat dissipation structures. In some embodiments, the EDA system obtains the fine layout of one or more thermal sensing resistor cells by generating a fine layout, receiving a fine layout from another EDA system, or receiving a fine layout from a memory storing layouts previously generated by an EDA system or other EDA systems.

[0055] Step 770 is referred to as the wafer completion step, in which the EDA system performs one or more physical and / or timing verifications. For example, step 770 includes one or more resistor and capacitor (RC) extractions, circuit layout verification (LVS) checks, design rule checks (DRC), and timing signature checks (also known as post-layout simulation). In some embodiments, other verification processes may be used in other embodiments.

[0056] In some embodiments, RC extraction is performed, for example, by an EDA system to determine parasitic parameters of components in the placement plan, such as parasitic resistance and capacitance, for timing simulation in subsequent operations. In some embodiments, an LVS check is performed to ensure that the resulting placement plan corresponds to the design of the integrated circuit. In some embodiments, DRC is performed, for example, by an EDA system to ensure that the placement plan meets certain manufacturing design rules, i.e., to ensure the manufacturability of the integrated circuit device. In some embodiments, timing sign-off checks (post-placement simulation) are performed, for example, by an EDA system to take into account the extracted parasitic parameters and determine whether the placement plan meets predetermined specifications for one or more timing requirements.

[0057] In some embodiments, at step 770, if the generated layout plan fails one or more verification operations, the design flow 700 proceeds to an earlier step, such as steps 710, 730, or 740, to make modifications based on the result of step 770. In some embodiments, at step 770, if the generated layout plan passes all verification operations, the layout plan is output and stored in the memory of the processing device, wherein the layout plan of the integrated circuit device includes the layout of a plurality of digital circuit units, a wiring plan, and a fine layout of one or more thermal sensing resistor units. In some embodiments, the layout plan is generated and / or stored in the form of a Graphical Design System (GDS) file. Other data formats describing integrated circuit designs are within the scope of various embodiments.

[0058] Figure 8 is a flowchart of a method 800 for forming an integrated circuit device layout plan according to some embodiments. In some embodiments, various operations of method 800 are performed by an EDA system, as discussed with respect to the EDA system in Figure 9. In some embodiments, method 800 corresponds to the integrated circuit design flow example in Figure 7. As shown in Figure 8, method 800 includes blocks 810-860.

[0059] In block 810, the layout of a plurality of digital circuit cells in an integrated circuit device layout planning area is obtained. In some embodiments, the layout planning area corresponds to an area designed based on a digital design flow and a set of design rules applicable to the digital circuit block. In some embodiments, the digital circuit cells are used to form a digital circuit block including one or more inverters, buffers, NAND gates, NOR gates, memory cells, multiplexers, any combination thereof, or the like. In some embodiments, block 810 corresponds to the operation of step 710 in FIG. 7. In some embodiments, the EDA system obtains the layout of the plurality of digital circuit cells by generating a layout, receiving a layout from another EDA system, or receiving a layout from memory storing layouts previously generated by the EDA system or other EDA systems.

[0060] At block 820, an initial layout of one or more thermal sensing resistor units is obtained in a subset of a plurality of metallization layers and a subset of a plurality of via layers in the layout plan. In some embodiments, one or more thermal sensing resistor units are used to form thermal sensing resistors 326 and 328 in FIG. 3, or thermal sensing resistor 510 in FIG. 5. In some embodiments, one or more thermal sensing resistor units correspond to thermal sensing resistor unit examples in FIG. 6A-6E. In some embodiments, block 820 corresponds to the operation of step 720 in FIG. 7. In some embodiments, the EDA system obtains the layout of one or more thermal sensing resistor units by generating a layout, receiving a layout from another EDA system, or receiving a layout from a memory storing layouts previously generated by the EDA system or other EDA systems.

[0061] In some embodiments, a subset of the plurality of metallization layers in the layout plan corresponds to the formation of conductive circuitry during back-end processes. In some embodiments, a subset of the plurality of metallization layers in the layout plan corresponds to one or more of a fourth, fifth, or sixth metallization layer above a plurality of circuit cells. In some embodiments, at least one of one or more thermal sensing resistor cells corresponds to the formation of one or more conductive circuitry with a width of 20 nm to 36 nm. In some embodiments, at least one of one or more thermal sensing resistor cells corresponds to the formation of a resistor with a resistance value of 10 kΩ to 50 kΩ.

[0062] In some embodiments, at least one of one or more thermal sensing resistor units corresponds to forming a first plurality of conductive circuits in a metallization layer along a first direction, forming a second plurality of conductive circuits in another metallization layer along a second direction, and forming a plurality of via structures. In some embodiments, the plurality of via structures connect the first plurality of conductive circuits and the second plurality of conductive circuits to form a first conductive strip extending back and forth along the first direction (e.g., based on example 600A of the first thermal sensing resistor unit), a conductive mesh (e.g., based on example 600B of the second thermal sensing resistor unit), a conductive trapezoidal mesh (e.g., based on example 600C of the third thermal sensing resistor unit), a second conductive strip extending in a zigzag pattern along a diagonal direction different from the first and second directions (e.g., based on example 600D of the fourth thermal sensing resistor unit), or a modified trapezoidal mesh with branches (e.g., based on example 600E of the fifth thermal sensing resistor unit).

[0063] In block 830, based on clock tree synthesis and the initial layout of one or more thermal sensing resistor units, a wiring plan is obtained indicating conductive paths for connecting pins of multiple digital circuit units through multiple metallization layers and multiple via layers. In some embodiments, block 830 corresponds to the operation of steps 730 and 740 in FIG. 7. In some embodiments, the EDA system obtains the wiring plan by generating the wiring plan, receiving the wiring plan from another EDA system, or receiving the wiring plan from memory storing wiring plans previously generated by the EDA system or other EDA systems.

[0064] In block 840, thermal analysis is performed based on the layout and routing plan of multiple digital circuit units to identify one or more regions of interest within the layout plan area. In some embodiments, block 840 corresponds to the operation of step 750 in FIG7.

[0065] In block 850, a fine layout of one or more thermal sensing resistor units is obtained, such that the one or more thermal sensing resistor units are respectively located on one or more regions of interest in the layout planning region. In some embodiments, the fine layout corresponds to positions 432 and 442 in FIG. 4B. In some embodiments, block 850 corresponds to the operation of step 760 in FIG. 7. In some embodiments, the EDA system obtains the fine layout of one or more thermal sensing resistor units by generating a fine layout, receiving a fine layout from another EDA system, or receiving a fine layout from a memory storing fine layouts previously generated by the EDA system or other EDA systems.

[0066] In block 860, the layout plan of an integrated circuit arrangement including the layout and wiring plan of a plurality of digital circuit units and the fine layout of one or more thermal sensing resistor units is stored in the memory of the processing device. In some embodiments, block 860 corresponds to the operation of step 770 in FIG7.

[0067] In some embodiments, method 800 further includes obtaining a layout of the drive circuit block in a layout planning area. In some embodiments, the formation of the drive circuit block and one of one or more thermal sensing resistor units corresponds to a portion of a temperature sensor block. In some embodiments, the wiring plan includes conductive paths for coupling terminals of one or more thermal sensing resistor units to the drive circuit block. In some embodiments, the conductive paths are located in one or more metallization layers above the one or more thermal sensing resistor units. In some embodiments, the EDA system obtains the layout of the drive circuit block by generating a layout, receiving a layout from another EDA system, or receiving a layout from a memory storing layouts previously generated by the EDA system or other EDA systems.

[0068] FIG9 is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments. In some embodiments, the EDA system 900 includes an automatic placement and routing (APR) system. According to some embodiments, the EDA system 900 may be used, for example, to implement a layout diagram representing the arrangement of wire routing in a design according to one or more embodiments described herein.

[0069] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a computer-readable storage medium 904. Among other things, the storage medium 904 is encoded, i.e., stored, with computer program code 906 (i.e., a set of executable instructions). Execution of the instructions 906 by the hardware processor 902 represents (at least in part) an EDA tool that implements some or all of the methods described herein according to one or more embodiments (processes and / or methods mentioned below).

[0070] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable storage medium 904 to be connected to external components via network 914. Processor 902 is configured to execute computer program code 906 encoded in computer-readable storage medium 904 so that system 900 can be used to perform some or all of the mentioned processes and / or methods. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0071] In one or more embodiments, the computer-readable storage medium 904 is a non-transitory computer-readable storage medium, including electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor systems (or devices or apparatuses). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 904 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0072] In one or more embodiments, storage medium 904 stores computer program code 906 configured to enable system 900 (wherein this execution representation is (at least partially) an EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 904 also stores information facilitating the execution of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 904 stores a cell library 907 of standard cells, including the standard cells as disclosed herein. In one or more embodiments, storage medium 904 stores one or more layout schemes 909 corresponding to one or more layout schemes disclosed herein.

[0073] The EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 902.

[0074] The EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914, to which one or more other computer systems are connected. The network interface 912 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more systems 900.

[0075] System 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, a library of standard cells, and / or other parameters for processing by processor 902. The information is transmitted to processor 902 via bus 908. EDA system 900 is configured to receive UI-related information via I / O interface 910. This information is stored as a user interface (UI) 942 in computer-readable media 904.

[0076] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application for processor execution. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by an EDA system 900. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS or other suitable layout generation tools.

[0077] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards; and the like.

[0078] FIG10 is a block diagram of an IC manufacturing system 1000 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a layer of semiconductor integrated circuit.

[0079] In Figure 10, the IC manufacturing system 1000 includes entities such as design room 1020, enclosure room 1030, and IC manufacturer / fab 1050, which interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 1060. The entities in system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1020, enclosure room 1030, and IC manufacturer 1050 are owned by a single larger company. In some embodiments, two or more of the design room 1020, enclosure room 1030, and IC manufacturer 1050 coexist in a common facility and use common resources.

[0080] The design studio (or design team) 1020 generates an IC design layout 1022 (e.g., a layout plan). The IC design layout 1022 includes various geometric patterns designed for an IC device 1060. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers constituting various components of the IC device 1060 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 1022 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads to be formed in and on various material layers of a semiconductor substrate (e.g., a silicon wafer). The design studio 1020 performs appropriate design procedures to form the IC design layout 1022. The design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout 1022 is presented in one or more files containing geometric pattern information. For example, IC design layout diagram 1022 can be expressed in GDSII file format or DFII file format.

[0081] Mask room 1030 includes data preparation 1032 and mask fabrication 1044. Mask room 1030 uses IC design layout 1022 to fabricate one or more masks 1045 for fabricating various layers of IC device 1060 according to IC design layout 1022. Mask room 1030 performs mask data preparation 1032, in which IC design layout 1022 is converted into a representative data file ("RDF"). Mask data preparation 1032 provides RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (network) 1045 or a semiconductor wafer 1053. Design layout 1022 is manipulated by mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturer 1050. In Figure 10, the mask data preparation 1032 and the mask manufacturing 1044 are shown as separate elements. In some embodiments, the mask data preparation 1032 and the mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0082] In some embodiments, the mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that can produce self-diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 1022. In some embodiments, the mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, and combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0083] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks the IC design layout 1022, which has been processed in the OPC, using a set of mask creation rules. This set of mask creation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for lithographic implementation effects during mask fabrication 1044, potentially reversing some modifications performed by the OPC to satisfy the mask creation rules.

[0084] In some embodiments, mask data preparation 1032 includes lithography process checking (LPC), which simulates the processes that IC manufacturer 1050 will implement to manufacture IC device 1060. The LPC simulates this process based on IC design layout 1022 to create a simulated manufactured device, such as IC device 1060. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the shape of the simulated device is not close enough to conform to design rules, OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0085] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1022 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in a variety of different sequences.

[0086] After mask data preparation 1032 and during mask manufacturing 1044, a mask 1045 or a set of masks 1045 is manufactured based on a modified IC design layout 1022. In some embodiments, mask manufacturing 1044 includes performing one or more lithography exposures based on the IC design layout 1022. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on the mask (photomask or marker) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1045. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in opaque areas of the binary mask. In another example, mask 1045 is formed using a phase-shifting technique. In a phase-shift mask (PSM) version of mask 1045, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 1044 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0087] IC manufacturer 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry enterprise.

[0088] IC manufacturer 1050 includes manufacturing tool 1052 configured to perform various manufacturing operations on semiconductor wafer 1053, such that IC device 1060 is manufactured according to a mask (e.g., mask 1045). In various embodiments, manufacturing tool 1052 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as described herein.

[0089] IC manufacturer 1050 uses a mask 1045 manufactured by mask chamber 1030 to manufacture IC device 1060. Therefore, IC manufacturer 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC manufacturer 1050 using mask 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent manufacturing steps).

[0090] In one aspect, a method of forming an IC device layout plan includes obtaining a layout of a plurality of digital circuit cells in a layout plan region, obtaining an initial layout of one or more thermally sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers in the layout plan, and obtaining a routing plan indicating conductive paths for connecting pins of the plurality of digital circuit cells through the plurality of metallization layers and the plurality of via layers, the routing plan being based on clock tree synthesis and the initial layout of one or more thermally sensing resistor cells. The method further includes performing thermal analysis based on the layout of the plurality of digital circuit cells and the routing plan to identify one or more regions of interest in the layout plan region, and obtaining a fine layout of one or more thermally sensing resistor cells such that the one or more thermally sensing resistor cells are respectively located above one or more regions of interest in the layout plan region. The method further includes storing an IC device layout plan containing the layout of the plurality of digital circuit cells, the routing plan, and the fine layout of one or more thermally sensing resistor cells in the memory of a processing device.

[0091] In one aspect, processing means for forming an IC device layout plan includes a memory and processing circuitry coupled to the memory. The processing circuitry is configured to obtain a layout of a plurality of digital circuit cells in a region of the layout plan, obtain an initial layout of one or more thermally sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan, and obtain a routing plan indicating conductive paths for connecting pins of the plurality of digital circuit cells through the plurality of metallization layers and the plurality of via layers, the routing plan being based on clock tree synthesis and the initial layout of one or more thermally sensing resistor cells. The processing circuitry is further configured to perform thermal analysis based on the layout of the plurality of digital circuit cells and the routing plan to identify one or more regions of interest in the region of the layout plan, and obtain a fine layout of one or more thermally sensing resistor cells such that the one or more thermally sensing resistor cells are respectively located above one or more regions of interest in the region of the layout plan. The processing circuitry is further configured to store in the memory an IC device layout plan including the layout of the plurality of digital circuit cells, the routing plan, and the fine layout of one or more thermally sensing resistor cells.

[0092] In one aspect, a non-transitory computer-readable storage medium stores instructions that, when executed by processing circuitry of a processing device, cause the processing device to obtain a layout of a plurality of digital circuit units in a layout planning region of an IC device, obtain an initial layout of one or more thermal sensing resistor units in a subset of a plurality of metallization layers and a subset of a plurality of via layers in the layout planning, and obtain a routing plan indicating conductive paths for connecting pins of the plurality of digital circuit units through the plurality of metallization layers and the plurality of via layers, the routing plan being based on clock tree synthesis and the initial layout of one or more thermal sensing resistor units. When executed by processing circuitry of the processing device, the instructions further cause the processing device to perform thermal analysis based on the layout and routing plan of the plurality of digital circuit units to identify one or more regions of interest in the layout planning region, and obtain a fine layout of one or more thermal sensing resistor units such that the one or more thermal sensing resistor units are respectively located above one or more regions of interest in the layout planning region. When the instruction is executed by the processing circuitry of the processing device, it further causes the processing device to store in its memory an IC device layout plan that includes the layout and routing plan of multiple digital circuit units and the fine layout of one or more thermal sensing resistor units.

[0093] In one aspect, the IC device includes a plurality of digital circuit blocks in an IC device region and a temperature sensor. The temperature sensor includes driving circuitry in the IC device region, one or more thermal sensing resistors located above the IC device region, a subset of a plurality of metallization layers of the IC device and a subset of a plurality of via layers of the IC device, and conductive circuitry for coupling a terminal of one or more thermal sensing resistors to the temperature sensor. The conductive circuitry is located in one or more metallization layers above one or more thermal sensing resistors.

[0094] The features of several embodiments or examples have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity. FIG1A is a block diagram of a semiconductor device according to some embodiments. FIG1B is a simplified plan view of a semiconductor device according to some embodiments. FIG2 is a cross-sectional view of a semiconductor device according to some embodiments. FIG3 is a circuit diagram of a temperature sensor according to some embodiments. FIG4A and 4B are simplified plan views of a semiconductor device according to some embodiments. FIG5 is a cross-sectional view of a semiconductor device having a thermal sensing resistor formed in a metallization layer according to some embodiments. FIG6A to FIG6E are layout diagrams of various thermal sensing resistor unit examples according to some embodiments. FIG7 is a process flowchart of at least a portion of the integrated circuit (IC) design flow of the digital area of ​​a semiconductor device according to some embodiments. FIG8 is a flowchart of a method for forming an integrated circuit device layout plan according to some embodiments. FIG9 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Figure 10 is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing process according to some embodiments.

Claims

1. A method for forming a layout plan for an integrated circuit (IC) device, comprising: Obtain the layout of multiple digital circuit units in the area of ​​the layout plan; The process involves: obtaining an initial layout of one or more thermally sensing resistor cells from a subset of multiple metallization layers and a subset of multiple via layers in the layout plan, the initial layout being located above the region of the layout plan; obtaining a wiring plan based on clock tree synthesis and the initial layout of the one or more thermally sensing resistor cells, indicating conductive paths for connecting pins of the multiple digital circuit units through the multiple metallization layers and the multiple via layers; performing thermal analysis based on the layout of the multiple digital circuit units and the wiring plan to identify one or more regions of interest in the region of the layout plan; obtaining a fine layout of the one or more thermally sensing resistor cells such that the one or more thermally sensing resistor cells are respectively located above the one or more regions of interest in the region of the layout plan; and storing the layout plan of the IC device in the memory of the processing device, the layout plan including the layout of the multiple digital circuit units, the wiring plan, and the fine layout of the one or more thermally sensing resistor cells.

2. The method of claim 1, wherein at least one of the one or more thermal sensing resistor units corresponds to forming: a first plurality of conductive lines in a metallization layer along a first direction; a second plurality of conductive lines in another metallization layer along a second direction; and a plurality of via structures connecting the first plurality of conductive lines and the second plurality of conductive lines to form a first conductive strip extending back and forth along the first direction, a conductive mesh, a conductive trapezoidal mesh, a second conductive strip extending in a zigzag manner along a diagonal direction different from the first direction and the second direction, or a modified trapezoidal mesh having branches.

3. The method as described in claim 1, further comprising: Obtain the layout of the drive circuit block in the region of the layout plan, wherein the drive circuit block and one of the one or more thermal sensing resistor units correspond to the formation of a portion of the temperature sensor block, the wiring plan includes a conductive path for coupling a terminal of the one or more thermal sensing resistor units to the drive circuit block, and the conductive path is located in one or more metallization layers above the one or more thermal sensing resistor units.

4. A processing apparatus for forming a layout plan for an integrated circuit (IC) device, comprising: Memory; And processing circuitry, coupled to the memory and configured to: acquire the layout of multiple digital circuit units in the area of ​​the layout plan; The process involves: obtaining an initial layout of one or more thermally sensing resistor cells located above the region of the layout plan, from a subset of the plurality of metallization layers and a subset of the plurality of via layers of the layout plan; obtaining a routing plan indicating conductive paths for connecting pins of the plurality of digital circuit units through the plurality of metallization layers and the plurality of via layers, based on clock tree synthesis and the initial layout of the one or more thermally sensing resistor cells; performing thermal analysis based on the layout of the plurality of digital circuit units and the routing plan to identify one or more regions of interest in the region of the layout plan; obtaining a fine layout of the one or more thermally sensing resistor cells such that the one or more thermally sensing resistor cells are respectively located above the one or more regions of interest in the region of the layout plan; and storing in memory the layout plan of an IC device comprising the layout of the plurality of digital circuit units, the routing plan, and the fine layout of the one or more thermally sensing resistor cells.

5. The processing apparatus of claim 4, wherein the processing circuitry is configured to acquire cell information indicating that the subset of the plurality of metallization layers of the layout plan corresponds to the formation of conductive lines in the back-end process (BEOL).

6. The processing apparatus of claim 4, wherein the processing circuitry is further configured to: obtain a layout of a drive circuit block in the region of the layout plan; and obtain the wiring plan including a conductive path for coupling a terminal of one of the one or more thermal sensing resistor units to the drive circuit block, wherein the drive circuit block and the one of the one or more thermal sensing resistor units correspond to a portion of a temperature sensor block, and the conductive path is located in one or more metallization layers above the one of the one or more thermal sensing resistor units.

7. A non-transitory computer-readable storage medium storing instructions, when executed by processing circuitry of a processing device, causing the processing device to: acquire a layout of a plurality of digital circuit units in a region of a layout plan for an integrated circuit (IC) device; acquire an initial layout of one or more thermally sensing resistor units located above the region of the layout plan, in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; acquire, based on clock tree synthesis and the initial layout of the one or more thermally sensing resistor units, a wiring plan indicating conductive paths for connecting pins of the plurality of digital circuit units through the plurality of metallization layers and the plurality of via layers; perform thermal analysis based on the layout of the plurality of digital circuit units and the wiring plan to identify one or more regions of interest in the region of the layout plan; acquire a fine layout of the one or more thermally sensing resistor units such that the one or more thermally sensing resistor units are respectively located above the one or more regions of interest in the region of the layout plan; and store in memory of the processing device the layout plan of the IC device, including the layout of the plurality of digital circuit units, the wiring plan, and the fine layout of the one or more thermally sensing resistor units.

8. The non-transitory computer-readable storage medium as claimed in claim 7, wherein the instructions, when executed by the processing circuitry of the processing device, further cause the processing device to acquire cell information indicating that a subset of the plurality of metallization layers of the layout corresponds to the formation of conductive lines in a back-end process (BEOL), and that the subset of the plurality of metallization layers of the layout corresponds to one or more of a fourth, fifth, or sixth metallization layer located above the plurality of digital circuit cells.

9. The non-transitory computer-readable storage medium as claimed in claim 7, wherein the instructions, when executed by the processing circuitry of the processing device, further cause the processing device to acquire cell information, the cell information indicating that at least one of the one or more thermal sensing resistor cells corresponds to forming: a first plurality of conductive lines in a metallization layer along a first direction; a second plurality of conductive lines in another metallization layer along a second direction; and a plurality of via structures connecting the first plurality of conductive lines and the second plurality of conductive lines to form a first conductive strip structure extending back and forth along the first direction, a conductive mesh structure, a conductive trapezoidal mesh, a second conductive strip structure extending in a zigzag manner along a diagonal direction different from the first direction and the second direction, or a modified trapezoidal mesh having branches.

10. The non-transitory computer-readable storage medium of claim 7, wherein the instructions, when executed by the processing circuitry of the processing device, further cause the processing device to: acquire a layout of a drive circuit block in the region of the layout plan; and acquire the wiring plan including a conductive path for coupling a terminal of one of the one or more thermal sensing resistor units to the drive circuit block, wherein the drive circuit block and the one of the one or more thermal sensing resistor units correspond to forming a portion of a temperature sensor block, and the conductive path is located in one or more metallization layers above the one of the one or more thermal sensing resistor units.

Images