Semiconductor layout pattern and manufacturing method thereof

Abstract

This invention provides a semiconductor layout pattern comprising a substrate on which a plurality of ternary content addressable memory (TCAM) cells are disposed, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry, and each TCAM cell comprises a plurality of transistors. The substrate comprises a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein the plurality of gate structures includes a first gate structure connected to a search line SLB and a second gate structure not connected to the search line SLB, wherein the first gate structure and the second gate structure are arranged parallel to each other and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

Claims

1. A semiconductor layout pattern, comprising: a substrate having a plurality of ternary content addressable memory (TCAM) cells thereon, wherein at least two TCAM cells are mirror-symmetrical about each other along an axis of symmetry; wherein each TCAM cell includes a plurality of transistors, the substrate having a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell; and wherein the plurality of gate structures includes a first gate structure connected to a search line and a second gate structure not connected to the search line, wherein the first gate structure and the second gate structure are arranged parallel to each other, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

2. The semiconductor layout pattern as described in claim 1, wherein an extension direction of the axis of symmetry is parallel to an extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to an extension direction of each of the gate structures.

3. The semiconductor layout pattern as described in claim 1, wherein each TCAM unit includes two six-transistor layout patterns and a comparison logic circuit, wherein each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2), and a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure included in the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

4. The semiconductor layout pattern as described in claim 3, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

5. The semiconductor layout pattern as described in claim 3, wherein the plurality of gate structures further includes a third gate structure that spans the fin structure and forms the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

6. The semiconductor layout pattern as described in claim 1, wherein the layout pattern includes a first metal layer (M1) including a plurality of metal wires, and a first metal wire included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire included in the first metal layer (M1) is electrically connected to the first gate structure via a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire.

7. The semiconductor layout pattern as described in claim 6, wherein the first metal wire is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

8. The semiconductor layout pattern as described in claim 7, wherein, in a cross-sectional view, the first layer contact plug (V1) is located above the first metal conductor, and there is no contact plug directly below the first metal conductor.

9. The semiconductor layout pattern as described in claim 6, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and an extension direction of the first metal wire is parallel to an extension direction of the axis of symmetry.

10. The semiconductor layout pattern as described in claim 1, further comprising a plurality of dummy fin structures located on the substrate, and some of the dummy fin structures located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

11. A method for fabricating a semiconductor layout pattern, comprising: providing a substrate; forming a plurality of ternary content addressable memory (TCAM) cells on the substrate, wherein the layout of at least two TCAM cells is mirror-symmetrical about each other along an axis of symmetry; wherein each TCAM cell includes a plurality of transistors, the substrate includes a plurality of fin structures arranged in a Y direction and a plurality of gate structures arranged in an X direction, wherein some of the gate structures span the fin structures and constitute the plurality of transistors of the TCAM cell; and wherein the plurality of gate structures includes a first gate structure connected to a search line and a second gate structure not connected to the search line, wherein the first gate structure and the second gate structure are arranged parallel to each other, and the first gate structure does not overlap with the axis of symmetry, while the second gate structure overlaps with the axis of symmetry.

12. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein an extension direction of the axis of symmetry is parallel to an extension direction of each of the fin structures, and the extension direction of the axis of symmetry is perpendicular to an extension direction of each of the gate structures.

13. The method for fabricating a semiconductor layout pattern as described in claim 11, wherein each TCAM unit includes two six-transistor layout patterns and a comparison logic circuit, wherein each six-transistor layout pattern includes: a first pull-up transistor (PU1) and a first pull-down transistor (PD1) forming a first inverter (INV1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) forming a second inverter (INV2), and a first transmission gate transistor (PG1) and a second transmission gate transistor (PG2) connecting the first inverter and the second inverter; the comparison logic circuit includes a first transistor T1 and a second transistor T2 connected in series, and a third transistor T3 and a fourth transistor T4 connected in series, wherein the gate structure included in the second transistor T2 is connected to the gate structure of the second pull-down transistor (PD2).

14. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the first gate structure spans a portion of the fin structure and constitutes the first transistor T1, and the second gate structure does not span the fin structure.

15. The method for fabricating a semiconductor layout pattern as described in claim 13, wherein the plurality of gate structures further includes a third gate structure that spans the fin structure and constitutes the second transistor T2, wherein the third gate structure and the second gate structure are aligned with each other in the X direction.

16. The method for fabricating a semiconductor layout pattern as described in claim 11, further comprising forming a first metal layer (M1) including a plurality of metal wires, wherein a first metal wire included in the first metal layer (M1) overlaps with the axis of symmetry, and a second metal wire included in the first metal layer (M1) is electrically connected to the first gate structure via a zero-layer contact plug (V0), wherein, from a cross-sectional view, the zero-layer contact plug (V0) is located below the second metal wire.

17. The method for fabricating a semiconductor layout pattern as described in claim 16, wherein the first metal wire is electrically connected to a second metal layer (M2) via a first contact plug (V1) and connected to a voltage source (Vss).

18. The method for fabricating a semiconductor layout pattern as described in claim 17, wherein, in a cross-sectional view, the first layer of contact plug (V1) is located above the first metal wire, and there is no contact plug directly below the first metal wire.

19. The method for fabricating a semiconductor layout pattern as described in claim 16, wherein the first metal wire and the second metal wire are parallel to each other, the first metal wire and the second metal wire are adjacent to each other, and an extension direction of the first metal wire is parallel to an extension direction of the axis of symmetry.

20. The method for fabricating a semiconductor layout pattern as described in claim 11, further comprising forming a plurality of dummy fin structures on the substrate, and some of the dummy fin structures being located between the fin structures, wherein the width and height of the dummy fin structures are smaller than the width and height of the fin structures.

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