Semiconductor memory devices

Abstract

In this embodiment, the plurality of memory cells correspond to the intersections of the plurality of word lines and the plurality of bit lines, and are constructed using oxide semiconductors. A word line control circuit activates or deactivates the first word line selected according to the voltage change of the first word line. A sense amplifier circuit detects and latches the data of the plurality of first memory cells connected to the first word line. A readout circuit continuously reads the data latched to the sense amplifier circuit to the outside according to the plurality of second addresses. During the readout operation, after the first word line is activated, the sense amplifier circuit latches the data of the plurality of first memory cells. Before the readout circuit finishes continuously reading the data of the plurality of first memory cells from the sense amplifier according to the plurality of second addresses, the word line control circuit deactivates the first word line.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Previous Technology]

[0002] In DRAM (Dynamic Random Access Memory), memory cells are composed of capacitors and transistors. Research on the use of oxide semiconductors for the transistors of this type of memory cell is ongoing.

[0003] However, there is a problem that the threshold voltage of transistors using oxide semiconductors varies significantly due to high temperature conditions or voltage application. [Summary of the Invention]

[0004] A semiconductor memory device is provided that suppresses the fluctuation of the threshold voltage of the transistor of the memory cell and has high reliability.

[0005] The semiconductor memory device of this embodiment includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells are arranged at intersections with the plurality of word lines and bit lines, and are constructed using oxide semiconductors. A word line control circuit activates or deactivates a first word line selected from the plurality of word lines according to a first address. A sense amplifier circuit is connected to the plurality of bit lines and detects and latches data of the plurality of first memory cells connected to the first word line. A readout circuit reads the data latched by the sense amplifier circuit to the outside according to a plurality of second addresses. During the readout operation, after the first word line is activated, the sense amplifier circuit latches the data of the plurality of first memory cells. Before the readout circuit finishes the continuous readout operation of continuously reading data of the plurality of first memory cells from the sense amplifier according to the plurality of second addresses, the word line control circuit deactivates the first word line.

Implementation Method

[0007] Hereinafter, embodiments of the present invention will be described with reference to drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual. In the specification and drawings, the same symbols are used for the same elements.

[0008] (First Embodiment) Figure 1 is a block diagram showing an example of the configuration of the memory device 100 according to the first embodiment. The memory device 100 of the first embodiment is, for example, DRAM (Dynamic Random Access Memory).

[0009] The memory device 100, as a semiconductor memory device, is electrically connected to an external memory controller 200. The memory device 100 is configured to read and write data based on commands from the memory controller 200. For example, the memory device 100 receives an address (ADR), an instruction (CMD), data (DQ), and a control signal (CNT) from the memory controller 200. Furthermore, the memory device 100 sends the control signal CNT and the data DQ to the memory controller 200. The memory device 100 includes, for example, a memory cell array 110, a column control circuit 120, a row control circuit 130, a read / write circuit 140, an input / output circuit 150, and a control circuit 160.

[0010] The memory cell array 110 is a circuit used for storing data. The memory cell array 110 includes a plurality of subarrays 111. The plurality of subarrays 111 are classified, for example, into groups of two subarrays 111. The plurality of subarrays 111 includes a first subarray 111A and a second subarray 111B corresponding to groups of two subarrays 111. Furthermore, each subarray 111 includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL. Each memory cell MC can store more than one bit of data. Each memory cell MC is correspondingly arranged at the intersection of one word line WL and one bit line BL, and connected between them. Column addresses are assigned to each word line WL. Row addresses are assigned to each bit line BL. Each memory cell MC can be specified by column addresses and row addresses.

[0011] The column control circuit 120, acting as a character line control circuit, controls the wiring (e.g., character lines WL) allocated to the column direction in the memory cell array 110. The column control circuit 120 selects at least one character line WL (activated) from a plurality of character lines WL according to the column address in the address ADR. Furthermore, the column control circuit 120 sets the unselected character lines WL to a non-selected state (deactivated). The column control circuit 120 applies a predetermined voltage to each of the selected and unselected character lines WL. The column control circuit 120 includes, for example, a driver circuit 121 and an address decoder 122. The driver circuit 121 generates a voltage applied to the character line WL. The address decoder 122 decodes the column address. The column control circuit 120 selects a character line WL based on the decoding result of the address decoder 122. Alternatively, the column control circuit 120 may be referred to as a column decoder.

[0012] The row control circuit 130 controls the wiring (e.g., bit lines BL) allocated to the row direction in the memory cell array 110. The row control circuit 130 includes, for example, an address decoder 131, a row selection circuit 132, and a sense amplifier circuit 133. The address decoder 131 decodes the row address in the address ADR. The sense amplifier circuit 133 is provided for each subarray and connected to the bit lines BL contained in the subarray. The sense amplifier circuit 133 includes a plurality of sense amplifiers SA corresponding to the number of subarrays and the number of bit lines BL contained in the subarrays. The bit lines BL can be configured as open-BL or as Folded-BL.

[0013] During the read operation, when the word line WL selected by the column control circuit 120 is activated, the data stored in the plurality of memory cells MC connected to the selected word line WL is transferred to the corresponding bit lines BL of each row. The sense amplifier circuit 133 of each row detects (amplifies) the voltage change of its corresponding bit line BL and latches it. On the other hand, since the data in the memory cell MC is lost due to the data read, the sense amplifier circuit 133 writes (restores) the original data back to the memory cell MC by amplifying and latching the voltage. This read and restore operation is performed simultaneously on the bit lines BL of all rows contained in the selected subarray. Furthermore, the row selection circuit 132 outputs the data of one or more row bit lines BL selected according to the row address from all the data of all rows latched by the sense amplifier circuit 133 to the read / write circuit 140.

[0014] On the other hand, during the write operation, when the read / write circuit 140 receives write data, the row selection circuit 132 transmits the write data to the sense amplifier SA of the row selected according to the row address. The selected sense amplifier SA latches the write data and transmits the write data to the bit line BL. Thereby, the sense amplifier SA writes updated data to the memory cell MC. Additionally, the row control circuit 130 may be referred to as a sense amplifier or a row decoder.

[0015] The read / write circuit 140 is a circuit capable of reading data from and writing data to the memory cell array 110. During the data read operation, the read / write circuit 140 independently controls the circuit 130 to receive the read data (voltage or current) latched by the sense amplifier circuit 133. At this time, the read / write circuit 140 continuously reads the data latched by the sense amplifier circuit 133 to the outside according to a plurality of consecutively issued row addresses (burst read).

[0016] During data writing, the read / write circuit 140 receives the write data (voltage or current) to the memory cell array 110 from the outside via the input / output circuit 150 and sends it to the sense amplifier circuit 133 of the row control circuit 130. At this time, the read / write circuit 140 causes the sense amplifier circuit 133 to continuously latch the write data (burst write) according to a plurality of consecutively issued row addresses. Alternatively, the write circuit and the read circuit can be configured independently.

[0017] The input / output circuit 150 is an interface circuit between the memory device 100 and the memory controller 200. The input / output circuit 150 receives instructions CMD, address ADR, data DQ (e.g., write data) and control signals CNT from the memory controller 200. The input / output circuit 150 sends control signals CNT and data DQ (e.g., read data) to the memory controller 200.

[0018] The control circuit 160, based on the instruction CMD and control signal CNT, controls the column control circuit 120, row control circuit 130, read / write circuit 140, etc. When the memory device 100 is DRAM, the control circuit 160, in addition to writing and reading data, also performs a refresh operation on the data within the memory cell array 110. The refresh operation involves sequentially activating multiple word lines WL according to the column address, temporarily reading out the data stored in each memory cell MC and latching it in the sense amplifier circuit 133, and then writing (restoring) the data back to the memory cell MC. Furthermore, the control circuit 160 controls the column control circuit 120, row control circuit 130, read / write circuit 140, etc., in a timing sequence synchronized with the clock signal CLK. That is, in the memory device 100, data writing and data reading are performed in a timing sequence synchronized with the clock signal CLK. The clock signal CLK can be generated internally in the memory device 100 or supplied externally. Additionally, the control circuit 160 can be referred to as a sequencer, internal controller, etc.

[0019] Furthermore, the memory device 100 is not limited to the configuration described above. For example, the memory device 100 may include a control circuit for controlling the refresh operation, a clock generation circuit, or an internal voltage generation circuit. The refresh operation is executed by a refresh command generated internally by the memory device 100 or by a signal from outside the memory device 100.

[0020] Next, the circuit configuration of the memory device 100 will be explained.

[0021] Figure 2 is a circuit diagram showing an example of the configuration of the memory cell array 110. Figure 2 shows a portion of the subarray 111 included in the memory cell array 110. The 3D orthogonal coordinate system shown in Figure 2 corresponds to the extension direction of the wiring. A plurality of memory cells MC are arranged in a matrix on a plane including the X and Y directions (XY plane). The memory cells MC can also be arranged in three dimensions in the X, Y, and Z directions. Furthermore, the subarray 111 further includes board lines PL. As in a DRAM with memory cells MC arranged in 2D, the Z direction can be the direction perpendicular to the substrate on which the memory device 100 is disposed. Alternatively, as in a DRAM with memory cells MC arranged in 3D, the X or Y direction can be the direction perpendicular to the substrate.

[0022] The plate line PL is a plate-shaped wiring extending along the XY plane. A plate voltage, such as half the voltage of BL, is applied to the plate line PL. One end of each of the plurality of memory cells MC is connected to the plate line PL. The other end of each of the plurality of memory cells MC is connected to the corresponding bit line BL. The plate line PL can be referred to as a plate electrode or a plate layer. The plate line PL can be divided according to the control unit of the subarray 111.

[0023] Each memory cell (MC) includes a cellular electrophysiological crystal (CT) and a cellular capacitor (CC). The CT and CC of each memory cell (MC) are connected in series between the corresponding bit line (BL) and the plate line (PL). In each memory cell (MC), one of the sources or drains of the CT is connected to the corresponding bit line (BL) among the plurality of bit lines (BL). The other source or drain of the CT is connected to node (ND). The gate of the CT is connected to the corresponding word line (WL) among the plurality of word lines (WL). One electrode of the CC is connected to node (ND) and to the other source or drain of the CT. The other electrode of the CC is connected to the plate line (PL). Cellular electrochemical crystal (CT) uses oxide semiconductor field-effect transistors (FETs) at least in the channel region. Cellular capacitors (CCs) are capacitive elements such as metal-insulator-metal (MIMs). Cellular electrochemical crystal (CT) can be simply referred to as "transistor". Cellular capacitors (CCs) can be simply referred to as "capacitors".

[0024] A cellular electrochemical crystal (CT) is constructed using oxide semiconductors. The channel material of the CT is composed of an oxide semiconductor material, for example, containing n-type or p-type material systems. The channel material may contain all or part of indium, gallium, zinc, and oxygen (e.g., indium gallium zinc oxide (IGZO) form), and such channel material may have n-type conductivity. The channel material may contain, for example, tin and oxygen (e.g., tin oxide form), antimony and oxygen (e.g., antimony oxide form), indium and oxygen (e.g., indium oxide form), indium, tin, and oxygen (e.g., indium tin oxide form), titanium and oxygen (e.g., titanium oxide form), zinc and oxygen (e.g., zinc oxide form), indium, zinc, and oxygen (e.g., indium zinc oxide form), gallium and oxygen (e.g., gallium oxide form), titanium, oxygen, and nitrogen (e.g., titanium oxynitride form), ruthenium and oxygen (e.g., ruthenium oxide form), or tungsten and oxygen (e.g., tungsten oxide form). The thickness of the channel material is, for example, 5 nanometers to 30 nanometers.

[0025] The material constituting the channel region of the cellular electrophysiological CT is preferably a crystalline oxide semiconductor, but it can also be an amorphous oxide semiconductor. Specific examples of oxide semiconductors include zinc tin oxide (ZTO), IGZO (also known as gallium indium zinc oxide (GIZO)), indium zinc oxide (IZO), ZnOx, InOx, In2O3, SnO2, TiOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaxSiyOz, and other similar materials.

[0026] The multiple word lines WL contained in the subarray 111 extend along the X direction and are arranged in the Y direction. Each word line WL is connected to the gate of the cellular transistor CT of each of the multiple memory cells MC arranged in the X direction. In other words, each word line WL is connected to the gate of the cellular transistor CT of each of the multiple memory cells MC assigned the same column address. In addition, the gate of the cellular transistor CT can be referred to as the "control electrode of the memory cell MC".

[0027] The multiple bit lines BL contained in the subarray 111 extend along the Y direction and are arranged in the X direction. Each bit line BL is connected to the source or drain of the cellular transistor CT of each of the multiple memory cells MC arranged in the Y direction. In other words, each bit line BL is connected to the source or drain of the cellular transistor CT of each of the multiple memory cells MC assigned the same row address.

[0028] The cellular capacitor CT is a switch that switches the state between electrical connection and electrical isolation between the cellular capacitor CC and the bit line BL. The cellular capacitor CT functions as a selection element of the memory cell MC. The cellular capacitor CC maintains the charge amount corresponding to data of one bit or more. The cellular capacitor CC functions as a memory element of the memory cell MC. The cellular capacitor CC is a ferroelectric capacitor and can also be a polarization-retained non-volatile memory.

[0029] Figures 3 and 4 are block diagrams showing an example of the configuration of the sensing amplifier SA and the bit line BL. This embodiment has a configuration of 1 cell / bit, where 1 memory cell MC stores 1 bit of data.

[0030] In Figure 3, memory cells MC are configured at a ratio of one cell at the intersection of two character lines WL and bit lines BL. Within a subarray 111, two adjacent bit lines BL in the Y direction are connected to one sensing amplifier SA. That is, a sensing amplifier SA (composed of folded bit lines) is provided for each pair of bit lines BL within the same subarray 111. In this case, cell data is read out one by one from the two bit lines BL. The sensing amplifier SA compares and detects the data from one pair of bit lines BL with the data from the reference bit line BL of the other pair.

[0031] In Figure 4, the two bit lines BL of each of the two adjacent subarrays 111 in the X direction are connected to a sensing amplifier SA. That is, the sensing amplifier SA is positioned between the two adjacent subarrays 111, configured according to each pair of bit lines BL contained in the two subarrays 111 (open bit line configuration). In this case, the word line WL of either the left or right subarray is selected to read out the data. The sensing amplifier SA compares and detects the data from one pair of bit lines BL with the data from the reference bit line BL of the other.

[0032] The memory device 100 of this embodiment can be constructed using any of the bit lines shown in FIG3 and FIG4.

[0033] Here, the PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability) characteristics of oxide semiconductor transistors will be explained.

[0034] If a positive or negative bias voltage is continuously applied between the gate and drain, or between the gate and source, for a prolonged period of time using an oxide semiconductor transistor, its threshold voltage will fluctuate significantly. For example, if a positive bias voltage is continuously applied to the transistor for a prolonged period of time, the threshold voltage of the transistor will increase with the application time (PBTI characteristic). On the other hand, if a negative bias voltage is continuously applied to the transistor for a prolonged period of time, the threshold voltage of the transistor will decrease with the application time (NBTI characteristic). If the threshold voltage of the cellular transistor CT of the memory cell MC fluctuates significantly, the memory cell MC will not function and will become a defective bit. Therefore, it is preferable to minimize the fluctuation of the threshold voltage of the cellular transistor CT. Furthermore, the aforementioned threshold voltage change occurs due to the capture or release of charge at the interface between the channel region of the oxide semiconductor and the gate insulating film. In cases where the movement of hydrogen ions (H+) is the cause, the polarity of the threshold voltage change is often opposite to that of the capture of charge at the interface.

[0035] If the application of positive or negative bias is stopped and the transistor is set to no bias, the fluctuation of the threshold voltage of the oxide semiconductor transistor will decrease and recover over time. Furthermore, if one of the positive or negative biases is applied to the transistor, and then another bias of opposite polarity is applied, the fluctuation of the threshold voltage will decrease and return to its original direction over time. That is, the PBTI and NBTI characteristics of the oxide semiconductor transistor can be restored by applying a bias of one polarity, stopping the application of that bias, and then applying the opposite bias or setting it to no bias.

[0036] Therefore, although the gate-drain voltage Vgd or gate-source voltage Vgs varies depending on the active and inactive states, the ratio of the activation time to the inactive time of the word line WL (Duty) becomes important in order to prevent the degradation of PBTI and NBTI characteristics. The duty cycle is the ratio of the time when a positive bias is applied to the word line WL to the time when a negative bias is applied (or the time without bias) (activation time / inactive time).

[0037] For example, when the voltages Vgd and Vgs in the active and inactive states are of opposite polarities and have equal absolute values, the duty cycle ratio is preferably 1. This suppresses transistor characteristic degradation (change) by applying equal positive and negative bias voltages to the transistor. Furthermore, in this embodiment, the column control circuit 120 sets the voltage of the non-selection word line WL (other than the selection word line WL1) to be of opposite polarity to the voltage of the selection word line WL1. That is, the voltages of the word line WL in the active and inactive states are set to opposite polarities. This sets the gate-drain voltage Vgd and the gate-source voltage Vgs in the active and inactive states to be of opposite polarities. Therefore, the duty cycle ratio is preferably close to 1.

[0038] When the voltage Vgd or Vgs in the non-active state is unbiased, the duty cycle should preferably be as small as possible. In this way, since the unbiased state of the transistor is prolonged, the degradation of PBTI and NBTI characteristics caused by bias in the active state can be reduced.

[0039] Next, the operation of the memory device 100 will be explained. Hereinafter, we will focus on the bit line BL in the bit line pair that reads data from the memory cell MC and writes it.

[0040] Figure 5 is a timing diagram showing an example of the operation of the memory device 100 according to the first embodiment. In this example, as an example of PBTI characteristic degradation, burst write operations are performed continuously after a burst read operation. The burst read operation is an operation in which the read / write circuit 140 continuously reads the data transferred from the memory cell MC and latched to the sense amplifier circuit 133 to the outside according to a plurality of consecutively issued column addresses. The data read at one time can be 1 bit or a plurality of bit units (e.g., 8 bits). The burst write operation is an operation in which the read / write circuit 140 causes the sense amplifier circuit 133 to continuously latch the write data from the outside according to a plurality of consecutively issued column addresses. The data latched by the sense amplifier circuit 133 follows the latch and is written to the memory cell MC at the column address selected by the bit lines BL of each row. The data written at one time can be 1 bit or a plurality of bit units (e.g., 8 bits).

[0041] The CLK in Figure 5 is a clock signal generated externally or internally and supplied to the control circuit 160. CA specifies the memory bank, column address, row address, etc., using instruction addresses. An instruction (Command) is a control signal that indicates the action (read action, write action, refresh action, etc.) to be performed in the memory cell array 110. DQ displays the data output from the input / output circuit 150 or the data input to the input / output circuit 150.

[0042] (Burst read action) The control circuit 160 synchronizes with the clock signal CLK generated externally or internally to activate the memory device 100.

[0043] When a read instruction (READ) is issued, and the column address of the object to be read is issued, the column control circuit 120 selectively activates the word line WL1 according to the column address. For example, at t1, the column control circuit 120 raises the word line WL1 to a high level voltage. Thereby, corresponding to the column address, a plurality of first memory cells MC connected to the word line WL1 are connected to the corresponding column bit lines BL1 to BLn (n is an integer of 2 or more).

[0044] Data from a plurality of first memory cells are transmitted to corresponding bit lines BL1 to BLn. For example, in t2 to t3 of Figure 5, the voltages of bit lines BL1 to BLn increase or decrease according to the logic of the data from the first memory cells.

[0045] Next, from t3 to t4, the sense amplifier circuit 133 detects (amplifies) the data transmitted to each bit line BL. Furthermore, from t4 to t5, the sense amplifier circuit 133 latches the data transmitted to each bit line BL. At this time, the data of the first memory cell MC of all columns specified by the column address is detected and latched in the sense amplifier circuit 133 almost simultaneously. By amplifying and latching the data by the sense amplifier circuit 133, the same data in each column is written back (restored) to each first memory cell MC via bit lines BL1 to BLn.

[0046] Thus, from t1 to t5, the recovery of the first memory cell MC is terminated by detecting and latching the data of the plurality of memory cells MC connected to the word line WL1 using the sensing amplifier circuit 133. Therefore, in this embodiment, after the sensing amplifier circuit 133 latches the data, the column control circuit 120 deactivates the word line WL1. For example, at t5, the column control circuit 120 lowers the word line WL1 to a low level voltage. This disconnects the plurality of first memory cells MC from the bit lines BL1 to BLn. On the other hand, the sensing amplifier circuit 133 maintains the state of latching the data of the plurality of first memory cells MC.

[0047] The control circuit 160 continuously issues a plurality of row addresses. From t6 to t7, the read / write circuit 140 continuously reads the data DQ latched by the sense amplifier circuit 133 to the outside according to the issued plurality of row addresses. That is, the read / write circuit 140 performs a burst read operation. A burst read operation can be performed as long as the sense amplifier circuit 133 has data latched. Therefore, as long as the sense amplifier circuit 133 restores the data to the first memory cell MC, there is no problem even if the word line WL1 is deactivated during the burst read operation. That is, there is no problem even if the column control circuit 120 deactivates the word line WL1 before t7, when the read / write circuit 140 ends the burst read operation.

[0048] (Burst Write Operation) After issuing the write instruction WRITE, the control circuit 160 continuously issues multiple row addresses.

[0049] From t8 to t11, write data DQ is input from the outside via input / output circuit 150. The read / write circuit 140 causes the sense amplifier circuit 133 to continuously latch the data DQ according to the plurality of row addresses retrieved by instruction address CA. At this time, the write data DQ is transferred to any of the bit lines (BL1 to BLn) connected to the sense amplifier circuit 133 that latches the write data DQ.

[0050] For example, when the sense amplifier SA corresponding to bit line BL1 latches write data DQ, at t9_1, bit line BL1 transmits a voltage according to the write data DQ. In the example of Figure 5, an example of writing data different from the data originally stored in the memory cell is shown. The latched data of the sense amplifier SA corresponding to bit line BL1 is logically inverted, and the data of bit line BL1 is also logically inverted. However, when the latched data of the sense amplifier SA corresponding to bit line BL1 is not inverted, the data of bit line BL1 is not inverted.

[0051] For example, when the sense amplifier SA corresponding to bit line BL2 latches write data DQ, at t9_2, bit line BL2 transmits a voltage according to the write data DQ. In the example of FIG5, the latched data of the sense amplifier SA corresponding to bit line BL2 is also logically inverted, and consequently, the data of bit line BL2 is also logically inverted. However, when the latched data of the sense amplifier SA corresponding to bit line BL2 is not inverted, the data of bit line BL2 is not inverted.

[0052] The data for the other sensing amplifiers SA and bit lines BL3 to BLn are also continuously updated according to the write data DQ. That is, the read / write circuit 140 performs a burst write operation.

[0053] Furthermore, in Figure 5, for convenience, the data of bit lines BL1 to BLn are updated continuously row by row. That is, one row address corresponds to one row of sense amplifier SA and bit line BL. However, one row address can also correspond to multiple rows of sense amplifier SA and bit lines BL. For example, when one row address corresponds to 8 bits of data, the 8 bits of data DQ are latched simultaneously by 8 sense amplifier SA and simultaneously transmitted to their respective 8 bit lines BL.

[0054] With the issuance of the WRITE instruction, the column control circuit 120 selectively activates the word line WL1 according to the column address extracted during the read operation. For example, at t10, the column control circuit 120 raises the word line WL1 to a high level voltage. Accordingly, corresponding to that column address, a plurality of first memory cells MC connected to the word line WL1 are connected to the corresponding row's bit lines BL1 to BLn. Therefore, data on bit lines BL1 to BLn is written to the plurality of first memory cells MC. At t10, there is no problem even if the burst write operation is in progress. When the word line WL1 is activated in the middle of a burst write operation, whenever data is written to the sense amplifier SA of a certain row, that data is written to the first memory cell MC via the bit line BL of that row.

[0055] At t11, at the point when the burst write operation of the sense amplifier circuit 133 ends, the column control circuit 120 maintains the word line WL1 in an active state. Therefore, the data latched by the sense amplifier circuit 133 at the end of the burst write operation can also be written to the first memory cell MC via the bit line BL. That is, during the write operation, at the point when the burst write ends, the column control circuit 120 only needs to activate the word line WL1 specified by the column address.

[0056] At t12, the column control circuit 120 deactivates the word line WL1. From t12 to t13, pre-charging of the bit line BL, etc., is performed.

[0057] Thus, during a burst write operation, if word line WL1 is active when all write data DQ is latched to the sense amplifier circuit 133, the write data DQ can be written to a plurality of first memory cells MC. Therefore, the column control circuit 120 needs to activate word line WL1 before the burst write operation ends, but it can also activate word line WL1 after the burst write operation begins. Furthermore, the column control circuit 120 deactivates word line WL1 after the burst write operation ends.

[0058] As shown in Figure 5, when a READ instruction is followed by a WRITE instruction, at t4, after latching the data of a plurality of first memory cells MC into the sense amplifier circuit 133, the column control circuit 120 keeps the word line WL1 in an inactive state until at least t8 when a burst write operation begins. Furthermore, before the burst write operation ends at t11, the column control circuit 120 activates the word line WL1. That is, the column control circuit 120 pulses the voltage of the word line WL1 according to each READ instruction or WRITE instruction.

[0059] Figure 6 shows the voltage applied to the memory cell MC during the read and write operations of the first embodiment. Figure 7 shows the voltage applied to the memory cell MC in the standby state of the first embodiment. Furthermore, the voltage of the word line WL1 in the inactive state is -1 V to -0.5 V, and the voltage of the word line WL1 in the active state is 2.5 V. Also, the voltage of node ND when data is "0" is 0 V, and the voltage of node ND when data is "1" is 1.2 V. In the standby state, the bit line BL maintains an intermediate voltage of 0.6 V between data "0" and data "1".

[0060] In this situation, as shown in Figure 6, the maximum value of the voltage Vgd or Vgs of the cellular electrophysiological crystal CT becomes 2.5 V when reading or writing data "0". If the state in Figure 6 continues for a long time, the characteristics of the cellular electrophysiological crystal CT will deteriorate due to the PBTI. Furthermore, as shown in Figure 7, the minimum value of the voltage Vgd or Vgs of the cellular electrophysiological crystal CT becomes -2.2 V in the standby state when data "1" is displayed. If the standby state in Figure 7 continues for a long time, the characteristics of the cellular electrophysiological crystal CT will deteriorate due to the NBTI.

[0061] In this example, a maximum positive bias voltage of 2.5 V and a minimum negative bias voltage of -2.2 V are applied to the cellular electrophysiological crystal CT. Thus, when the voltages Vgd and Vgs in the activated and deactivated states have opposite polarities, the duty cycle is preferably close to approximately 1. Therefore, by applying equal positive and negative bias voltages to the crystal, the characteristic degradation of the cellular electrophysiological crystal CT can be suppressed.

[0062] In the memory device 100 of this embodiment, as shown in FIG5, the word line WL1 is activated upon receiving the issuance of the read instruction READ, and deactivated before the end of the burst read operation. The activation period (t1 to t5) of the word line WL1 for the read instruction READ is, for example, 50 ns. Subsequently, the word line WL1 receives the issuance of the write instruction WRITE, and is activated again before the end of the burst write to the sense amplifier circuit 133, becoming activated at the end of the burst write, and deactivated after the burst write ends. The activation period (t10 to t12) of the word line WL1 for the write instruction WRITE is, for example, 50 ns. After the issuance of the read instruction READ, the deactivation period (t5 to t10) from the deactivation of the word line WL1 until the activation of the word line WL1 by the write instruction WRITE is, for example, approximately 1100 ns. After the burst write, the precharge period (t12 to t13) is, for example, approximately 14 ns. This t1 to t13 becomes the unit of continuous read and write operations. In this case, the duty cycle is approximately 0.09 ((50 ns × 2) / (1100 ns + 14 ns)).

[0063] As a comparative example, when continuously issuing READ and WRITE instructions using the previous method, the column control circuit 120 keeps the word line WL1 in an active state during the period from the start of the burst read to the end of the burst write. In this case, the duty cycle (active time / inactive time) becomes very large. Therefore, the threshold voltage of the cellular electrophysiological crystal CT changes significantly, and the characteristic degradation caused by PBTI becomes significant. Applying the above comparative example to the example in Figure 5, when the word line WL1 is continuously kept active from the time the READ instruction activates the word line WL1 (t1) to the time the word line WL1 is deactivated (t12), the duty cycle is approximately 86 ((50 ns × 2 + 1100 ns) / 14 ns)).

[0064] The duty cycle of this embodiment is close to 1 compared with the duty cycle of the comparative example, indicating that the degradation of the PBTI characteristics of the cellular electrophysiological crystal CT is suppressed.

[0065] Next, referring to FIG5, the case of issuing a read instruction READ or a write instruction WRITE separately will be described.

[0066] For example, in the case of issuing a read instruction READ alone, similar to t1 to t5 in Figure 5, the column control circuit 120 activates the word line WL1, and after the sense amplifier circuit 133 latches the data, it deactivates the word line WL1. The activation time of the word line WL1 is, for example, 50 ns. Subsequently, the sense amplifier circuit 133 performs a burst read of the data and enters the precharge operation. The burst read period depends on the number of row addresses issued, and the shortest is only one row address read (for example, 8 ns). Furthermore, the precharge operation is the same as the period of t12 to t13, for example, set to 14 ns. In this case, the deactivation time of the word line WL1 is, for example, 22 ns (8 ns + 14 ns). Therefore, the duty cycle becomes approximately 2.3 (50 ns / (8 ns + 14 ns)). Thus, even with a relatively large duty cycle, it is only about 2.3, which is very small compared to Comparative Example 86 and close to 1. Therefore, it can be seen that the characteristic degradation of the cellular electrochemical crystal CT caused by PBTI is suppressed. As a result, the lifetime of the memory cell MC can be extended, and the reliability of the memory device 100 can be improved.

[0067] (Second Embodiment) Figure 8 is a timing diagram showing an example of the operation of the memory device 100 according to the second embodiment. In the second embodiment, the column control circuit 120 makes the voltage of the word line WL1 during the data detection period t1 to t2_1 of the sense amplifier circuit 133 during the read operation lower than the voltage of the word line WL1 during the data latching period t2_1 to t5 of the sense amplifier circuit 133 and restoring the data to the memory cell MC. The voltage of the word line WL1 during the data detection period t1 to t2_1 is, for example, 1.3 V. The voltage of the word line WL1 during the data latching period t2_1 to t5 of the sense amplifier circuit 133 and restoring the data to the memory cell MC is, for example, 2.5 V. The reason why the voltage of the word line WL1 during the read operation can be lower than the voltage of the word line WL1 during the write operation is as follows. If the operation is only for reading data from memory cell MC to sense amplifier SA, the potential of word line WL can be relatively low. In contrast, during the write operation, data "1" that raises the potential of the bit line needs to be written to memory cell MC. Furthermore, the potential of word line WL needs to be at least a threshold voltage above the potential of bit line BL. Therefore, the voltage of word line WL1 during the read operation can be lower than the voltage of word line WL1 during the write operation. Additionally, if the potential of bit line BL in standby mode drops to 0 V, the potential of word line WL during read can be further reduced. The column control circuit 120 sets the voltage of the first word line up until the sense amplifier circuit latches the data of the plurality of first memory cells to a voltage lower than the voltage of the second word line after latching the data of the plurality of first memory cells.

[0068] As described above, in order to suppress the characteristic degradation caused by PBTI, it is preferable to make the duty cycle close to or decrease to 1. Furthermore, in order to suppress the characteristic degradation caused by PBTI, the bias voltage (voltage Vgd, Vgs) applied to the cellular electrophysiological crystal CT can be decreased.

[0069] For example, if the voltage of the character line WL1 shown in Figure 6 is set from 2.5 V to 1.3 V, then the voltage Vgd or Vgs will drop from 2.5 V to 1.3 V. In this way, the characteristic degradation of the cellular electrophysiological crystal CT caused by PBTI can be suppressed.

[0070] If the word line WL1 of t1 to t2_1 is set to an inactive state, the duty cycle when continuously issuing the READ and WRITE instructions is approximately 0.07 ((25 ns + 50 ns) / (1100 ns + 25 ns + 14 ns)). This is because the reliability of applying 1.3 V is significantly improved compared to applying 2.5 V.

[0071] When the READ instruction or WRITE instruction is issued separately, the duty cycle when reading only one line address is approximately 0.53 (25 ns / (25 ns+8 ns+14 ns)).

[0072] In the second embodiment, the value is also very small compared to 86 in the comparative example, and is close to 1. Therefore, according to the second embodiment, the characteristic degradation of cellular electrophysiological crystal CT caused by PBTI can be suppressed. The configuration and other operations of the second embodiment are the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effect as the first embodiment.

[0073] (Third Embodiment) FIG9 is a block diagram showing an example of the configuration of the memory device 100 according to the third embodiment. The memory device 100 of the third embodiment further includes a cache memory 170. The cache memory 170 temporarily holds the data read from the read / write circuit 140 with the column address and row address of the first memory cell MC where the data is stored. Furthermore, when the control circuit 160 reads data from the first memory cell MC at the same column address and row address, the control circuit 160 reads the data held in the cache memory 170 to the outside.

[0074] This reduces the number of accesses to the same first memory cell MC. In the comparative example above, according to the previous method, when issuing READ and WRITE instructions consecutively, the character line WL1 is continuously kept active during the period from the start of the burst read to the end of the burst write. Even in this case, the duty cycle can be reduced by reducing the number of accesses. Therefore, according to the third embodiment, it helps to suppress the characteristic degradation caused by PBTI.

[0075] The structure and other actions of the third embodiment may be the same as those of the first embodiment. Alternatively, the other actions of the third embodiment may also be the same as those of the comparative example described above.

[0076] (Fourth Embodiment) Figure 10 is a timing diagram showing the refresh operation of the memory device 100 in the fourth embodiment. In the refresh operation of the fourth embodiment, after the data of a plurality of first memory cells MC is latched into the sense amplifier circuit 133, the data is logically inverted and written back (restored) to the plurality of first memory cells MC. In the memory device 100 such as DRAM, even in the standby state, the charge of the cell capacitor CC disappears over time. Therefore, in order to maintain the data, the memory device 100 needs to perform a refresh operation periodically in the standby state.

[0077] In the fourth embodiment, the memory device 100 performs a refresh operation once every 100 ms in standby mode, for example. The refresh operation period is, for example, 64 ns, which is negligible compared to the refresh operation period. Therefore, in standby mode, the bias voltage (Vgd, Vgs) applied to the cellular transistor CT depends on the data stored in the memory cell MC (the voltage of node ND).

[0078] For example, as shown in Figure 7, when the memory cell MC stores data "1" and the voltage of node ND is 1.2 V, the bias voltage applied to the cellular electrophysiological crystal CT is -2.2 V. On the other hand, when the memory cell MC stores data "0" and the voltage of node ND is 0 V, the bias voltage applied to the cellular electrophysiological crystal CT is -1 V. Therefore, the degradation of the NBTI characteristics of the cellular electrophysiological crystal CT storing data "1" is more severe than that of the cellular electrophysiological crystal CT storing data "0".

[0079] Here, during the refresh operation, when writing back the data of the first memory cell MC in a non-reverse state, the memory cell MC of data "1" is continuously subjected to a bias voltage of -2.2 V in the standby state. If the standby state is maintained for a long time, the duty cycle on the negative bias side becomes very large, and the threshold voltage of the cellular electrophysiological crystal CT drops significantly. That is, the characteristics of the NBTI of the cellular electrophysiological crystal CT deteriorate significantly.

[0080] To suppress the degradation of the NBTI characteristics of this type of cellular electro-acoustic crystal CT, in the fourth embodiment, during the refresh operation, the data latched in the sensing amplifier circuit 133 is logically inverted and written back (restored) to the first memory cell MC. The refresh operation is an operation that sequentially specifies the column addresses within the subarray and restores the data corresponding to a plurality of first memory cells MC for each column address. The refresh operation is completed by performing it on all column addresses within the subarray. In addition, in Figure 10, for convenience, the voltages of word line WL1, bit line BL, and node ND are shown one by one.

[0081] For example, in the example of Figure 10, before t1, the first memory cell MC stores the data "0" shown by the solid line.

[0082] At t1, for the refresh operation, the column control circuit 120 activates the word line WL1 corresponding to a certain column address. Hereby, the data stored in the first memory cell MC is transferred to the bit line BL. When the first memory cell MC stores data "0" (solid line), the voltage of node ND (e.g., 0 V) ​​is transferred to the bit line BL. When the first memory cell MC stores data "1" (dashed line), the voltage of node ND (e.g., 1.2 V) is transferred to the bit line BL.

[0083] The sensing amplifier circuit 133 detects and latches the data of each first memory cell MC via the bit line BL.

[0084] At t2, the read / write circuit 140 reverses the data of each first memory cell MC latched by the sense amplifier circuit 133. The reversed data is latched by the sense amplifier circuit 133, and each first memory cell MC stores the reversed data.

[0085] At t3, after the data of each of the plurality of first memory cells MC corresponding to the column address is inverted in the sensing amplifier circuit 133, the column control circuit 120 deactivates the word line WL1 corresponding to the column address. In this way, the refresh operation of the column address ends.

[0086] Although not illustrated, the memory device 100 then performs a refresh operation on the plurality of memory cells MC of the next column address.

[0087] Thus, by performing a refresh operation on all memory cells MC of all column addresses in the order of column addresses, one refresh operation is completed.

[0088] Subsequently, after remaining in standby mode for approximately 100 ms, the next refresh operation is performed. In the next refresh operation, the inverted data stored in each memory cell (MC) is further inverted. Therefore, each memory cell (MC) stores the original data (non-inverted data).

[0089] Thus, in the fourth embodiment, whenever a refresh operation is performed, the data in each memory cell (MC) is reversed and written back. Therefore, in standby mode, each memory cell (MC) stores approximately 50% of the data "1" and data "0". That is, the duty cycle of data "1" and "0" becomes almost 1. As a result, it helps to suppress characteristic degradation caused by NBTI.

[0090] In the example of Figure 10, the voltages applied to the cellular electrophysiological crystal CT are negative (-2.2 V, -1 V) in data "1" and data "0". Therefore, although the characteristic degradation of NBTI cannot be avoided, the variation is significantly suppressed compared to the variation of the threshold voltage of the memory cell MC when -2.2 V (data "1") is continuously applied in standby mode. Therefore, the overall lifespan of the memory device 100 can be extended.

[0091] Furthermore, during each access in a normal read or write operation, as described above, it is considered to invert and restore the data in the memory cell MC. However, in this case, due to random access, the duty cycle may not be close to 1. That is, there is a risk that the threshold voltage of the memory cell MC will fluctuate more, and the characteristics may actually deteriorate due to NBTI. Also, the access speed or power consumption will deteriorate. Moreover, for each column address, it is necessary to remember the inverted / non-inverted flag and read the flag.

[0092] In contrast, in the periodic refresh operation performed by the memory device 100 in the fourth embodiment during standby mode, the data in the memory cell MC is reversed and restored for each refresh operation. Therefore, the duty cycle becomes almost 1. That is, the fluctuation of the threshold voltage of the memory cell MC can be reduced, and the characteristic degradation caused by NBTI can be suppressed.

[0093] In the fourth embodiment, a reverse / non-reverse flag is required. However, the refresh operation is performed on all memory cell arrays 110 or all subarrays (111A, 111B). Therefore, one bit of data is sufficient for the reverse / non-reverse flag relative to memory cell array 110 or each subarray. This flag indicates whether the data of a plurality of memory cells MC within memory cell array 110 or each subarray is reversed from the original data to the opposite logic data, or restored from the opposite logic data to the original data. As shown below, it is only necessary to know which word line of memory cell MC is currently being refreshed. One flag (1 bit of data) is stored for memory cell array 110, or one flag is stored for each of the subarrays 111A, 111B. This flag can be stored in memory (not shown) within control circuit 160, such as a flip-flop in peripheral circuitry. Thus, in the fourth embodiment, although inverted / non-inverted markers are required, their number of bits is very small, and they have almost no impact on the data capacity of the memory cell array 110.

[0094] Furthermore, when refreshing operations are performed sequentially according to column addresses, the memory device 100 needs to retain the most recently refreshed column address (the most recent column address). Since the original refreshed column address is stored in DRAM, including the flag in the column address will not increase the data capacity. Alternatively, the refreshed column address can be stored in memory (not shown) within the control circuit 160, such as a flip-flop in the peripheral circuit.

[0095] Figure 11 is a table showing an example of the refresh operation in the fourth embodiment. The table in Figure 11 shows the refresh operations for column addresses R1 to R3. When the flag FLG is 1, the refresh operation from non-inverted state N to inverted state I is shown. When the flag FLG is 0, the refresh operation from inverted state I to non-inverted state N is shown. That is, when the flag FLG is 1, the memory cells MC of the memory cell array 110 store the original data (non-inverted data). When the flag FLG is 0, the memory cells MC of the memory cell array 110 store data inverted relative to the original data (inverted data).

[0096] t11 displays the state before the refresh action.

[0097] At t12, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R1. This reverses the data at column address R1 from non-inverted state N to inverted state I. At this time, the data at column address R1 and the flag FLG remain in memory.

[0098] At t13, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R2. This reverses the data at column address R2 from non-inverted state N to inverted state I. At this time, the data at column address R2 and the flag FLG remain in memory.

[0099] At t14, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R3. This reverses the data at column address R3 from non-inverted state N to inverted state I. At this time, the data at column address R3 and the flag FLG remain in memory.

[0100] When the refresh operation of all column addresses R1 to R3 is completed, the flag FLG is changed from 1 to 0. Thus, it can be seen that the memory cells MC of the memory cell array 110 store data that has been reversed relative to the original data (reverse data).

[0101] At t15, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R1. Hereby, the data at column address R1 is reversed (restored) from inverted state I to non-inverted state N. At this time, the data at column address R1 and the flag FLG are retained in memory.

[0102] At t16, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R2. Hereby, the data at column address R2 is reversed (restored) from inverted state I to non-inverted state N. At this time, the data at column address R2 and the flag FLG are retained in memory.

[0103] At t17, a refresh operation is performed on a plurality of first memory cells MC corresponding to column address R3. Hereby, the data at column address R3 is reversed (restored) from inverted state I to non-inverted state N. At this time, the data at column address R3 and the flag FLG are retained in memory.

[0104] Thus, we return to the initial state of t11. When the refresh operation of all column addresses R1 to R3 is completed, the flag FLG is changed from 0 to 1. Thus, it can be seen that the memory cells MC of memory cell array 110 store the original data (non-reverse data).

[0105] Then, repeat t12~t17.

[0106] As one method, after the refresh operation of all column addresses R1 to R3 is completed, read and write operations (after FLG inversion) are performed. At this time, when FLG is marked as 1, the memory cell array 110, which stores the original non-inverted data, can be directly read or written. When FLG is marked as 0, the memory cell array 110, which stores inverted data, can invert (restore) the data and then read or write it.

[0107] Alternatively, read and write operations can be performed during the refresh of each character line (WL). In this case, it is sufficient to have the refreshed column address stored in the current memory, the data marked FLG, and the column address for which normal random access read and write operations are to be performed. For example, when the refresh is complete up to t13 and the refresh completion address is R2, the FLG is marked 1. Therefore, when the normal random access address number is below the refresh completion address R2, that is, when the random access address number is R1 or R2, it can be determined that the data is inverted data. When the random access address number is greater than the refresh completion address R2, that is, when the random access address number is R3, it can be determined that the data is non-inverted data. Similarly, for example, when the refresh is complete up to t15 and the refresh completion address is R1, the FLG is marked 0. Therefore, when the address number of the normal random access is lower than or equal to the refresh completion address R1 (i.e., when the address number of the random access is R1), the data can be determined to be non-reversed data. When the address number of the normal random access is higher than the refresh completion address R1 (i.e., when the address number of the random access is R2 or R3), the data can be determined to be reversed data.

[0108] The fourth embodiment can be combined with any of the first to third embodiments. In this way, the characteristic degradation caused by PBTI and NBTI can be suppressed.

[0109] (Fifth Embodiment) Figure 12 is a block diagram showing an example of the configuration of the column control circuit 120, the row control circuit 130, and the memory cell MC according to the fifth embodiment. According to the fifth embodiment, not only is oxide semiconductor used for the memory cell MC, but also oxide semiconductor is used for the channel regions of the transistors constituting the column control circuit 120 and the row control circuit 130.

[0110] The transistors Tgwl and Tsink constituting the column control circuit 120 are transistors that drive the voltage of the word line WL. The transistor Tgwl applies the word drive line WDRV to the word line WL (the gate of the cell transistor CT) according to the gate voltage GWC. The transistor Tsink applies the voltage of the reference voltage source Vss to the word line WL according to the gate voltage Sink. When oxide semiconductors are used in the channel regions of the transistors Tgwl and Tsink, there are concerns about the degradation of their characteristics. Therefore, in the fifth embodiment, the gate voltages GWC and Sink of the transistors Tgwl and Tsink are pulse-driven in the same way as the word line WL. This reduces the duty cycle of the transistors Tgwl and Tsink, suppressing characteristic degradation caused by PBTI. For example, to set the word line WL to a high voltage, transistor Tgwl is briefly turned on (ON), and then turned off (OFF), thereby setting the word line WL to an electrically floating state under a high voltage condition. To set the word line WL to a low voltage, transistor Tsink is briefly turned on, and then turned off, thereby setting the word line WL to an electrically floating state under a low voltage condition. When both transistors Tgwl and Tsink are off in standby mode or other states, and the voltage of the floating word line WL fluctuates unstablely, short pulses are periodically applied to transistor Tsink to maintain the word line WL in a low voltage state.

[0111] Furthermore, when the word line WL is separated from the word drive line WDRV, the word line WL is in an electrically floating state. Therefore, even if the transistor Tgwl is pulse-driven, the voltage of the word line WL will maintain the voltage of the word drive line WDRV until the transistor Tsink is turned on. Also, even if the transistor Tsink is pulse-driven, as long as a reference voltage source Vss (or a negative voltage source) is connected to the word line WL, the voltage of the word line WL can be reduced to Vss (or a negative voltage). Therefore, there is no problem even if the transistors Tgwl and Tsink are pulse-driven.

[0112] For example, the gate voltage GWC of transistor Tgwl is 3.5 V in the active state and -0.5 V in the inactive state. In this case, by pulse driving transistor Tgwl, the duty cycle of transistor Tgwl can be reduced, suppressing the characteristic degradation caused by PBTI. The same applies to transistor Tsink.

[0113] Furthermore, when the inactive period of transistor Tgwl is much longer than the active period, the gate voltage GWC in the inactive state is preferably slightly close to a negative voltage or 0 V (no bias). This reduces the duty cycle of transistor Tgwl, suppressing characteristic degradation caused by PBTI. Also, when the active and inactive periods of transistor Tgwl are equal, the gate voltage GWC of transistor Tgwl is preferably of opposite polarity in the active and inactive states. This reduces the duty cycle of transistor Tgwl, suppressing characteristic degradation caused by PBTI.

[0114] Furthermore, when the memory cell array 110 is a three-dimensional array formed by arranging memory cells MC in three dimensions, the bit lines may be configured as a hierarchical bit line structure with one global bit line GBL for each of the plurality of local bit lines LBL. In this case, the select transistor Tgbc is connected between each local bit line LBL and the global bit line GBL. The transistor Tgbc constituting the row control circuit 130 selectively connects one of the plurality of local bit lines LBL, specified by the row address, to the global bit line GBL. When an oxide semiconductor is used for the select transistor Tgbc, the row control circuit 130 pulses the gate voltage of the select transistor Tgbc only when needed for a short time. This reduces the duty cycle of the transistor Tgbc, suppressing characteristic degradation caused by PBTI.

[0115] For example, the gate voltage GBC of transistor Tgbc is 2.5 V in the active state and -0.5 V in the inactive state. In this case, by pulse driving transistor Tgbc, the duty cycle of transistor Tgbc can be reduced, suppressing the characteristic degradation caused by PBTI. Thus, in order to suppress the threshold voltage variation caused by PBTI and NBTI, it is preferable to set voltages Vgs and Vds to positive voltages when transistor Tgbc is in the on state and negative voltages when transistor Tgbc is in the off state, and combine the positive and negative voltages.

[0116] In this way, not only can the degradation of the memory cell array 110 be suppressed, but also the degradation of the column control circuit 120 and the row control circuit 130 can be suppressed, thus extending the lifespan of the memory device 100.

[0117] Furthermore, when the inactive period of the transistor Tgbc is much longer than the active period, the gate voltage GBC in the inactive state is preferably a lower negative voltage or close to 0 V (no bias). This reduces the duty cycle of the transistor Tgbc, suppressing characteristic degradation caused by PBTI. Also, when the active and inactive periods of the transistor Tgbc are equal, the gate voltage GBC of the transistor Tgbc is preferably of opposite polarity in the active and inactive states. This reduces the duty cycle of the transistor Tgbc, suppressing characteristic degradation caused by PBTI.

[0118] The fifth embodiment can be combined with any of the first to fourth embodiments. In this way, the characteristic degradation of the memory cell array 110, the column control circuit 120 and the row control circuit 130 can be suppressed.

[0119] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and similarly, are included in the scope of the invention described in the patent application and its equivalents. [Simplified Explanation of the Diagram]

[0006] Figure 1 is a block diagram showing an example of the configuration of the memory device according to the first embodiment. Figure 2 is a circuit diagram showing an example of the configuration of the memory cell array. Figure 3 is a block diagram showing an example of the configuration of the sense amplifier and bit lines. Figure 4 is a block diagram showing an example of the configuration of the sense amplifier and bit lines. Figure 5 is a timing diagram showing an example of the operation of the memory device according to the first embodiment. Figure 6 is a diagram showing the voltage applied to the memory cell during the read and write operations of the first embodiment. Figure 7 is a diagram showing the voltage applied to the memory cell in the standby state of the first embodiment. Figure 8 is a timing diagram showing an example of the operation of the memory device according to the second embodiment. Figure 9 is a block diagram showing an example of the configuration of the memory device according to the third embodiment. Figure 10 is a timing diagram showing the refresh operation of the memory device according to the fourth embodiment. Figure 11 is a table showing an example of the refresh operation of the fourth embodiment. Figure 12 is a block diagram showing an example of the configuration of the column control circuit, row control circuit, and memory cell in the fifth embodiment.

Claims

1. A semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each disposed corresponding to an intersection of the plurality of word lines and the plurality of bit lines, and constructed using an oxide semiconductor; a word line control circuit that activates or deactivates a first word line by causing a voltage change of a first word line selected from the plurality of word lines according to a first address; a sense amplifier circuit connected to the plurality of bit lines that detects and latches data of the plurality of first memory cells connected to the first word lines; a readout circuit that continuously reads the data latched by the sense amplifier circuit to an external location according to a plurality of second addresses; and a write circuit that causes the sense amplifier circuit to continuously latch data from the external location according to the plurality of second addresses; and during the readout operation, after the first word line is activated, the sense amplifier circuit latches the data of the plurality of first memory cells. Before the readout circuit finishes its continuous readout operation of continuously reading data from the plurality of first memory cells according to the plurality of second addresses, the word line control circuit deactivates the first word line. During the write operation, before the write circuit finishes its continuous write operation of continuously writing data from the outside to the sense amplifier circuit according to the plurality of second addresses, the word line control circuit reactivates the first word line.

2. The semiconductor memory device of claim 1, wherein during a write operation, after the write circuit begins the continuous write operation, the word line control circuit reactivates the first word line.

3. The semiconductor memory device of claim 1, wherein when performing a write operation, after latching the data of the plurality of first memory cells into the sense amplifier circuit, the word line control circuit sets the first word line to an inactive state until the continuous write operation begins.

4. The semiconductor memory device of claim 1, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the oxide semiconductor is included in the channel region; and a capacitor connected to the other of the source and drain of the plurality of transistors.

5. The semiconductor memory device of any one of claims 1 to 3, wherein the word line control circuit sets the voltage of the first word line up until the sense amplifier circuit detects the data of the plurality of first memory cells to be lower than the voltage of the first word line after the data of the plurality of first memory cells is latched.

6. The semiconductor memory device of claim 1 further includes: a memory that temporarily holds data corresponding to the first and second addresses read from the readout circuit; and when the data corresponding to the first and second addresses is read out, the data held in the memory is read out to the outside.

7. A semiconductor memory device comprising: a plurality of memory cells, each disposed at an intersection with a plurality of word lines and a plurality of bit lines, and constructed using an oxide semiconductor; a word line control circuit that activates or deactivates a first word line by causing a voltage change in a first word line selected from the plurality of word lines according to a first address; and a sense amplifier circuit connected to the plurality of bit lines that detects and latches data in the plurality of first memory cells connected to the first word lines, and performs a write-back operation to the plurality of first memory cells after latching. The readout circuit continuously reads the data latched to the aforementioned sense amplifier circuit to the outside according to a plurality of second addresses; and the write circuit continuously latches the data from the outside to the aforementioned sense amplifier circuit according to the aforementioned plurality of second addresses; and in the aforementioned recovery operation in the refresh command of the internally generated signal or the external signal, it reverses the data of each of the plurality of first memory cells latched by the aforementioned sense amplifier circuit and writes it back to the plurality of first memory cells.

8. The semiconductor memory device of claim 7, comprising: a memory section storing a mark that is displayed in the refresh command during the recovery operation, whether the data of the plurality of first memory cells is reversed from the original data to the opposite logic data, or restored from the opposite logic data to the original data.

9. The semiconductor memory device of claim 7, comprising: a memory unit that, when performing the recovery operation by sequentially specifying the plurality of word lines according to the first address, stores the first address of the most recently executed recovery operation in the refresh command.

10. A semiconductor memory device as claimed in any one of claims 1, 7, and 8, wherein the word line control circuit sets the voltage of the word lines other than the first word line among the plurality of word lines to be opposite in polarity to the voltage of the first word line.

11. A semiconductor memory device according to any one of claims 1, 7, and 8, wherein the word line control circuit includes a mechanism for driving the voltage of the first word line with a positive terminal and a mechanism for driving the voltage of the first word line with a negative terminal, and includes a mechanism for setting the first word line to float for a time longer than the time for driving the first word line with a positive or negative terminal.

12. A semiconductor memory device as claimed in any of claims 1, 7, and 8, wherein the word line control circuit includes a transistor that includes an oxide semiconductor in the channel region.

13. A semiconductor memory device as claimed in any one of claims 1, 7, and 8, wherein the plurality of bit lines correspond to one global bit line, and further includes: a selection transistor connected between the plurality of bit lines and the global bit line, and containing an oxide semiconductor in the channel region; and the selection transistor system is driven by the variation of its gate voltage between two potentials of different polarities.

14. The semiconductor memory device of claim 7 or claim 8, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the oxide semiconductor is included in the channel region; and a capacitor connected to the other of the source and drain of the plurality of transistors.

15. The semiconductor memory device of claim 10, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the channel region comprising the oxide semiconductor; and a capacitor connected to the other of the source and drain of the plurality of transistors.

16. The semiconductor memory device of claim 11, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the oxide semiconductor is included in the channel region; and a capacitor connected to the other of the source and drain of the plurality of transistors.

17. The semiconductor memory device of claim 12, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the oxide semiconductor is included in the channel region; and a capacitor connected to the other of the source and drain of the plurality of transistors.

18. The semiconductor memory device of claim 13, wherein each of the memory cells comprises: a transistor, the gate of which is connected to any of the plurality of word lines, one of which is connected to any of the plurality of bit lines, and the oxide semiconductor is included in the channel region; and a capacitor connected to the other of the source and drain of the plurality of transistors.

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