Power amplifier system, method of adjusting a gain of a power amplifier stage, and mobile device

Abstract

This invention discloses a system and method incorporating a variable power amplifier bias impedance. In one embodiment, a power amplifier system is provided, comprising a bias circuit configured to receive a bias voltage and generate a bias signal, and a power amplifier stage configured to receive an input radio frequency (RF) signal and generate an output RF signal. The power amplifier system may also include a bias impedance component operatively coupled between the bias circuit and the power amplifier stage. The bias impedance component is configured to receive a control signal and adjust its impedance value in response to the control signal.

Description

Technical Field

[0001] Embodiments of the present technology relate to electronic systems and, in particular, to systems including power amplifiers for radio frequency (RF) electronics. Prior Art

[0002] RF power amplifiers can be used to boost the power of an RF signal having a relatively low power. Thereafter, the boosted RF signal can be used for various purposes, including driving an antenna of a transmitter.

[0003] Power amplifiers may be included in cell phones to amplify an RF signal for transmission. For example, in a cell phone that communicates using a cellular standard, a wireless local area network (WLAN) standard, and / or any other suitable communication standard, a power amplifier may be used to amplify RF signals. Managing the amplification of an RF signal may be important because amplifying an RF signal to an incorrect power level or introducing significant distortion of the original RF signal may cause a wireless device to transmit out of band or violate accepted standards. The biasing of a power amplifier device is an important part of managing amplification because it may determine the voltage and / or current operating points of the amplifying devices within the power amplifier.

[0004] Improved power amplifier systems are needed. Additionally, improved power amplifier biasing is needed. Summary of the invention

[0005] Aspects of the present invention relate to techniques and electronic systems that can be used to improve power amplifier bias. For example, in one aspect, a power amplifier system includes: a bias circuit configured to receive a bias voltage and generate a bias signal; a power amplifier stage configured to receive an input radio frequency signal and generate an output radio frequency signal. The system further includes a bias impedance component operably coupled between the bias circuit and the power amplifier stage, the bias impedance component configured to receive a control signal and adjust an impedance value of the bias impedance component in response to the control signal.

[0006] According to another aspect of the present invention, a method for adjusting a gain of a power amplifier stage is provided. The method includes: receiving a bias voltage at a bias circuit; generating a bias signal based on the bias voltage by the bias circuit; and receiving the bias voltage and a control signal at a bias impedance element. The method further includes adjusting an impedance value of the bias impedance element at the bias impedance element based on the received control signal; receiving an input RF signal and the bias voltage from the bias impedance element at a power amplifier stage; and generating an output RF signal based on the input RF signal and the bias voltage.

[0007] According to another aspect of the present invention, a mobile device is provided. The mobile device includes: a power amplifier configured to amplify an input radio frequency signal and generate an output radio frequency signal; and a modulator configured to generate a radio frequency transmission signal based on the output radio frequency signal. The power amplifier includes a bias circuit configured to receive a bias voltage and generate a bias signal, a power amplifier stage configured to receive the input radio frequency signal and generate the output radio frequency signal, and a bias impedance component operably coupled between the bias circuit and the power amplifier stage. The bias impedance component is configured to receive a control signal and adjust an impedance value of the bias impedance component in response to the control signal. Simple diagram description

[0008] FIG. 1 is a schematic diagram of a power amplifier module for amplifying a radio frequency (RF) signal.

[0009] 2 is a schematic block diagram of an exemplary wireless device that may include one or more power amplifier modules of FIG. 1 .

[0010] FIG. 3 is a schematic block diagram of an example of a power amplifier system.

[0011] FIG. 4 is a schematic block diagram of another example of a power amplifier system according to an aspect of the present invention.

[0012] FIG. 5A is a schematic block diagram of yet another example of a power amplifier system according to an aspect of the present invention.

[0013] FIG. 5B is a schematic block diagram of yet another example of a power amplifier system according to an aspect of the present invention.

[0014] 6A to 6F are graphs showing the effect of changes in bias impedance on the characteristics of a power amplifier according to aspects of the present invention.

[0015] 7 is a graph showing the gain at the output stage of a power amplifier as a function of output power according to aspects of the present invention.

[0016] 8A to 8D illustrate several power amplifier characteristics according to aspects of the present invention.

[0017] FIG. 9 illustrates an embodiment of a multi-stage power amplifier system according to an aspect of the present invention.

[0018] FIG. 10 is a schematic block diagram of another example of a power amplifier system according to an aspect of the present invention.

[0019] FIG. 11 is a schematic block diagram of yet another example of a power amplifier system according to an aspect of the present invention. Implementation

[0020] CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 62 / 713,150, filed on August 1, 2018, the entirety of which is hereby incorporated by reference herein.

[0021] Headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the invention.

[0022] Apparatus and methods for biasing a power amplifier are disclosed herein. In certain embodiments, a power amplifier system is provided that includes a power amplifier and a bias circuit. The power amplifier can be used to amplify a radio frequency (RF) signal for transmission, and the bias circuit can be used to generate a bias voltage to bias the power amplifier. The power amplifier bias circuit can receive an enable signal that can be used to enable or disable the power amplifier to pulse the output of the power amplifier.

[0023] As described in more detail below, the bias impedance of a signal provided by a bias circuit to a power amplifier can affect certain characteristics of the power amplifier and, in particular, the power amplifier gain characteristic. Therefore, the design and selection of the bias impedance provided by the bias circuit is an important design characteristic to consider during the design of a power amplifier system. Aspects of the present invention relate to a power amplifier system that can have an adjustable bias impedance and can be used to select the power amplifier gain characteristic depending on the design and / or application requirements of the power amplifier system. [Overview of Power Amplifier System Example] []

[0024] FIG. 1 is a schematic diagram of a power amplifier module 10 for amplifying a radio frequency (RF) signal. The illustrated power amplifier module (PAM) 10 may be configured to amplify an RF signal RF_IN to generate an amplified RF signal RF_OUT. As described herein, the power amplifier module 10 may include one or more power amplifiers, including, for example, a multi-stage power amplifier.

[0025] 2 is a schematic block diagram of an exemplary wireless or mobile device 11 that may include one or more power amplifier modules of FIG 1. The wireless device 11 may include a power amplifier bias circuit that implements one or more features of the present invention.

[0026] The exemplary wireless device 11 depicted in FIG2 may represent a multi-band and / or multi-mode device, such as a multi-band / multi-mode mobile phone. In the illustrated configuration, the wireless device 11 includes a switch 12, a transceiver 13, an antenna 14, a power amplifier 17, a control element 18, a computer readable medium 19, a processor 20, and a battery 21.

[0027] The transceiver 13 may generate RF signals for transmission via the antenna 14. In addition, the transceiver 13 may receive incoming RF signals from the antenna 14.

[0028] It will be appreciated that various functionalities associated with the transmission and reception of RF signals may be achieved by one or more components collectively represented in FIG2 as transceiver 13. For example, a single component may be configured to provide both transmission and reception functionalities. In another example, the transmission and reception functionalities may be provided by separate components.

[0029] Similarly, it will be appreciated that various antenna functionalities associated with the transmission and reception of RF signals may be achieved by one or more components collectively represented as antenna 14 in FIG. 2 . For example, a single antenna may be configured to provide both transmission and reception functionalities. In another example, transmission and reception functionalities may be provided by separate antennas. In yet another example, different antennas may be used to provide different frequency bands associated with wireless device 11 .

[0030] In FIG. 2 , one or more output signals from the transceiver 13 are depicted as being provided to the antenna 14 via one or more transmission paths 15. In the example shown, different transmission paths 15 may represent output paths associated with different frequency bands and / or different power outputs. For example, the two exemplary power amplifiers 17 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output) and / or amplification associated with different frequency bands. Although FIG. 2 illustrates one configuration using two transmission paths 15, the wireless device 11 may be adapted to include more or fewer transmission paths 15.

[0031] The power amplifiers 17 may be used to amplify a wide variety of RF signals. For example, one or more power amplifiers 17 may receive an enable signal that may be used to pulse the output of the power amplifier to assist in transmitting a wireless local area network (WLAN) signal or any other suitable pulsed signal. In some configurations, one or more power amplifiers 17 are configured to amplify a Wi-Fi signal. Each of the power amplifiers 17 need not amplify the same type of signal. For example, one power amplifier may amplify a WLAN signal while another power amplifier may amplify, for example, a Global System for Mobile (GSM) signal, a Code Division Multiple Access (CDMA) signal, a W-CDMA signal, a Long Term Evolution (LTE) signal, or an EDGE signal.

[0032] One or more features of the present invention may be implemented in the aforementioned exemplary modes and / or frequency bands and in other communication standards.

[0033] In FIG2 , one or more detected signals from antenna 14 are depicted as being provided to transceiver 13 via one or more receive paths 16. In the example shown, different receive paths 16 may represent paths associated with different frequency bands. Although FIG2 illustrates a configuration using one of four receive paths 16, wireless device 11 may be adapted to include more or fewer receive paths 16.

[0034] To facilitate switching between receive and transmit paths, switch 12 may be configured to electrically connect antenna 14 to a selected transmit or receive path. Thus, switch 12 may provide a number of switching functionalities associated with an operation of wireless device 11. In certain configurations, switch 12 may include a number of switches that provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. Switch 12 may also provide additional functionality including filtering and / or duplexing of signals.

[0035] 2 shows that in certain configurations, a control component 18 may be provided for controlling various control functionalities associated with the operation of the switch 12, the power amplifier 17, and / or (several) other operating components (such as bias circuits). Non-limiting examples of control components 18 are described in more detail herein.

[0036] In some configurations, a processor 20 may be configured to facilitate the implementation of the various procedures described herein. The processor 20 may operate using computer program instructions. These computer program instructions may be provided to the processor 20.

[0037] In some configurations, these computer program instructions may also be stored in a computer readable memory 19 that can direct the processor 20 or other programmable data processing device to operate in a specific manner.

[0038] Battery 21 may be any suitable battery for use in wireless device 11, including, for example, a lithium-ion battery.

[0039] FIG3 is a schematic block diagram of an example of a power amplifier system 26. The illustrated power amplifier system 26 includes a switch 12, an antenna 14, a battery 21, a directional coupler 24, a power amplifier bias circuit 30, a power amplifier 32, and a transceiver 33. The illustrated transceiver 33 includes a baseband processor 34, an I / Q modulator 37, a mixer 38, and an analog-to-digital converter (ADC) 39. Although not shown in FIG3 for clarity, the transceiver 33 may include circuits associated with receiving signals via one or more receive paths.

[0040] The baseband signal processor 34 may be used to generate an I signal and a Q signal that may be used to represent a sine wave or signal having a desired amplitude, frequency, and phase. For example, the I signal may be used to represent an in-phase component of the sine wave and the Q signal may be used to represent a quadrature component of the sine wave, which may be an equivalent representation of the sine wave. In certain implementations, the I signal and the Q signal may be provided to the I / Q modulator 37 in a digital format. The baseband processor 34 may be any suitable processor configured to process a baseband signal. For example, the baseband processor 34 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Furthermore, in some implementations, two or more baseband processors 34 may be included in the power amplifier system 26.

[0041] The I / Q modulator 37 may be configured to receive the I and Q signals from the baseband processor 34 and process the I and Q signals to generate an RF signal. For example, the I / Q modulator 37 may include a DAC configured to convert the I and Q signals to an analog format, a mixer for up-converting the I and Q signals to radio frequency, and a signal combiner for combining the up-converted I and Q signals into an RF signal suitable for amplification by the power amplifier 32. In certain implementations, the I / Q modulator 37 may include one or more filters configured to filter the frequency content of the signals processed therein.

[0042] The power amplifier bias circuit 30 may receive an enable signal ENABLE from the baseband processor 34 and a battery or power high voltage V CC from the battery 21 , and may use the enable signal ENABLE to generate a bias voltage V BIAS for the power amplifier 32 .

[0043] Although FIG3 shows that the battery 21 directly generates the power supply high voltage VCC, in some embodiments, the power supply high voltage VCC may be a regulated voltage generated by a regulator powered by the battery 21. In one example, a switching regulator (such as a buck and / or boost converter) may be used to generate the power supply high voltage VCC.

[0044] The power amplifier 32 may receive an RF signal from the I / Q modulator 37 of the transceiver 33 and may provide an amplified RF signal to the antenna 14 via the switch 12 .

[0045] The directional coupler 24 may be positioned between the output of the power amplifier 32 and the input of the switch 12, thereby allowing an output power measurement of the power amplifier 32 that does not include the insertion loss of the switch 12. The sensed output signal from the directional coupler 24 may be provided to a mixer 38, which may multiply the sensed output signal by a reference signal having a controlled frequency so as to frequency shift down the frequency content of the sensed output signal to produce a down-shifted signal. The down-shifted signal may be provided to an ADC 39, which may convert the down-shifted signal to a digital format suitable for processing by the baseband processor 34.

[0046] By including a feedback path between the output of the power amplifier 32 and the baseband processor 34, the baseband processor 34 can be configured to dynamically adjust the I signal and the Q signal to optimize the operation of the power amplifier system 26. For example, configuring the power amplifier system 26 in this manner can help control the power added efficiency (PAE) and / or linearity of the power amplifier 32. [Power amplifier bias] []

[0047] A theoretically ideal power amplifier has linear gain and phase characteristics regardless of the input or output power of the power amplifier. The gain characteristic of a power amplifier may be plotted on an AM / AM graph, which plots changes in output amplitude versus changes in input amplitude. As used herein, AM may refer to amplitude variation. A theoretically ideal power amplifier has a variation of 0 dB / dB in an AM / AM graph. The phase characteristic of a power amplifier may be plotted on an AM / PM graph, which plots changes in output phase versus changes in input amplitude. As used herein, PM may refer to phase variation. Similar to the ideal AM / AM characteristic, a theoretically ideal power amplifier has a variation of 0 dB / dB in an AM / PM graph.

[0048] Since real-world power amplifiers cannot achieve the flat gain and phase characteristics of a theoretically ideal power amplifier, an important aspect of power amplifier design is to improve the linearity of the gain and phase characteristics of the power amplifier. In certain implementations, there may be a tradeoff regarding the linearity that can be achieved for the gain and phase characteristics of a power amplifier without negatively affecting the output power and efficiency of the power amplifier. In a multi-stage power amplifier system, the gain and phase characteristics of the power amplifier at each stage in the system may be selected so that the overall gain and phase characteristics are substantially linear.

[0049] FIG. 4 is a schematic block diagram of another example of a power amplifier system according to an aspect of the present invention. Specifically, the illustrated power amplifier system 27 includes a power amplifier bias circuit 30, a power amplifier stage 41, a current source 75, and a bias impedance component 80. The power amplifier bias circuit 30 may include a transistor 71 and two diodes 73 and 74. The components of the power amplifier bias circuit 30 together with the current source 75 may be configured to generate a current mirror that mirrors the current generated by the power amplifier stage 41. The output of the power amplifier bias circuit 30 is supplied to the bias impedance component 80, which in turn is coupled to the power amplifier stage 41 to provide a bias signal thereto.

[0050] The power amplifier stage 41 is configured to receive both an input RF signal RFIN and a bias signal from the bias impedance element 80. Based on the received signal, the power amplifier stage 41 is configured to generate an output RF signal RFOUT. The power amplifier stage 41 is configured to generate the output RF signal RFOUT as an amplified version of the input RF signal RFIN having gain and phase characteristics close to those of a theoretically ideal power amplifier (e.g., gain and phase characteristics designed to be within a threshold range of 0 dB / dB). The power amplifier stage 41 includes a transistor 61, a plurality of capacitors 52, 65 and 64, and a plurality of inductors 53, 63 and 66. The capacitors 52, 65 and 64 and the inductors 53, 63 and 66 couple the transistor 61 to receive the input RF signal RFIN and a power supply voltage Vcc and generate the output RF signal RFOUT.

[0051] The base of transistor 61 receives a bias signal generated by power amplifier bias circuit 30 via bias impedance component 80. In some embodiments, the impedance value of bias impedance component 80 may be selected to dominate the overall bias impedance applied to the base of transistor 61. In some embodiments, the bias impedance applied to the base of transistor 61 may be equal to the sum of the output impedance of transistor 71 and the impedance value of bias impedance component 80. Therefore, the impedance value of bias impedance component 80 may be selected to dominate the impedance value of transistor 71 (for example, the impedance value of bias impedance component 80 may be one or more orders of magnitude greater than the impedance value of transistor 71). In an exemplary embodiment, the output impedance of transistor 71 is inversely related to the transconductance of transistor 71, which may result in an output impedance of transistor 71 of approximately 10 Ω.

[0052] In some embodiments, transistor 61 may include a heterojunction bipolar transistor (HBT) that may be adapted for use with high frequency signals that power amplifier system 27 is adapted to receive and amplify. In particular, HBTs may have high performance and efficiency for RF power amplification as used in embodiments disclosed herein. In order to properly generate mirror currents in the power amplifier bias circuit, in some embodiments, transistor 71 may also include an HBT.

[0053] One technique for adjusting the gain and phase characteristics of a power amplifier may be to select a fixed bias impedance to be applied to the bias signal to be supplied to the base of transistor 61. The particular bias impedance may be selected during the design and development of the power amplifier stage 41 and implemented by selecting the impedance value of the bias impedance component 80. For example, the impedance value of the bias impedance component 80 may be selected via die variations and / or laser trimmable resistors. However, the impedance value of the bias impedance component 80 may be selected to adjust and / or improve the linearity of the gain and phase characteristics of the power amplifier system 27 for a single power level, modulation, and frequency. Thus, if the power amplifier system 27 is used at a power level, modulation, and / or frequency that is different from the value used when selecting the value of the bias impedance component 80, the linearity of the gain and / or phase characteristics of the power amplifier system may be affected.

[0054] Therefore, some aspects of the present invention are directed to using a variable bias impedance element that can be applied to bias a power amplifier. FIG. 5A is a schematic block diagram of another example of a power amplifier system according to aspects of the present invention. Components of the power amplifier system 28 shown in FIG. 5A that are similar or substantially the same as components in the power amplifier system 27 shown in FIG. 4 are represented by the same reference numerals and their detailed descriptions may be omitted for clarity.

[0055] As shown in FIG. 5A , the power amplifier system 28 includes a power amplifier bias circuit 30, a power amplifier stage 41, a current source 75, and a bias impedance component 81. In FIG. 5A , the bias impedance component can be implemented as a variable bias impedance component 85. Similar to the power amplifier system 27 of FIG. 4 , in the embodiment of FIG. 5A , the output of the power amplifier bias circuit 30 is supplied to the variable bias impedance component 85, which in turn is coupled to the power amplifier stage 41 to provide a bias signal thereto. The variable bias impedance component 85 can be configured to receive a control signal CTRL configured to adjust the impedance value of the variable bias impedance component 85. Thus, the impedance value of the variable bias impedance component 85 can be adjusted based on the voltage of the control signal CTRL. In the illustrated example, the variable bias impedance component 85 can be implemented using any variable impedance element (e.g., a variable resistor) that can be controlled by a control signal CTRL.

[0056] Certain variable impedance techniques may not be applicable to all power amplifier systems 28 and, in particular, power amplifiers that may be implemented in cell phones to amplify RF signals for transmission. As discussed above, in certain RF power amplifier applications, it may be desirable to implement transistor 61 of amplifier stage 41 as an HBT transistor because an HBT may have performance and efficiency characteristics that may be desirable for use in an RF power amplifier. In future semiconductor manufacturing technologies, it may be difficult to combine different device technologies on a single semiconductor die. For example, the combination of an HBT and a field effect transistor (FET) on the same semiconductor die may not result in a device having the desired transistor properties. As discussed in U.S. Pat. No. 9,105,488 B2, issued Aug. 11, 2015, the entirety of which is incorporated by reference, some attempts to integrate a FET into a GaAs HBT process have resulted in only an n-type FET device. However, recent developments in fabrication techniques, as exemplified by US Pat. No. 9,105,488 B2, have enabled the fabrication of HBTs and FETs on a single semiconductor die.

[0057] Using technology that enables the fabrication of semiconductor devices having both HBT and FET technologies, an embodiment of the power amplifier 28 of FIG. 5A is illustrated in FIG. 5B . FIG. 5B is a schematic block diagram of yet another example of a power amplifier system according to an aspect of the present invention. The power amplifier 29 illustrated in FIG. 5B includes a power amplifier bias circuit 30, a power amplifier stage 41, and a current source 75, each of which may be the same or similar to the power amplifier bias circuit 30, power amplifier stage 41, and current source 75 discussed above in conjunction with FIG. 5A . The power amplifier 29 further includes a bias impedance component 81, which includes a FET 90 in place of the variable bias impedance component 85 of FIG. 5A . The FET 90 may be configured to receive a control signal CTRL at one of its gates via a select resistor 95. The control signal is configured to adjust the impedance value of the FET 90. Thus, the impedance value of the FET 90 may be adjusted by selecting the voltage of the control signal CTRL. In an exemplary embodiment, the FET 90 can be operated in a triode through selection of the voltage of the control signal CTRL. As understood by those skilled in the art, the triode region of the FET 90 can refer to a voltage range that can be applied to the gate of the FET 90 so that the FET 90 operates in a manner similar to a resistor (e.g., the FET 90 can have a substantially linear response when operated in a triode). Thus, when the FET 90 is operated in the triode region, the impedance of the FET 90 can be controlled by the control signal CTRL.

[0058] The value of the bias impedance supplied to the base of transistor 61 of amplifier stage 41 can affect the gain and phase characteristics of power amplifier 28 or 29. Specifically, FIGS. 6A-6F are graphs illustrating the effect of changes in bias impedance on power amplifier characteristics according to aspects of the present invention. FIGS. 6A-6C illustrate power amplifier characteristics when a relatively high impedance is applied to the base of a power amplifier transistor and FIGS. 6D-6F illustrate power amplifier characteristics when a relatively low impedance is applied to the base of a power amplifier transistor. FIGS. 6A-6F are intended only to illustrate how increasing or decreasing the bias impedance value affects power amplifier characteristics and, therefore, the specific values ​​of the bias impedance values ​​that result in the illustrated graphs are non-limiting. In certain embodiments, a "low" impedance value may be substantially zero impedance and a "high" impedance value may be an infinite impedance value.

[0059] 6A and 6D are graphs showing the base-collector voltage (V) and base current (A) of a transistor in a power amplifier (such as transistor 61 of FIG. 5A or FIG. 5B ) as a function of input power (dBm) to the transistor at “high” and “low” bias impedances. Note that in the high bias impedance of FIG. 6A , the base-collector voltage (V) decreases as input power increases, while in the low bias impedance of FIG. 6D , the base-collector voltage (V) is substantially constant as input power increases.

[0060] FIG6B and FIG6E are graphs showing the gain (dB) and output power (dBm) of a transistor in a power amplifier as a function of input power (dBm) to the transistor at "high" and "low" bias impedances. Here, in the high bias impedance of FIG6B, the gain "compresses" or decreases as the input power increases, while in the low bias impedance of FIG6E, the gain increases as the input power increases. Thus, by selecting a bias impedance having a value between the "high" and "low" values ​​shown, the gain characteristic of the power amplifier can be improved by flattening the gain, thereby improving gain linearity.

[0061] 6C and 6F are graphs showing the output current (A) of a transistor in a power amplifier as a function of input power (dBm) to the transistor at "high" and "low" bias impedances. Here, in the high bias impedance of FIG. 6C , the DC output current is substantially constant with respect to the input power, while in the low bias impedance of FIG. 6F , the DC output current decreases as the input power increases.

[0062] FIG. 7 is a graph showing the gain at the output stage of a power amplifier as a function of output power according to aspects of the present invention. Various gain curves are shown in FIG. 7 at different impedance bias levels (which range from an impedance of 5 Ω to an impedance of 1000 Ω, as shown in the legend). As the bias impedance increases, the gain decreases as the output power increases. In the illustrated embodiment, an impedance bias of 50 Ω may be selected to provide a substantially flat gain. However, other power amplifier topologies may result in different output stage gain graphs, and therefore, the particular impedance bias that results in a substantially flat gain may depend on the characteristics of the power amplifier implementation.

[0063] 8A to 8D illustrate several power amplifier characteristics according to aspects of the present invention. Specifically, FIG. 8A illustrates gain (dB) according to output power of a power amplifier at several different bias impedance values; FIG. 8B illustrates phase (degrees) according to output power of a power amplifier at different bias impedance values; FIG. 8C illustrates power amplifier efficiency (%) according to output power of a power amplifier at different bias impedance values; and FIG. 8D illustrates transistor collector current (mA) according to output power of a power amplifier at different bias impedance values.

[0064] As shown in FIGS. 8B-8D , the bias impedance value does not have a significant effect on the phase of the power amplifier, the power amplifier efficiency, or the transistor collector current characteristics. However, as shown in FIG. 8A , the bias impedance value affects the gain characteristics of the power amplifier, where increasing the gate control voltage (e.g., increasing the bias impedance) results in an increase in the gain that varies according to the output power. Therefore, adjustment of the bias impedance can be an effective tool for adjusting the gain characteristics of the power amplifier without significantly affecting the phase of the power amplifier, the power amplifier efficiency, and the transistor collector current characteristics.

[0065] FIG. 9 illustrates an embodiment of a multi-stage power amplifier system according to an aspect of the present invention. Specifically, the power amplifier system 121 of FIG. 9A includes a first power amplifier 120 and a second power amplifier 125 connected in series between an RF input port RFIN and an RF output port RFOUT. Each of the first power amplifier 120 and the second power amplifier 125 may be the same or similar to the power amplifier 29 illustrated in FIG. 5B . Therefore, a detailed description of each of the constituent components will not be provided. In the embodiment of FIG. 9 , the bias impedance value supplied to the base of the transistor of each of the power amplifiers 120 and 125 may be individually selected according to the specific implementation of the amplifier stage 41 and the power amplifier bias circuit 30 in each of the first power amplifier 120 and the second power amplifier 125. In addition, the bias impedance selected by the gate control voltage Gate CTRL applied to the respective amplifier stage 41 may be selected so that the overall gain of the power amplifier system 121 (e.g., the gain at the output port RFOUT for a signal applied to the input port RFIN) is sufficiently flat. Thus, in certain implementations, the gain of each of the first power amplifier 120 and the second power amplifier 125 may not be substantially flat as long as the overall gain of the power amplifier system 121 has a variation that is less than a threshold from an ideal variation of 0 dB / dB.

[0066] FIG. 10 is a schematic block diagram of another example of a power amplifier system according to an aspect of the present invention. The power amplifier 130 shown in FIG. 10 includes a power amplifier bias circuit 30, a power amplifier stage 41, and a current source 75, each of which may be the same or similar to the power amplifier bias circuit 30, power amplifier stage 41, and current source 75 discussed above in conjunction with FIG. 5A or FIG. 5B. The power amplifier 130 further includes a bias impedance component 81, which includes a pair of FETs 91 and 92 in place of the single FET 90 of FIG. 5B. The control signal CTRL may be applied to the gate of each of the FETs 91 and 92 via respective resistors 95 and 97. Depending on the implementation, the use of two FETs 91 and 92 may increase the range of values ​​of the impedance bias provided by the combination of the FETs 91 and 92 while maintaining the FETs 91 and 92 in triodes. Although not shown in FIG. 10 , a similar structured circuit (including two FETs and an input resistor) may be included in the power amplifier bias circuit to maintain the correct current mirror ratio.

[0067] FIG. 11 is a schematic block diagram of yet another example of a power amplifier system according to an aspect of the present invention. The power amplifier 131 depicted in FIG. 11 is similar to the power amplifier 130 depicted in FIG. 10 , except that three or more FETs 91-92 are included in the bias impedance component 81 , wherein the inclusion of the additional FETs is depicted by ovals. By including three or more FETs 91-92 in the bias impedance component 81 , the range of bias impedance values ​​that can be produced while maintaining FETs 91 and 92 in triodes is increased. As described above in conjunction with FIG. 10 , the same structure (including the same number of FETs and resistors) can be included in the power amplifier bias circuit to maintain the current mirror ratio. [in conclusion]

[0068] Unless the context clearly requires otherwise, throughout the description and the scope of the invention claims, the words "comprise", "comprising" and the like should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to". The word "coupled" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the word "connected" as generally used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, the words "herein", "above", "below" and words of similar meaning when used in this application shall refer to the application as a whole and not to any particular part of the application. Where the context permits, the words in the above embodiments using the singular or plural may also include the plural or singular respectively. The word "or" refers to a list of two or more items and includes all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

[0069] Furthermore, unless otherwise specifically stated or otherwise understood within the context in which they are used, conditional terms used herein, such as, inter alia, "may," "could," "might," "for example," "for example," "such as," and the like, are generally intended to convey that some embodiments include and other embodiments do not include certain features, elements, and / or states. Thus, such conditional terms are generally not intended to imply that features, elements, and / or states are required in any manner for one or more embodiments or that one or more embodiments necessarily include logic for determining, with or without author input or prompting, whether such features, elements, and / or states are included or performed in any particular embodiment.

[0070] The above detailed description of the embodiments of the present invention is not intended to be exhaustive or to limit the present invention to the precise form disclosed above. Although specific embodiments and examples of the present invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the present invention, as will be recognized by those skilled in the relevant art. For example, although the procedures or blocks are presented in a given order, alternative embodiments may perform routines with steps in a different order or employ a system with blocks, and some procedures or blocks may be deleted, moved, added, subdivided, combined and / or modified. Each of these procedures or blocks may be implemented in a variety of different ways. Again, although procedures or blocks are sometimes shown as being executed in series, these procedures or blocks may alternatively be executed in parallel or may be executed at different times.

[0071] The teachings of the present invention provided herein may be applicable to other systems, not necessarily the systems described above. The elements and actions of the various embodiments described above may be combined to provide further embodiments.

[0072] Although certain embodiments of the present invention have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the present invention. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present invention. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present invention.

[0073] 10: Power Amplifier Module (PAM) 11: Wireless devices / mobile devices 12: Switch 13: Transceiver 14: Antenna 15: Transmission path 16: Receiving path 17: Power Amplifier 18: Control components 19: Computer readable media 20: Processor 21:Battery 24: Directional Coupler 26: Power Amplifier System 27: Power Amplifier System 28: Power Amplifier System 29: Power Amplifier System 30: Power amplifier bias circuit 32: Power Amplifier 33: Transceiver 34: Baseband processor 37:I / Q Modulator 38:Mixer 39: Analog to Digital Converter (ADC) 41: Power amplifier stage 52: Capacitor 53: Inductor 61: Transistor 63: Inductor 64:Capacitor 65:Capacitor 66: Inductor 71: Transistor 73: Diode 74: Diode 75: Current Source 80: Bias impedance component 81: Bias impedance component 85: variable bias impedance component 90: Field Effect Transistor (FET) 91: Field Effect Transistor (FET) 92: Field Effect Transistor (FET) 95: Resistor 97: Resistor 120: First power amplifier 125: Second power amplifier 130: Power Amplifier 131: Power Amplifier CTRL: control signal ENABLE: Enable signal GATE CTRL: Gate control voltage Vbias: bias voltage Vcc: power supply high voltage RF_IN: Radio frequency (RF) signal RF_OUT: Amplified radio frequency (RF) signal RFIN: Input RF signal / RF input port RFOUT: Output RF signal / RF output port

Claims

1. A power amplifier system comprising: A bias circuit configured to receive a bias voltage and generate a bias signal; a power amplifier configured to receive an input radio frequency signal and generate an output radio frequency signal; at least one first bias impedance transistor having a first variable impedance value operably coupled between the bias signal and the power amplifier, the first variable impedance value varying in response to a control signal received separately from the bias circuit; and at least one second bias impedance transistor having a second variable impedance value operably coupled between the first bias impedance transistor and the power amplifier, the second variable impedance value varying in response to the control signal.

2. The power amplifier system of claim 1, wherein the control signal has a voltage configured to operate one of the first bias impedance transistors in a triode region of the first bias impedance transistor.

3. The power amplifier system of claim 2, wherein the first bias impedance transistor comprises a field-effect transistor and the power amplifier comprises a heterojunction bipolar transistor configured to amplify the input radio frequency signal.

4. The power amplifier system of claim 3, wherein the field-effect transistor and the heterojunction bipolar transistor system are fabricated on a single semiconductor die.

5. The power amplifier system of claim 1, wherein the first variable impedance value of the first bias impedance transistor is selected such that the variation in the gain of the power amplifier is less than a threshold value from 0 dB / dm.

6. The power amplifier system of claim 1, wherein the control signal has a voltage configured to operate the second bias impedance transistor in one of the triode regions of the second bias impedance transistor.

7. The power amplifier system of claim 1, wherein the first variable impedance value and the second variable impedance value are selected such that the variation in the overall gain of the power amplifier is less than a threshold value from 0 dB / dm.

8. The power amplifier system of claim 1, wherein the power amplifier is configured to generate the output radio frequency signal having a first current, and the bias circuit is configured to generate the bias signal having a second current mirroring the first current.

9. A method for adjusting the gain of a power amplifier, comprising: A bias signal is generated based on a bias voltage using a bias circuit; The system receives a bias signal and a control signal separately received from the bias circuit at a first bias impedance transistor; adjusts a first variable impedance value of the first bias impedance transistor based on the control signal to generate a modified bias signal; adjusts a second variable impedance value of a second bias impedance transistor based on the control signal, the second bias impedance transistor being operatively coupled between the first bias impedance transistor and the power amplifier; receives an input RF signal and the modified bias signal at a power amplifier; and generates an output RF signal based on the input RF signal and the bias voltage.

10. The method of claim 9, wherein the control signal has a voltage configured to operate one of the first bias impedance transistors in a triode region of the first bias impedance transistor.

11. The method of claim 10, wherein the first bias impedance transistor comprises a field-effect transistor and the power amplifier comprises a heterojunction bipolar transistor, the method further comprising amplifying the input radio frequency signal at the heterojunction bipolar transistor.

12. The method of claim 11, wherein the field-effect transistor and the heterojunction bipolar transistor system are fabricated on a single semiconductor die.

13. The method of claim 9, further comprising selecting a voltage of the control signal to generate the first variable impedance value of the first bias impedance transistor such that the variation in the gain of the power amplifier stage is less than a threshold value from 0 dB / dm.

14. As claimed in claim 9, wherein the control signal has a voltage configured to operate the second bias impedance transistor in one of the triode regions of the second bias impedance transistor.

15. The method of claim 9, wherein the first variable impedance value and the second variable impedance value are selected such that the variation in the overall gain of the power amplifier is less than a threshold value from 0 dB / dm.

16. The method of claim 9, wherein the power amplifier is configured to generate the output radio frequency signal having a first current, and the bias circuit is configured to generate the bias signal having a second current mirroring the first current.

17. A mobile device comprising: A power amplifier configured to amplify an input radio frequency signal and generate an output radio frequency signal; A modulator configured to generate an RF transmission signal based on the output RF signal; a bias circuit configured to receive a bias voltage and generate a bias signal; at least one first bias impedance transistor having a first variable impedance value coupled between the bias signal and the power amplifier, the first variable impedance value varying in response to a control signal separately received from the bias circuit; and at least one second bias impedance transistor having a second variable impedance value operably coupled between the first bias impedance transistor and the power amplifier, the second variable impedance value varying in response to the control signal.

18. The operating device of claim 17, wherein the control signal has a voltage configured to operate one of the first bias impedance transistors in a triode region of the first bias impedance transistor.

19. The mobile device of claim 17, wherein the first bias impedance transistor comprises a field-effect transistor and the power amplifier comprises a heterojunction bipolar transistor configured to amplify the input radio frequency signal.

20. The mobile device of claim 17, wherein the control signal has a voltage configured to operate the second bias impedance transistor in a triode region of the second bias impedance transistor.

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