Memory system

Abstract

This invention provides a memory system capable of accurately retrieving data from a non-volatile memory. The memory system of this embodiment includes a non-volatile memory and a controller electrically connected to the non-volatile memory. The controller sends a write instruction and address to the non-volatile memory via a first signal line. During at least a portion of the period from sending the address to sending the write data, dummy data is sent to the non-volatile memory via the first signal line. After sending the dummy data, a data strobe signal is sent to the non-volatile memory via a second signal line. Synchronously with the data strobe signal, write data is sent to the non-volatile memory via the first signal line.

Description

Technical Field

[0001] An embodiment of the present invention relates to a memory system. Prior Art

[0002] As an example of a memory system using a non-volatile memory, a solid state drive (hereinafter referred to as SSD) is known. The SSD has a non-volatile memory (e.g., NAND (Not AND) type flash memory) and a memory controller. The memory controller sends a command (and address) and data to the non-volatile memory via an I / O (Input-Output) signal line. The memory controller sends a data strobe signal to the non-volatile memory via a signal line different from the I / O signal line. The non-volatile memory captures data within a period of a specified width centered on the rising timing of the data strobe signal.

[0003] The waveform of the data strobe signal may be deformed during transmission. When the rising timing of the data strobe signal deviates from the specified timing due to the waveform deformation, the non-volatile memory cannot capture accurate data. Summary of the invention

[0004] One embodiment provides a memory system in which a non-volatile memory is capable of capturing accurate data.

[0005] A memory system according to one embodiment comprises: a non-volatile memory including a memory cell array; and A controller electrically connected to the non-volatile memory using a first signal line and a second signal line; and The above controller is: The first instruction and address indicating the writing of data are sent to the non-volatile memory via the first signal line. After the first instruction and the address are sent and before the write data is sent, the dummy data is sent to the non-volatile memory via the first signal line. After the sending of the dummy data starts, a data selection signal is sent to the non-volatile memory via the second signal line, and the write data is sent to the non-volatile memory via the first signal line synchronously with the data selection signal. After completing the sending of the above written data, send the second instruction corresponding to the above first instruction. The above non-volatile memory system: After receiving the second instruction, the write data is written into the memory cell array. The above-mentioned fictitious data includes the first fictitious data and the second fictitious data subsequent to the first fictitious data. The first dummy data is data in which the even-numbered bits are the first value and the odd-numbered bits are the second value different from the first value. The second dummy data is data in which the even-numbered bits are the second value and the odd-numbered bits are the first value. Simple diagram description

[0006] FIG. 1 is a diagram for explaining an example of an information processing system including a memory system according to a first embodiment. FIG. 2 is a diagram for explaining an example of the structure of a NAND chip according to the first embodiment. FIG. 3 is a diagram for explaining an example of a signal waveform during a write operation in the first embodiment. FIG. 4 is a circuit diagram for explaining an example of an input circuit according to the first embodiment. 5(a) to (d) are waveform diagrams for explaining an operation example of the input circuit of the first embodiment. FIG. 6 is a circuit diagram for explaining another example of the input circuit of the first embodiment. 7(a) to (d) are waveform diagrams for illustrating another operation example of the input circuit of the first embodiment. 8(a) to (c) are diagrams for explaining an example of a power supply voltage drop caused by an output signal of the NAND interface circuit of the first embodiment. 9(a) to (c) are diagrams for explaining an example of the operation of the NAND interface circuit of the first embodiment. 10(a) to (c) are diagrams for explaining an example of the operation of the NAND interface circuit of the second embodiment. 11(a) to (d) are diagrams for explaining an example of the operation of the NAND interface circuit of the third embodiment. Implementation

[0007] Hereinafter, the implementation mode will be described with reference to the drawings. The following description illustrates the device and method for realizing the technical idea of ​​the implementation mode, and the technical idea of ​​the implementation mode is not limited to the structure, shape, configuration, material, etc. of the constituent elements described below. Changes that can be easily thought of by a person skilled in the art are of course included in the scope of the disclosure. In order to explain more clearly, in the drawings, the size, thickness, plane size or shape of each element may sometimes be changed relative to the actual implementation form and represented in a schematic manner. In multiple drawings, elements with different size relationships or ratios may also be included. In multiple drawings, the same reference numerals are sometimes marked for corresponding elements and repeated descriptions are omitted. Although multiple names are sometimes marked for several elements, the examples of such names are only for illustration, and other names are allowed to be marked for such elements. In addition, for elements that are not marked with multiple names, other names are also allowed to be marked. Furthermore, in the following description, "connection" not only includes direct connection, but sometimes also includes connection via other elements.

[0008] Hereinafter, this embodiment will be described in detail with reference to the drawings.

[0009] (First embodiment) 1 is a diagram for explaining an example of an information processing system including a memory system according to a first embodiment. The information processing system 10 includes a host 12 and a memory system 14. The memory system 14 is, for example, an SSD. In the following description, the memory system 14 is referred to as SSD14.

[0010] The host 12 is an information processing device configured to control the SSD 14. Examples of the host 12 are a personal computer, a server computer, a mobile terminal, and a vehicle-mounted device.

[0011] The SSD 14 may be connected to the host 12 via a cable or a network, or may be built into the host 12. The SSD 14 includes a memory controller 20, a non-volatile memory 40, and a power circuit 50.

[0012] An example of the non-volatile memory 40 is a NAND flash memory. The non-volatile memory 40 is not limited to the NAND flash memory, and a NOR (Not OR) flash memory or other types of non-volatile memory may be used. The non-volatile memory 40 may be a two-dimensional memory or a three-dimensional memory. In the following description, the non-volatile memory 40 is referred to as the NAND flash memory 40.

[0013] The NAND flash memory 40 has a plurality of memory chips. In the following description, the memory chip is referred to as a NAND chip. For example, the NAND flash memory 40 has four NAND chips 42-0 to 42-3. When the NAND chips 42-0 to 42-3 do not need to be distinguished individually, they are referred to as NAND chip 42. The NAND chip 42 has a peripheral circuit 44 and a memory circuit 46.

[0014] The SSD 14 may further include a random access memory, such as a DRAM (Dynamic Random Access Memory) 36. The DRAM 36 functions as a buffer for data transmission between the host 12 and the NAND flash memory 40. A portion of the memory area of ​​the DRAM 36 may also be used as a write buffer, a read buffer, and a command buffer. The write buffer temporarily stores data written to the NAND flash memory 40. The read buffer temporarily stores data read from the NAND flash memory 40. The command buffer temporarily stores commands received from the host 12 until the commands are executed.

[0015] The memory controller 20 can be implemented by a circuit such as a SoC (System on a Chip). The functions of each part of the memory controller 20 can be implemented by a dedicated hardware circuit, a processor that executes a program (firmware), or a combination of these components.

[0016] The memory controller 20 has a host interface (host I / F) circuit 22, a CPU (Central Processing Unit) 24, a DRAM interface (DRAM I / F) circuit 26, a static RAM (SRAM) 28, an encoder / decoder 30, a NAND interface (NAND I / F) circuit 32, and a temporary register 38. The host I / F circuit 22, the CPU 24, the DRAM I / F circuit 26, the SRAM 28, the encoder / decoder 30, the NAND I / F circuit 32, and the temporary register 38 are connected to each other via a bus 34. Some of the above components may also be arranged outside the memory controller 20.

[0017] The NAND I / F circuit 32 is electrically connected to the NAND flash memory 40. The NAND I / F circuit 32 is a controller configured to control the NAND flash memory 40 under the control of the CPU 24. Therefore, the NAND I / F circuit 32 is also called a NAND controller. As an example of an interface between the memory controller 20 and the NAND flash memory 40, a toggle interface is known.

[0018] In the switching interface, I / O signal lines are used to transmit commands, addresses and data. That is, the I / O signal lines are shared in command transmission, address transmission and data transmission. Therefore, during the data transmission between the memory controller 20 and the NAND flash memory 40, the command or address transmission cannot be performed. Similarly, during the transmission of commands or addresses, data transmission cannot be performed.

[0019] The host I / F circuit 22 performs communication with the host 12. The host I / F circuit 22 performs communication with the host 12 according to protocols based on SATA (Serial ATA (Advanced Technology Attachment), SAS (Serial Attached SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnect) Express (PCIe) (TM (trademark)), and Ethernet (TM (trademark)) as standards, for example. The host I / F circuit 22 receives various commands or data such as write commands, user data, and read commands from the host 12.

[0020] The DRAM I / F circuit 26 is an interface circuit configured to control the DRAM 36 under the control of the CPU 24. The DRAM I / F circuit 26 is also called a DRAM controller.

[0021] The SRAM 28 is used as a work area of ​​the CPU 24, for example.

[0022] The encoder / decoder 30 performs encoding and decoding of data to realize error detection and error correction of data read from the NAND flash memory 40. The encoder / decoder 30 encodes data (write data) written to the NAND flash memory 40 (more specifically, the memory cell array 120 described below). The encoder / decoder 30 decodes data (read data) read from the NAND flash memory 40. During decoding, the encoder / decoder 30 performs error detection and error correction of the read data.

[0023] The temporary register 38 stores dummy data, for example. The CPU 24 can write any dummy data into the temporary register 38. Furthermore, the temporary register 38 can be omitted, and the dummy data can be stored in a portion of the memory area of ​​the SRAM 28, DRAM 36, or a memory in the CPU 24. The dummy data is data that is not written into the NAND flash memory 40 (more specifically, the memory cell array 120 described below).

[0024] The CPU 24 is a processor configured to control the host I / F circuit 22, the DRAM I / F circuit 26, the SRAM 28, the encoder / decoder 30, the NAND I / F circuit 32, and the temporary register 38. The CPU 24 performs various processes in the following manner: in response to the activation of the SSD 14, the control program (called firmware) is loaded from the NAND flash memory 40 or the ROM (Read Only Memory) not shown to the SRAM 28, and the firmware is executed.

[0025] The power circuit 50 supplies power to each part of the SSD 14 using power supplied from an external device (eg, the host 12 ) connected to the SSD 14 .

[0026] 2 is a diagram for explaining an example of the configuration of the NAND chip 42 of the first embodiment. The peripheral circuit 44 includes an input / output circuit 102, a logic control circuit 104, a chip control circuit 106, a command register 108, an address register 110, and a ready / busy circuit 112. The memory circuit 46 includes a memory cell array 120, a row decoder 122, a data register 124, a sense amplifier 126, and a column decoder 128.

[0027] The signal lines connecting the NAND chip 42 and the NAND I / F circuit 32 include an I / O signal line DQ[7:0] for transmitting an I / O signal and a control signal line for transmitting a control signal.

[0028] The I / O signal lines DQ[7:0] each include 8 signal lines for transmitting 1-bit I / O signal DQ. The I / O signal DQ includes a command, an address, and data. That is, the I / O signal lines DQ[7:0] transmit 8-bit wide commands, 8-bit wide addresses, and 8-bit wide data. The bit width of the signal transmitted by the I / O signal lines DQ[7:0] is not limited to 8-bit width.

[0029] The control signal lines include a chip enable signal line CEn, a command latch enable signal line CLE, an address latch enable signal line ALE, a write enable signal line WEn, a pair of read enable signal lines REn / RE, a pair of data strobe signal lines DQS / DQSn, and a ready / busy signal line RY / BYn. Each control signal line is used to transmit a 1-bit control signal.

[0030] The 'n' at the end of each signal line name indicates that the signal transmitted by the signal line is a low active signal. In the following description, a signal at a valid level is called "signal valid". A signal at an invalid level is called "signal invalid". A high active signal is valid at a high level and invalid at a low level. A low active signal is invalid at a high level and valid at a low level.

[0031] The chip enable signal line CEn, the command latch enable signal line CLE, and the address latch enable signal line ALE are connected to the logic control circuit 104. The I / O signal line DQ[7:0], the write enable signal line WEn, the read enable signal line REn / RE, and the data strobe signal line DQS / DQSn are connected to the input / output circuit 102. The ready / busy signal line RY / BYn is connected to the ready / busy circuit 112.

[0032] The chip enable signal line CEn is used to transmit a chip enable signal CEn. The chip enable signal CEn is a signal used to enable the NAND chip 42 to be accessed.

[0033] The command latch enable signal line CLE is used to transmit the command latch enable signal CLE. The command latch enable signal CLE indicates that the signal transmitted using the I / O signal line DQ[7:0] is a command.

[0034] The address latch enable signal line ALE is used to transmit the address latch enable signal ALE. The address latch enable signal ALE indicates that the signal transmitted using the I / O signal line DQ[7:0] is an address.

[0035] The write enable signal line WEn is used to transmit the write enable signal WEn. The write enable signal WEn is a data strobe signal indicating the timing of capturing the command or address transmitted using the I / O signal line DQ[7:0].

[0036] The ready / busy signal line RY / BYn is used to transmit the ready / busy signal RY / BYn. The ready / busy signal RY / BYn indicates whether the NAND chip 42 is in a ready state or a busy state.

[0037] A pair of read enable signal lines REn / RE are used to transmit a pair of read enable signals REn / RE. The pair of read enable signals REn / RE are configured as differential signals. The pair of read enable signals REn / RE are timing signals for the memory controller 20 to indicate the output timing of data to the NAND chip 42. In the following, when describing the pair of read enable signals REn / RE, only the read enable signal REn is mentioned, and the description of the read enable signal RE is omitted.

[0038] A pair of data strobe signal lines DQS / DQSn are used to transmit a pair of data strobe signals DQS / DQSn. The pair of data strobe signals DQS / DQSn is constituted as a differential signal. The pair of data strobe signals DQS / DQSn indicates the timing of data acquisition to the transmission destination during data transmission. During a write operation, the memory controller 20 (more specifically, the NAND I / F circuit 32) sends a pair of data strobe signals DQS / DQSn. That is, during a write operation, data is transmitted using the I / O signal line DQ[7:0] in synchronization with a pair of data strobe signals DQS / DQSn sent by the memory controller 20. During a read operation, the NAND chip 42 (more specifically, the peripheral circuit 44) sends a pair of data strobe signals DQS / DQSn. That is, during the read operation, data is transmitted using the I / O signal line DQ[7:0] in synchronization with a pair of data strobe signals DQS / DQSn sent by the NAND chip 42. Hereinafter, when describing a pair of data strobe signals DQS / DQSn, only the data strobe signal DQS is mentioned, and the description of the data strobe signal DQSn is omitted.

[0039] The input / output circuit 102 is a buffer circuit for transmitting and receiving I / O signals with the NAND I / F circuit 32. The input / output circuit 102 latches the I / O signals. The instructions, addresses and data latched by the input / output circuit 102 are respectively allocated to the instruction register 108, the address register 110 and the data register 124 for storage.

[0040] The address stored in the address register 110 includes a chip number, a column address, and a row address. The chip number is used to distinguish the identification information of the NAND chips 42-1, 42-2, 42-3, and 42-4. The chip number is provided to the chip control circuit 106, the column address is provided to the row decoder 128, and the row address is provided to the row decoder 122. Furthermore, the address may not include the chip number. In this case, the address space is divided into chip regions one by one, and the address may also include information for identifying the chip.

[0041] The logic control circuit 104 receives the input of the control signal. Based on the received control signal, the logic control circuit 104 allocates the register of the storage destination of the I / O signal received by the input / output circuit 102. The logic control circuit 104 transmits the received control signal to the chip control circuit 106.

[0042] The chip control circuit 106 is a circuit that changes state based on various control signals received from the logic control circuit 104 and the instructions stored in the instruction register 108. The chip control circuit 106 controls the operation of each NAND chip 42.

[0043] The ready / busy circuit 112 changes the state of the ready / busy signal RY / BYn between a ready state and a busy state under the control of the chip control circuit 106.

[0044] The memory cell array 120 of the NAND chip 42 has a plurality of blocks. Each block has a plurality of pages. Each page has a plurality of memory cells connected to the same word line. The block is the unit of data erase operation for erasing data from the NAND flash memory 40. The page is the unit of data write operation and data read operation.

[0045] The row decoder 122 and the column decoder 128 specify the memory cells of the memory cell array 120 according to the row address and the column address. During a write operation, the data in the data register 124 is written to the memory cells specified by the row decoder 122 and the column decoder 128. During a read operation, the sense amplifier reads the data from the memory cells specified by the row decoder 122 and the column decoder 128. The read data is written to the data register 124.

[0046] Next, an overview of the switching interface between the memory controller 20 (more specifically, the NAND I / F circuit 32) and the NAND chip 42 (more specifically, the peripheral circuit 44) is described.

[0047] FIG3 is a diagram for explaining an example of a signal waveform during a write operation in the first embodiment. In the initial state, the chip enable signal CEn is invalid, the I / O signal line DQ[7:0] is in a high impedance (Hi-Z) state, and the states of other signal lines are not required to be paid attention to (don't care). The oblique lines in FIG3 represent the state of not requiring attention.

[0048] The NAND I / F circuit 32 enables the chip enable signal CEn and the command latch enable signal CLE, disables the address latch enable signal ALE, and disables the read enable signal REn, and starts switching the write enable signal WEn. The level of the write enable signal WEn periodically becomes a low level and a high level. The switching period of the write enable signal WEn is tWC.

[0049] The NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to sequentially transmit the commands AA and BB to the NAND chip 42 in synchronization with the rising of the write enable signal WEn. The input / output circuit 102 uses the I / O signal line DQ[7:0] to sequentially latch the sequentially input commands AA and BB in synchronization with the rising of the write enable signal WEn. The latched commands are transmitted to the command register 108.

[0050] After the transmission of the command BB, the NAND I / F circuit 32 disables the command latch enable signal CLE and enables the address latch enable signal ALE.

[0051] The NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to sequentially transmit the row addresses C1 and C2 of 2 cycles and the column addresses R1, R2, and R3 of 3 cycles to the NAND chip 42 in synchronization with the rising of the write enable signal WEn. The input / output circuit 102 sequentially latches the row addresses C1 and C2 and the column addresses R1, R2, and R3 sequentially input using the I / O signal line DQ[7:0] in synchronization with the rising of the write enable signal WEn. The latched addresses are transmitted to the address register 110.

[0052] After the column address R3 is transmitted, the NAND I / F circuit 32 maintains the write enable signal WEn at a high level, thereby stopping the switching of the write enable signal WEn.

[0053] After the column address R3 is transmitted, the NAND I / F circuit 32 maintains the data strobe signal DQS at a high level.

[0054] The NAND I / F circuit 32 disables the address latch enable signal ALE while maintaining the data strobe signal DQS at a high level.

[0055] The NAND I / F circuit 32 maintains the data strobe signal DQS at a low level after the address latch enable signal ALE is disabled.

[0056] The NAND I / F circuit 32 starts switching the data strobe signal DQS after the write preamble period t WPRE after the data strobe signal DQS is maintained at a low level. The NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to sequentially transmit the write data d0, d1, ... to the NAND chip 42 in synchronization with the rising and falling edges of the data strobe signal DQS. The input / output circuit 102 of the NAND chip 42 sequentially latches the write data sequentially input using the I / O signal line DQ[7:0] in synchronization with the rising and falling edges of the data strobe signal DQS. The latched write data is transmitted to the data register 124.

[0057] The period from when the switching of the write enable signal WEn stops to when the switching of the data select signal DQS starts (Address to Data Loading time) is called t ADL.

[0058] After the transmission of the write data is completed, the NAND I / F circuit 32 stops switching of the data strobe signal DQS.

[0059] After stopping the switching of the data strobe signal DQS, the NAND I / F circuit 32 enables the command latch enable signal CLE after a fixed time, and performs only one switching of the write enable signal WEn.

[0060] The NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to transmit the command EE to the NAND chip 42 in synchronization with the rising of the write enable signal WEn. The command EE indicates the start of the data write operation from the data register 124 to the memory cell array 120.

[0061] The input / output circuit 102 latches the command EE inputted using the I / O signal line DQ[7:0] in synchronization with the rising edge of the write enable signal WEn.

[0062] The NAND I / F circuit 32 maintains the data strobe signal DQS at a high level after a fixed time has passed since the write enable signal WEn falls.

[0063] As a switching interface between the memory controller 20 and the NAND flash memory 40, there are known a switching interface using a matched DQS (Data Quality Services) method and a switching interface using an unmatched DQS (unmatched DQS) method.

[0064] Regarding the switching interface of the matching DQS method, the data selection signal DQS and the I / O signal DQ input to the input-output circuit 102 are latched via delay circuits with the same delay time.

[0065] Regarding the switching interface that does not match the DQS mode, the data selection signal DQS input to the input-output circuit 102 is latched via the delay circuit, but the I / O signal DQ is not latched via the delay circuit.

[0066] FIG. 4 is a circuit diagram for explaining an example of the input-output circuit 102 of the first embodiment. FIG. 4 shows an example of the input-output circuit 102 when a switching interface using a matching DQS method is adopted. The input-output circuit 102 includes an input receiver 150 and eight input circuits 132-0 to 132-7. When the input circuits 132-0 to 132-7 do not need to be distinguished individually, they are referred to as input circuits 132. An input circuit 132 is provided for each I / O signal line DQ. The data strobe signal line DQS is connected to the input receiver 150. The output of the input receiver 150 is commonly connected to the eight input circuits 132-0 to 132-7. The input circuit 132 includes an input receiver 140, delay circuits 142, 152, and a latch 144. Examples of the delay circuits 142, 152 are each a buffer amplifier and / or a serially connected circuit of an inverter. An example of the latch 144 is a D-type flip-flop.

[0067] The input receiver 140 is connected to an I / O signal line DQ. The output signal of the input receiver 140 is input to the input terminal D of the latch 144 via the delay circuit 142. The output signal of the input receiver 150 is input to the clock terminal CK of the latch 144 via the delay circuit 152.

[0068] The output signal of the latch 144 is input to the data register 124 of the memory circuit 46 .

[0069] FIG. 5 is a waveform diagram for explaining an operation example of the input circuit 132 of the first embodiment.

[0070] FIG5(a) shows the waveform of the data strobe signal DQS input to the input receiver 150. FIG5(b) shows the waveform of the I / O signal DQ input to the input receiver 140. FIG5(c) shows the waveform of the data strobe signal DQS input to the clock terminal CK of the latch 144. FIG5(d) shows the waveform of the I / O signal DQ input to the input terminal D of the latch 144.

[0071] When transmitting write data, the NAND I / F circuit 32 switches the data strobe signal DQS. The NAND I / F circuit 32 outputs the write data d0, d1, ... to the I / O signal line DQ[7:0] in synchronization with the rising and falling edges of the data strobe signal DQS.

[0072] As shown in FIG. 5( a) and FIG. 5( b), the data strobe signal DQS and the I / O signal DQ are input to the input receivers 150 and 140 at the same time. The data strobe signal DQS and the I / O signal DQ output from the input receivers 150 and 140 are input to the latch 144 via the delay circuits 152 and 142 respectively. Here, it is assumed that the delay time of the delay circuits 152 and 142 is equal to each other, that is, the time t D. Therefore, as shown in FIG. 5( c) and FIG. 5( d), the data strobe signal DQS and the I / O signal DQ are input to the clock terminal CK and the input terminal D of the latch 144 at the same time after the fixed delay time t D.

[0073] The circuit is designed so that the delay time of each of the delay circuits 142 of the eight input circuits 132-0 to 132-7 is equal to each other. However, the delay time associated with each bit of the I / O signal DQ[7:0] may sometimes deviate from the designed value. In this case, there may be a deviation between the 8-bit I / O signals DQ[7:0], causing the latch 144 to be unable to latch accurate data.

[0074] In order to prevent this deviation, a switching interface with unmatched DQS mode was developed.

[0075] FIG6 is a circuit diagram for explaining another example of the input-output circuit 102 of the first embodiment. FIG6 shows an example of the input-output circuit 102 when the switching interface of the unmatched DQS method is adopted. The input-output circuit 102 includes an input receiver 150 and eight input circuits 134-0 to 134-7. The input circuits 134-0 to 134-7 are referred to as input circuits 134 when they do not need to be distinguished individually. An input circuit 134 is provided for each I / O signal line DQ. The data strobe signal line DQS is connected to the input receiver 150. The output of the input receiver 150 is commonly connected to the eight input circuits 134-0 to 134-7. The difference between the input circuit 134 and the input circuit 132 of the matched DQS method is that the delay circuit 142 is not connected between the input receiver 140 and the latch 144. The output signal of the input receiver 140 is directly input to the input terminal D of the latch 144.

[0076] FIG. 7 is a waveform diagram for explaining an operation example of the input circuit 134 according to the first embodiment.

[0077] FIG7(a) shows the waveform of the data strobe signal DQS input to the input receiver 150. FIG7(b) shows the waveform of the I / O signal DQ input to the input receiver 140. FIG7(c) shows the waveform of the data strobe signal DQS input to the clock terminal CK of the latch 144. FIG7(d) shows the waveform of the I / O signal DQ input to the input terminal D of the latch 144.

[0078] When transmitting write data, the NAND I / F circuit 32 switches the data strobe signal DQS. After the NAND I / F circuit 32 starts switching the data strobe signal line DQS, it outputs the write data d0, d1, ... to the I / O signal line DQ[7:0] after a delay time tD. The NAND I / F circuit 32 outputs the write data d0, d1, ... to the I / O signal line DQ[7:0] synchronously with both the rising and falling edges of the data strobe signal DQS.

[0079] As shown in FIG. 7(a) and FIG. 7(b), the data strobe signal DQS is input to the input receiver 150 earlier than the I / O signal DQ is input to the input receiver 140 by time tD. The data strobe signal DQS output from the input receiver 150 is input to the latch 144 via the delay circuit 152. Here, it is assumed that the delay time of the delay circuit 152 is time tD. On the other hand, the I / O signal DQ output from the input receiver 140 is input to the latch 144 without passing through the delay circuit. Therefore, as shown in FIG. 7(c) and FIG. 7(d), the data strobe signal DQS and the I / O signal DQ are simultaneously input to the clock terminal CK and the input terminal D of the latch 144, respectively.

[0080] For each of the eight input circuits 134-0 to 134-7 that use the unmatched DQS method, the timing of the data strobe signal DQS and the I / O signal DQ arriving at the latch 144 is adjusted only by the delay circuit 152. That is, the I / O signal DQ is not delayed in the input circuit 134. Therefore, it is not easy to generate deviation between the 8-bit I / O signals DQ[7:0], and the latch 144 can latch accurate data.

[0081] Another reason for the timing deviation of the I / O signal DQ and the data strobe signal DQS is, for example, the temperature and the power supply voltage of the SSD 14 .

[0082] If the temperature of SSD 14 changes, the delay time of delay circuits 142 and 152 may also change. For example, if the temperature changes, the delay time of delay circuits 142 and 152 may also change from time tD.

[0083] In the case of a switching interface that does not match the DQS method, the NAND I / F circuit 32 starts switching the data strobe signal DQS and outputs the write data d0, d1, ... to the I / O signal line DQ[7:0] after a delay time t D. However, if the delay time of the delay circuit 152 changes from the time t D, the data strobe signal DQS and the I / O signal DQ will not be simultaneously input to the clock terminal CK and the input terminal D of the latch 144 of the input circuit 134.

[0084] In the case of a switching interface using a matched DQS method, the I / O signal DQ and the data strobe signal DQS are simultaneously input to the input receivers 140 and 150. However, if the delay time of the delay circuits 142 and 152 varies, the data strobe signal DQS and the I / O signal DQ will not be simultaneously input to the clock terminal CK and the input terminal D of the latch 144 of the input circuit 132.

[0085] Since the temperature of the SSD 14 changes over a relatively long period of several seconds, the input timing of the data strobe signal DQS and the I / O signal DQ to the latch 144 can be adjusted by, for example, training during the operation of the SSD 14. The training takes, for example, several microseconds to several milliseconds. For example, by changing the timing of the output data strobe signal DQS by the NAND I / F circuit 32, the offset of the timing of the data strobe signal DQS and the I / O signal DQ caused by the temperature change can be compensated.

[0086] The power supply voltage of the SSD 14 decreases, for example, after the NAND I / F circuit 32 sends the I / O signal DQ or the control signal.

[0087] FIG8 is a diagram for explaining an example of a power supply voltage drop caused by the NAND I / F circuit 32 sending an I / O signal DQ or a control signal. FIG8 shows an example of using a switching interface of an unmatched DQS method as an interface between the memory controller 20 and the NAND flash memory 40. FIG8(a) shows an example of a waveform of a data selection signal DQS at an input terminal of an input circuit 134. FIG8(b) shows an example of a waveform of an I / O signal DQ at an input terminal of an input circuit 134. FIG8(c) shows an example of a power supply voltage VCCQ output by a power supply circuit 50. The power supply voltage VCCQ is a power supply voltage for the NAND I / F circuit 32 to send an I / O signal DQ and a control signal.

[0088] After the switching of the data strobe signal DQS starts, the power supply voltage VCCQ decreases. After that, the power supply voltage VCCQ changes synchronously with the switching of the data strobe signal DQS. After the data transmission via the I / O signal line DQ[7:0] starts, the power supply voltage VCCQ further decreases. The decrease in the power supply voltage VCCQ is the largest immediately after the data transmission via the I / O signal line DQ[7:0] starts (for example, several nanoseconds), and then decreases. The decrease in the power supply voltage VCCQ is caused by, for example, an ohmic voltage drop (IR voltage drop).

[0089] FIG. 8 is an example of a switching interface without a matched DQS method. However, when a switching interface with a matched DQS method is used, the power supply voltage VCCQ is also reduced.

[0090] When the power supply voltage VCCQ decreases, the driving capability of the NAND I / F circuit 32 decreases, and the signal quality of the I / O signal DQ or the control signal deteriorates. Specifically, the level or pulse width of the I / O signal DQ or the control signal changes. As a result, the latch 144 may not be able to correctly capture data.

[0091] The power supply voltage VCCQ changes in a relatively short period of about several nanoseconds. Therefore, the timing offset of the data strobe signal DQS and the I / O signal DQ caused by the change of the power supply voltage VCCQ cannot be adjusted by training.

[0092] The first embodiment prevents the timing deviation of the data strobe signal DQS and the I / O signal DQ caused by the power supply voltage reduction. FIG9 is a diagram for explaining an example of the operation of the NAND I / F circuit 32 of the first embodiment. In FIG9, the waveforms of signals other than the data strobe signal DQS, the I / O signal DQ[7:0] and the power supply voltage VCCQ are omitted.

[0093] Before the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send the write data d0, d1, ... to the NAND chip 42 (more specifically, the input / output circuit 102), it uses the I / O signal line DQ[7:0] to send the dummy data r0, r1, r2, r3 to the NAND chip 42. The dummy data r0, r1, r2, r3 are used to swing the level of the I / O signal line DQ[7:0] between a high level and a low level. The dummy data r0, r1, r2, r3 are pre-stored in the register 38.

[0094] An example of dummy data r0, r1, r2, and r3 is data in which all bits of each are 0. That is, r0 = 0x00, r1 = 0x00, r2 = 0x00, and r3 = 0x00. Here, ''0x'' represents hexadecimal.

[0095] Another example of the dummy data r0, r1, r2, and r3 is data in which all bits of each are 1. That is, r0=0xFF, r1=0xFF, r2=0xFF, and r3=0xFF.

[0096] Another example of the dummy data r0, r1, r2, and r3 is data in which all bits are 1, all bits are 0, all bits are 1, and all bits are 0 appear in sequence. That is, r0=0xFF, r1=0x00, r2=0xFF, and r3=0x00.

[0097] Another example of the dummy data r0, r1, r2, and r3 is data in which all bits are 0, all bits are 1, all bits are 0, and all bits are 1 appear in sequence. That is, r0=0x00, r1=0xFF, r2=0x00, and r3=0xFF.

[0098] By changing all I / O signal lines DQ[7:0] to a high level, the power supply voltage VCCQ may change significantly, and it takes time to become a stable state. Therefore, as another example of dummy data r0, r1, r2, and r3, consider data in which each even bit is 1 and each odd bit is 0. That is, r0=0x55, r1=0x55, r2=0x55, and r3=0x55. In this way, after sending the dummy data, the VCCQ voltage is easy to stabilize in a shorter period of time, and the NAND I / F circuit 32 can output high-quality write data to the I / O signal line DQ[7:0].

[0099] Another example of the dummy data r0, r1, r2, and r3 is data in which each even-numbered bit is 0 and each odd-numbered bit is 1. That is, r0=0xAA, r1=0xAA, r2=0xAA, and r3=0xAA.

[0100] Another example of the dummy data r0, r1, r2, and r3 is data in which the even bit is 1 and the odd bit is 0, the even bit is 0 and the odd bit is 1, the even bit is 1 and the odd bit is 0, and the even bit is 0 and the odd bit is 1 appear in sequence. That is, r0=0x55, r1=0xAA, r2=0x55, r3=0xAA.

[0101] Another example of the dummy data r0, r1, r2, and r3 is data in which the even bit is 0 and the odd bit is 1, data in which the even bit is 1 and the odd bit is 0, data in which the even bit is 0 and the odd bit is 1, and data in which the even bit is 1 and the odd bit is 0 appear in sequence. That is, r0=0xAA, r1=0x55, r2=0xAA, r3=0x55.

[0102] As described with reference to FIG. 3 , after sending the address, the NAND I / F circuit 32 disables the address latch enable signal ALE and then maintains the data strobe signal DQS at a low level. After maintaining the data strobe signal DQS at a low level, the NAND I / F circuit 32 starts switching the data strobe signal DQS after a write leading period t WPRE. During the write leading period t WPRE, the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send dummy data r0-r3.

[0103] The NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send the write data d0 after sending the dummy data r3. The NAND I / F circuit 32 sends the write data d0, d1, ... in synchronization with the switching of the data strobe signal DQS.

[0104] The power supply voltage VCCQ decreases due to the NAND I / F circuit 32 sending the dummy data r0. Afterwards, when the NAND I / F circuit 32 sends the dummy data r1, r2, and r3 to swing the level of the I / O signal line DQ[7:0], the power supply voltage VCCQ gradually increases.

[0105] The size of the dummy data is not limited to 4 bytes but is arbitrary. The pulse width of the dummy data does not need to be equal to the pulse width of the write data. The plural pulse widths of the dummy data may be different from each other. The amplitude of the dummy data does not need to be equal to the amplitude of the write data. The plural amplitudes of the dummy data may be different from each other. The plural dummy data do not need to be sent continuously. The plural dummy data may be sent discretely. The final dummy data r3 and the initial write data d0 do not need to be sent continuously. There may be a no-signal period between the final dummy data r3 and the initial write data d0. For example, the NAND I / F circuit 32 may also make the I / O signal line DQ[7:0] in the Hi-Z state from the sending of the final dummy data r3 to the sending of the initial write data d0. The transmission form of the dummy data including bit composition, size, pulse width, amplitude, and transmission timing can be freely set within the range that the power supply voltage VCCQ can be restored to the level before the dummy data r0 is sent before the initial write data d0 is sent.

[0106] By sending dummy data, when the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send the write data d0, d1, ... to the NAND chip 42, the power supply voltage VCCQ becomes stable. The NAND I / F circuit 32 can output high-quality write data to the I / O signal line DQ[7:0] and can send a high-quality data strobe signal DQS to the data strobe signal line DQS. Therefore, the data strobe signal DQS and the write data are input to the latch 144 at the same timing, and the latch 144 can accurately capture the write data.

[0107] The operation of the NAND I / F circuit 32 shown in FIG. 9 is applicable regardless of whether the interface between the memory controller 20 and the NAND flash memory 40 is a switching interface matching the DQS method or a switching interface not matching the DQS method.

[0108] According to the first embodiment, even if the power supply voltage varies, the NAND I / F circuit 32 can send high-quality data selection signals and write data, and the latch 144 can capture accurate write data.

[0109] (Second embodiment) Another embodiment is described below. The other embodiment is about a change in the operation of the NAND I / F circuit 32. The structure of the memory system is the same as that of the first embodiment.

[0110] Fig. 10 is a diagram for explaining an example of the operation of the NAND I / F circuit 32 of the second embodiment. The NAND I / F circuit 32 of the second embodiment switches the data strobe signal DQS during the DQS delay period.

[0111] Each of the input receivers 140 and 150 may generate inter-symbol interference. That is, when the value of data changes from a state where data of the same value is continuously input to each of the input receivers 140 and 150, the waveform of the signal corresponding to the changed value may be degraded. In particular, the waveform of the data strobe signal DQS in the input receiver 150 may be degraded. In addition, as described in the first embodiment, in the initial switching of the data strobe signal DQS, the ohmic voltage drop may cause the NAND I / F circuit 32 to be unable to increase (or decrease) the amplitude to a prescribed voltage. Therefore, the latch 144 may not accurately obtain the data strobe signal DQS input to the clock terminal.

[0112] The NAND I / F circuit 32 of the second embodiment switches the data strobe signal DQS during the DQS delay period before the transmission timing of the write data d0. Furthermore, the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to transmit dummy data r0 to r3 during the write preamble period t WPRE before the DQS delay period. In this way, the NAND I / F circuit 32 can increase (or decrease) the amplitude of the data strobe signal DQS to a specified voltage in the initial switching during the DQS delay period. The latch 144 can accurately obtain the data strobe signal DQS input to the clock terminal. Therefore, for example, the latch 144 is unlikely to fail to obtain the number of data strobe signals DQS expected to be input during the DQS delay period. The expected number of data strobe signals DQS is predetermined, for example, as the specification of the interface between the memory controller 20 and the NAND flash memory 40.

[0113] Before the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send the write data d0, d1, ... to the NAND chip 42, it uses the I / O signal line DQ[7:0] to send the dummy data r0-r7 to the NAND chip 42. The dummy data r0-r7 is used to make the level of the I / O signal line DQ[7:0] swing between a high level and a low level. The dummy data r0-r7 is pre-stored in the register 38.

[0114] The NAND I / F circuit 32 sends dummy data r0-r3 while maintaining the data strobe signal DQS at a low level, and sends dummy data r4-r7 in synchronization with the switching of the data strobe signal DQS. The period of sending dummy data r4-r7 in synchronization with the switching of the data strobe signal DQS is the DQS delay period.

[0115] The NAND I / F circuit 32 transmits the write data d0 after transmitting the dummy data r7. The NAND I / F circuit 32 transmits the write data d0, d1, ... in synchronization with the switching of the data strobe signal DQS.

[0116] Thus, the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send dummy data before the start of the DQS delay period. Thus, at the start timing of the DQS delay period, the power supply voltage VCCQ becomes a stable state. Thus, the NAND I / F circuit 32 can increase (or decrease) the amplitude of the initial data strobe signal DQS during the DQS delay period to a predetermined voltage. Furthermore, similarly to the first embodiment, when the NAND I / F circuit 32 uses the I / O signal line DQ[7:0] to send the write data d0, d1, ... to the NAND chip 42, the power supply voltage VCCQ becomes a stable state. Thus, the NAND I / F circuit 32 can output high-quality write data to the I / O signal line DQ[7:0].

[0117] In the second embodiment, the transmission form of the dummy data is freely set within a range in which the power supply voltage VCCQ can be restored to the level before the dummy data r0 is transmitted before the DQS delay period starts.

[0118] Furthermore, in the second embodiment, the switching cycle of the data strobe signal DQS during the DQS delay period is set equal to the switching cycle of the data strobe signal DQS during the write data output period, but the present invention is not limited thereto. For example, the switching cycle of the data strobe signal DQS during the DQS delay period may be different from the switching cycle of the data strobe signal DQS during the write data output period. That is, the pulse width of the dummy data r4 to r7 may be different from the pulse width of the write data d0, d1, ...

[0119] Furthermore, the switching cycle of the data strobe signal DQS during the DQS delay period can be varied and not fixed. For example, the switching cycle of the data strobe signal DQS at the beginning of the DQS delay period can be increased, then gradually shortened, and finally equal to the switching cycle of the data strobe signal DQS during the write data output period. When the switching cycle of the data strobe signal DQS increases, the time required for the amplitude of the data strobe signal DQS to become a state capable of rising (or falling) to a prescribed voltage is shorter. Therefore, it is expected that the amplitude of the data strobe signal DQS rises (or falls) to a prescribed voltage in the initial switching during the write data output period.

[0120] In addition to the change of the switching cycle of the data strobe signal line DQS, the transmission cycle of the dummy data and the written data can also be changed. For example, the transmission cycle of the dummy data r0~r3 can be set to 3p, the transmission cycle of the dummy data r4-r7 can be set to 2p, and the transmission cycle of the written data d0, d1, ... can be set to p.

[0121] (Third embodiment) The NAND I / F circuit 32 of the first and second embodiments transmits dummy data in the write leading period t WPRE immediately before the write data d0 is transmitted. The transmission timing of the dummy data r0 is not limited to this, and may be before the period t WPRE. FIG. 11 is a diagram for explaining an example of the operation of the NAND I / F circuit 32 of the third embodiment.

[0122] As described with reference to FIG. 3 , after sending the address, the NAND I / F circuit 32 maintains the write enable signal WEn and the data strobe signal DQS at a high level. The NAND I / F circuit 32 outputs dummy data r0-r4 to the I / O signal line DQ[7:0] while maintaining the write enable signal WEn and the data strobe signal DQS at a high level.

[0123] After the dummy data r4 is output, the NAND I / F circuit 32 maintains the data strobe signal DQS at a low level.

[0124] The NAND I / F circuit 32 maintains the data strobe signal DQS at a low level during the write leading period tWPRE, and then starts switching the data strobe signal DQS. The NAND I / F circuit 32 outputs the write data d0, d1, ... to the I / O signal line DQ[7:0] in synchronization with the switching of the data strobe signal DQS.

[0125] In the third embodiment, the transmission form of the dummy data is freely set within a range in which the power supply voltage VCCQ can be restored to the level before the dummy data r0 is transmitted before the first write data d0 is transmitted.

[0126] The NAND I / F circuit 32 of the third embodiment outputs dummy data to the I / O signal line DQ[7:0] immediately after sending the address. This allows the power supply voltage VCCQ to be stabilized earlier than in the first and second embodiments.

[0127] (Variation Example) The dummy data memorized in the register 38 may also be any pattern that easily causes the I / O signal line DQ[7:0] to swing. For example, the dummy data r0 may also be the data with the largest value among the dummy data r0~r3 (or r0~r7), and the value becomes smaller as it becomes the dummy data r1, r2, ...

[0128] The dummy data is data that causes the I / O signal line DQ[7:0] to swing to compensate for the decrease in the power supply voltage VCCQ caused by the output of the I / O signal line DQ[7:0]. However, the decrease in the power supply voltage VCCQ may vary with temperature. Considering this point, the dummy data may also be changed by temperature.

[0129] Several embodiments of the present invention are described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the scope of the patent application and its equivalent.

[0130] [Related applications] This application claims priority based on Japanese Patent Application No. 2023-041613 (filing date: March 16, 2023). This application incorporates all the contents of the basic application by reference.

[0131] 10: Information Processing System 12: Host 14:Memory System 20:Memory controller 22: Host interface circuit 24:CPU 26: DRAM interface circuit 28:SRAM 30: Encoder / Decoder 32:NAND interface circuit 34: Bus 36: DRAM 38: Register 40:NAND flash memory 42:NAND chip 42-0~42-3: NAND chip 44: Peripheral circuit 46:Memory Circuit 50: Power circuit 102: Input and output circuit 104:Logic control circuit 106: Chip control circuit 108: Instruction register 110: Address register 112: Ready / Busy Circuit 120:Memory cell array 122: Line decoder 124: Data register 126: Sense Amplifier 128: Column decoder 132: Input circuit 132-0~132-7: Input circuit 134: Input circuit 134-0~134-7: Input circuit 140: Input Receiver 142: Delay circuit 144: Latch 150: Input receiver 152: Delay circuit AA, BB: Instructions ALE: Address latch enable signal line BYn: Ready / Busy signal line C1, C2: row address CEn: Chip enable signal line CK: Clock terminal CLE: Command latch enable signal line D: Input terminal d0, d1, …: write data DQ: I / O signal line DQ[7:0]: I / O signal line DQS: Data selection signal line DQSn: Data strobe signal line EE: Instructions Hi-Z: High impedance state r0~r7: dummy data R1, R2, R3: column address RE: Read enable signal line REn: Read enable signal line RY: Ready / Busy signal line tADL: The period from when the write enable signal stops switching to when the data strobe signal starts switching (address to data loading time) t D: Delay time t WC: switching cycle t WPRE: Write leading period VCCQ: power supply voltage WEn: Write enable signal line

Claims

1. A memory system comprising: a non-volatile memory; and a controller electrically connected to the non-volatile memory using at least a first signal line and a second signal line; and configured to: after sending a write instruction and an address to the non-volatile memory, during at least a portion of the period between sending the address and sending write data of the write instruction via the first signal line, send dummy data to the non-volatile memory via the first signal line. After sending the dummy data via the first signal line, a data strobe signal is sent to the non-volatile memory via the second signal line. Simultaneously with the data strobe signal, the write data of the write instruction is sent to the non-volatile memory via the first signal line. When the address latch enable signal is enabled, the address is sent to the non-volatile memory. After sending the address, the address latch enable signal is disabled. After the address latch enable signal is disabled, while keeping the data strobe signal at a low level, the dummy data is sent to the non-volatile memory via the first signal line. During the transmission of the dummy data, the data strobe signal is switched.

2. The memory system of claim 1, wherein the controller is configured to, after sending the dummy data, start switching the data strobe signal, and synchronously send the write data to the non-volatile memory via the first signal line in sync with the switching of the data strobe signal.

3. The memory system of claim 1, wherein the controller is configured to transmit a first portion of the dummy data to the non-volatile memory via the first signal line when the data strobe signal is maintained at a low level, and to transmit a second portion of the dummy data to the non-volatile memory via the first signal line synchronously with the switching of the data strobe signal.

4. The memory system of claim 1, wherein the aforementioned dummy data includes first dummy data and second dummy data following the first dummy data, wherein the first dummy data is data in which even-numbered bits have a first value and odd-numbered bits have a second value different from the first value, and the second dummy data is data in which even-numbered bits have the second value and odd-numbered bits have the first value.

5. The memory system of claim 1, wherein the controller is configured to send the write instruction and the address to the non-volatile memory via the first signal line.

6. A memory system comprising: a non-volatile memory; and a controller electrically connected to the non-volatile memory using at least a first signal line and a second signal line; and configured to: after sending a write instruction and an address to the non-volatile memory, during at least a portion of the period between sending the address and sending write data of the write instruction via the first signal line, send dummy data to the non-volatile memory via the first signal line. After sending the dummy data via the first signal line, a data strobe signal is sent to the non-volatile memory via the second signal line. Simultaneously with the data strobe signal, the write data of the write instruction is sent to the non-volatile memory via the first signal line. While the data strobe signal remains high, the dummy data is sent to the non-volatile memory via the first signal line. After the dummy data is completely sent, the data strobe signal is kept low for a specified period of time. After the specified period of time has elapsed, the data strobe signal is switched. Simultaneously with the switching of the data strobe signal, the write data is sent to the non-volatile memory via the first signal line.

7. A memory system comprising: a non-volatile memory; and a controller electrically connected to the non-volatile memory using at least a first signal line and a second signal line; and configured to: after sending a write instruction and an address to the non-volatile memory, during at least a portion of the period between sending the address and sending write data of the write instruction via the first signal line, send dummy data to the non-volatile memory via the first signal line; after sending the dummy data via the first signal line, send a data strobe signal to the non-volatile memory via the second signal line, and the data strobe signal is connected at rising and falling edges. Synchronously, the write data of the write instruction is sent to the non-volatile memory via the first signal line, and the address is sent to the non-volatile memory when the address latch enable signal is enabled. After sending the address, the address latch enable signal is disabled. After the address latch enable signal is disabled, the dummy data is sent to the non-volatile memory via the first signal line while the data strobe signal is kept low. During the sending of the dummy data, the data strobe signal is switched.

8. The memory system of claim 7, wherein the controller is configured to, after sending the dummy data, start switching the data strobe signal, and send the write data to the non-volatile memory via the first signal line synchronously with the rising and falling edges of the data strobe signal.

9. The memory system of claim 7, wherein the controller is configured to transmit a first portion of the dummy data to the non-volatile memory via the first signal line when the data strobe signal is maintained at a low level, and to transmit a second portion of the dummy data to the non-volatile memory via the first signal line synchronously with the rising and falling edges of the data strobe signal.

10. The memory system of claim 7, wherein the aforementioned dummy data includes first dummy data and second dummy data following the first dummy data, wherein the first dummy data is data in which even-numbered bits have a first value and odd-numbered bits have a second value different from the first value, and the second dummy data is data in which even-numbered bits have the second value and odd-numbered bits have the first value.

11. The memory system of claim 7, wherein the controller is configured to send the write instruction and the address to the non-volatile memory via the first signal line.

12. A memory system comprising: a non-volatile memory; and a controller electrically connected to the non-volatile memory using at least a first signal line and a second signal line; and configured to: after sending a write instruction and an address to the non-volatile memory, during at least a portion of the period between sending the address and sending write data of the write instruction via the first signal line, send dummy data to the non-volatile memory via the first signal line; after sending the dummy data via the first signal line, send a data strobe signal to the non-volatile memory via the second signal line, and the data strobe signal is connected at rising and falling edges. Synchronously with the edges, the write data of the write instruction is sent to the non-volatile memory via the first signal line, and while the data strobe signal is maintained at a high level, the dummy data is sent to the non-volatile memory via the first signal line. After the dummy data is completely sent, the data strobe signal is maintained at a low level for a specified period of time. After the specified period of time has elapsed, the data strobe signal is switched, and the write data is sent to the non-volatile memory synchronously with the rising and falling edges of the data strobe signal via the first signal line.

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