Display device and electronic device

Abstract

One embodiment of the present invention provides a display device capable of improving image quality. A storage node is provided in each pixel, which can hold first data. Second data is attached to the first data by capacitive coupling, and the first data can be supplied to a display element. Therefore, the display device can display a corrected image. Furthermore, since a reference potential for capacitive coupling is supplied from a power line or the like, the first and second data can be supplied from a shared signal line.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, driving methods for these devices, or manufacturing methods for these devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are one embodiment of a semiconductor device. In addition, memory devices, display devices, imaging devices, and electronic devices sometimes include semiconductor devices. [Previous Technology]

[0004] Silicon semiconductor materials are widely known as semiconductor thin films that can be applied to transistors. Among other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxides (hereinafter also referred to as IGZO) is particularly active.

[0005] Through research on IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, were discovered in oxide semiconductors (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing transistors using oxide semiconductors with CAAC structures. Furthermore, Non-Patent Documents 4 and 5 disclose oxide semiconductors with even lower crystallinity than CAAC and nc structures, which also exhibit minute crystals.

[0006] Transistors using IGZO as the active layer have extremely low off-state current (see Non-Patent Document 6), and LSIs and displays that utilize this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, Patent Document 1 discloses a memory device having a structure that uses transistors with extremely low off-state current in memory cells. [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2011-119674 [Non-Patent Document]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, pp. 021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 [Invention Content]

[0010] As the resolution of display devices continues to improve, hardware capable of displaying 8K4K (7680×4320 pixels) or higher resolution images has been developed. In addition, the introduction of HDR (High Dynamic Range) display technology, which improves image quality through brightness adjustment, has been advanced.

[0011] In order for the display device to display the image data appropriately, the image data needs to correspond to the resolution of the display device. For example, when the resolution of the display device is 8K4K and the image data is for 4K2K (pixel count: 3840×2160), full-screen display is not possible unless the data quantity is converted to 4 times. Conversely, when the resolution of the display device is 4K2K and the image data is for 8K4K, the data quantity needs to be converted to 1 / 4.

[0012] Furthermore, the generation and conversion of image data in HDR processing require dedicated circuitry, leading to increased power consumption. It is preferable to at least input the original image data into the pixels of the display device without converting it.

[0013] Therefore, one objective of an embodiment of the present invention is to provide a display device capable of improving image quality. Another objective of an embodiment of the present invention is to provide a display device capable of performing appropriate display without converting image data. Another objective of an embodiment of the present invention is to provide a display device capable of HDR display. Another objective of an embodiment of the present invention is to provide a display device capable of performing upconversion. Another objective of an embodiment of the present invention is to provide a display device capable of improving the brightness of the displayed image. Another objective of an embodiment of the present invention is to provide a display device capable of displaying two images in an overlapping manner.

[0014] Furthermore, one objective of an embodiment of the present invention is to provide a low-power display device. Additionally, one objective of an embodiment of the present invention is to provide a highly reliable display device. Furthermore, one objective of an embodiment of the present invention is to provide a novel display device, etc. Furthermore, one objective of an embodiment of the present invention is to provide a driving method for the above-described display device. Furthermore, one objective of an embodiment of the present invention is to provide a novel semiconductor device, etc.

[0015] Note that the description of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Furthermore, objectives other than those described above are obvious from the description in the specification, drawings, and claims, and can be derived from the description in the specification, drawings, and claims.

[0016] One embodiment of the present invention relates to a display device capable of improving image quality. Another embodiment of the present invention relates to a display device capable of image processing.

[0017] One embodiment of the present invention is a display device, comprising: a first transistor, a second transistor, a third transistor, a first capacitor, a circuit block, a first wiring, and a second wiring, wherein one of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the second transistor is electrically connected to one electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to one of the source and drain of the third transistor, one of the source and drain of the third transistor is electrically connected to the circuit block, the other of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the third transistor is electrically connected to the first wiring, the gate of the second transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the second wiring, and the circuit block includes a display element.

[0018] In another embodiment of the present invention, a display device is provided, comprising: a first transistor, a second transistor, a first circuit, a second circuit, a first wiring, and a second wiring, wherein both the first circuit and the second circuit include a third transistor, a first capacitor, and a circuit block; one of the source and drain electrodes of the third transistor is electrically connected to one electrode of the first capacitor; one electrode of the first capacitor is electrically connected to the circuit block; the other electrode of the first capacitor is electrically connected to one of the source and drain electrodes of the first transistor; one of the source and drain electrodes of the first transistor is electrically connected to one of the source and drain electrodes of the second transistor; the other of the source and drain electrodes of the third transistor included in the first circuit is electrically connected to the first wiring; the other of the source and drain electrodes of the first transistor is electrically connected to the first wiring; the gate of the third transistor included in the first circuit is electrically connected to the second wiring; the gate of the third transistor included in the second circuit is electrically connected to the second wiring; the gate of the second transistor is electrically connected to the second wiring; and the circuit block includes a display element.

[0019] The circuit block includes a fourth transistor, a fifth transistor, a second capacitor, and an organic EL element as a display element, and may have the following structure: one electrode of the organic EL element is electrically connected to one of the source and drain electrodes of the fifth transistor, the other of the source and drain electrodes of the fifth transistor is electrically connected to one electrode of the second capacitor, one electrode of the second capacitor is electrically connected to one of the source and drain electrodes of the fourth transistor, the gate of the fourth transistor is electrically connected to the other electrode of the second capacitor, and the other electrode of the second capacitor is electrically connected to one electrode of the first capacitor.

[0020] In the above structure, the other of the source and drain of the fourth transistor can be electrically connected to the other of the source and drain of the second transistor.

[0021] In addition, the circuit block includes a sixth transistor, a third capacitor, and a liquid crystal element as a display element, and may have the following structure: one electrode of the liquid crystal element is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to one of the source and drain electrodes of the sixth transistor, and the other of the source and drain electrodes of the sixth transistor is electrically connected to one electrode of the first capacitor.

[0022] In the above structure, the other electrode of the third capacitor can be electrically connected to the other of the source and drain electrodes of the second transistor.

[0023] The third transistor has a metal oxide in the channel forming region, and the metal oxide is preferably In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

[0024] By using one embodiment of the present invention, a display device capable of improving image quality can be provided. By using one embodiment of the present invention, a display device capable of performing appropriate display without converting image data can be provided. By using one embodiment of the present invention, a display device capable of performing HDR display can be provided. By using one embodiment of the present invention, a display device capable of performing upconversion can be provided. By using one embodiment of the present invention, a display device capable of improving the brightness of the displayed image can be provided. By using one embodiment of the present invention, a display device capable of displaying two images overlay can be provided.

[0025] Additionally, a low-power display device can be provided. Furthermore, a highly reliable display device can be provided. Additionally, a novel display device can be provided, etc. Furthermore, a driving method for the above-mentioned display device can be provided. Furthermore, a novel semiconductor device can be provided, etc.

Implementation Method

[0027] The embodiments will be described in detail using drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same element symbols are used in different drawings to represent the same parts or parts having the same function, and repeated descriptions are omitted. Note that sometimes the shading of the same components is appropriately omitted or changed in different drawings.

[0028] Embodiment 1 In this embodiment, a display device according to an embodiment of the present invention will be described with reference to the drawings.

[0029] One embodiment of the present invention is a display device having the function of correcting image data in pixels. A storage node is provided in each pixel, and first data can be stored in the storage node. Second data is attached to the first data by capacitive coupling, and the first data can be supplied to a display element. Alternatively, the first data can be attached by capacitive coupling after the second data is written to the storage node.

[0030] Thus, the display device can display the calibrated image. Through this calibration, image upconversion can be performed. Alternatively, HDR display can be performed by calibrating part or all of the image in the display unit. Alternatively, by using the same image data as the first and second data, the brightness of the displayed image can be significantly improved. Alternatively, by using different image data as the first and second data, arbitrary images can be displayed in an overlay manner.

[0031] Furthermore, by using one embodiment of the present invention, two image data for high resolution and low resolution can be displayed appropriately without up-converting or down-converting them. In the case of high-resolution display, different data is supplied to each pixel via a first transistor included in each pixel. In the case of low-resolution display, the same data is supplied to the multiple pixels via a second transistor electrically connected to the multiple pixels.

[0032] Here, high-resolution image data is, for example, equivalent to data corresponding to 8K4K (pixel count: 7680 × 4320). Furthermore, low-resolution image data is, for example, equivalent to data corresponding to 4K2K (pixel count: 3840 × 2160). That is, it is assumed that the effective ratio of the number of high-resolution image data to low-resolution image data (corresponding to the effective number of pixels) is 4:1.

[0033] Furthermore, as long as the ratio of data quantity (pixel count) is 4:1, it is not limited to the above examples. The high-resolution image data can be data corresponding to 4K2K, and the low-resolution image data can be data corresponding to FullHD (pixel count: 1920×1080). Alternatively, the high-resolution image data can be data corresponding to 16K8K (pixel count: 15360×8640), and the low-resolution image data can be data corresponding to 8K4K.

[0034] FIG1 is a diagram illustrating a pixel 10 of a display device that can be used in one embodiment of the present invention. Pixel 10 includes transistors 101, 102, 103, capacitor 104, and circuit block 110. Circuit block 110 may include transistors, capacitors, and display elements, etc. Details will be described later.

[0035] One of the source and drain terminals of transistor 101 is electrically connected to one of the source and drain terminals of transistor 102. One of the source and drain terminals of transistor 102 is electrically connected to one electrode of capacitor 104. The other electrode of capacitor 104 is electrically connected to one of the source and drain terminals of transistor 103. One of the source and drain terminals of transistor 103 is electrically connected to circuit block 110.

[0036] Here, the wiring connecting one of the source and drain electrodes of transistor 103, the other electrode of capacitor 104, and circuit block 110 is designated as node NM. Furthermore, the components of circuit block 110 connected to node NM can allow node NM to be in a floating state.

[0037] The gate of transistor 101 is electrically connected to wiring 122. The gates of transistor 102 and 103 are electrically connected to wiring 121. The other of the source and drain of transistor 101 and the other of the source and drain of transistor 103 are electrically connected to wiring 123. The other of the source and drain of transistor 102 is electrically connected to wiring capable of supplying a specific potential "Vref".

[0038] Wiring 121 and 122 can function as signal lines for controlling the operation of transistors. Wiring 123 can function as a signal line for supplying first data or second data. As wiring capable of supplying "Vref", power lines electrically connected to components in circuit block 110 can be used, for example.

[0039] In addition, in order to perform the capacitive coupling operation described later, it is necessary to supply “Vref” and first data (e.g., correction data) to the pixel during the same period. Therefore, when supplying “Vref” from the signal line, at least a signal line supplying the first data and a signal line supplying “Vref” or second data (e.g., image data) are required.

[0040] On the other hand, since "Vref" is supplied from a power line or the like in the display device of one embodiment of the present invention, the first data or the second data can be supplied using a single signal line (wiring 123) depending on the switching timing. In other words, the display device of one embodiment of the present invention can be configured with fewer wirings.

[0041] Node NM is a storage node. By turning on transistor 103, data supplied to wiring 123 can be written to node NM. Furthermore, by turning off transistor 103, this data can be retained in node NM. By using a transistor with extremely low off-state current as transistor 103, the potential of node NM can be maintained for a long time. For example, a transistor using metal oxide in the channel formation region (hereinafter, OS transistor) can be used as this transistor.

[0042] OS transistors can be used not only in transistor 103 but also in other transistors constituting pixels. Transistor 103 can also use transistors containing Si in the channel forming region (hereinafter referred to as Si transistors), or both OS transistors and Si transistors. Examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (typically low-temperature polycrystalline silicon and monocrystalline silicon).

[0043] As semiconductor materials for OS transistors, metal oxides with a bandgap of 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS mentioned later. In CAAC-OS, the atoms constituting the crystal are stable, making it suitable for transistors where reliability is important. CAC-OS exhibits high mobility characteristics, making it suitable for transistors used in high-speed driving.

[0044] OS transistors have a large bandgap and exhibit extremely low off-state current characteristics. Unlike Si transistors, OS transistors do not experience impact ionization, sudden breakdown, or short-channel effects, thus enabling the formation of highly reliable circuits.

[0045] As the semiconductor layer in the OS transistor, for example, a film containing indium, zinc and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium) and referred to as "In-M-Zn oxide".

[0046] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. Preferred atomic ratios of the metal elements in such sputtering targets are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. Note that the atomic ratio of the formed semiconductor layer may vary within ±40% of the atomic ratio of the metal elements in the sputtering target described above.

[0047] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, an oxide semiconductor with a carrier density of 1×10¹⁷ / cm³ or less, preferably 1×10¹⁵ / cm³ or less, more preferably 1×10¹³ / cm³ or less, further preferably 1×10¹¹ / cm³ or less, and even more preferably less than 1×10¹⁰ / cm³ or more than 1×10⁻⁹ / cm³ can be used as the semiconductor layer. Such an oxide semiconductor is referred to as a high-purity or substantially high-purity oxide semiconductor. This oxide semiconductor has a low defect energy level density, and therefore can be considered an oxide semiconductor with stable characteristics.

[0048] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the desired semiconductor characteristics and electrical characteristics (field-effect mobility, critical voltage, etc.) of the transistor. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0049] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which are elements of Group 14, oxygen defects increase, causing the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10¹⁸ atoms / cm³ or less, preferably 2×10¹⁷ atoms / cm³ or less.

[0050] In addition, sometimes when alkali metals and alkaline earth metals bond with oxide semiconductors, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10¹⁸ atoms / cm³ or less, preferably 2×10¹⁶ atoms / cm³ or less.

[0051] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, increasing the carrier density and making it easier to become n-type. As a result, transistors using nitrogen-containing oxide semiconductors are more likely to become normally-on. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5 × 10¹⁸ atoms / cm³ or less.

[0052] In addition, the semiconductor layer may also have a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with c-axis alignment, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest defect state density.

[0053] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not have crystalline components. Alternatively, an amorphous oxide film, for example, is a completely amorphous structure and does not have crystalline portions.

[0054] Furthermore, the semiconductor layer may also be a mixture of two or more regions having an amorphous structure, a microcrystalline structure, a polycrystalline structure, a CAAC-OS region, and a single-crystal structure. The mixture may sometimes have, for example, a single-layer structure or a stacked structure including two or more of the aforementioned regions.

[0055] The following describes the structure of CAC (Cloud-Aligned Composite)-OS in one embodiment of a non-single-crystal semiconductor layer.

[0056] CAC-OS refers, for example, to a configuration in which elements contained in an oxide semiconductor are non-uniformly distributed, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed in an oxide semiconductor and the regions containing the metal elements are mixed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately, is also referred to as mosaic or patch.

[0057] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0058] For example, CAC-OS in In-Ga-Zn oxide (in particular, In-Ga-Zn oxide can be called CAC-IGZO) refers to a material divided into indium oxide (hereinafter referred to as InOX1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter referred to as InX2ZnY2OZ2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaOX3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as GaX4ZnY4OZ4 (X4, Y4 and Z4 are real numbers greater than 0)) etc., which are mosaic-shaped, and the mosaic-shaped InOX1 or InX2ZnY2OZ2 is uniformly distributed in the film (hereinafter also referred to as cloud-like).

[0059] In other words, CAC-OS is a composite oxide semiconductor composed of regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components. In this specification, for example, when the ratio of the number of In atoms to the number of M atoms in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0060] Note that IGZO is a general term and sometimes refers to compounds containing In, Ga, Zn and O. As a typical example, crystalline compounds can be represented as InGaO3(ZnO)m1 (m1 is a natural number) or In(1+x0)Ga(1-x0)O3(ZnO)m0 (-1≤x0≤1, m0 is any number).

[0061] The above-mentioned crystalline compounds have a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-orienting manner on the ab plane.

[0062] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in one part of which nanoparticle-like regions with Ga as the main component are observed, and in another part of which nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0063] CAC-OS does not contain a stacked structure of two or more different membranes. For example, it does not contain a structure consisting of two layers: a membrane with In as the main component and a membrane with Ga as the main component.

[0064] Note that sometimes it is not possible to observe a clear boundary between regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components.

[0065] When CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a structure in which nanoparticle-like regions with the element as the main component are observed in one part and nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern in another part.

[0066] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the deposition gas. Furthermore, the lower the oxygen gas flow rate in the total flow rate of the deposition gas during film formation, the better; for example, the oxygen gas flow rate ratio is set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0067] CAC-OS has the following characteristics: when measured using the out-of-plane method, one of the X-ray diffraction measurement methods, with θ / 2θ scanning, no clear peak is observed. In other words, according to X-ray diffraction measurement, there is no alignment in the ab plane direction and the c-axis direction in the measurement area.

[0068] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating with an electron beam with a beam diameter of 1 nm (also known as a nano-beam), a ring-shaped region of high brightness and multiple bright spots within the ring-shaped region were observed. Thus, based on the electron diffraction pattern, it can be known that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is not aligned in the planar direction or the cross-sectional direction.

[0069] In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis image (EDX-mapping) obtained by Energy Dispersive X-ray spectroscopy (EDX), it can be confirmed that there is a mixture of regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components.

[0070] The structure of CAC-OS differs from that of IGZO compounds, where metallic elements are uniformly distributed, and it possesses different properties. In other words, CAC-OS has a mosaic-like structure in which regions with GaOX3 as the main component and regions with InX2ZnY2OZ2 or InOX1 as the main components are separated from each other.

[0071] Here, the conductivity of regions with InX2ZnY2OZ2 or InOX1 as the main components is higher than that of regions with GaOX3 or the like. In other words, when carriers flow through regions with InX2ZnY2OZ2 or InOX1 as the main components, they exhibit the conductivity of oxide semiconductors. Therefore, when regions with InX2ZnY2OZ2 or InOX1 as the main components are distributed in a cloud-like manner in an oxide semiconductor, a high field-efficiency mobility (µ) can be achieved.

[0072] On the other hand, regions with GaOX3 as the main component have higher insulation properties than regions with InX2ZnY2OZ2 or InOX1 as the main component. In other words, when regions with GaOX3 as the main component are distributed in oxide semiconductors, leakage current can be suppressed and good switching operation can be achieved.

[0073] Therefore, when CAC-OS is used in semiconductor devices, high on-state current (Ion) and high field-effect mobility (µ) can be achieved by means of the complementary effect of the insulation caused by GaOX3 and the conductivity caused by InX2ZnY2OZ2 or InOX1.

[0074] In addition, semiconductor components using CAC-OS have high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0075] An example of the operation of pixel 10, which adds correction data to image data, will be described with reference to the timing diagrams shown in Figures 2A and 2B. In the following description, "H" represents a high potential and "L" represents a low potential. Furthermore, the correction data is "Vp", the image data is "Vs", and the specific potential is "Vref". For example, "Vref" can be 0V, GND potential, or a specific reference potential. Additionally, "Vp" can be referred to as any first data, and "Vs" can be referred to as any second data.

[0076] First, the process of writing the correction data "Vp" to node NM will be explained with reference to FIG2A. Note that detailed changes due to circuit structure, operating timing, etc., are not considered in the potential distribution, coupling, or loss here. The potential change caused by capacitive coupling depends on the capacitance ratio of the supply side to the supplied side, but for ease of explanation, it is assumed that the capacitance value of node NM is small enough.

[0077] At time T1, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "Vp". As a result, transistor 102 is turned on, and the potential of one electrode of capacitor 104 becomes "Vref". This operation is used to reset the subsequent correction operation (capacitive coupling operation).

[0078] In addition, when transistor 103 is turned on, the potential of wiring 123 (correction data "Vp") is written to node NM.

[0079] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "L". As a result, transistors 102 and 103 are de-conducted, and node NM maintains the correction data "Vp". In addition, capacitor 104 maintains "Vp-Vref".

[0080] This is where the correction data "Vp" is written. Alternatively, without correction, the same potential as "Vref" can be supplied as correction data "Vp" in the above operation.

[0081] Next, the correction of the image data “Vs” and the display operation of the display element included in the circuit block 110 will be described with reference to FIG2B.

[0082] The work in Figures 2A and 2B can be performed continuously within a single horizontal period. Alternatively, the work in Figure 2A can be performed in the k-th frame (k is a natural number), while the work in Figure 2B can be performed in the (k+1)-th frame. Alternatively, the work in Figure 2B can be performed multiple times after the work in Figure 2A.

[0083] At time T11, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "H", and the potential of wiring 123 is set to "Vs". This causes transistor 101 to conduct, and the potential of wiring 123 "Vs" is added to the potential of node NM by the capacitive coupling of capacitor 104. At this time, the potential of node NM is "Vp-Vref+Vs", while when "Vref" = 0, the potential of node NM is "Vp+Vs".

[0084] At time T12, the potential of wiring 121 is set to “L”, the potential of wiring 122 is set to “L”, and the potential of wiring 123 is set to “L”. As a result, transistor 103 is not turned on, and the potential of node NM is maintained at “Vp+Vs”.

[0085] Then, the display element included in the circuit block 110 performs the display operation corresponding to the potential of node NM. In addition, depending on the structure of the circuit block, the display operation may sometimes be performed from time T1 or time T11.

[0086] Here, the correction of image data will be explained with reference to FIG3A.

[0087] Figure 3A shows four pixels (P1 to P4) in the horizontal and vertical directions. From left to right, it shows the input image data (Vs1, Vs2, Vs3), the input correction data (+Vp1, Vp0, -Vp1), and the generated corrected image data. Note that in the following description, the display element can perform high-brightness display when the potential of the image data is relatively high, and low-brightness display when the potential of the image data is relatively low.

[0088] For example, in pixel P1, when image data "Vs1" is combined with positive correction data "+Vp1", the image data is "Vs1+Vp1", and the brightness increases. In pixels P2 and P3, when image data Vs2 is combined with correction data "Vp0" which is essentially uncorrected, the image data is "Vs2+Vp0=Vs1", and the brightness remains unchanged. In pixel P4, when image data "Vs3" is combined with negative correction data "-Vp1", the image data is "Vs1-Vp1", and the brightness decreases.

[0089] This combination of image data and correction data can be used for upconversion, HDR display, correction of display non-uniformity inherent in display devices, correction of the critical voltage of the transistors included in the pixels, etc.

[0090] In the upconversion operation, for example, the same image data is supplied to all four pixels. Through correction, each pixel can display a different image. For example, data suitable for a specific pixel of a display device with 4K2K pixels can be input to specific four pixels of a display device with 8K4K pixel count, thereby achieving a higher resolution display.

[0091] Furthermore, different images can be displayed over each other, which is a generalized correction of image data. Figure 3B shows the overall image of the display unit. From the left, a first image composed of image data "Vs", a second image composed of correction data "Vp", and an image combining the first and second images are shown.

[0092] This combination of image data and correction data not only allows for the synthetic display of different images, but also improves the overall brightness of the displayed image. For example, it can be applied to text insertion and AR (Augmented Reality) display.

[0093] Figures 4A to 4C are examples of structures that can be applied to circuit block 110 and include EL elements as display elements.

[0094] The structure shown in Figure 4A includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain electrodes of the transistor 111 is electrically connected to one electrode of the EL element 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to node NM.

[0095] Another electrode of the source and drain of transistor 111 is electrically connected to wiring 128. The other electrode of EL element 114 is electrically connected to wiring 129. Wiring 128 and 129 have the function of supplying power. For example, wiring 128 can supply a high-potential power supply. In addition, wiring 129 can supply a low-potential power supply.

[0096] Here, the other of the source and drain of the transistor 102 shown in FIG1 for supplying "Vref" can be electrically connected to wiring 128. Since "Vref" is preferably 0V, GND, or a low potential, wiring 128 also has the function of supplying at least one of these potentials. For wiring 128, "Vref" is supplied when writing data to node NM, and a high potential power supply is supplied when EL element 114 emits light.

[0097] In the structure shown in FIG4A, current flows through EL element 114 when the potential of node NM is above the critical voltage of transistor 111. As a result, EL element 114 sometimes starts emitting light at time T1 in the timing diagram shown in FIG2A, so the application of this structure may be limited.

[0098] Figure 4B shows the structure of Figure 4A with the addition of transistor 112. One of the source and drain terminals of transistor 112 is electrically connected to one of the source and drain terminals of transistor 111. The other of the source and drain terminals of transistor 112 is electrically connected to EL element 114. The gate of transistor 112 is electrically connected to wiring 126. Wiring 126 can function as a signal line to control the conduction of transistor 112.

[0099] In this structure, current flows through EL element 114 when the potential of node NM is above the critical voltage of transistor 111 and transistor 112 is turned on. Therefore, the EL element 114 can start emitting light after time T12 in the timing diagram shown in FIG2B, thus this structure is suitable for operation with accompanying correction.

[0100] Figure 4C shows the structure of Figure 4B with the addition of transistor 115. One of the source and drain terminals of transistor 115 is electrically connected to one of the source and drain terminals of transistor 111. The other of the source and drain terminals of transistor 115 is electrically connected to wiring 130. The gate of transistor 115 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 115. Alternatively, the gate of transistor 115 can also be electrically connected to wiring 122.

[0101] Wiring 130 can be electrically connected to a supply source of a specific potential, such as a reference potential. By supplying a specific potential from wiring 130 to one of the source and drain of transistor 111, the writing of image data can also be stabilized.

[0102] Furthermore, wiring 130 can be connected to circuit 120 and can have the function of monitoring lines. Circuit 120 can have one or more functions such as supplying the aforementioned specific potential, obtaining the electrical characteristics of transistor 111, and generating correction data.

[0103] When wiring 130 is used as a monitoring line, circuit 120 generates the potential of the critical voltage of correction transistor 111 as the above-mentioned correction data "Vp".

[0104] Figures 5A to 5C are examples of structures that can be applied to circuit block 110 and include liquid crystal elements as display elements.

[0105] The structure shown in Figure 5A includes a capacitor 116 and a liquid crystal element 117. One electrode of the liquid crystal element 117 is electrically connected to one electrode of the capacitor 116. One electrode of the capacitor 116 is electrically connected to node NM.

[0106] The other electrode of capacitor 116 is electrically connected to wiring 132. The other electrode of liquid crystal element 117 is electrically connected to wiring 133. Wiring 132 and 133 have the function of supplying power. For example, wiring 132 and 133 can supply reference potentials such as GND and 0V or any potential.

[0107] Here, another of the source and drain of the transistor 102 used to supply the “Vref” shown in FIG1 can be electrically connected to the wiring 132.

[0108] In this structure, the operation of the liquid crystal element 117 begins when the potential of node NM becomes above the operating threshold of the liquid crystal element 117. Therefore, sometimes the display operation begins at time T1 in the timing diagram shown in FIG2A, thus limiting the applicability of this structure. Note that in the case of a transmissive liquid crystal display device, by also employing operations such as turning off the backlight until time T12 shown in FIG2B, unwanted display operations can be suppressed from being seen.

[0109] Figure 5B shows the structure of Figure 5A with the addition of transistor 118. One of the source and drain terminals of transistor 118 is electrically connected to one electrode of capacitor 116. The other of the source and drain terminals of transistor 118 is electrically connected to node NM. The gate of transistor 118 is electrically connected to wiring 126. Wiring 126 can function as a signal line to control the conduction of transistor 118.

[0110] In this structure, the potential of node NM is applied to the liquid crystal element 117 simultaneously with the conduction of transistor 118. Therefore, the operation of the liquid crystal element can begin after time T12 in the timing diagram shown in FIG2B, making this structure suitable for operation accompanied by correction.

[0111] Furthermore, since the potential supplied to the capacitor 116 and the liquid crystal element 117 is maintained while the transistor 118 is in a non-conductive state, it is preferable to reset the potential supplied to the capacitor 116 and the liquid crystal element 117 before rewriting the image data. This reset can be achieved, for example, by supplying a reset potential to the wiring 123 and simultaneously turning on the transistors 103 and 118.

[0112] Figure 5C shows the structure of Figure 5B with the addition of transistor 119. One of the source and drain electrodes of transistor 119 is electrically connected to one electrode of liquid crystal element 117. The other of the source and drain electrodes of transistor 119 is electrically connected to wiring 130. The gate of transistor 119 is electrically connected to wiring 131. Wiring 131 can function as a signal line to control the conduction of transistor 119. Alternatively, the gate of transistor 119 can also be electrically connected to wiring 122.

[0113] The circuit 120, which is electrically connected to the wiring 130, is similar to the description in FIG4C above, and may also have the function of resetting the potential of the supply capacitor 116 and the liquid crystal element 117.

[0114] Furthermore, although Figures 4A to 4C and Figures 5A to 5C show examples of "Vref" being supplied from a power line, "Vref" can also be supplied from a scan line. For example, as shown in Figure 6A, "Vref" can also be supplied from wiring 122. As shown in Figure 6A, since wiring 122 is supplied with a potential equivalent to "L" when writing correction data (when transistor 103 is turned on), this potential can be used as "Vref".

[0115] Furthermore, as shown in Figures 6B and 6C, transistors 101, 102, and 103 can also be configured with a back gate. Figure 6B shows a configuration where the back gate is electrically connected to the front gate, which improves the turn-on current. Figure 6C shows a configuration where the back gate is electrically connected to wiring 134, which can supply a constant potential, and this configuration can control the threshold voltage of the transistor. Alternatively, a back gate can be provided for the transistors included in the circuit blocks 110 shown in Figures 4A to 4C and Figures 5A to 5C.

[0116] Figure 7 is a diagram showing a portion (four pixels) of a pixel array including the basic structure of a pixel 11, which is applicable to pixel 10. Pixel 11 is provided with a transistor 103, a capacitor 104, and a circuit block 110. In addition, n and m in parentheses attached to the symbols represent specific rows, and i represents specific columns (n, m, and i are natural numbers).

[0117] Each of the pixels 11 is configured in a matrix, that is, it can be configured in the nth row and i-th column, the nth row and (i+x)-th column (x is a natural number), the (n+1)th row and i-th column, and the (n+1)th row and (i+x)-th column. In addition, Figure 7 shows the layout when x=1.

[0118] In addition, a transistor 101, a transistor 102a, and a transistor 102b electrically connected to four pixels 11 are provided in the pixel array. The transistors 102a and 102b have the functions of the transistor 102 in the pixel 10.

[0119] Furthermore, transistor 101 is a component of each pixel 11, meaning that four pixels share transistor 101. Transistor 102a is a component of pixels 11[n, i] and 11[n, i+1], meaning that two pixels share transistor 102a. Transistor 102b is a component of pixels 11[n+1, i] and 11[n+1, i+1], meaning that two pixels share transistor 102b. Additionally, transistors 101, 102a, and 102b can also be distributed across any pixel area.

[0120] In each pixel 11, one of the source and drain electrodes of transistor 103 is electrically connected to one electrode of capacitor 104. One electrode of capacitor 104 is electrically connected to circuit block 110. The other electrode of capacitor 104 is electrically connected to one of the source and drain electrodes of transistor 101. One of the source and drain electrodes of transistor 101 is electrically connected to one of the source and drain electrodes of transistor 102a. Furthermore, one of the source and drain electrodes of transistor 101 is electrically connected to one of the source and drain electrodes of transistor 102b.

[0121] In this pixel array, several identical operations can be performed using a structure with fewer wiring and transistors than the simple matrix structure of pixel 10.

[0122] Furthermore, when the resolution of the display device and the image data are different, the image data and the input path of the correction data can be switched so that the display can be performed appropriately without up-conversion or down-conversion.

[0123] Referring to the timing diagrams shown in Figures 8A1 and 8A2, an example of writing different data to each of pixel 11 will be described. This operation is equivalent to, for example, inputting high-resolution image data (8K4K data) to a display device with a pixel count corresponding to 8K4K. Furthermore, although this description pertains to one pixel 11, the same operation can be applied to all pixels 11.

[0124] In the following description, a high potential is represented by "H", a low potential by "L", and a specific potential between a high potential and a low potential by "M". Note that "M" can be a reference potential such as 0V or GND, or other potentials. Furthermore, high-resolution image data is designated as "VsH", and high-resolution correction data is designated as "Vp1". Additionally, "Vp1" can also be referred to as any first data, and "VsH" can also be referred to as any second data.

[0125] First, the process of writing image data "VsH" to node NM will be explained with reference to FIG8A1. Note that detailed changes in potential distribution, coupling, or loss due to circuit structure, operating timing, etc. are not considered here.

[0126] At time T1, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "VsH". As a result, transistor 102 is turned on, and the potential of the other electrode of capacitor 104 becomes "Vref". This operation is used to reset the subsequent correction operation (capacitive coupling operation).

[0127] In addition, when transistor 103 is turned on, the potential of wiring 123 (image data "VsH") is written to node NM.

[0128] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "M". As a result, transistors 102 and 103 are de-conducted, and node NM holds the image data "VsH". In addition, capacitor 104 holds "VsH-Vref".

[0129] The writing of image data "VsH" is now complete. Next, the correction of image data "VsH" and the display operation of the display elements included in circuit block 110 will be explained with reference to FIG8A2.

[0130] The work in Figures 8A1 and 8A2 can be performed consecutively within a single horizontal period. Alternatively, the work in Figure 8A1 can be performed in the k-th frame (k is a natural number), while the work in Figure 8A2 can be performed in the (k+1)-th frame. Alternatively, the work in Figure 8A2 can be performed multiple times after the work in Figure 8A1.

[0131] At time T11, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "H", and the potential of wiring 123 is set to "Vp1". Transistor 101 is then turned on, and the potential of wiring 123 "Vp1" is added to the potential of node NM by capacitive coupling through capacitor 104. At this time, the potential of node NM is "VsH-Vref+Vp1", while when "Vref" = 0, the potential of node NM is "VsH+Vp1". Alternatively, without correction, the same potential as "Vref" can be supplied as correction data "Vp1" in the above operation.

[0132] At time T12, the potential of wiring 121 is set to “L”, the potential of wiring 122 is set to “L”, and the potential of wiring 123 is set to “M”. As a result, transistor 101 is not turned on, and the potential of node NM is maintained at “VsH+Vp1”.

[0133] Then, the display element included in the circuit block 110 performs the display operation corresponding to the potential of node NM. In addition, depending on the structure of the circuit block, the display operation may sometimes be performed from time T1 or time T11.

[0134] Thus, HDR display and the like can be achieved by correcting selected pixels. Furthermore, although the value of the correction data "Vp1" is the same for all four pixels, it is sufficient to obtain a visual effect of brightness and darkness. Alternatively, without correction, at time T11, the potential of wiring 123 can be maintained at "M". Or, the potential of wiring 122 can be set to "L" to prevent transistor 101 from conducting.

[0135] Next, the operation of writing the same data to the four pixels 11 will be described with reference to the timing diagrams shown in Figures 8B1 and 8B2. This operation is equivalent to, for example, inputting low-resolution image data (4K2K data) to a display device with a pixel count corresponding to 8K4K.

[0136] First, the process of writing the correction data "Vp2" to node NM will be explained with reference to FIG8B1. Hereinafter, the low-resolution image data is referred to as "VsL", and the low-resolution correction data is referred to as "Vp2". Note that "Vp2" can also be referred to as any first data, and "VsL" can also be referred to as any second data.

[0137] At time T1, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "Vp2". As a result, transistor 102 is turned on, and the potential of the other electrode of capacitor 104 becomes "Vref". This operation is used to reset the subsequent correction operation (capacitive coupling operation).

[0138] In addition, when transistor 103 is turned on, the potential of wiring 123 (correction data "Vp2") is written to node NM.

[0139] At time T2, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "M". As a result, transistors 102 and 103 are de-conducted, and node NM maintains the correction data "Vp2". In addition, capacitor 104 maintains "Vp2-Vref".

[0140] This is where the correction data "Vp2" is written. Alternatively, without correction, the same potential as "Vref" can be supplied as correction data "Vp2" in the above operation.

[0141] Next, the correction of the image data “VsL” and the display operation of the display element included in the circuit block 110 will be described with reference to FIG8B2.

[0142] The work of Figures 8B1 and 8B2 can be performed continuously within a horizontal period. Alternatively, the work of Figure 8B1 can be performed in the k-th frame, while the work of Figure 8B2 can be performed in the (k+1)-th frame. Alternatively, the work of Figure 8B2 can be performed multiple times after the work of Figure 8B1.

[0143] At time T11, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "H", and the potential of wiring 123 is set to "VsL". This causes transistor 101 to conduct, and the potential of wiring 123 "VsL" is added to the potential of node NM by the capacitive coupling of capacitor 104. At this time, the potential of node NM is "Vp2-Vref+VsL", while when "Vref" = 0, the potential of node NM is "Vp2+VsL".

[0144] At time T12, the potential of wiring 121 is set to “L”, the potential of wiring 122 is set to “L”, and the potential of wiring 123 is set to “M”. As a result, transistor 101 is not turned on, and the potential of node NM is maintained at “Vp2+VsL”.

[0145] Then, the display element included in the circuit block 110 performs the display operation corresponding to the potential of node NM. In addition, depending on the structure of the circuit block, the display operation may sometimes start from time T11.

[0146] Because the correction data "Vp2" can input different values ​​for each pixel 11, even if the image data "VsL" is the same, each pixel 11 can display a different image. In other words, upconversion can be performed. In addition, without correction, the four pixels display the same image.

[0147] By performing the work as described above, the original image data can be input to the display device without up-conversion, thereby enabling proper display. Alternatively, corrections suitable for image display can be performed.

[0148] FIG9A is an example of a block diagram of a display device according to an embodiment of the present invention. The display device includes a pixel array 12 in which pixels 11 are arranged in a matrix, a row driver 13, a column driver 14, a circuit 15, and a selection circuit 16. In addition, in FIG9A, transistors 102a and 102b are represented by a block, and the connection method of the wiring to the supply potential "Vref" is omitted.

[0149] The row driver 13 may, for example, adopt a structure combining a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, data is output to wiring 121 or wiring 122.

[0150] The column driver 14 may, for example, adopt a structure combining a shift register 22 and a buffer circuit 23. By controlling the conduction of the buffer circuit 23, data can be output to the wiring 123.

[0151] Circuit 15 has the function of generating calibration data. Note that circuit 15 can also be described as an external device used to generate calibration data.

[0152] The row driver 13 can control the conduction of transistors 101 and 102a, 102b. The column driver 14 can supply correction data or image data to the wiring 123.

[0153] Input high-resolution image data "VsH" (e.g., 8K4K data) or low-resolution image data "VsL" (e.g., 4K2K data) to circuit 15. When inputting image data "VsH", correction data "Vp1" is generated, and when inputting image data "VsL", correction data "Vp2" is generated.

[0154] In addition to the correction data “Vp1” and “Vp2” generated by the circuit 15, the selection circuit 16 can also output the externally generated correction data “Vp1” and “Vp2” or image data “VsH” and “VsL” to the column driver 14.

[0155] In the structure shown in FIG9A, for example, when performing uncorrected display operations at low resolution, the output stage of each driver can be halved, thereby reducing power consumption.

[0156] Circuit 15 may have a neural network. For example, a deep neural network that has been trained using a large number of images as supervised data can be used to generate high-precision correction data.

[0157] As shown in Figure 10A, a neural network (NN) can be composed of an input layer (IL), an output layer (OL), and intermediate layers (hidden layers) (HL). Each of the input layer (IL), output layer (OL), and intermediate layers (HL) includes one or more neurons (units). Note that the intermediate layers (HL) can be one or more layers. A neural network including two or more intermediate layers (HL) can be called a deep neural network (DNN), and learning using deep neural networks can be called deep learning.

[0158] Each neuron in the input layer IL receives input data, each neuron in the intermediate layer HL receives the output signals of neurons in the previous or next layer, and each neuron in the output layer OL receives the output signals of neurons in the previous layer. Note that each neuron can be connected to all neurons in the previous and next layers (full connection), or it can be connected to some neurons.

[0159] Figure 10B illustrates an example of computation using neurons. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N is input with the outputs x1 and x2 of the neurons in the previous layer. In neuron N, the sum x1w1 + x2w2, which is the result of multiplying output x1 with weight w1 (x1w1) and output x2 with weight w2 (x2w2), is calculated and then biased by a voltage b as needed to obtain the value a = x1w1 + x2w2 + b. The value a is transformed by the activation function h, and the output signal y = h(a) is output from neuron N.

[0160] Thus, the operation using neurons includes adding the product of the output and weight of the neurons in the previous layer, that is, a product summation operation (x1w1 + x2w2 above). This product summation operation can be performed in software or in hardware. When performing the product summation operation in hardware, a product summation circuit can be used. This product summation circuit can be either a digital circuit or an analog circuit.

[0161] The summation circuit can be constructed using either Si transistors or OS transistors. In particular, OS transistors are preferred as analog memory for constructing the summation circuit because they have extremely small off-state current. Note that the summation circuit can also be constructed using both Si transistors and OS transistors.

[0162] Furthermore, the generation of calibration data is not limited to using circuit 15, but can also be performed using the aforementioned circuit 120 (see FIG9B). Additionally, calibration data can be generated based on data from grayscale display on the display unit and the brightness of the display read by a luminance meter, or data from the displayed photograph. Furthermore, a sensor 24 capable of detecting the brightness of the display and a circuit 25 capable of detecting degradation of the display element and generating calibration data can also be provided (see FIG9C).

[0163] Next, the analogy results of applying the circuit block shown in FIG4A to the structure of the pixel array shown in FIG7 (refer to FIG11) will be explained. The parameters are as follows: The transistor size is L / W = 6µm / 6µm (transistor 111), L / W = 4µm / 4µm (other transistors), the capacitance value of capacitor 104 is 150fF, the capacitance value of capacitor 113 is 50fF, EL element 114 is an FN diode model, making wiring 128 an anode potential of +10V, "Vref" is +1V, making wiring 129 a cathode potential of -5V, and the minimum value of image data and correction data is +1V, and the maximum value is +8V. Note that SPICE is used as the circuit analogy software.

[0164] Figures 12A to 12C show the analog results of verifying a high-resolution display (without correction). Figure 12A is a timing diagram used for verification. At times T1 to T2 in Figure 12A, image data “Vs” (s[n]) is written from wiring 123 by turning on transistor 103. Furthermore, at times T3 to T4, image data “Vs” (s[n+1]) is written. At this time, wiring 128 is at the anode potential.

[0165] Figure 12B is an analog result of the current (ILED) flowing through the EL element 114 relative to the image data "Vs". Although Figure 12B is an analog result in one pixel, it confirms that grayscale display can be performed on any pixel (pix1 to pix4).

[0166] Furthermore, Figure 12C is an analogy of the change in the potential "VNM" of node NM relative to the image data "Vs". It was confirmed that the potential "VNM" of node NM is proportional to the image data "Vs" in any pixel.

[0167] That is to say, it was confirmed that the high-resolution image data “Vs” supplied from the wiring 123 can be displayed.

[0168] Figures 13A to 13D show the analog results of verifying a low-resolution display (without correction). Figures 13A and 13B are timing diagrams used for verification. First, the potential of wiring 123 is set to a minimum (+1V). At times T1 to T4 in Figure 13A, correction data "Vp" (p) is written to all pixels. At this time, because wiring 128 is at potential "Vref" (+1V), the difference potential held by capacitor 104 is 0. That is, there is no correction.

[0169] Then, at times T1 to T2 in Figure 13B, image data “Vs” (s[m]) is written from wiring 123 by turning on transistor 101.

[0170] Figure 13C is an analog result of the current (ILED) flowing through the EL element 114 relative to the image data "Vs". Although Figure 13C is an analog result in one pixel, it confirms that grayscale display can be performed on any pixel (pix1 to pix4).

[0171] Furthermore, Figure 13D is an analogy of the change in the potential "VNM" of node NM relative to the image data "Vs". It was confirmed that the potential "VNM" of node NM is proportional to the image data "Vs" in any pixel.

[0172] That is to say, it was confirmed that the low-resolution image data “Vs” supplied from the wiring 123 can be displayed.

[0173] Figures 14A to 14D show the analog results of verifying a low-resolution display (with correction). Figures 14A and 14B are timing diagrams used for verification. First, the desired correction data "Vp" is supplied to wiring 123. At times T1 to T2 in Figure 14A, the correction data "Vp" (p[n]) is written. Furthermore, at times T3 to T4, the correction data "Vp" (p[n+1]) is written. At this time, because wiring 128 is at a potential of "Vref" (+1V), the difference potential maintained by capacitor 104 is "Vp-1".

[0174] Then, at times T1 to T2 in Figure 14B, by turning on transistor 101, image data "Vs" is written from wiring 123, and correction data is added to the image data. At this time, wiring 128 is at the anode potential.

[0175] Figure 14C is an analog result of the current (ILED) flowing through the EL element 114 in each correction data relative to the image data "Vs". It was confirmed that grayscale display can be performed in any case where 1V to 8V is written as correction data "Vp" and combined with image data "Vs".

[0176] Furthermore, Figure 14D is an analogy of the variation of the potential "VNM" of node NM in each correction data "Vp" relative to the image data "Vs". It was confirmed that in any case where 1V to 8V is written as correction data "Vp" and combined with image data "Vs", the potential "VNM" of node NM tends to be proportional to the image data "Vs".

[0177] That is to say, it has been confirmed that the calibration data "Vp" supplied from the wiring 123 and the low-resolution image data "Vs" can be used for effective display.

[0178] FIG15 is an example of applying the pixels of one embodiment of the present invention to an EL display device capable of color display. Generally speaking, the pixels of a display device capable of color display have a combination of sub-pixels emitting R (red), G (green), and B (blue) colors. In FIG15, three sub-pixels of each color of sub-pixels 10R, 10G, and 10B arranged in the horizontal direction constitute one pixel, and four pixels in the horizontal and vertical directions are shown. In addition, in FIG15, transistors 102a and 102b are represented by a block.

[0179] As described above, in one embodiment of the present invention, correction data "Vp1" or image data "VsL" can be input to four pixels arranged in a matrix (here, equivalent to four sub-pixels emitting the same color) by transistor 101. In addition, potential "Vref" can be supplied to two pixels arranged in the horizontal direction (here, equivalent to two sub-pixels emitting the same color) by transistors 102a and 102b.

[0180] Although it is preferable that each sub-pixel be configured with the same spacing in a stripe arrangement, it is sometimes difficult to keep the spacing of each sub-pixel (the spacing of components with the same function) constant when each sub-pixel shares wiring and transistors.

[0181] Therefore, when the pixel electrodes connected to sub-pixels 10R, 10G, and 10B are respectively electrodes 26R, 26G, and 26B, as shown in FIG15, it is preferable to adopt a structure in which electrodes 26R, 26G, and 26B are arranged at the same interval. Note that although pixel electrodes can also be referred to as components of each sub-pixel, for clarity, they are represented here as different components from each other. This structure is effective for top-emitting EL display devices or reflective liquid crystal display devices.

[0182] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0183] Embodiment 2 This embodiment describes a structural example of a display device using a liquid crystal element and a structural example of a display device using an EL element. Note that the components, operation, and functions of the display device described in Embodiment 1 are omitted in this embodiment.

[0184] Figures 16A to 16C show the structure of a display device that can use one embodiment of the present invention.

[0185] In FIG16A, a sealant 4005 is provided around the display portion 215 provided on the first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006.

[0186] The display unit 215 is provided with the pixel array shown in FIG7 of Embodiment 1. Note that the scan line driving circuit described below is equivalent to a row driver, while the signal line driving circuit is equivalent to a column driver.

[0187] In FIG16A, the scan line driving circuit 221a, signal line driving circuit 231a, signal line driving circuit 232a, and common line driving circuit 241a all include multiple integrated circuits 4042 disposed on the printed circuit board 4041. The integrated circuits 4042 are formed of single-crystal semiconductors or polycrystalline semiconductors. The signal line driving circuits 231a and 232a have the function of column drivers as shown in Embodiment 1. The scan line driving circuit 221a has the function of row drivers as shown in Embodiment 1. The common line driving circuit 241a has the function of supplying a predetermined potential to the wiring for the power supply and the wiring for the Vref supply as shown in Embodiment 1.

[0188] Various signals and potentials are supplied to the scan line drive circuit 221a, common line drive circuit 241a, signal line drive circuit 231a and signal line drive circuit 232a by means of FPC (Flexible printed circuit) 4018.

[0189] The integrated circuit 4042 included in the scan line drive circuit 221a and the common line drive circuit 241a has the function of supplying selection signals to the display unit 215. The integrated circuit 4042 included in the signal line drive circuit 231a and the signal line drive circuit 232a has the function of supplying image data to the display unit 215. The integrated circuit 4042 is installed in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0190] Note that there are no particular restrictions on the connection method of the integrated circuit 4042. Wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), and COF (Chip On Film) can be used.

[0191] Figure 16B shows an example of mounting an integrated circuit 4042 included in signal line drive circuit 231a and signal line drive circuit 232a using the COG method. In addition, by forming part or all of the drive circuit on a substrate on which the display section 215 is formed, a system-on-panel can be formed.

[0192] FIG16B shows an example in which the scan line driving circuit 221a and the common line driving circuit 241a are formed on a substrate on which the display section 215 is formed. By forming the driving circuit and the pixel circuit in the display section 215 at the same time, the number of components can be reduced. As a result, productivity can be improved.

[0193] Furthermore, in FIG16B, a sealant 4005 is provided around the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a provided on the first substrate 4001. A second substrate 4006 is provided on the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a. Thus, the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0194] Although FIG. 16B shows an example of separately forming signal line driving circuits 231a and 232a and mounting them to the first substrate 4001, one embodiment of the present invention is not limited to this structure. A scan line driving circuit may also be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit may be separately formed and mounted. Furthermore, as shown in FIG. 16C, the signal line driving circuits 231a and 232a may also be formed on a substrate on which the display portion 215 is formed.

[0195] In addition, the display device sometimes includes a panel in which the display element is sealed and a module in which an IC including a controller is installed.

[0196] The display section and scan line driving circuit disposed on the first substrate include a plurality of transistors. The transistors shown in the above embodiment can be used as such transistors.

[0197] The transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit can have the same structure or different structures. The transistors included in the peripheral driving circuit can all have the same structure or a combination of two or more structures. Similarly, the transistors included in the pixel circuit can all have the same structure or a combination of two or more structures.

[0198] Additionally, an input device 4200 may be provided on the second substrate 4006. The structure shown in Figures 16A to 16C for providing an input device 4200 to a display device can be used as a touch panel.

[0199] There are no particular limitations on the sensing elements (also referred to as sensing elements) included in the touch panel of one embodiment of the present invention. Various sensors capable of detecting the proximity or contact of a detection object such as a finger or stylus can also be used as sensing elements.

[0200] For example, as a sensor, various methods can be used, such as electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive.

[0201] In this embodiment, a touch panel including an electrostatic capacitive sensing element will be used as an example for explanation.

[0202] As electrostatic capacitive types, there are surface-type electrostatic capacitive types, projection-type electrostatic capacitive types, etc. Furthermore, as projection-type electrostatic capacitive types, there are self-capacitance types, mutual-capacitance types, etc. Mutual-capacitance types are preferred because they allow for simultaneous multi-point sensing.

[0203] The touch panel of one embodiment of the present invention can adopt various structures such as a structure in which a display device and a sensing element manufactured separately are bonded together, or a structure in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0204] Figures 17A and 17B show an example of a touch panel. Figure 17A is a perspective view of touch panel 4210. Figure 17B is a perspective schematic diagram of input device 4200. Note that, for clarity, only typical components are shown.

[0205] The touch panel 4210 has a structure in which a display device and a sensing element manufactured separately are bonded together.

[0206] The touch panel 4210 includes an input device 4200 and a display device arranged in an overlapping manner.

[0207] The input device 4200 includes a substrate 4263, electrodes 4227 and 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, electrodes 4227 may be electrically connected to wirings 4237 or 4239. Additionally, electrodes 4228 may be electrically connected to wirings 4239. The FPC 4272b may be electrically connected to the plurality of wirings 4237 and 4238 respectively. The FPC 4272b may be equipped with an IC 4273b.

[0208] A touch sensor may be disposed between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is disposed between the first substrate 4001 and the second substrate 4006, an optical touch sensor utilizing a photoelectric conversion element may be used in addition to an electrostatic capacitive touch sensor.

[0209] Figures 18A and 18B are cross-sectional views along the dotted line N1-N2 in Figure 16B. The display device shown in Figures 18A and 18B includes an electrode 4015, which is electrically connected to the terminals of FPC 4018 via an anisotropic conductive layer 4019. Additionally, in Figures 18A and 18B, the electrode 4015 is electrically connected to wiring 4014 through openings formed in insulating layers 4112, 4111, and 4110.

[0210] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source and drain electrodes of the transistors 4010 and 4011 are formed using the same conductive layer.

[0211] Furthermore, the display unit 215 and the scan line driving circuit 221a provided on the first substrate 4001 include a plurality of transistors. In Figures 18A and 18B, transistors 4010 in the display unit 215 and 4011 in the scan line driving circuit 221a are shown. Although bottom-gate transistors are shown as transistors 4010 and 4011 in Figures 18A and 18B, top-gate transistors may also be used.

[0212] In Figures 18A and 18B, an insulating layer 4112 is provided on transistors 4010 and 4011. In addition, in Figure 18B, a partition wall 4510 is formed on the insulating layer 4112.

[0213] In addition, transistors 4010 and 4011 are disposed on insulating layer 4102. Furthermore, transistors 4010 and 4011 include electrodes 4017 formed on insulating layer 4111. Electrode 4017 can be used as a back gate electrode.

[0214] Additionally, the display device shown in Figures 18A and 18B includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps with the others separated by an insulating layer 4103.

[0215] Generally, the capacitance of the capacitor installed in the pixel section of the display device is set considering factors such as the leakage current of the transistors arranged in the pixel section, so that it can maintain its charge for a specified period. The capacitance of the capacitor can be set considering factors such as the off-state current of the transistors.

[0216] The transistor 4010 disposed in the display unit 215 is electrically connected to the display element. FIG18A is an example of a liquid crystal display device using a liquid crystal element as the display element. In FIG18A, the liquid crystal element 4013, which is the display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033, which are used as alignment films, are disposed in a manner that holds the liquid crystal layer 4008. The second electrode layer 4031 is disposed on one side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with the liquid crystal layer 4008.

[0217] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the spacing (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0218] Furthermore, as needed, optical components (optical substrates) such as a black matrix (light-shielding layer), a color layer (color filter), a polarizing component, a phase difference component, and an anti-reflection component can be appropriately provided. For example, circular polarization utilizing a polarizing substrate and a phase difference substrate can also be used. In addition, backlighting or sidelighting can be used as light sources. Micro-LEDs can also be used as the aforementioned backlighting or sidelighting.

[0219] In the display device shown in FIG18A, a light-shielding layer 4132, a color layer 4131 and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.

[0220] Examples of materials suitable for use in the light-shielding layer include carbon black, titanium black, metals, metal oxides, or composite oxides comprising solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film containing inorganic materials such as metals. Alternatively, a laminated film containing a material with a colored layer can be used for the light-shielding layer. For example, a laminated structure can be used consisting of a film containing a material with a colored layer for transmitting a certain color of light and a film containing a material with a colored layer for transmitting other colors of light. By using the same material for the colored layer and the light-shielding layer, the same equipment can be used, and the manufacturing process can be simplified, which is preferable.

[0221] Examples of materials that can be used for color layers include metallic materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the color layer can be formed, for example, using inkjet printing.

[0222] In addition, the display device shown in Figures 18A and 18B includes an insulating layer 4111 and an insulating layer 4104. As insulating layers 4111 and 4104, insulating layers that do not easily allow impurity elements to pass through are used. By sandwiching the semiconductor layer of the transistor by insulating layers 4111 and 4104, the ingress of impurities from the outside can be prevented.

[0223] Furthermore, as a display element included in the display device, a light-emitting element (also called an EL element) utilizing electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (also called an EL layer) between a pair of electrodes. When a potential difference higher than the critical voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, while electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, thereby causing the light-emitting compound contained in the EL layer to emit light.

[0224] EL elements are distinguished based on whether the light-emitting material is an organic compound or an inorganic compound. The former is usually called an organic EL element, while the latter is called an inorganic EL element.

[0225] In organic EL devices, by applying a voltage, electrons are injected into the EL layer from one electrode, while holes are injected into the EL layer from the other electrode. Through the recombination of these carriers (electrons and holes), the luminescent organic compound forms an excited state, and emits light when it returns from the excited state to the ground state. Due to this mechanism, such luminescent devices are called current-excited luminescent devices.

[0226] In addition to luminescent compounds, the EL layer may also include materials with high hole injection capacity, materials with high hole transport capacity, hole blocking materials, materials with high electron transport capacity, materials with high electron injection capacity, or bipolar materials (materials with high electron transport capacity and high hole transport capacity), etc.

[0227] The EL layer can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0228] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structure. Dispersed inorganic EL devices include a light-emitting layer in which particles of the light-emitting material are dispersed in a binder, and their light emission mechanism is donor-acceptor recombination type light emission utilizing donor and acceptor energy levels. Thin-film inorganic EL devices are structures in which the light-emitting layer is sandwiched between dielectric layers, and the dielectric layer containing the light-emitting layer is sandwiched between electrodes, and their light emission mechanism is localized light emission utilizing inner-shell electron transitions of metal ions. Note that organic EL devices are used here as light-emitting elements for explanation.

[0229] In order to extract light emission, at least one of the pair of electrodes of the light-emitting element is made transparent. A transistor and a light-emitting element are formed on a substrate. The light-emitting element can be a top-emitting structure that extracts light emission from a surface opposite to the substrate; a bottom-emitting structure that extracts light emission from a surface on one side of the substrate; or a double-sided emitting structure that extracts light emission from both surfaces.

[0230] FIG18B is an example of a light-emitting display device (also called an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513 used as a display element is electrically connected to a transistor 4010 disposed in the display section 215. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light extracted from the light-emitting element 4513, etc.

[0231] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferred to use a photosensitive resin material to form an opening on the first electrode layer 4030, and the side of the opening is formed as an inclined surface with a continuous curvature.

[0232] The light-emitting layer 4511 can be composed of a single layer or a stack of multiple layers.

[0233] The light emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta or yellow, etc., depending on the material constituting the light-emitting layer 4511.

[0234] As a method for achieving color display, there are the following methods: a method of combining a white-emitting element 4513 and a color layer; and a method of setting a different emitting element 4513 for each pixel. The former method has higher productivity than the latter method. On the other hand, in the latter method, an emitting layer 4511 needs to be formed for each pixel, so its productivity is lower than that of the former method. However, in the latter method, an emitting color with higher color purity can be obtained than that of the former method. By giving the emitting element 4513 a microcavity structure in the latter method, the color purity can be further improved.

[0235] The light-emitting layer 4511 may also contain inorganic compounds such as quantum dots. For example, by using quantum dots in the light-emitting layer, they can also be used as light-emitting materials.

[0236] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc., from entering the light-emitting element 4513, a protective layer may be formed on the second electrode layer 4031 and the partition wall 4510. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), etc., can be formed as the protective layer. Furthermore, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. Thus, to prevent exposure to external gases, it is preferable to use a protective film (adhesive film, UV-curable resin film, etc.) with high hermeticity and low degassing for encapsulation (sealing).

[0237] As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-curable resins or thermosetting resins can also be used, such as PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). Filler 4514 may also contain a desiccant.

[0238] As sealant 4005, glass materials such as glass powder or resin materials such as two-component mixed resins that cure at room temperature, light-curing resins, and thermosetting resins can be used. Sealant 4005 may also contain a desiccant.

[0239] Additionally, as needed, optical thin films such as polarizing plates or circular polarizing plates (including elliptical polarizing plates), phase retardation plates (λ / 4 plates, λ / 2 plates), and color filters may be appropriately provided on the light-emitting surface of the light-emitting element. Furthermore, an anti-reflective film may be provided on the polarizing plate or circular polarizing plate. For example, an anti-glare treatment can be performed, which reduces reflected glare by utilizing the surface irregularities to diffuse reflected light.

[0240] By giving the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining the microcavity structure and the color filter, reflected glare can be prevented, thereby improving the visibility of the image.

[0241] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, opposite electrode layer, etc.) to which voltage is applied to the display element, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location where the electrode layer is set, and the pattern structure of the electrode layer.

[0242] As the first electrode layer 4030 and the second electrode layer 4031, conductive materials with light transmittance such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0243] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or their alloys or nitrides.

[0244] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0245] Furthermore, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear components.

[0246] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0247] Embodiment 3 In this embodiment, an example of a transistor that can be used instead of the transistors shown in the above embodiments will be described with reference to the drawings.

[0248] The display device according to one embodiment of the present invention can be manufactured using transistors of various forms, such as bottom-gate transistors or top-gate transistors. Therefore, the semiconductor layer material or transistor structure used can be easily changed to correspond to conventional production lines.

[0249] [Bottom-gate transistor] FIG19A1 shows a cross-sectional view along the channel length of a channel-protected transistor 810, one type of bottom-gate transistor. In FIG19A1, the transistor 810 is formed on a substrate 771. Furthermore, the transistor 810 includes an electrode 746 on the substrate 771, separated by an insulating layer 772. Additionally, a semiconductor layer 742 is included on the electrode 746, separated by an insulating layer 726. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0250] Additionally, an insulating layer 741 is included in the channel formation region of the semiconductor layer 742. Furthermore, electrodes 744a and 744b are included on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can be used as one of a source electrode and a drain electrode. Electrode 744b can be used as the other of a source electrode and a drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0251] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel forming region, the semiconductor layer 742 can be prevented from being exposed when forming electrodes 744a and 744b. This prevents the channel forming region of the semiconductor layer 742 from being etched during the formation of electrodes 744a and 744b. According to one embodiment of the present invention, a transistor with excellent electrical characteristics can be realized.

[0252] In addition, the transistor 810 includes an insulating layer 728 on the electrodes 744a, 744b and the insulating layer 741, and an insulating layer 729 on the insulating layer 728.

[0253] When an oxide semiconductor is used in the semiconductor layer 742, it is preferable to use a material capable of abstracting oxygen from a portion of the semiconductor layer 742 to generate oxygen defects in at least the portions of electrodes 744a and 744b that are in contact with the semiconductor layer 742. The carrier concentration in the region where oxygen defects are generated in the semiconductor layer 742 increases, and this region becomes n-type, forming an n-type region (n+ layer). Therefore, this region can be used as a source region or a drain region. Examples of materials capable of abstracting oxygen from the semiconductor layer 742 to generate oxygen defects when an oxide semiconductor is used in the semiconductor layer 742 include tungsten and titanium.

[0254] By forming source and drain regions in the semiconductor layer 742, the contact resistance between electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and critical voltage, can be improved.

[0255] When silicon or other semiconductors are used in semiconductor layer 742, it is preferable to provide layers used as n-type or p-type semiconductors between semiconductor layer 742 and electrode 744a and between semiconductor layer 742 and electrode 744b. The layers used as n-type or p-type semiconductors can be used as source or drain regions of transistors.

[0256] Preferably, the insulating layer 729 is formed of a material that has the function of preventing impurities from diffusing into the transistor from the outside or reducing the diffusion of impurities. Alternatively, the insulating layer 729 may be omitted if necessary.

[0257] The transistor 811 shown in FIG19A2 differs from the transistor 810 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode. The electrode 723 can be formed using the same material and method as the electrode 746.

[0258] Generally, the back gate electrode is formed using a conductive layer and is positioned such that the channel forming region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be ground potential (GND potential) or any potential. In addition, by changing the potential of the back gate electrode independently without linkage with the gate electrode, the threshold voltage of the transistor can be changed.

[0259] Both electrode 746 and electrode 723 can be used as gate electrodes. Therefore, insulating layer 726, insulating layer 728, and insulating layer 729 can all be used as gate insulating layers. Alternatively, electrode 723 can be disposed between insulating layer 728 and insulating layer 729.

[0260] Note that when one of electrodes 746 and 723 is referred to as the "gate electrode," the other is referred to as the "back gate electrode." For example, in transistor 811, when electrode 723 is referred to as the "gate electrode," electrode 746 is referred to as the "back gate electrode." Furthermore, when electrode 723 is used as the "gate electrode," transistor 811 is a type of top-gate transistor. Additionally, sometimes one of electrodes 746 and 723 is referred to as the "first gate electrode," and sometimes the other is referred to as the "second gate electrode."

[0261] By setting electrodes 746 and 723 across semiconductor layer 742 and setting the potentials of electrodes 746 and 723 to be the same, the area through which carriers flow in semiconductor layer 742 is further expanded in the film thickness direction, thus increasing the amount of carrier movement. As a result, the on-state current of transistor 811 increases, and the field-effect mobility also increases.

[0262] Therefore, transistor 811 is a transistor with a large on-state current relative to its occupied area. That is, the occupied area of ​​transistor 811 can be reduced relative to the required on-state current. According to one embodiment of the present invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device with high integration density can be realized.

[0263] Furthermore, since the gate electrode and the back gate electrode are formed using a conductive layer, they have the function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed to be larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0264] Furthermore, by using a conductive film with light-shielding properties to form the back gate electrode, light can be prevented from entering the semiconductor layer from the back gate electrode side. As a result, light degradation of the semiconductor layer can be prevented, as well as degradation of electrical characteristics such as the critical voltage drift of the transistor.

[0265] According to one embodiment of the present invention, a transistor with high reliability can be realized. Furthermore, a semiconductor device with high reliability can be realized.

[0266] FIG1 shows a cross-sectional view along the channel length of a channel-protected transistor 820 with a structure different from that in FIG19A1. The transistor 820 has a structure substantially the same as that of the transistor 810, except that an insulating layer 741 covers the end of the semiconductor layer 742. In openings formed by selectively removing portions of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to an electrode 744a. Additionally, in other openings formed by selectively removing portions of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to an electrode 744b. The region of the insulating layer 741 overlapping the channel-forming region can be used as a channel protection layer.

[0267] The difference between transistor 821 shown in Figure 19B2 and transistor 820 is that: an electrode 723 that can be used as a back gate electrode is included on the insulating layer 729.

[0268] By providing the insulating layer 741, the exposure of the semiconductor layer 742 generated during the formation of electrodes 744a and 744b can be prevented. Therefore, the semiconductor layer 742 can be prevented from being thinned during the formation of electrodes 744a and 744b.

[0269] Furthermore, compared to transistors 810 and 811, the distances between electrodes 744a and 746, and between electrodes 744b and 746, are longer in transistors 820 and 821. Therefore, the parasitic capacitance generated between electrodes 744a and 746 can be reduced. Additionally, the parasitic capacitance generated between electrodes 744b and 746 can be reduced. According to one embodiment of the present invention, a transistor with excellent electrical characteristics can be provided.

[0270] Figure 19C1 shows a cross-sectional view along the channel length of a channel-etched transistor 825, which is one type of bottom-gate transistor. In the transistor 825, the electrodes 744a and 744b are formed without using an insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed during the formation of electrodes 744a and 744b is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the transistor's productivity can be improved.

[0271] The difference between the transistor 826 shown in Figure 19C2 and the transistor 825 is that the transistor 826 has an electrode 723 on the insulating layer 729 that can be used as a back gate electrode.

[0272] Figures 20A1, 20A2, 20B1, 20B2, 20C1 and 20C2 show cross-sectional views of the channel width direction of transistors 810, 811, 820, 821, 825 and 826.

[0273] In the structures shown in Figures 20B2 and 20C2, the gate electrode and the back gate electrode are connected to each other, so that the gate electrode and the back gate electrode have the same potential. In addition, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0274] In the channel width direction, the lengths of the gate electrode and the back gate electrode are greater than those of the semiconductor layer 742, and the semiconductor layer 742 is covered by the gate electrode or the back gate electrode, sandwiching the insulating layers 726, 741, 728, and 729.

[0275] By adopting this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric fields of the gate electrode and the back gate electrode.

[0276] A device structure of a transistor, such as transistor 821 or transistor 826, that uses the electric fields of the gate electrode and the back gate electrode to surround the semiconductor layer 742 forming the channel forming region is called a Surrounded channel (S-channel) structure.

[0277] By employing the S-channel structure, an electric field for inducing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate electrode and the back gate electrode. This improves the current-driving capability of the transistor, resulting in higher on-state current characteristics. Furthermore, the increased on-state current allows for transistor miniaturization. Additionally, the S-channel structure enhances the mechanical strength of the transistor.

[0278] [Top-gate transistor] The transistor 842 illustrated in FIG21A1 is one of the top-gate transistors. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 through openings formed in insulating layers 728 and 729.

[0279] Furthermore, a portion of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities 755 are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask. This allows impurity regions to be formed in the semiconductor layer 742 in a self-aligned manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where impurities 755 are introduced via the insulating layer 726 is lower than in the region where impurities 755 are not introduced via the insulating layer 726. Therefore, LDD (Lightly Doped Drain) regions are formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0280] The transistor 843 shown in FIG. 21A2 differs from transistor 842 in that it includes an electrode 723. Transistor 843 includes an electrode 723 formed on substrate 771. Electrode 723 is separated from the region where the insulating layer 772 overlaps with the semiconductor layer 742. Electrode 723 can be used as a back gate electrode.

[0281] Alternatively, as shown in Figure 21B1 for transistor 844 and Figure 21B2 for transistor 845, the insulating layer 726 in the area not overlapping with the electrode 746 can be completely removed. Alternatively, as shown in Figure 21C1 for transistor 846 and Figure 21C2 for transistor 847, the insulating layer 726 can be left intact.

[0282] In transistors 842 to 847, impurities 755 may be introduced into the semiconductor layer 742 after the electrode 746 is formed, using the electrode 746 as a mask, thereby forming impurity regions in the semiconductor layer 742 in a self-aligned manner. According to one embodiment of the present invention, a transistor with excellent electrical characteristics can be realized. In addition, according to one embodiment of the present invention, a semiconductor device with high integration density can be realized.

[0283] Figures 22A1, 22A2, 22B1, 22B2, 22C1 and 22C2 show cross-sectional views of the channel width direction of transistors 842, 843, 844, 845, 846 and 847.

[0284] Transistors 843, 845, and 847 have the above-described S-channel structure. However, they are not limited to this; transistors 843, 845, and 847 may also not have an S-channel structure.

[0285] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0286] Embodiment 4 Examples of electronic devices that can utilize a display device according to one embodiment of the present invention include display devices, personal computers, image memory devices and image playback devices equipped with storage media, mobile phones, game consoles including portable game consoles, portable data terminals, e-book readers, shooting devices such as video cameras or digital cameras, head-mounted displays, navigation systems, audio playback devices (car audio systems, digital audio players, etc.), photocopiers, fax machines, printers, multi-function printers, automatic teller machines (ATMs), and vending machines. Figures 23A to 23F show specific examples of these electronic devices.

[0287] Figure 23A shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom button 968, a lens 969, etc. By using the display device of one embodiment of the present invention in the display unit 965, various images can be displayed.

[0288] Figure 23B is a digital signage panel that includes a large display unit 922. For example, it can be installed on the side of a pillar 921. By using a display device according to one embodiment of the present invention in the display unit 922, various images can be displayed.

[0289] Figure 23C shows a mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations, such as making calls or inputting text, can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the housing 951 and the display unit 952 are flexible and can be bent as shown in the figure. By using the display device of one embodiment of the present invention in the display unit 952, various images can be displayed.

[0290] Figure 23D shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Data can be input or output using the touch panel function of the display unit 912. By using the display device of one embodiment of the present invention in the display unit 912, various images can be displayed.

[0291] Figure 23E shows a television set, which includes a housing 971, a display unit 973, operation keys 974, a speaker 975, a communication connection terminal 976, and a light sensor 977, etc. The display unit 973 is equipped with a touch sensor, which allows for input operations. By using the display device of one embodiment of the present invention in the display unit 973, various images can be displayed.

[0292] Figure 23F shows an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, and a sensor 904. The display units 902 and 903 are composed of a single display panel and are flexible. Furthermore, the housing 901 is also flexible, allowing the information processing terminal to be folded for use as shown in the figure, and enabling it to be used in a flat, tablet-like form. The sensor 904 can detect the shape of the housing 901; for example, when the housing is bent, the display of the display units 902 and 903 can be switched. By using the display device according to one embodiment of the present invention for the display units 902 and 903, various images can be displayed.

[0293] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc. [Simplified Explanation of the Diagram]

[0026] In the figures; Figure 1 is a diagram illustrating the pixel circuit; Figures 2A and 2B are timing diagrams illustrating the operation of the pixel circuit; Figures 3A and 3B are diagrams illustrating image data correction and image synthesis; Figures 4A to 4C are diagrams illustrating circuit blocks; Figures 5A to 5C are diagrams illustrating circuit blocks; Figures 6A to 6C are diagrams illustrating the pixel circuit; Figure 7 is a diagram illustrating the pixel array; Figures 8A1, 8A2, 8B1, and 8B2 are timing diagrams illustrating the operation of the pixel array; Figures 9A to 9C are block diagrams illustrating the display device; Figures 10A and 10B are diagrams illustrating an example of the structure of a neural network; Figure 11 is a diagram illustrating the structure of a pixel array used for analog; Figures 12A to 12C are diagrams illustrating the analog results; Figures 13A to 13D are diagrams illustrating the analog results; Figures 14A to 14D are diagrams illustrating the analog results. Figure 15 is a diagram illustrating the structure of a pixel; Figures 16A to 16C are diagrams illustrating a display device; Figures 17A and 17B are diagrams illustrating a touch panel; Figures 18A and 18B are diagrams illustrating a display device; Figures 19A1, 19A2, 19B1, 19B2, 19C1, and 19C2 are diagrams illustrating a transistor; Figures 20A1, 20A2, 20B1, 20B2, 20C1, and 20C2 are diagrams illustrating a transistor; Figures 21A1, 21A2, 21B1, 21B2, 21C1, and 21C2 are diagrams illustrating a transistor; Figures 22A1, 22A2, 22B1, 22B2, 22C1, and 22C2 are diagrams illustrating a transistor; Figures 23A to 23F are diagrams illustrating an electronic device. [Biomaterial Storage]

[0295] None

Claims

1. A display device, comprising: First transistor; Second transistor; First pixel; Second pixel; First wiring; Second wiring; Third wiring; The first pixel and the second pixel each include a third transistor, a first capacitor, and a circuit block. The circuit block of each of the first pixel and the second pixel includes a display element. One of the source and drain electrodes of the first transistor is electrically connected to one of the source and drain electrodes of the second transistor. The other of the source and drain electrodes of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the third wiring. The gate of the second transistor is electrically connected to the second wiring. In each of the first pixel and the second pixel, one of the source and drain electrodes of the third transistor is electrically connected to the first electrode of the first capacitor. In each of the first pixel and the second pixel, the first electrode of the first capacitor is electrically connected to the circuit block. In each of the first pixel and the second pixel, the second electrode of the first capacitor is electrically connected to one of the source and drain electrodes of the first transistor. In the first pixel, the other of the source and drain electrodes of the third transistor is electrically connected to the first wiring. Furthermore, in the second pixel, another of the source and drain electrodes of the third transistor is electrically connected to the fourth wiring.

2. A display device, comprising: First transistor; Second transistor; First pixel; Second pixel; First wiring; Second wiring; Third wiring; The first pixel and the second pixel each include a third transistor, a first capacitor, and a circuit block. The circuit block of each of the first pixel and the second pixel includes a display element. One of the source and drain electrodes of the first transistor is electrically connected to one of the source and drain electrodes of the second transistor. The other of the source and drain electrodes of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the third wiring. The gate of the second transistor is electrically connected to the second wiring. In each of the first pixel and the second pixel, one of the source and drain electrodes of the third transistor is electrically connected to the first electrode of the first capacitor. In each of the first pixel and the second pixel, the gate of the third transistor is electrically connected to the second wiring. In each of the first pixel and the second pixel, the first electrode of the first capacitor is electrically connected to the circuit block. In each of the first pixel and the second pixel, the second electrode of the first capacitor is electrically connected to one of the source and drain electrodes of the first transistor. In the first pixel, the other of the source and drain of the third transistor is electrically connected to the first wiring, and in the second pixel, the other of the source and drain of the third transistor is electrically connected to the fourth wiring.

3. The display device as claimed in claim 1 or 2, wherein in each of the first pixel and the second pixel, the circuit block further includes a fourth transistor and a second capacitor, the display element is an organic EL element, in each of the first pixel and the second pixel, a first electrode of the organic EL element is electrically connected to a first electrode of the second capacitor, in each of the first pixel and the second pixel, the first electrode of the organic EL element is electrically connected to one of the source and drain of the fourth transistor, in each of the first pixel and the second pixel, the other of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the second transistor, and in each of the first pixel and the second pixel, the gate of the fourth transistor is electrically connected to a second electrode of the second capacitor.

4. The display device as claimed in claim 3, wherein in each of the first pixel and the second pixel, the second electrode of the second capacitor is electrically connected to one of the source and the drain of the third transistor.

5. The display device as claimed in claim 1 or 2, wherein in each of the first pixel and the second pixel, the circuit block further includes a third capacitor, the display element is a liquid crystal element, in each of the first pixel and the second pixel, a first electrode of the liquid crystal element is electrically connected to a first electrode of the third capacitor, and in each of the first pixel and the second pixel, a second electrode of the third capacitor is electrically connected to the other of the source and drain electrodes of the second transistor.

6. The display device as claimed in claim 5, wherein in each of the first pixel and the second pixel, the first electrode of the third capacitor is electrically connected to one of the source and the drain of the third transistor.

7. The display device as claimed in claim 1 or 2, wherein the third transistor in each of the first pixel and the second pixel comprises a metal oxide in the channel forming region, and the metal oxide comprises at least In.

8. The display device as claimed in claim 1 or 2, wherein the third transistor in each of the first pixel and the second pixel comprises a metal oxide in the channel forming region, and the metal oxide comprises In, Zn, and M, wherein M is selected from Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, and Hf.

9. An electronic device comprising a display device and a camera as described in claim 1 or 2.

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