Semiconductor memory devices

Abstract

This invention provides a preferred semiconductor memory device. The semiconductor memory device includes: a plurality of memory layers arranged along a first direction; a via wiring extending along the first direction; a first wiring disposed on one side of the plurality of memory layers in the first direction and extending along a second direction; and an insulating layer disposed on the other side of the plurality of memory layers in the first direction and covering the end of the via wiring. Each of the plurality of memory layers includes: a semiconductor layer connected to the via wiring; a gate electrode facing the semiconductor layer; a second wiring extending along a third direction and connected to the gate electrode; and a memory portion disposed on the side opposite to the second wiring in the second direction and connected to the semiconductor layer. The via wiring includes: a conductive member extending along the first direction; and an internal region extending along the first direction with its outer peripheral surface surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer or continuous with the insulating layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Prior Technology

[0002] With the increasing integration of semiconductor memory devices, research related to the three-dimensionalization of semiconductor memory devices is underway. Summary of the Invention

[0003] The present invention provides a semiconductor memory device that operates optimally.

[0004] One embodiment of a semiconductor memory device includes: a plurality of memory layers arranged along a first direction; a via wiring extending along the first direction; a first wiring disposed on one side of the plurality of memory layers in the first direction and extending along a second direction intersecting the first direction; and an insulating layer disposed on the other side of the plurality of memory layers in the first direction and covering the end of the via wiring. Each of the plurality of memory layers includes: a semiconductor layer electrically connected to the via wiring; a gate electrode facing the semiconductor layer; a second wiring extending along a third direction intersecting the first and second directions and electrically connected to the gate electrode; and a memory portion disposed on the side opposite to the second wiring in the second direction and electrically connected to the semiconductor layer. The via wiring includes: a conductive member extending along the first direction; and an internal region extending along the first direction with its outer peripheral surface surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer or continuous with the insulating layer. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic exploded perspective view showing a structural example of the semiconductor memory device according to the first embodiment. Figure 2 is a schematic circuit diagram showing the structure of the semiconductor memory device. Figure 3 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 4 is a schematic perspective view showing a portion of the structure of the semiconductor memory device. Figure 5 is a schematic cross-sectional view showing a portion of the structure of the memory layer ML. Figure 6 is a schematic cross-sectional view showing a portion of the structure of the memory layer ML. Figure 7 is a cross-sectional view of the structure shown in Figure 6 cut along line A1-A1' and viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view showing a portion of the structure of the transistor layer TL. Figure 9 is a cross-sectional view of the structure shown in Figure 8 cut along line B1-B1' and viewed in the direction of the arrow. Figure 10 is a schematic cross-sectional view showing a portion of the structure of the bit line BL. Figure 11 is a cross-sectional view of the structure shown in Figure 10 cut along line C1-C1' and viewed in the direction of the arrow. Figure 12 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. Figure 13 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 14 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 15 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 16 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 17 is a schematic cross-sectional view illustrating the manufacturing method. Figure 18 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 19 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 20 is a schematic cross-sectional view illustrating the manufacturing method. Figure 21 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 22 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 23 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 24 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 25 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 26 is a schematic cross-sectional view illustrating the manufacturing method. Figure 27 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 28 is a schematic cross-sectional view illustrating the manufacturing method. Figure 29 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 30 is a schematic cross-sectional view illustrating the manufacturing method. Figure 31 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 32 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 33 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 34 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 35 is a schematic cross-sectional view illustrating the manufacturing method. Figure 36 is a schematic cross-sectional view illustrating the manufacturing method. Figure 37 is a schematic cross-sectional view illustrating the manufacturing method. Figure 38 is a schematic cross-sectional view illustrating the manufacturing method. Figure 39 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 40 is a schematic cross-sectional view illustrating the manufacturing method. Figure 41 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 42 is a schematic cross-sectional view illustrating the manufacturing method. Figure 43 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 44 is a schematic cross-sectional view illustrating the manufacturing method. Figure 45 is a schematic cross-sectional view illustrating the manufacturing method. Figure 46 is a schematic cross-sectional view illustrating the manufacturing method. Figure 47 is a schematic cross-sectional view illustrating the manufacturing method. Figure 48 is a schematic cross-sectional view illustrating the manufacturing method. Figure 49 is a schematic cross-sectional view illustrating the manufacturing method. Figure 50 is a schematic cross-sectional view illustrating the manufacturing method. Figure 51 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 52 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 53 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 54 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 55 is a schematic cross-sectional view illustrating the manufacturing method. Figure 56 is a schematic cross-sectional view illustrating the manufacturing method. Figure 57 is a schematic cross-sectional view illustrating the manufacturing method. Figure 58 is a schematic cross-sectional view illustrating the manufacturing method. Figure 59 is a schematic cross-sectional view showing a portion of the structure of a semiconductor memory device according to a variation of the first embodiment 1. Figure 60 is a cross-sectional view of the structure shown in Figure 59 cut along line D1-D1' and viewed in the direction of the arrow. Figure 61 is a schematic cross-sectional view showing a portion of the structure of a semiconductor memory device according to a variation of the first embodiment, Example 2. Figure 62 is a schematic circuit diagram showing the structure of the semiconductor memory device according to the second embodiment. Figure 63 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 64 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 65 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. Figure 66 is a schematic cross-sectional view illustrating the manufacturing method. Figure 67 is a schematic cross-sectional view illustrating the manufacturing method. Figure 68 is a schematic cross-sectional view illustrating the manufacturing method. Figure 69 is a schematic cross-sectional view illustrating the manufacturing method. Figure 70 is a schematic cross-sectional view illustrating the manufacturing method. Figure 71 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 72 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 73 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 74 is a schematic cross-sectional view illustrating the manufacturing method. Figure 75 is a schematic cross-sectional view illustrating the manufacturing method. Figure 76 is a schematic cross-sectional view illustrating the manufacturing method. Figure 77 is a schematic cross-sectional view illustrating the manufacturing method. Figure 78 is a schematic cross-sectional view illustrating the manufacturing method. Figure 79 is a schematic cross-sectional view illustrating the manufacturing method. Figure 80 is a schematic cross-sectional view illustrating the manufacturing method. Figure 81A is a schematic cross-sectional view showing a portion of the structure of a semiconductor memory device according to a modified example of the second embodiment. Figure 81B is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. Figure 82 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device according to the third embodiment. Figure 83 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 84 is a cross-sectional view of the structure shown in Figure 83 cut along line A3-A3' and viewed in the direction of the arrow. Figure 85 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device. Figure 86 is a schematic cross-sectional view illustrating the manufacturing method. Figure 87 is a schematic cross-sectional view illustrating the manufacturing method. Figure 88 is a schematic cross-sectional view illustrating the manufacturing method. Figure 89 is a schematic cross-sectional view illustrating the manufacturing method. Figure 90 is a schematic cross-sectional view illustrating the manufacturing method. Figure 91 is a schematic cross-sectional view illustrating the manufacturing method. Figure 92 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 93 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 94 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 95 is a schematic cross-sectional view illustrating the manufacturing method. Figure 96 is a schematic cross-sectional view illustrating the manufacturing method. Figure 97 is a schematic cross-sectional view illustrating the manufacturing method. Figure 98 is a schematic cross-sectional view illustrating the manufacturing method. Figure 99 is a schematic cross-sectional view illustrating the manufacturing method. Figure 100 is a schematic cross-sectional view illustrating the manufacturing method. Figure 101 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 102 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 103 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 104 is a schematic cross-sectional view for illustrating the manufacturing method. Implementation

[0006] Next, the semiconductor memory device of the embodiments will be described in detail with reference to the drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and sometimes some structures are omitted for ease of explanation. Also, sometimes common parts in multiple embodiments are labeled with the same symbols and their descriptions are omitted.

[0007] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes refers to a memory die, and sometimes to a memory system including a controller die, such as a memory chip, memory card, or solid-state drive (SSD). Moreover, it sometimes refers to the structure of a smartphone, tablet, personal computer, or host computer.

[0008] Furthermore, in this specification, when referring to the "electrical connection" between the first structure and the second structure, the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is still "electrically connected" to the third transistor.

[0009] In addition, in this specification, when referring to the "electrical connection" between the first structure, the second structure and the third structure, it sometimes means that the first structure, the second structure and the third structure are connected in series, and the second structure is electrically connected to the third structure through the first structure.

[0010] Furthermore, in this specification, when referring to a circuit or the like that makes two wirings "conduct", it may mean, for example, that the circuit or the like includes a transistor or the like, which is placed in the current path between the two wirings and is in an ON state.

[0011] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0012] In addition, in this specification, the direction intersecting the surface of the substrate is sometimes referred to as the first direction. Furthermore, the direction along a predetermined surface intersecting the first direction is sometimes referred to as the second direction, and the direction along said surface intersecting the second direction is sometimes referred to as the third direction. The first direction may or may not be the same as the Z direction. Furthermore, the second direction and the third direction may or may not correspond to either the X direction or the Y direction.

[0013] Furthermore, in this specification, when referring to the "center position" of a structure, it may refer to, for example, the center of the circumcircle of the structure, or the centroid of the structure in a graphic representation.

[0014] [First Implementation Method] [Structure of memory chip MD] Figure 1 is a schematic exploded perspective view showing a structural example of the semiconductor memory device according to the first embodiment. As shown in Figure 1, the memory die MD includes a chip CM and a chip CP. The chip CM includes a memory cell array MCA. The chip CP includes peripheral circuitry connected to the memory cell array MCA.

[0015] Multiple external bonding pad electrodes PX are provided on one side of the wafer CM. Multiple first bonding electrodes PI1 are provided on the other side of the wafer CM. Multiple second bonding electrodes PI2 are provided on one side of the wafer CP. Hereinafter, for the wafer CM, the side with the multiple first bonding electrodes PI1 is referred to as the surface, and the side with the multiple external bonding pad electrodes PX is referred to as the back side. Similarly, for the wafer CP, the side with the multiple second bonding electrodes PI2 is referred to as the surface, and the side opposite to the surface is referred to as the back side.

[0016] The wafer CM and wafer CP are arranged with the surfaces of the wafer CM and wafer CP facing each other. Multiple first bonding electrodes PI1 are respectively disposed corresponding to multiple second bonding electrodes PI2, and are positioned to bond with the multiple second bonding electrodes PI2. The first bonding electrodes PI1 and the second bonding electrodes PI2 function as bonding electrodes for bonding the wafer CM and wafer CP and making them electrically conductive.

[0017] Furthermore, in the example of Figure 1, corners a1, a2, a3, and a4 of the wafer CM correspond to corners b1, b2, b3, and b4 of the wafer CP, respectively.

[0018] [Circuit Structure] Figure 2 is a schematic circuit diagram showing the structure of the semiconductor memory device according to the first embodiment. The memory cell array MCA includes: multiple memory layers ML; transistor layers TL; multiple bit lines BL connected to the multiple memory layers ML and transistor layers TL; multiple global bit lines GBL electrically connected to the multiple bit lines BL via the multiple transistor layers TL; and board lines PL connected to the multiple memory layers ML.

[0019] The memory layer ML includes multiple word lines WL0~WL2 (hereinafter sometimes referred to as "word lines WL") and multiple memory cells MC connected to these word lines WL0~WL2. Each memory cell MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. Furthermore, one and the other electrodes of the transistor TrC function as source or drain electrodes depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to any one of the word lines WL0~WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to the plate line PL.

[0020] Furthermore, each bit line BL is connected to multiple memory cells MC corresponding to multiple memory layers ML.

[0021] In addition, each memory layer ML includes multiple transistors TrLa and TrLb (hereinafter sometimes referred to as "transistors TrL") corresponding to multiple word lines WL0 to WL2. One electrode of each transistor TrL is connected to any one of the word lines WL0 to WL2. The other electrode of each transistor TrL is connected to the word line select lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter sometimes referred to as "word line select lines LW"). Furthermore, one and the other electrodes of each transistor TrL function as source or drain electrodes depending on the voltage supplied to the transistor TrL. The gate electrode of each transistor TrL is connected to the layer select lines LLa and LLb (hereinafter sometimes referred to as "layer select lines LL").

[0022] Furthermore, the character selection line LW is connected to multiple transistors TrL corresponding to multiple memory layers ML. Additionally, the layer selection line LLa is connected to all transistors TrLa corresponding to multiple memory layers ML. Similarly, the layer selection line LLb is connected to all transistors TrLb corresponding to multiple memory layers ML.

[0023] The transistor layer TL includes multiple bit line select lines LB0~LB2 (hereinafter sometimes referred to as "bit line select lines LB") and multiple transistors TrB connected to the multiple bit line select lines LB0~LB2. One electrode of the transistor TrB is connected to the global bit line GBL via electrode Cn1. The other electrode of the transistor TrB is connected to the bit line BL. Furthermore, one electrode of the transistor TrB and the other electrode function as source electrodes or drain electrodes depending on the voltage supplied to the transistor TrB. The gate electrode of the transistor TrB is connected to any one of the bit line select lines LB0~LB2.

[0024] Multiple bit selection lines LB0~LB2 are connected to a drive circuit disposed on the chip CP, for example, via a first bonding electrode PI1 and a second bonding electrode PI2 (Fig. 1).

[0025] [Structure of the chip CP] Figure 3 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device according to this embodiment. A portion of the structure of the wafer CM and the wafer CP is shown in Figure 3.

[0026] In the chip CP (Figure 3), multiple transistors Tr and wirings are disposed on a substrate Sub2, such as silicon (Si). These multiple transistors Tr and wirings constitute control circuits and drive circuits for controlling the memory cell array MCA. For example, the control circuit includes a sense amplifier circuit. The sense amplifier circuit is electrically connected to the bit line BL disposed on the chip CM via the second bonding electrode PI2, the first bonding electrode PI1, and the global bit line GBL. During readout, the sense amplifier circuit can read out the data stored in the select memory cell MC by detecting the voltage change or current of the bit line BL.

[0027] [Structure of a chip CM] The wafer CM (Figure 3) includes region R MCA and region R PC. At the bottom of region R MCA and region R PC are a wiring layer M0 including global bit lines GBL and wiring m0, a wiring layer M1 including wiring m1, and a first bonding electrode PI1. At the top of region R MCA and region R PC are insulating layers 210 (silicon nitride (SiN) or similar), 211, 212, and 213 (silicon oxide (SiO2) or similar).

[0028] [Structure of Region R MCA] The region R MCA contains a memory cell array MCA and a conductive layer MA10 above the memory cell array MCA.

[0029] Figure 4 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device according to this embodiment. Figure 4 shows a portion of the structure of the memory cell array (MCA) disposed in the wafer CM.

[0030] Furthermore, in the following description of the memory cell array (MCA), the expressions "up" or "down" are based on the global bit line (GBL). For example, the direction away from the global bit line GBL along the Z direction is called "up," and the direction closer to the global bit line GBL along the Z direction is called "down." Additionally, when referring to the upper surface or upper end of a structure, it refers to the face or end of the structure opposite to the side of the global bit line GBL; when referring to the lower surface or lower end, it refers to the face or end of the structure on the side of the global bit line GBL. Furthermore, the surface intersecting the X or Y direction is called the side surface, etc.

[0031] For example, as shown in Figures 3 and 4, the memory cell array (MCA) includes: multiple memory layers ML, stacked along the Z direction; a transistor layer TL, disposed between the memory layers ML and the global bit line GBL; and a conductive layer PM10, disposed on the opposite side of the global bit line GBL relative to the multiple memory layers ML. The length of the memory layer ML in the Z direction is the same as the length of the transistor layer TL in the Z direction.

[0032] An insulating layer 103, such as silicon oxide (SiO2), is provided between each of the multiple memory layers ML. Additionally, an insulating layer 203, such as silicon oxide (SiO2), is provided between the first memory layer ML from the bottom and the transistor layer TL. The length of the insulating layer 203 in the Z direction is greater than the length of the insulating layer 103 in the Z direction.

[0033] [Structure of memory layer ML and transistor layer TL] Next, based on Figures 3 and 4, and referring to Figures 5 to 11, the structure of the memory layer ML and the transistor layer TL will be described.

[0034] Figure 5 is a schematic cross-sectional view showing a portion of the memory layer ML. Figure 6 is a schematic cross-sectional view showing a portion of the memory layer ML, enlarged to show a portion of Figure 5. Figure 7 shows a cross-section taken along line A1-A1' of the structure shown in Figure 6, viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view showing a portion of the transistor layer TL. Figure 9 shows a cross-section taken along line B1-B1' of the structure shown in Figure 8, viewed in the direction of the arrow. Figure 10 is a schematic cross-sectional view showing a portion of the bit line BL. Figure 11 shows a cross-section taken along line C1-C1' of the structure shown in Figure 10, viewed in the direction of the arrow.

[0035] As shown in Figure 5, the memory layer ML includes: multiple insulating layers 101 arranged along the X direction; and a conductive layer 102 disposed between two adjacent insulating layers 101 in the X direction. The insulating layers 101 and the conductive layer 102 extend along the Y and Z directions, and divide the multiple memory layers ML along the X direction.

[0036] The insulating layer 101 may contain, for example, silicon oxide (SiO2).

[0037] The conductive layer 102 may include, for example, a multilayer structure of titanium nitride (TiN) and tungsten (W). Alternatively, the conductive layer 102 may also include a multilayer structure of titanium nitride (TiN) and silicon germanium (SiGe), or a multilayer structure of titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W). The conductive layer 102 functions as a board line PL (FIG. 2).

[0038] A plurality of via wirings 104 are provided in the region between the insulating layer 101 and the conductive layer 102 (Fig. 5). The plurality of via wirings 104 are arranged along the Y direction, and, for example, as shown in Fig. 4, extend along the Z direction through the transistor layer TL and a plurality of memory layers ML.

[0039] As shown in Figures 7 and 9, the via wiring 104 includes, for example, a conductive oxide film 104a extending along the Z direction, and an internal region CAV described later. The via wiring 104 functions, for example, as a bit line BL (Figure 2). For example, as shown in Figures 3-5, multiple bit lines BL are provided corresponding to multiple transistors TrC included in the memory layer ML and multiple transistors TrB included in the transistor layer TL.

[0040] The conductive oxide film 104a has a generally cylindrical shape extending along the Z direction. The conductive oxide film 104a functions as a conductive component for, for example, through-hole wiring 104. The conductive oxide film 104a may contain, for example, indium tin oxide (ITO).

[0041] The memory layer ML and transistor layer TL include: a plurality of transistor structures 110, corresponding to a plurality of via wirings 104; and a conductive layer 120, disposed on the opposite side of the conductive layer 102 relative to the plurality of transistor structures 110. Additionally, the memory layer ML includes a plurality of capacitor structures 130 disposed between the plurality of transistor structures 110 and the conductive layer 102. Furthermore, the transistor layer TL (FIG. 9) includes an electrode structure 130c disposed between the plurality of transistor structures 110 and a plurality of contacts GBLC1.

[0042] For example, as shown in Figures 6 to 9, the transistor structure 110 includes: a semiconductor layer 111, which is connected to the outer peripheral surface of the via wiring 104 and extends along the X direction; an insulating layer 112, which is disposed on the upper surface, lower surface, two sides in the Y direction, and one side (the conductive layer 120 side) in the X direction of the semiconductor layer 111; and a conductive layer 113, which is disposed on the upper surface, lower surface, two sides in the Y direction, and one side (the conductive layer 120 side) in the X direction of the insulating layer 112.

[0043] In the XY cross-section illustrated in Figures 6 and 8, one side of the semiconductor layer 111 in the X direction (the conductive layer 120 side) can be formed along a circle centered on the center position of the via wiring 104. Furthermore, the other side of the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the X direction (the conductive layer 102 side) can be formed as a straight line along the side of the conductive layer 102. Additionally, the two sides of the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the Y direction can be formed as a straight line along the side of the insulating layer 115.

[0044] Semiconductor layer 111 functions as a channel region for transistors TrC and TrB (FIG. 2). Semiconductor layer 111 may be a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be other oxide semiconductors. The plurality of semiconductor layers 111 arranged along the Z-direction are commonly connected to via wiring 104 extending along the Z-direction.

[0045] The insulating layer 112 functions as a gate insulating film for transistors TrC and TrB (Fig. 2). The insulating layer 112 may contain silicon oxide (SiO2) or the like.

[0046] The conductive layer 113 functions as the gate electrode of transistors TrC and TrB (FIG. 2), for example. The conductive layer 113 may contain conductive oxides such as titanium nitride (TiN) or indium tin oxide (ITO). Multiple conductive layers 113 arranged along the Y direction are connected in common with a conductive layer 120 extending along the Y direction (see FIG. 4 and FIG. 5). The conductive layer 113 faces the upper surface, lower surface, both sides in the Y direction, and one side (the conductive layer 120 side) of the semiconductor layer 111 via an insulating layer 112. Furthermore, in this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO₂), iridium oxide (IrO₂), or other oxygen-containing conductive materials.

[0047] An insulating layer 115, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 111 in the Y direction. The insulating layer 115 extends along the Z direction, penetrating the transistor layer TL and multiple memory layers ML.

[0048] The conductive layer 120 functions as a word line WL in the memory layer ML, for example, and as a bit line select line LB in the transistor layer TL (FIG. 2). The conductive layer 120 extends along the Y direction and connects to a plurality of conductive layers 113 arranged along the Y direction. For example, as shown in FIG. 6 and FIG. 8, the conductive layer 120 is connected to the conductive layer 113 on one side in the X direction and to the insulating layer 101 on the other side. The conductive layer 120 includes, for example, a barrier conductive film 121 of titanium nitride (TiN) or the like, and a conductive film 122 of tungsten (W). The barrier conductive film 121 is disposed on the upper surface, lower surface, and one side (transistor structure 110 side) of the conductive film 122 in the X direction.

[0049] For example, as shown in Figures 6 and 7, the capacitor structure 130 includes: a conductive layer 131; an insulating layer 132 disposed on the upper surface, lower surface, both sides in the Y direction, and one side (transistor structure 110 side) of the conductive layer 131; and a conductive layer 133 disposed on the upper surface, lower surface, both sides in the Y direction, and one side (transistor structure 110 side) of the insulating layer 132.

[0050] The conductive layer 131 functions as one of the electrodes in the capacitor CpC (Figure 2). The conductive layer 131 may, for example, comprise a multilayer structure of titanium nitride (TiN) and germanium silicon (SiGe). Alternatively, the conductive layer 131 may also comprise a multilayer structure of titanium nitride (TiN) and tungsten (W), or a multilayer structure of titanium nitride (TiN), germanium silicon (SiGe), and tungsten (W). One side of the conductive layer 131 in the X direction is connected to the conductive layer 102.

[0051] The insulating layer 132 functions as the insulating layer of the capacitor CpC (Figure 2). The insulating layer 132 may be, for example, zirconium oxide (ZrO 2), aluminum oxide (Al 2O 3), or other insulating metal oxides. Alternatively, the insulating layer 132 may be, for example, a laminated film of multiple insulating metal oxides (e.g., a laminated film of zirconium oxide and aluminum oxide).

[0052] Conductive layer 133 functions as another electrode in capacitor CpC (FIG. 2), for example. Conductive layer 133 contains, for example, a conductive oxide such as indium tin oxide (ITO). Conductive layer 133 is insulated from conductive layer 131 via insulating layer 132. Conductive layer 133 is connected to the X-direction side of semiconductor layer 111. Conductive layer 133 is insulated from conductive layer 102 via insulating layer 132.

[0053] For example, as shown in Figures 8 and 9, the electrode structure 130c includes: a conductive layer 131c; an insulating layer 132c disposed on the upper surface, lower surface, two sides in the Y direction, and one side (transistor structure 110 side) of the conductive layer 131c; and a conductive layer 133c disposed on the upper surface, lower surface, two sides in the Y direction, and one side (transistor structure 110 side) of the insulating layer 132c.

[0054] The conductive layer 131c contains the same material as the conductive layer 131. One side of the conductive layer 131c in the X direction (the conductive layer 102 side) is in contact with an insulating layer 106 such as silicon oxide (SiO2).

[0055] Insulating layer 132c contains the same material as insulating layer 132. One side of insulating layer 132c in the X direction (the conductive layer 102 side) is in contact with insulating layer 106.

[0056] The conductive layer 133c functions as a conductive component, for example, in the electrode Cn1 (FIG. 2). The conductive layer 133c contains the same material as the conductive layer 133. One side of the conductive layer 133c in the X direction (the side of transistor structure 110) is connected to the side of the semiconductor layer 111 in the X direction. The other side of the conductive layer 133c in the X direction (the side of insulating layer 106) is connected to the insulating layer 106.

[0057] A contact GBLC1 is disposed below the electrode structure 130c (Figs. 3, 4, and 9). For example, as shown in Fig. 9, the contact GBLC1 includes a conductive film 206 such as indium tin oxide (ITO) and an insulating film 207 such as silicon oxide (SiO2). The upper surface of the contact GBLC1 is connected to the lower surface of the conductive layer 133c included in the electrode structure 130c. The lower surface of the contact GBLC1 is connected to the global bit line GBL (Fig. 3). The contact GBLC1 functions, for example, as an electrode that connects the transistor TrB to the global bit line GBL via the electrode Cn1.

[0058] Global bit lines (GBLs) extend along the X direction and are arranged in multiples along the Y direction, as shown in Figure 3. The GBLs can be arranged at the same spacing as the transistor structure 110 along the Y direction (Figure 5). Examples of GBLs include barrier conductive films such as titanium nitride (TiN) and conductive films of tungsten (W).

[0059] The conductive layer PM10 (FIG. 3) includes a portion PM10a (FIG. 3) connected to the plate line PL (conductive layer 102). The conductive layer PM10 functions, for example, as wiring to connect multiple plate lines PL (FIG. 5) arranged along the X direction. The conductive layer PM10 (FIG. 3) includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W).

[0060] Additionally, the conductive layer PM10 (FIG. 3) includes a portion of PM10b (FIG. 3) at the location where it overlaps with the via wiring 104 when viewed from the Z direction. The conductive layer PM10 functions, for example, as a layer to prevent hydrogen (H) from diffusing into the multiple memory layers ML and transistor layers TL during the manufacturing steps described later.

[0061] The conductive layer MA10 is disposed above the conductive layer PM10, with insulating layers 212 and 213 as a barrier. The conductive layer MA10 may include, for example, a laminated structure of titanium nitride (TiN) and aluminum (Al).

[0062] [Structure of Regional RPC] The RPC area is provided with a contact CC, a conductive layer PM20 connected to the upper end of the contact CC, and a conductive layer MA20 connected to the upper surface of the conductive layer PM20.

[0063] The contact CC (Figure 3) extends along the Z direction. The contact CC is connected below to the wiring m0 included in the wiring layer M0, and is electrically connected to the first bonding electrode PI1 via wiring m0, wiring m1, etc. The contact CC may, for example, comprise a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0064] The conductive layer PM20 includes a portion PM20a (FIG. 3) connected to the contact CC. The conductive layer PM20 functions, for example, as wiring connecting the contact CC to the conductive layer MA20. The conductive layer PM20 (FIG. 3) contains, for example, the same material as the conductive layer PM10.

[0065] The portion of conductive layer MA20 that connects to conductive layer PM20 functions, for example, as an external pad electrode PX (Figure 1). Conductive layer MA20 (Figure 3) contains, for example, the same material as conductive layer MA10.

[0066] [Details of the Internal Area CAV] Next, the details of the internal region CAV will be described with reference to Figures 10 and 11. Figures 10 and 11 are schematic cross-sectional views showing the structure at the end of the bit line BL. Figure 11 shows a cross-section taken along line C1-C1', showing the structure shown in Figure 10 and viewed in the direction of the arrow. Furthermore, the end of the internal region CAV that is opposite to the global bit line GBL in the Z direction relative to the memory layer ML will sometimes be referred to as the upper end PT10 of the internal region CAV.

[0067] For example, as shown in Figures 10 and 11, the inner region CAV has a generally cylindrical shape extending along the Z direction. The outer peripheral surface of the inner region CAV is, for example, surrounded by a conductive oxide film 104a.

[0068] The upper end PT10 of the inner region CAV (Figs. 10 and 11) is not covered by the conductive oxide film 104a. The upper end PT10 of the inner region CAV is covered, for example, by the insulating layer 211.

[0069] As shown in Figure 10, the upper end PT10 of the inner region CAV can be connected to the insulating layer 211.

[0070] Furthermore, a portion of the insulating layer 211 may also be formed to extend into the interior of the cylindrical conductive oxide film 104a. In this case, the upper end of the interior region CAV is continuous with the insulating layer 211.

[0071] The internal region CAV can be, for example, a cavity. Furthermore, a cavity refers to a space surrounded by solid material disposed around the cavity, but the cavity itself does not contain any solid material. A cavity is a space containing, for example, air containing a mixture of gases such as nitrogen, oxygen, and rare gases. Furthermore, a cavity can also be degassed to contain no gas.

[0072] The internal region CAV may include, for example, an insulating layer of silicon oxide (SiO 2), silicon nitride (SiN), etc.

[0073] For example, as shown in Figure 3, the internal region CAV can be configured to extend along the Z-direction from the transistor layer TL, located closest to the global bit line GBL, to the memory layer ML, located furthest from the global bit line GBL. Alternatively, the internal region CAV can also be configured to extend along the Z-direction from the memory layer ML, located closest to the global bit line GBL, to the memory layer ML, located furthest from the global bit line GBL.

[0074] [Manufacturing Method] Figures 12 to 58 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment.

[0075] Figures 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, and 40 show the XY cross-sections corresponding to Figure 6.

[0076] Figures 42, 44, 46, and 48 show the XY cross-sections corresponding to Figure 8.

[0077] Figures 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, and 49 show the XZ cross-sections corresponding to a portion of the memory layer ML and the transistor layer TL.

[0078] Figures 50-53 and 55-58 show the cross-sections corresponding to Figure 3. Figure 54 shows a cross-section with the end of the bit line magnified.

[0079] Furthermore, in Figures 12-49 illustrating the manufacturing of the wafer CM, during the manufacturing process, the upward orientation is described as the positive Z-direction, and the downward orientation as the negative Z-direction. For example, in Figures 12-49, the surface of the wafer CM is described as the upper side (positive Z-direction), and the back side as the lower side (negative Z-direction). In Figures 50-58, the surface and back sides of the wafer CM are reversed, with the surface described as the lower side (negative Z-direction) and the back side as the upper side (positive Z-direction). In Figures 12-49, the positive and negative Z-direction orientations differ from those described with reference to Figures 3-11. In Figures 50-58, the positive and negative Z-direction orientations are the same as those described with reference to Figures 3-11.

[0080] In the manufacturing method described above, an insulating layer 221 of silicon oxide (SiO2) and a semiconductor layer 220 (see FIG50) are formed on a substrate Sub. The substrate Sub may be a semiconductor substrate, such as silicon (Si) containing p-type impurities such as boron (B), or it may be a substrate containing other impurities or materials. The semiconductor layer 220 may be, for example, polycrystalline silicon (p-Si).

[0081] Next, as shown in Figures 12 and 13, multiple insulating layers 103 and 203 and multiple sacrificial layers MLA are alternately formed above the semiconductor layer 220. The sacrificial layers MLA may contain, for example, silicon nitride (SiN). This step is performed, for example, by chemical vapor deposition (CVD).

[0082] Next, as shown in FIG12, an insulating layer 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating layer 115. The opening extends along the Z direction and penetrates the plurality of insulating layers 103, insulating layer 203, and plurality of sacrificial layers MLA stacked along the Z direction, exposing the semiconductor layer 220. This step is performed, for example, by reactive ion etching (RIE). After the opening is formed, the insulating layer 115 is formed within the opening. This step is performed, for example, by CVD.

[0083] Next, as shown in Figures 14 and 15, for example, an opening 104A is formed at a position corresponding to the via wiring 104. As shown in Figures 14 and 15, the opening 104A extends along the Z direction, penetrating the plurality of insulating layers 103, insulating layer 203, and plurality of sacrificial layers MLA stacked along the Z direction, thus exposing the semiconductor layer 220. This step is performed, for example, by means of a RIE (Residual Insulation Layer).

[0084] Next, as shown in Figures 16 and 17, for example, an opening 111A is formed. The opening 111A exposes a portion of the upper and lower surfaces of the insulating layer 103 and the sacrificial layer 203, as well as a portion of the X-direction side surface of the sacrificial layer MLA. In this step, for example, a portion of the sacrificial layer MLA is selectively removed via the opening 104A. This step is performed, for example, by wet etching.

[0085] Next, as shown in Figures 18 and 19, a conductive layer 113' is formed inside opening 111A, and a sacrificial layer 104Sc' is formed inside openings 104A and 111A. In this step, a conductive film such as titanium nitride (TiN) is formed inside openings 104A and 111A. Next, inside opening 104A, a portion of the conductive film (the portion formed on the side of insulating layers 103 and 203) is removed, and the conductive film is cleaved along the Z-direction to form conductive layer 113'. Next, silicon (Si) or the like is embedded in openings 104A and 111A to form sacrificial layer 104Sc'. This step is performed, for example, by CVD and RIE.

[0086] Next, as shown in Figures 20 and 21, openings 101A and 120A are formed at positions corresponding to the insulating layer 101 and the conductive layer 120, respectively. Opening 120A exposes a portion of the upper and lower surfaces of the insulating layer 103 and the X-direction side surface of the conductive layer 113'. In this step, for example, after forming opening 101A, a portion of the sacrificial layer MLA is selectively removed through opening 101A. This step is performed, for example, by RIE and wet etching.

[0087] Next, as shown in Figures 22 and 23, a conductive layer 120 and an insulating layer 101 are formed inside openings 120A and 101A, for example. In this step, a conductive film containing the same material as the conductive layer 120 is formed inside openings 120A and 101A. Next, inside opening 101A, a portion of the conductive film (the portion formed on the side of insulating layers 103 and 203) is removed, and the conductive film is cleaved along the Z direction to form the conductive layer 120. Next, the insulating layer 101 is embedded in opening 101A. This step is performed, for example, by methods such as CVD and RIE.

[0088] Next, as shown in Figures 24 and 25, for example, an opening 102A is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A extends along the Z direction and penetrates the plurality of insulating layers 103, insulating layer 203 and the plurality of sacrificial layers MLA that are stacked along the Z direction, exposing the semiconductor layer 220. This step is performed, for example, by means of a RIE (Residual Insulation Layer).

[0089] Additionally, as shown in Figures 24 and 25, an opening 130A is formed. The opening 130A exposes the insulating layer 103, a portion of the upper surface and a portion of the lower surface of the insulating layer 203, and a portion of the X-direction side surface of the conductive layer 113'. In this step, for example, a portion of the sacrificial layer MLA is selectively removed via the opening 102A. This step is performed, for example, by wet etching.

[0090] Next, as shown in Figures 26 and 27, the insulating layer 103, a portion of the upper surface and a portion of the lower surface of the insulating layer 203, and a portion of the side surface of the conductive layer 113' in the X direction exposed in the opening 130A are removed. This step increases the width of the opening 130A in the Z direction. This step is performed, for example, by wet etching.

[0091] Additionally, as shown in Figures 26 and 27, the sacrificial layer 104Sc' is removed to form openings 104A and 111A. Through this step, openings 102A, 104A, 111A, and 130A are connected. This step is performed, for example, by wet etching.

[0092] Next, as shown in Figures 28 and 29, for example, an insulating layer 112 is formed inside the openings 102A, 104A, 111A, and 130A. This step is performed, for example, by CVD.

[0093] Next, as shown in Figures 30 and 31, for example, a sacrificial layer 111Sc' of silicon nitride (SiN) or titanium nitride (TiN) is formed inside openings 102A, 104A, 111A, and 130A via openings 102A and 104A. In this step, opening 111A is embedded by the sacrificial layer 111Sc', while openings 102A, 104A, and 130A are not embedded by the sacrificial layer 111Sc'. This step is performed, for example, by CVD.

[0094] Next, as shown in Figures 32 and 33, for example, a portion of the sacrificial layer 111Sc' is removed through openings 102A and 104A, and the sacrificial layer 111Sc' is divided along the Z direction to form a sacrificial layer 111Sc of silicon nitride (SiN) or titanium nitride (TiN). This step is performed, for example, by wet etching.

[0095] Next, as shown in Figures 34 and 35, silicon (Si) or similar material is embedded in opening 104A to form a sacrificial layer 104Sc. In this step, silicon (Si) or similar material is embedded in openings 102A and 104A, for example, and then the silicon (Si) or similar material embedded in opening 102A is removed. This step is performed, for example, by CVD, wet etching, or the like.

[0096] Next, as shown in Figures 36 and 37, conductive layers 133 and 133c are formed inside the opening 130A. In this step, a conductive oxide layer, such as indium tin oxide (ITO), is formed inside the openings 102A and 130A. Next, inside the opening 102A, a portion of the conductive oxide layer (the portion formed on the side of the insulating layer 103 and 203) is removed, and the conductive oxide layer is divided along the Z direction to form conductive layers 133 and 133c. This step is performed, for example, by CVD and RIE.

[0097] Next, as shown in Figures 38 and 39, for example, an insulating layer 132' containing the same material as the insulating layer 132 is formed inside the openings 102A and 130A and on the upper surface of the structure shown in Figure 37. This step is performed, for example, by CVD.

[0098] Next, as shown in Figures 40 and 41, for example, a conductive layer 131' containing the same material as conductive layer 131 is formed inside openings 102A and 130A. Then, a conductive layer 102' containing the same material as conductive layer 102 is formed inside opening 102A. In this step, opening 130A is embedded by conductive layer 131', while opening 102A is not embedded by conductive layer 131'. This step is performed, for example, by CVD.

[0099] Next, as shown in Figures 42 and 43, for example, a portion of the conductive layer 102', conductive layer 131', and insulating layer 132' are removed to form conductive layer 131, conductive layer 131c, insulating layer 132, insulating layer 132c, conductive layer 102, and opening 205A. This step is performed, for example, by means of a RIE (Radio Interchange Equipment).

[0100] Next, as shown in Figures 44 and 45, for example, an insulating layer 106 is formed inside the opening 205A and on the upper surface of the structure shown in Figure 43. Then, the portion of the insulating layer 106 located above the sacrificial layer 104Sc is removed to form the opening 106A. The sacrificial layers 104Sc and 111Sc are then removed through the opening 106A to form the openings 104A and 111A. This step is performed, for example, by CVD, RIE, wet etching, etc.

[0101] Next, as shown in Figures 46 and 47, for example, a semiconductor layer 111 is formed inside openings 104A and 111A. Opening 111A is embedded in the semiconductor layer 111. On the other hand, opening 104A is not embedded in the semiconductor layer 111. This step is performed, for example, by atomic layer deposition (ALD).

[0102] Additionally, as shown in Figures 46 and 47, a conductive oxide film 104a' containing the same material as the conductive oxide film 104a is formed inside the opening 104A. In this step, the opening 104A is not embedded by the conductive oxide film 104a'. This step is performed, for example, by a method such as CVD.

[0103] Next, as shown in Figures 48 and 49, for example, an insulating layer 107 of silicon oxide (SiO2) or the like is formed on the upper surface of the structure shown in Figure 47, and an internal region CAV' is formed inside the through-hole wiring 104. Furthermore, openings are formed by removing portions corresponding to the contact GBLC1 from the insulating layers 106 and 107, and conductive films 206 and 207 are formed within these openings. This step is performed, for example, by methods such as RIE or CVD.

[0104] Next, a wiring layer M0 including a global bit line GBL and multiple wiring lines m0, a wiring layer M1 including multiple wiring lines m1, and multiple first bonding electrodes PI1 are formed on the upper surface of the structure shown in Figure 49.

[0105] Next, as shown in Figures 50 and 51, the wafer of the chip CM, which includes the memory cell array MCA formed in the above steps, is flipped so that the substrate Sub is on top and the global bit line GBL is on the bottom, so that the surface of the wafer including the chip CM faces the surface of the wafer including the chip CP (Figure 50), and is bonded via the first bonding electrode PI1 and the second bonding electrode PI2 (Figure 51). Furthermore, hydrogen (H) and the like may be generated during the forming steps of these bonding electrodes (Figure 49) or the bonding steps (Figures 50 and 51).

[0106] Next, as shown in Figure 51, the substrate Sub and insulating layer 221 are removed. This step is performed, for example, by grinding, chemical mechanical polishing (CMP), wet etching, etc.

[0107] Next, as shown in FIG52, the semiconductor layer 220 is removed, and an insulating layer 210' containing the same material as the insulating layer 210 is formed on the upper surface of the structure. This step is performed, for example, by CVD.

[0108] Next, as shown in Figure 53, a portion of the insulating layer 210' above the bit line BL and the upper end of the bit line BL are removed, making the upper part of the inner region CAV' open. This step is performed, for example, by means of a RIE (Residual Insulation Layer).

[0109] Next, as shown in Figures 53 and 54, annealing is performed in an oxygen (O2) atmosphere. In this step, a relatively large amount of oxygen (O2) diffuses into the inner region CAV' through the opening at the top of the inner region CAV'. Therefore, oxygen (O2) diffuses through the conductive oxide film 104a containing oxide material into the plurality of semiconductor layers 111 arranged along the Z direction, repairing excessive oxygen defects present in the plurality of semiconductor layers 111. Furthermore, in this step, as shown in Figure 53, the board line PL and the contact CC are covered by the insulating layer 210', therefore, oxidation of these is not performed.

[0110] Next, as shown in FIG55, an insulating layer 211' containing the same material as the insulating layer 211 is formed. This step is performed, for example, by CVD.

[0111] Next, as shown in Figure 56, a portion of insulating layer 211' and insulating layer 210' is removed to form insulating layer 210, insulating layer 211, opening PM10aA, and opening PM20aA. The upper end of the board line PL is exposed at opening PM10aA. The upper end of the contact CC is exposed at opening PM20aA. This step is performed, for example, by means of a RIE (Residual Insulator).

[0112] Next, as shown in FIG57, the same material as conductive layer PM10 and conductive layer PM20 and the same material as insulating layer 212 are formed on the upper surface of the structure shown in FIG56. The conductive layer PM10, conductive layer PM20 and insulating layer 212 are formed by photolithography or the like. This step is performed, for example, by CVD, wet etching or the like.

[0113] Next, as shown in FIG58, the same material as the insulating layer 213 is formed on the upper surface of the structure shown in FIG57, and the portion corresponding to the external pad electrode PX is removed, forming the insulating layer 213 and the opening P XA. A portion of the upper surface of the conductive layer PM20 is exposed at the opening P XA. This step is performed, for example, by CVD, RIE, etc.

[0114] Next, the same material as conductive layers MA10 and MA20 is formed on the upper surface of the structure shown in Figure 58, and patterned by photolithography to form conductive layers MA10 and MA20. This step is performed, for example, by CVD or wet etching.

[0115] This forms the structure illustrated in Figures 1 to 11.

[0116] [Effect] In transistors with oxide semiconductors as channels, oxygen defects in the oxide semiconductor (semiconductor layer 111) can sometimes increase due to hydrogen (H) and other substances generated during the manufacturing process after transistor formation, which can degrade the characteristics of the transistor.

[0117] In the semiconductor memory device of this embodiment, oxygen defects in the oxide semiconductor (semiconductor layer 111) included in the transistors TrC and TrB sometimes increase due to hydrogen (H) generated, for example, in the electrode formation step (FIG. 49) or bonding step (FIG. 50, FIG. 51) after the transistors TrC and TrB are formed.

[0118] However, the semiconductor memory device of this embodiment includes an internal region CAV. Therefore, as shown in Figures 53 and 54, after the bonding step, for example, oxygen annealing can be performed on the entire semiconductor layer 111, which is stacked for several μm in length, from the upper end (oxygen introduction portion) of the via wiring 104 (bit line BL) to the lower end via the internal region CAV, to uniformly supply oxygen. Therefore, the semiconductor memory device of this embodiment can produce stacked transistors TrC and TrB with good and homogeneous characteristics.

[0119] Furthermore, the semiconductor memory device of this embodiment includes a conductive layer PM10 (FIG. 3) covering the upper end of the via wiring 104 (bit line BL). Through the conductive layer PM10, after its formation (FIG. 57 onwards), the diffusion of hydrogen (H) and other ions from the top of the conductive layer PM10 towards the transistors TrC and TrB can be prevented. Therefore, the degradation of the characteristics of the transistors TrC and TrB can be suppressed.

[0120] [Modification 1 of the First Embodiment] Next, referring to FIGS. 59 and 60, a modification 1 of the semiconductor memory device according to the first embodiment will be described. FIGS. 59 and 60 are schematic cross-sectional views showing a portion of the structure of the semiconductor memory device of this modification. FIG. 60 shows a cross-section taken along line D1-D1' of the structure shown in FIG. 59 and viewed in the direction of the arrow.

[0121] The semiconductor memory device of this modified example (Figures 59 and 60) is basically constructed in the same way as the semiconductor memory device of the first embodiment (Figures 6 and 7). However, the semiconductor memory device of this modified example does not provide through-hole wiring 104, but instead provides through-hole wiring 104_2.

[0122] The via wiring 104_2 is basically constructed in the same way as the via wiring 104 (Figures 6 and 7). However, the via wiring 104_2 includes, for example, a conductive layer 104b between the conductive oxide film 104a and the internal region CAV.

[0123] The conductive layer 104b has, for example, a generally cylindrical shape extending along the Z direction. The outer peripheral surface of the conductive layer 104b is in contact with the inner peripheral surface of the conductive oxide film 104a. The conductive layer 104b contains, for example, a conductive oxide such as ruthenium oxide (RuO2) with a lower resistivity than the conductive oxide film 104a.

[0124] This structure enables the provision of a semiconductor memory device with further reduced resistance of bit line BL and higher speed.

[0125] [Modification 2 of the First Embodiment] Next, referring to FIG61, a modification 2 of the semiconductor memory device of the first embodiment will be described. FIG61 is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device of this modification.

[0126] The semiconductor memory device of this modified example (FIG. 61) is basically constructed in the same way as the semiconductor memory device of the first embodiment (FIG. 7). However, in this modified example, the semiconductor memory device (FIG. 61) does not have semiconductor layer 111, but instead has semiconductor layer 111_2.

[0127] Semiconductor layer 111_2 is constructed in essentially the same way as semiconductor layer 111 (Fig. 7). However, semiconductor layer 111_2 is formed by dividing each memory layer ML along the Z direction.

[0128] [Second Implementation] Figure 62 is a schematic circuit diagram showing the structure of the semiconductor memory device according to the second embodiment. Figures 63 and 64 are schematic cross-sectional views showing a portion of the structure of the semiconductor memory device according to this embodiment. In the following description, the same symbols are used for the same parts as in the first embodiment, and the descriptions are omitted.

[0129] The semiconductor memory device of the second embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment includes multiple transistor layers TL (Figs. 62-64). In addition, the semiconductor memory device of the second embodiment includes a contact GBLC2 and a plug 150 (Fig. 64) instead of a contact GBLC1 (Fig. 9). Furthermore, as the structure for realizing the electrode Cn1, an electrode structure 130c2 (Fig. 64) is included instead of an electrode structure 130c (Fig. 9).

[0130] For example, as shown in Figure 62, in a plurality of transistors TrB, one electrode of which is connected to the same bit line BL, the other electrode of which is connected to the same global bit line GBL via electrode Cn1. These plurality of transistors TrB are connected in parallel between bit line BL and global bit line GBL.

[0131] Contact GBLC2 (Fig. 64) extends along the Z direction. The upper part of contact GBLC2 is connected to a plurality of electrode structures 130c2 arranged along the Z direction. Contact GBLC2 is connected to plug 150 on its lower surface. Contact GBLC2 functions, for example, as an electrode that connects a plurality of transistors TrB to the global bit line GBL via electrode Cn1.

[0132] The electrode structure 130c2 and the contact GBLC2 include an integrally formed conductive layer 131d, an insulating layer 132d, and a conductive layer 133d.

[0133] The conductive layer 131d is integrally disposed inside the electrode structure 130c2 and inside the contact GBLC2. The conductive layer 131d contains the same material as the conductive layer 131c.

[0134] An insulating layer 132d is integrally disposed inside the electrode structure 130c2 and the contact GBLC2. The insulating layer 132d covers the outer peripheral surface of the conductive layer 131d. The insulating layer 132d contains the same material as the insulating layer 132c.

[0135] A conductive layer 133d is integrally disposed inside the electrode structure 130c2 and inside the contact GBLC2. The conductive layer 133d covers the outer peripheral surface of the insulating layer 132d. In the electrode structure 130c2 of each transistor layer TL, the conductive layer 133d is connected to the X-direction side surface of the semiconductor layer 111 of each transistor layer TL. The conductive layer 133d is connected to the plug 150 on the lower surface portion of the contact GBLC2. The conductive layer 133d contains the same material as the conductive layer 133c.

[0136] The plug 150 extends along the Z direction, for example, through an insulating layer 141 such as silicon nitride (SiN) and an insulating layer 143 such as silicon oxide (SiO2), and is connected to the global bit line GBL on its lower surface. The plug 150 may, for example, include a multilayer structure of titanium nitride (TiN) and tungsten (W).

[0137] [Manufacturing Method] Figures 65 to 80 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the second embodiment.

[0138] Figures 65, 67, 69, 71, and 73 show the XY cross-sections corresponding to the memory layer ML and the transistor layer TL.

[0139] Figures 66, 68, 70, 72, and 74-80 show the XZ cross-sections corresponding to a portion of the memory layer ML and the transistor layer TL.

[0140] Furthermore, in Figures 65-80 illustrating the manufacturing of the wafer CM, during the manufacturing process, the upward orientation is described as the positive Z-direction, and the downward orientation as the negative Z-direction. For example, in Figures 65-80, the surface of the wafer CM is described as the upper side (positive Z-direction), and the back side is described as the lower side (negative Z-direction). After the steps described with reference to Figure 50, the surface and back sides of the wafer CM are reversed, and the surface of the wafer CM is described as the lower side (negative Z-direction), and the back side is described as the upper side (positive Z-direction). In Figures 65-80, the positive and negative Z-direction orientations differ from those described with reference to Figures 63 and 64.

[0141] In the manufacturing method, the same steps as those shown in Figures 12-21 are performed. However, unlike Figures 12-21, multiple sacrificial layers MLA are formed above the insulating layer 203.

[0142] Next, as shown in Figures 65 and 66, a conductive layer 120 is formed inside the opening 120A. This step is performed in the same manner as shown in Figures 22 and 23. Additionally, an insulating layer 101_2, such as silicon oxide (SiO2), is formed inside the opening 101A and on the upper surface of the structure shown in Figure 21. This step is performed, for example, by a method such as CVD.

[0143] Next, as shown in Figures 67 and 68, for example, an opening 102A_2 is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A_2 extends along the Z direction and penetrates the insulating layer 101_2, multiple insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked along the Z direction. This step is performed, for example, by means of a RIE (Reinforcing Interchange).

[0144] Next, as shown in Figures 67 and 68, for example, a portion of the sacrificial layer MLA is selectively removed through opening 102A_2, similar to the steps shown in Figures 24 and 25, to form opening 130A. This step is performed, for example, by wet etching.

[0145] Next, as shown in Figures 69 and 70, for example, a portion of the upper and lower surfaces of insulating layers 103 and 203, and a portion of the X-direction side surface of conductive layer 113' exposed in opening 130A are removed. This step increases the width of opening 130A in the Z direction. This step is performed, for example, by wet etching. Furthermore, the sacrificial layer 104Sc' is removed through openings 102A_2 and 130A to form openings 104A and 111A. This step connects openings 102A_2, 104A, 111A, and 130A. This step is performed, for example, by wet etching.

[0146] Next, as shown in Figures 71 and 72, for example, an insulating layer 112 is formed inside the openings 102A_2, 104A, 111A, and 130A via the opening 102A_2. This step is performed, for example, by CVD.

[0147] Next, as shown in Figures 73 and 74, for example, a sacrificial layer of silicon nitride (SiN) or titanium nitride (TiN) is formed inside openings 102A_2, 104A, 111A, and 130A through opening 102A_2. A portion of the sacrificial layer formed in openings 102A_2 and 130A is then removed through opening 102A_2, forming a sacrificial layer 111Sc2. In this step, opening 111A is embedded by the sacrificial layer 111Sc2, while openings 102A_2, 104A, and 130A are not embedded by the sacrificial layer 111Sc2. This step is performed, for example, by CVD.

[0148] Next, as shown in FIG75, for example, an opening GBLLC2A is formed at a position corresponding to the contact GBLC2. The opening GBLLC2A extends along the Z direction, penetrating the insulating layer 101_2 and the plurality of insulating layers 103 above the insulating layer 203. Through this step, the opening GBLLC2A communicates with the opening 130A above the insulating layer 203. This step is performed, for example, by means of a RIE (Residual Insulation Equipment).

[0149] Next, as shown in FIG76, for example, a sacrificial layer 102_2Sc' of silicon (Si) or the like is formed inside the openings 102A_2, GBL_C2A, and 130A. This step is performed, for example, by CVD.

[0150] Next, as shown in Figure 77, a film of the same material as insulating layers 141 and 142 is formed on the upper surface of insulating layer 101_2 and sacrificial layer 102_2Sc'. The portion corresponding to the upper part of conductive layer 102 is removed to form insulating layer 141 and insulating layer 142. Furthermore, sacrificial layer 102_2Sc' is removed to form opening 102A_2, opening GBL_C2A, and opening 130A. This step is performed, for example, by CVD, RIE, wet etching, etc.

[0151] Next, as shown in FIG78, conductive layers 133 and 133d are formed inside openings 130A and GBL C2A, for example. In this step, a conductive oxide layer such as indium tin oxide (ITO) is formed inside openings 102A_2, 130A, and GBL C2A, for example. Next, a portion of the conductive oxide layer (the portion formed on the side of insulating layers 103 and 203) is removed inside opening 102A_2, and the conductive oxide layer is divided along the Z direction to form conductive layers 133 and 133d. This step is performed, for example, by CVD and RIE.

[0152] Next, as shown in Figure 79, insulating layers 132 and 132d, and conductive layers 131 and 131d are formed inside openings 102A_2, 130A, and GBLLC2A, respectively. The same material as conductive layer 102 is formed inside opening 102A_2. Unnecessary portions are removed, resulting in a capacitor structure 130, electrode structure 130c2, contact GBLC2, and conductive layer 102 (PL). This step is performed, for example, by CVD or RIE.

[0153] Next, as shown in FIG80, an insulating layer 106 is formed in the opening 102A_2. Then, after removing the insulating layer 101_2 and the portion above the opening 104A in the insulating layer 141, and removing the sacrificial layer 111Sc2 through the opening 104A, a semiconductor layer 111 is formed. Furthermore, a conductive oxide film 104a' containing the same material as the conductive oxide film 104a and an internal region CAV' are formed inside the opening 104A. In this step, the opening 104A is not buried by the conductive oxide film 104a'. This step is performed, for example, by methods such as CVD or CMP.

[0154] Next, an insulating layer 143 (Fig. 64) is formed on the upper surface of the structure shown in FIG. 80. The upper portion of the contact GBLC2 in the insulating layer 141 and the insulating layer 143 is removed, and a plug 150 is formed in the removed portion. In addition, a wiring layer M0 including a global bit line GBL and multiple wiring lines m0, a wiring layer M1 including multiple wiring lines m1, and multiple first bonding electrodes PI1 are formed above the insulating layer 143 and the plug 150.

[0155] Next, for example, the same steps as those described with reference to Figures 50-58 are performed to form the structure described with reference to Figures 63 and 64.

[0156] [Effect] In this embodiment, by using an integral film structure to form the contact GBLC2 and multiple electrode structures 130c2, the contact GBLC2 and electrode structures 130c2 can be manufactured efficiently, which can help reduce the manufacturing cost of semiconductor memory devices. In addition, it is possible to provide a high-speed semiconductor memory device that connects the contact GBLC2 and multiple electrode structures 130c2 with low resistance.

[0157] [Modifications of the Second Embodiment] Next, referring to FIG81A, a modified example of the semiconductor memory device of the second embodiment will be described. FIG81A is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device of this modified example.

[0158] The semiconductor memory device of this modified example (FIG. 81A) is basically constructed in the same way as the semiconductor memory device of the second embodiment (FIG. 64). However, the semiconductor memory device of this modified example includes a contact GBLC3 instead of a contact GBLC2, and no plug 150 is provided. In addition, in the semiconductor memory device of this modified example, the portion of the semiconductor layer 111 and the conductive oxide film 104a that is closer to the global bit line GBL than the transistor layer TL is removed, and an insulating layer 101_3 of silicon oxide (SiO2) or the like is provided in the removed portion.

[0159] Contact GBLC3 (Fig. 81A) is constructed in essentially the same way as contact GBLC2 (Fig. 64). However, the conductive layer 133d included in contact GBLC3 is directly connected to the global bit line GBL on its lower surface.

[0160] [Manufacturing Method] Figure 81B is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device of this modified example.

[0161] The semiconductor memory device of this modified example (FIG. 81A) is manufactured in essentially the same manner as the semiconductor memory device of the second embodiment. However, in the manufacture of the semiconductor memory device of this modified example, after the step corresponding to FIG. 80, as shown in FIG. 81B, the portion of the semiconductor layer 111 and the conductive oxide film 104a' closer to the global bit line GBL than the transistor layer TL is removed. This step is performed, for example, by means of RIE (Residual Insulation Electrode).

[0162] Next, an insulating layer 101_3 is formed on the portion removed in the step shown in FIG81B by CVD or the like. In addition, after removing a portion of the insulating layer 141, insulating layer 101_3, and insulating layer 106 on the upper surface of the structure shown in FIG81B, exposing the conductive layer 133d included in the contact GBLC3, a wiring layer M0 including global bit lines GBL, multiple wiring lines m0, a wiring layer M1 including multiple wiring lines m1, and multiple first bonding electrodes PI1 are formed.

[0163] Next, for example, the same steps as those described with reference to Figures 50 to 58 are performed to form the structure described with reference to Figure 81A.

[0164] [Third Implementation Method] Figures 82-84 are schematic cross-sectional views showing a portion of the structure of the semiconductor memory device according to the third embodiment. Figure 82 is a schematic cross-sectional view showing a portion of the structure of the memory layer ML. Figure 83 is a schematic cross-sectional view showing a portion of the structure of the memory layer ML, enlarged to show a portion of Figure 82. Figure 84 shows a cross-section taken along line A3-A3', showing the structure shown in Figure 83 and viewed in the direction of the arrow. In the following description, the same symbols are used for the same parts as in the first embodiment, and the descriptions are omitted.

[0165] The semiconductor memory device of the third embodiment is basically constructed in the same way as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the third embodiment does not have a conductive layer 120 and an insulating layer 101 (FIG. 5), but instead includes a conductive layer 120_3 (FIG. 82).

[0166] The conductive layer 120_3 (Figs. 83 and 84) is constructed in essentially the same manner as the conductive layer 120 (Figs. 6 and 7). However, for example, as shown in Fig. 83, the conductive layer 120_3 functions as a word line WL (Fig. 2) in the memory layer ML, corresponding to the transistors TrC located on both sides of the conductive layer 120_3 in the X direction. The conductive layer 120_3 functions, for example, as a bit line selection line LB (Fig. 2) in the transistor layer TL, corresponding to the transistors TrB located on both sides of the conductive layer 120_3 in the X direction. The side surfaces of the conductive layer 120_3 on both sides of the X direction are connected to the conductive layers 113 located on both sides of the X direction. The conductive layer 120_3 includes, for example, a barrier conductive film 121_3 of titanium nitride (TiN) and the like, and a conductive film 122_3 of tungsten (W).

[0167] The barrier conductive film 121_3 (Fig. 84) is basically constructed in the same way as the barrier conductive film 121 (Fig. 7). However, unlike the barrier conductive film 121, the barrier conductive film 121_3 is not disposed on one side of the conductive layer 113 in the X direction (the side of the conductive layer 120_3).

[0168] [Manufacturing Method] Figures 85 to 104 are schematic cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the third embodiment.

[0169] Figures 85, 87, 89, 91, 93, 95, 97, 99, 101, and 103 show the XY cross-sections corresponding to Figure 83.

[0170] Figures 86, 88, 90, 92, 94, 100, 102, and 104 show the XZ cross-sections corresponding to a portion of the memory layer ML and the transistor layer TL.

[0171] Furthermore, in Figures 85 to 104, during the manufacturing process, the orientation that will become the upper direction is described as the positive side of the Z direction, and the orientation that will become the lower direction is described as the negative side of the Z direction.

[0172] In the manufacturing method described herein, for example as shown in Figures 85 and 86, a plurality of insulating layers 103 and 203 and a plurality of sacrificial layers MLA are alternately formed over a substrate Sub (not shown). This step is performed, for example, by CVD.

[0173] Next, as shown in Figures 85 and 86, for example, an insulating layer 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating layer 115. The opening extends along the Z direction and penetrates the plurality of insulating layers 103, insulating layer 203, and plurality of sacrificial layers MLA that are stacked along the Z direction. This step is performed, for example, by RIE (Reinforcing Interchange). After the opening is formed, the insulating layer 115 is formed. This step is performed, for example, by CVD (Continuous Chemical Deposition).

[0174] Next, as shown in Figures 87 and 88, for example, an opening 102A_3 is formed at a position corresponding to the conductive layer 102 and the insulating layer 106. The opening 102A_3 extends along the Z direction and penetrates the plurality of insulating layers 103 and 203 and the plurality of sacrificial layers MLA that are stacked along the Z direction. This step is performed, for example, by means of a RIE (Reinforcing Interchange).

[0175] Next, as shown in Figures 89 and 90, for example, an opening 130A_3 is formed through an opening 102A_3. A portion of the upper surface and a portion of the lower surface of the insulating layer 103 and the insulating layer 203 are exposed through the opening 130A_3. In this step, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 102A_3. This step is performed, for example, by wet etching.

[0176] Next, as shown in Figures 91 and 92, silicon (Si) or the like is embedded inside the openings 102A_3 and 130A_3 to form a sacrificial layer 102Sc'_3. This step is performed, for example, by CVD.

[0177] Next, as shown in Figures 91 and 92, for example, an opening 104A_3 is formed. The opening 104A_3 extends along the Z direction and penetrates the plurality of insulating layers 103, insulating layer 203, and multiple sacrificial layers MLA that are stacked along the Z direction. This step is performed, for example, by means of a RIE (Residual Insulation Layer).

[0178] Next, as shown in Figures 93 and 94, the sacrificial layer MLA is selectively removed through opening 104A_3 to form opening 111A_3. This step is performed, for example, by wet etching.

[0179] Next, as shown in Figures 95 and 96, a barrier conductive film 121_3' containing the same material as the barrier conductive film 121_3 and a conductive film 122_3' containing the same material as the conductive film 122_3 are formed inside the opening 104A_3 and the opening 111A_3, respectively. In this step, the opening 111A_3 is embedded by the barrier conductive film 121_3' and the conductive film 122_3', while the opening 104A_3 is not embedded by the barrier conductive film 121_3' and the conductive film 122_3'. This step is performed, for example, by CVD.

[0180] Next, as shown in Figures 97 and 98, for example, a portion of the barrier conductive film 121_3' and the conductive film 122_3' are removed through the opening 104A_3, and the barrier conductive film 121_3 and the conductive film 122_3 are formed in a portion inside the opening 111A_3. This step is performed, for example, by CVD.

[0181] Next, as shown in Figures 99 and 100, a conductive layer 113' is formed inside the opening 111A_3. In this step, a conductive film such as titanium nitride (TiN) is formed inside the openings 104A_3 and 111A_3, for example. Next, inside the opening 104A_3, a portion of the conductive film (the portion formed on the side of the insulating layer 103 and the insulating layer 203) is removed, and the conductive film is cleaved along the Z direction to form the conductive layer 113'. This step is performed, for example, by CVD and RIE.

[0182] Next, as shown in Figures 101 and 102, the sacrificial layer 102Sc'_3 is removed to form openings 102A_3 and 130A_3. Furthermore, the insulating layer 103 exposed in opening 130A_3, a portion of the upper and lower surfaces of the insulating layer 203, and a portion of the X-direction side surface of the conductive layer 113' are removed to form a conductive layer 113. This step increases the width of opening 130A_3 in the Z-direction. This step is performed, for example, by wet etching.

[0183] Next, as shown in Figures 103 and 104, for example, an insulating layer 112 is formed inside the openings 102A_3, 104A_3, 111A_3, and 130A_3. This step is performed, for example, by CVD.

[0184] Next, in the same manner as shown in Figures 30 to 49, a capacitor structure 130 or an electrode structure 130c is formed inside the opening 130A_3, a conductive layer 102 (PL) is formed inside the opening 102A_3, a transistor structure 110 is formed inside the opening 111A_3, a through-hole wiring 104 is formed inside the opening 104A_3, and a contact GBLC1 connected to the electrode structure 130c is formed.

[0185] Next, for example, the same steps as those shown in Figures 50 to 58 are performed to form the structure described with reference to Figures 82 to 84.

[0186] [Effect] The semiconductor memory device of this embodiment (FIG. 82) does not require an insulating layer 101 compared to the semiconductor memory device of the first embodiment (FIG. 5). Therefore, it is possible to achieve high density in the semiconductor memory device. In addition, by eliminating the step of forming the insulating layer 101, the number of steps can be reduced, which can help reduce the manufacturing cost of the semiconductor memory device.

[0187] [Other Implementation Methods] The semiconductor memory devices according to the first to third embodiments have been described above. However, these semiconductor memory devices are merely examples, and the specific structure, etc., can be appropriately adjusted.

[0188] For example, in the semiconductor memory devices of the second and third embodiments, examples are shown where the through-hole wiring 104 (BL) includes an internal region CAV. However, in the second and third embodiments, the through-hole wiring 104 (BL) may include a conductive component instead of the internal region CAV. The conductive component may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), etc.

[0189] For example, in the semiconductor memory device of the second embodiment, two transistor layers TL arranged along the Z direction are illustrated. However, three or more transistor layers TL may also be arranged along the Z direction. The three or more transistors TrB disposed on these three or more transistor layers TL may also be connected in parallel between the via wiring 104 (BL) and the global bit line GBL.

[0190] Furthermore, the above description illustrates an example of using a capacitor CpC as the memory unit connected to the transistor structure 110. However, the memory unit may not necessarily be a capacitor CpC. For example, the memory unit may be a memory containing a strong dielectric, a strong magnetic material, a chalcogenide material such as GeSbTe, or other materials, and utilizing the properties of these materials to record data. For example, in any of the structures described above, any of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[0191] Furthermore, the manufacturing methods of the semiconductor memory devices according to the first to third embodiments can also be adapted. For example, the order of any two of the steps can be changed, or any two of the steps can be performed simultaneously.

[0192] [other] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0193] 101, 101_2, 101_3, 103, 106, 107, 112, 115, 132, 132', 132c, 132d, 141, 142, 143, 203, 210, 210', 211, 211', 212, 213, 221: Insulation layer 101A, 102A, 102A_2, 102A_3, 104A, 104A_3, 106A, 111A, 111A_3, 120A, 130A, 130A_3, 205A, GBLC2A, PM10aA, PM20aA, P XA: Opening 102, 102', 104b, 113, 113', 120, 120_3, 131, 131', 131c, 131d, 133, 133c, 133d, MA10, MA20, PM10, PM20: Conductive layer 102_2Sc', 102Sc'_3, 104Sc, 104Sc': Sacrificial layer 104, 104_2: Through-hole wiring 104a, 104a': Conductive oxide film 110: Transistor Structure 111, 111_2, 220: Semiconductor layer 121, 121_3, 121_3', 122, 122_3, 122_3', 206: Conductive film 130: Capacitor Structure 130C, 130C2: Electrode Structure 150: Plug 207: Insulating film a1, a2, a3, a4, b1, b2, b3, b4: Corners BL: Bitline CAV, CAV': Internal region CC, GBLC1, GBLC2, GBLC3: Contacts CM, CP: Chip Cn1: Electrode CpC: Capacitor GBL: Global Bitline LB, LB0, LB1, LB2: Bit line selection lines LLa, LLb: Layer selection lines LW, LW0a, LW0b, LW1a, LW1b, LW2a, LW2b: Character line selection lines M0, M1: Wiring layer m0, m1: Wiring MC: Memory Cell MCA: Memory Cell Array MD: Memory chip ML: Memory Layer P I1: First bonding electrode P I2: Second bonding electrode PL: Board Line PM10a, PM10b, PM20a: Partial PT10: Upper end PX: External solder pad electrode R MCA, R PC: Region Sub, Sub2: Substrate TL: Transistor layer Tr, TrB, TrC, TrL, TrLa, TrLb: Transistors WL, WL0, WL1, WL2: Character lines X, Y, Z: Direction

Claims

1. A semiconductor memory device, comprising: Multiple memory layers are arranged along the first direction; Through-hole wiring extends along the first direction; The first wiring is disposed on one side of the first direction relative to the plurality of memory layers and extends along a second direction that intersects the first direction; The system includes an insulating layer disposed on the opposite side of the first direction relative to the plurality of memory layers and covering the end of the via wiring. The plurality of memory layers each include: a semiconductor layer electrically connected to the via wiring; a gate electrode facing the semiconductor layer; a second wiring extending along a third direction intersecting the first and second directions and electrically connected to the gate electrode; and a memory portion disposed on the opposite side of the second wiring in the second direction relative to the semiconductor layer and electrically connected to the semiconductor layer. The via wiring includes: a conductive member extending along the first direction; and an internal region extending along the first direction with its outer peripheral surface surrounded by the conductive member. The end of the internal region on the insulating layer side in the first direction is not covered by the conductive member, but is covered by the insulating layer or continuous with the insulating layer, and the internal region includes a cavity.

2. The semiconductor memory device as claimed in claim 1, wherein, The internal region is in contact with the insulating layer.

3. The semiconductor memory device as claimed in claim 1, wherein, The internal region contains silicon oxide or silicon nitride.

4. The semiconductor memory device as claimed in claim 1, wherein, The conductive component includes a first oxide conductive layer extending along the first direction and a second oxide conductive layer extending along the first direction, wherein the second oxide conductive layer is disposed between the first oxide conductive layer and the internal region.

5. The semiconductor memory device as claimed in claim 1, wherein, The plurality of memory layers include: a first memory layer disposed in the first direction at a position closest to the first wiring; and a second memory layer disposed in the first direction at a position farthest from the first wiring, wherein the internal region extends along the first direction from the first memory layer to the second memory layer.

6. The semiconductor memory device as claimed in claim 1, comprising: The board wiring extends along the first direction and is electrically connected to the plurality of memory units; A conductive layer is disposed on the insulating layer side in the first direction relative to the plurality of memory layers, and is disposed at a position that overlaps with the via wiring when viewed from the first direction, wherein the board wiring is electrically connected to the conductive layer.

7. The semiconductor memory device of claim 1, comprising a first wafer and a second wafer interconnected, the first wafer comprising: The multiple memory layers; The through-hole wiring; First wiring; The second wafer includes: a substrate; a plurality of transistors disposed on the surface of the substrate; and a plurality of second bonding electrodes electrically connected to the plurality of transistors, wherein the plurality of first bonding electrodes are connected to the plurality of second bonding electrodes.

8. The semiconductor memory device as claimed in claim 1, wherein, The gate electrode faces one side and the other side of the semiconductor layer in the first direction, and faces one side and the other side of the semiconductor layer in the third direction.

9. The semiconductor memory device as claimed in claim 1, wherein, The semiconductor layer contains at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

10. A semiconductor memory device, comprising: Multiple memory layers are arranged along a first direction; a first wiring is disposed on one side of the first direction relative to the multiple memory layers and extends along a second direction intersecting the first direction; multiple select transistor layers are disposed between the multiple memory layers and the first wiring and are arranged along the first direction; a via wiring extends along the first direction within the range corresponding to the multiple memory layers and the multiple select transistor layers. The plurality of memory layers include a contact electrode extending along the first direction within a range corresponding to the plurality of selective transistor layers. Each of the plurality of memory layers includes: a first semiconductor layer electrically connected to the via wiring; a first gate electrode facing the first semiconductor layer; a second wiring extending along a third direction intersecting the first and second directions and electrically connected to the first gate electrode; and a memory portion disposed in the second direction opposite to the second wiring and electrically connected to the first semiconductor layer, relative to the first semiconductor layer. Each of the plurality of selective transistor layers includes: a second semiconductor layer electrically connected to the via wiring; a second gate electrode facing the second semiconductor layer; a third wiring extending along the third direction and electrically connected to the second gate electrode; and a connection electrode disposed in the second direction opposite to the third wiring and electrically connected to both the second semiconductor layer and the first wiring, relative to the second semiconductor layer. The contact electrode is continuous with the plurality of connection electrodes included in the plurality of selective transistor layers. The contact electrode and the plurality of connection electrodes include an integrally formed oxide conductive layer.

11. The semiconductor memory device as claimed in claim 10, wherein, A portion of the oxide conductive layer included in the contact electrode is connected to the first wiring, and a portion of the oxide conductive layer included in the connection electrode is connected to the second semiconductor layer.

12. The semiconductor memory device as claimed in claim 10, wherein, The through-hole wiring includes a first surface on the side of the first wiring in the first direction, and the contact electrode includes a second surface on the side of the first wiring in the first direction, wherein the position of the second surface in the first direction is closer to the first wiring than the position of the first surface in the first direction.

13. The semiconductor memory device as claimed in claim 10, wherein, The through-hole wiring includes a first surface on the side of the first wiring in the first direction, and the contact electrode includes a second surface on the side of the first wiring in the first direction, wherein the position of the second surface in the first direction is further away from the first wiring than the position of the first surface in the first direction.

14. The semiconductor memory device as claimed in claim 10, wherein, The first semiconductor layer and the second semiconductor layer contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O).

15. A semiconductor memory device, comprising: Multiple memory layers are arranged along the first direction; The first through-hole wiring extends along the first direction; The plurality of memory layers each include: a wiring disposed between the first and second via wirings and extending along a third direction intersecting the first and second directions; a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing the first semiconductor layer and electrically connected to the wiring; a first memory portion disposed in the second direction opposite to the wiring and electrically connected to the first semiconductor layer; a second semiconductor layer electrically connected to the second via wiring; a second gate electrode facing the second semiconductor layer and electrically connected to the wiring; and a second memory portion disposed in the second direction opposite to the wiring and electrically connected to the second semiconductor layer, wherein no through-hole extending along the first direction is provided in the wiring.

16. The semiconductor memory device as claimed in claim 15, wherein, The first semiconductor layer and the second semiconductor layer contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O).

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