Display device

Abstract

A display device includes a substrate, comprising an active region and a non-active region; and power supply voltage lines and a gate driver disposed on the non-active region of the substrate and adjacent to each other, wherein the gate driver comprises: a first type transistor comprising a first active layer on the substrate, a first gate insulating film located on the first active layer, and a first gate electrode overlapping the first active layer and located on the first gate insulating film; a second type transistor comprising a second active layer located further away from the substrate than the first gate electrode, a second gate insulating film located on the second active layer, and a second gate electrode overlapping the second active layer and located on the second gate insulating film; and a first electrode pattern overlapping the first gate electrode and located on the second gate insulating film.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device that prevents hydrogen diffusion within the device and improves transistor driving reliability by using a structural configuration that separates the gate driver from the peripheral portion. Prior Technology

[0002] Various methods and forms have been applied to display devices to display images on devices such as televisions, monitors, smartphones, tablets, and laptops.

[0003] The display device contains multiple pixels to realize images and has transistors to control the operation of each pixel.

[0004] The display device includes a driving circuit and wires connected to transistors for applying various signals to drive multiple pixels.

[0005] The transistors in a display device can have different layer structures depending on the application.

[0006] Transistors consist of multiple electrodes and an insulating film. The hydrogen content in the insulating film may affect the active layer. Research has been conducted to address this issue. Summary of the Invention

[0007] Therefore, this disclosure aims to provide a display device that substantially overcomes the problems caused by one or more limitations and disadvantages in the related art.

[0008] By including a first type of transistor close to the substrate and a second type of transistor further away from the substrate than the first type of transistor, and including at least one electrode pattern on the first type of transistor, one technical challenge of the disclosed embodiments is to capture hydrogen from the adjacent insulating film through the electrode pattern and prevent hydrogen from diffusing to the active layer of the adjacent second type of transistor.

[0009] A technical challenge of the display device disclosed herein is that, by using a first type transistor comprising a first active layer having polysilicon and a second type transistor comprising a second active layer having oxide semiconductor, and in a region where the arrangement density of the second type transistor is greater than that of the first type transistor, a plurality of electrode patterns overlapping with the first gate electrode of the first type transistor are provided, the electrode patterns being located in the upper and lower layers of the second active layer to prevent hydrogen from being horizontally transported to the second active layer.

[0010] In the display device of this disclosed embodiment, in order to prevent the active layer of the second type transistor, which is heterogeneous and disposed in the gate driver of the substrate, from becoming conductive, multiple electrode pattern light-shielding devices located in the same layer as the gate electrode and light-shielding pattern of the second type transistor are sequentially arranged on the gate electrode of the first type transistor to capture hydrogen between the first type transistor and the second type transistor, thereby preventing hydrogen from horizontally diffusing from the first type transistor to the second type transistor.

[0011] The display device of this disclosed embodiment can electrically connect multiple electrode patterns disposed on a first type of transistor to each other to stabilize the potential, prevent hydrogen flow, and improve the hydrogen capture effect.

[0012] The display device of this disclosed embodiment can prevent hydrogen diffusion in a second type of transistor containing an oxide semiconductor by means of an electrode pattern located on a first type of transistor, thereby preventing the problem of shortening of the effective channel length due to hydrogen diffusion. Therefore, it is possible to prevent the threshold voltage from shifting in the negative direction due to shortening of the effective channel length. In this way, the channel length margin of the second type of transistor can be minimized and driving stability improved.

[0013] The display device of this disclosed embodiment can further improve the reliability of the transistor in the active region of the active layer containing oxide semiconductor by including a first connection pattern and a second connection pattern that overlap with and are electrically connected to each other multiple power supply voltage lines surrounding the active region.

[0014] The display device of this disclosure embodiment can form a first connection pattern and a second connection pattern light-shielding on a first type of transistor that overlaps with the electrode pattern and power supply voltage line on the same layer as the light-shielding pattern and gate electrode of the second type of transistor, thereby improving the reliability of the device without adding additional materials or processes. In other words, process optimization can be achieved. Furthermore, since there are no additional processes, no processes that generate harmful gases are added, thereby reducing greenhouse gas emissions.

[0015] Other advantages, objects, and features of this disclosure will be described in part in the description which follows, and in part will be obvious to those skilled in the art upon examination of the following, or may be learned by practice of the disclosure. The objects and other advantages of this disclosure may be realized and achieved through the structures particularly pointed out in the written description and claims, and through the accompanying drawings.

[0016] To achieve these objectives and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, the display device includes a substrate comprising an active region and a non-active region, and power supply voltage lines and gate drivers disposed in the non-active region of the substrate and adjacent to each other.

[0017] In a display device, a gate driver includes a first type of transistor, a second type of transistor, and a first electrode pattern. The first type of transistor includes a first active layer on a substrate, a first gate insulating film on the first active layer, and a first gate electrode that overlaps with the first active layer and is located on the first gate insulating film. The second type of transistor includes a second active layer located further away from the substrate than the first gate electrode, a second gate insulating film on the second active layer, and a second gate electrode that overlaps with the second active layer and is located on the second gate insulating film. The first electrode pattern overlaps with the first gate electrode and is located on the second gate insulating film.

[0018] It should be understood that the foregoing general description and the following detailed description of this disclosure are merely exemplary and explanatory, intended to provide a further explanation of the scope of the claims disclosed herein. Simple Explanation of the Diagram

[0019] The accompanying drawings, incorporated and forming part of this application, are intended to provide a further understanding of the disclosure and to illustrate embodiments thereof, serving, together with the description, to explain the principles of the disclosure. In the drawings: Figure 1 shows a plan view of a display device according to an embodiment of the present disclosure; Figure 2 shows a circuit diagram of a sub-pixel in Figure 1 according to an embodiment of this disclosure; Figure 3 shows a circuit diagram of a portion of a gate-in-panel (GIP) according to an embodiment of this disclosure; Figure 4 shows a cross-sectional view of the storage capacitor and transistors with different layer structures of the display device according to an embodiment of the present disclosure; Figure 5 shows a plan view of region A in Figure 1; Figure 6 is a cross-sectional view along line segment I-I' in Figure 5; Figure 7 is a cross-sectional view along line segment II-II' in Figure 5; Figure 8 shows an enlarged view of region B in Figure 5; Figure 9 is a cross-sectional view along line segment III-III' in Figure 8; Figure 10 shows a plan view of the first and second electrode patterns and the first and second connection patterns on the same layer in region A of Figure 1; and Figure 11 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Implementation

[0020] The preferred embodiments of this disclosure will now be described with reference to the accompanying drawings. In the following description of this disclosure, detailed descriptions of relevant known steps, elements, functions, techniques, and structures may be omitted if they unnecessarily obscure the focus of this disclosure. Furthermore, the component names used in the following description are chosen for clarity and may differ from the component names in actual products.

[0021] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to illustrate various exemplary embodiments of this disclosure are given by way of example only. This disclosure is not limited to the presentation shown in the drawings. In this disclosure, descriptive terms such as "comprising," "having," and "consisting of" as used may include one or more other components, unless "only" is used. The terminology used in this disclosure is used to describe specific aspects and is not intended to limit this disclosure. In this disclosure, terms used to describe singular elements are intended to include plural elements. Unless explicitly stated otherwise, any element described in the singular also includes elements in the plural, and vice versa.

[0022] When interpreting components or values, even if the error or tolerance range is not explicitly described, the component or value should be understood to include the error or tolerance range.

[0023] In describing the various exemplary embodiments of this disclosure, if terms such as "above," "over," "below," and "adjacent" are used to describe the positional relationship between two elements, then at least one intermediate element may exist between the two elements, unless terms such as "directly," "directly," or "closely" are used. It should be understood that when referring to an element or layer as "connected to" or "coupled to" another element or layer, it can be a direct connection or coupling to that element or layer, or one or more intermediate elements or layers may exist therein.

[0024] In describing the various exemplary embodiments disclosed herein, when using terms such as "after," "following," "next," and "before" to describe the temporal relationship between two events, another event may occur in between, unless more restrictive terms such as "only," "immediately after," or "directly" are used.

[0025] In describing the various exemplary embodiments of this disclosure, terms such as "first" and "second" are used to describe various elements. These terms are intended to distinguish identical or similar elements from one another and do not limit the elements. Therefore, throughout the specification, unless expressly stated otherwise, a "first" element may be the same as a "second" element in the technical concept of this disclosure.

[0026] The features of the various embodiments disclosed herein can be partially or entirely coupled or combined with each other, and can cooperate with each other in various ways, and can be fully understood and technically driven by those skilled in the art. The embodiments disclosed herein can be implemented independently of each other, or can be implemented together in an interrelated relationship.

[0027] Figure 1 shows a plan view of a display device according to an embodiment of the present disclosure. Figure 2 shows a circuit diagram of a sub-pixel in Figure 1 according to an embodiment of the present disclosure. Figure 3 shows a circuit diagram of a portion of a gate-in-panel (GIP) according to an embodiment of the present disclosure.

[0028] Referring to Figures 1 and 2, a display device 1000 according to an embodiment of this disclosure may include a display panel 110 and a housing (not shown), the housing accommodating the sides and lower portion of the display panel 110. The inactive area NA of the display panel 110 may be hidden by the housing or covered by a separate light-shielding film. A printed circuit film and / or a battery may be included between the lower portion of the display panel 110 and the housing.

[0029] The display panel 110 may include a substrate 111 and a driving unit. The substrate 111 includes an active region AA and a non-active region NA surrounding the active region AA. The driving unit is connected to the substrate 111. The driving unit may be integrated with components arranged in an array in the active region AA and formed in the substrate 111, or it may be connected to the substrate 111 using a chip-on-glass (COG) package, or it may be connected to a printed circuit board on the substrate 111 through a film or connector using a chip-on-film (COF) package. Alternatively, the driving unit may also include components integrated in the substrate 111, as well as external components from the chip-on-glass or chip-on-film packages.

[0030] The active area AA is the area for displaying images. Multiple subpixels SP are configured in the active area AA of the display panel 110, and images can be displayed using these subpixels SP. The area outside the active area AA can be the non-active area NA.

[0031] The non-active area NA can be arranged in the edge region surrounding the active area AA of the displayed image. At least one driving unit for driving multiple sub-pixels SP can be configured in the non-active area NA. The driving unit may include a gate driver GIP, which is formed directly on the substrate 111 as a gate-in-panel (GIP). The gate driver (GIP) can be formed using the same process as the transistors provided in the active area AA. The gate driver (GIP) is connected to multiple gate lines GL in the active area AA and can sequentially provide gate voltage signals to these gate lines GL.

[0032] A pad (PAD) may be disposed on one side of the substrate 111, wherein the pad (PAD) includes pad electrodes connected to multiple gate lines (GL) and multiple data lines (DL). The pad (PAD) may be located on one side of the substrate 111. The pad (PAD) may be disposed between the gate drivers (GIPs) on both sides of the substrate 111.

[0033] Various additional components can be arranged in the non-active area NA to drive the sub-pixels SP in the active area AA.

[0034] As shown in Figure 2, at least one sub-pixel SP among multiple pixels may include a first transistor T1, a second transistor T2, a storage capacitor Cst, a compensation circuit CC, and a light-emitting element ED.

[0035] For example, the first transistor T1 can be a switching transistor, while the second transistor T2 can be a driving transistor.

[0036] The first transistor T1 has a first electrode (e.g., a drain electrode) electrically connected to the data line DL, and a second electrode (e.g., a source electrode) electrically connected to the first node N1. The gate electrode of the first transistor T1 is electrically connected to the gate line GL. In response to a scan signal provided through the gate line GL, the first transistor T1 transmits a data signal provided through the data line DL to the first node N1.

[0037] The storage capacitor Cst is electrically connected to the first node N1 and is charged with the voltage applied to the first node N1.

[0038] The second transistor T2 has a first electrode (e.g., a drain electrode) to which a high-potential driving voltage (EVDD) is applied, and a second electrode (e.g., a source electrode) electrically connected to the first electrode (e.g., an anode) of the light-emitting element ED. The second transistor T2 can control the amount of driving current flowing to the light-emitting element ED based on the voltage difference between the gate electrode and the source electrode.

[0039] The semiconductor layer of the first transistor T1 and / or the second transistor T2 may contain amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polysilicon (LTPS), or may contain oxide semiconductors.

[0040] The display device in this disclosed embodiment may have the following advantages: at least one transistor formed on substrate 111 includes an oxide semiconductor layer; it can be formed at a relatively low temperature compared to other materials; it maintains amorphous properties; it has high light transmittance properties; and it can adjust the S-factor to easily express grayscale.

[0041] Meanwhile, in the display device of this disclosed embodiment, the plurality of transistors formed on the substrate 111 include a first type transistor having polysilicon as an active layer and a second type transistor having an oxide semiconductor layer as an active layer. The structure includes a configuration that can prevent hydrogen diffusion into the second type transistor.

[0042] In each sub-pixel SP, the light-emitting element ED outputs light corresponding to the driving current. The light-emitting element ED can output any light corresponding to red, green, blue, and white.

[0043] An ED (Emitting Light Emitting Device) may include an anode, an intermediate layer disposed on the anode, and a cathode that provides a common voltage. The intermediate layer includes at least one emitting layer, which, when an electric field is formed between the anode and the cathode, can enable each pixel to emit light of the same color, such as white light, or to emit light of a different color, such as red, green, or blue light, for each sub-pixel SP. The intermediate layer may include various types of common layers and multiple functional layers, which, together with the emitting layer, effectively supply holes and electrons to the emitting layer.

[0044] The light-emitting element (ED) can be a forward-emitting diode or a backward-emitting diode.

[0045] A compensation circuit CC can be additionally provided in the sub-pixel SP to compensate for the critical voltage of the second transistor T2, etc. The compensation circuit CC may contain one or more transistors. The compensation circuit CC may contain one or more transistors and multiple capacitors, and can be configured in different ways depending on the compensation method. The sub-pixel SP containing the compensation circuit CC may contain circuits with various structures having different numbers of transistors and / or capacitors, such as 3T (transistor) 1C (capacitor), 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C, etc.

[0046] Among the transistors placed in sub-pixels, the switching transistors may require high-speed driving to perform rapid switching actions. Driving transistors can provide high current to the light-emitting elements and require high current output to exhibit high brightness.

[0047] The gate driver (GIP) contained in the non-active region (NA) outputs a gate signal to the gate line according to a gate control signal, for example, from a timing controller. The gate driver (GIP) may contain multiple transistors, which may be formed in the same process as the transistors of the sub-pixel SP.

[0048] For example, a gate driver (GIP) may include multiple stages of STT1 connected together, as shown in Figure 3, which can sequentially output gate signals to the gate line.

[0049] As shown in Figure 3, each stage STT1 includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU that turns on when the pull-up node NQ is charged to the gate high voltage, a pull-down transistor TD that turns on when the pull-down node NQB is charged to the gate high voltage, and a node controller NC that controls the charging and discharging of the pull-up node NQ and the pull-down node NQB.

[0050] The node controller NC can be connected to a start signal line that receives a start signal or carry signal from the previous stage, and a clock line that receives one of the gate clock signals. The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB based on the start signal or carry signal input to the start signal line from the previous stage, and the gate clock signal input to the clock line. To stabilize the output of the control stage STT1, the node controller discharges the pull-down node NQB to a low gate voltage when the pull-up node NQ is charged to a high gate voltage, and discharges the pull-up node NQ to a low gate voltage when the pull-down node NQB is charged to a high gate voltage. For this purpose, the node controller NC may include multiple transistors.

[0051] When stage STT1 is pulled up, the pull-up transistor TU is turned on. That is, when the pull-up node NQ is charged to the gate high voltage, the gate clock signal of the clock line CL is output to the output terminal OT. When stage STT1 is pulled down, the pull-down transistor TD is turned on. That is, when the pull-down node NQB is charged to the gate high voltage, the output terminal OT is discharged to the gate low voltage of the gate low voltage terminal VGLT.

[0052] In Figure 3, the pull-up transistor TU, pull-down transistor TD, and multiple transistors of each stage STT1 of the gate driver (GIP) and the node controller NC can be transistors with wide channel widths for high-voltage outputs with high response speed and high-voltage gates.

[0053] Meanwhile, the example shown in Figure 3 is merely an example. In addition to the two transistors shown, the gate driver (GIP) containing stage STT1 also includes transistors for various purposes, and the transistors included in the gate driver may include a first type transistor with polysilicon as the active layer and a second type transistor with oxide semiconductor as the active layer.

[0054] Furthermore, Figures 2 and 3 illustrate that the transistors T1 and T2 of the sub-pixel SP, as well as the pull-up transistors TU, pull-down transistors TD, and multiple transistors of the node controller NC of each stage STT1 of the gate driver (GIP), are all formed as N-type semiconductor transistors with N-type semiconductor characteristics. However, the embodiments disclosed herein are not limited thereto. That is, at least one of the pull-up transistors TU, pull-down transistors TD, and multiple transistors of the node controller NC of each stage STT1 of the gate driver (GIP) can be formed as a P-type semiconductor transistor with P-type semiconductor characteristics.

[0055] In addition to the gate driver (GIP), the display panel 110 may include a data driving unit. For example, the data driving unit may include at least one source driver integrated circuit (hereinafter referred to as the source driver IC). The source driver IC receives digital video data and source control signals from the timing controller. The source driver IC converts the digital video data into analog data voltage according to the source control signals and provides the converted analog data voltage to the data line DL.

[0056] When the source driver IC is formed as a driver chip (such as an integrated circuit), the source driver IC can be mounted on a flexible film using a COF (Chip-on-Foil) method. Wires connecting multiple pads to the source driver IC, as well as wires connecting these pads to circuit board conductors, are formed on the flexible film. The flexible film, using anisotropic conductive film, is attached to multiple pads, such as data pads, formed in the non-display area NA of the display panel DP, allowing the pads to be connected to the wires on the flexible film.

[0057] The circuitry of each sub-pixel SP in the active region of Figure 2 and the circuitry in the gate-in-the-input (GIP) of Figure 3 can include transistors with different mobilities for various purposes. For example, the active layer material of each transistor can be different to achieve different mobilities. Furthermore, depending on the material of the active layer, a first-type transistor using polysilicon as the first active layer and a second-type transistor using oxide semiconductor as the second active layer can be formed.

[0058] In some cases, depending on the crystallinity of polycrystalline silicon, the mobility of oxide semiconductors can vary according to the metal composition and metal content ratio that binds with oxygen. Therefore, in the display device disclosed herein, the first type transistor and the second type transistor of the same type can each comprise transistors with different structures and different mobilities.

[0059] Next, in the display device disclosed herein, we will examine the gate driver (GIP) or transistors LT, OT1 and OT2 with different layer structures in the gate driver (GIP), and the storage capacitor STC formed with the gate driver (GIP) or transistor using the same process.

[0060] Type I transistors refer to transistors that use polysilicon as the active layer, while Type II transistors refer to transistors that use oxide semiconductors as the active layer. Type I transistors refer to LT shown in Figure 4, while Type II transistors can refer to OT1 and OT2 shown in Figure 4.

[0061] Figure 4 shows a cross-sectional view of a storage capacitor and transistors with different layer structures in a display device according to an embodiment of the present disclosure.

[0062] As shown in FIG4, the first type transistor LT includes a first active layer 161 located on a substrate 111, a first gate electrode 173 overlapping the first active layer 161 and sandwiched therebetween with a third insulating film 123, and a first source-drain electrode 227 and a second source-drain electrode 228 connected to the opposite side of the first active layer 161 and separated from each other.

[0063] Here, the first active layer 161 may be made of polycrystalline silicon.

[0064] The first-type transistor LT, comprising an active layer of polysilicon, has high mobility and can be used as a transistor requiring high-speed operation, such as a gate-in-progress (GIP). In the display device disclosed herein, the first-type transistor LT is not limited to being configured in a gate-in-progress (GIP). For example, the first-type transistor LT can be used as a switching transistor requiring high-speed operation in the driving circuitry provided in a sub-pixel.

[0065] The first type transistor LT may be further included in a first light-shielding pattern 151 below the first active layer 161 to prevent the generation of photocurrent or to prevent the first active layer 161 from being affected by light entering from below the substrate 111. The first light-shielding pattern 151 may be connected to a first gate electrode layer 174 connected to the first gate electrode 173, thereby having the same potential as the first gate electrode 173. In this case, the first light-shielding pattern 151 may serve as a dual-gate together with the first gate electrode 173. Compared to a structure with a single gate electrode, the first type transistor LT has the advantage of achieving fast switching operation in a limited area because the first gate electrode 173 and the first light-shielding pattern 151 located below the first active layer 161 jointly perform a dual-switching function. Therefore, the first type transistor LT can be highly integrated and placed in a sub-pixel.

[0066] The third insulating film 123 performs the function of the first gate insulating film of the first type transistor LT.

[0067] The second type of transistor includes a first oxide semiconductor transistor OT1 and a second oxide semiconductor transistor OT2 with different structures.

[0068] The first oxide semiconductor transistor OT1 of the second type transistor may include a second active layer 201, a second gate electrode 210 overlapping the second active layer 201 and with a seventh insulating film 127 therebetween, and a third source-drain electrode (not shown) and a fourth source-drain electrode 222 connected to the opposite side of the second active layer 201 and separated from each other. The second active layer 201 of the second type transistor OT1 may be located at a position far from the first active layer 161 of the first type transistor LT, and the vertical phase of the second type transistor OT1 may be higher than the vertical phase of the first type transistor LT. Therefore, the second active layer 201 of the second type transistor OT1 is formed sequentially after the first active layer 161 and the first gate electrode 173 of the first type transistor LT are formed.

[0069] Here, the second active layer 201 may comprise an oxide semiconductor.

[0070] Oxide semiconductor materials may contain compounds of oxygen, and compounds of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). In some cases, to improve mobility, oxide semiconductor materials may further contain metals with high conductivity, such as iron (Fe).

[0071] More specifically, examples of oxide semiconductor materials included in the second active layer 201 include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), iron indium zinc oxide (FIZO), etc.

[0072] The first oxide semiconductor transistor OT1 of the second type transistor may further include a second light-shielding pattern 171 located below the second active layer 201 to prevent light entering from below the substrate 111 from generating photocurrent and to prevent the second active layer 201 from being affected. The second light-shielding pattern 171 may be connected to the second gate electrode 210, thereby having the same potential as the second gate electrode 210. In this case, the second light-shielding pattern 171 and the second gate electrode 210 together serve as a dual gate. Compared to a structure with a single gate electrode, the first type transistor LT has the advantage of achieving fast switching operation in a limited area because the first gate electrode 173 and the first light-shielding pattern 151 located below the first active layer 161 perform a dual switching function. When the second type transistor OT1 is included in a sub-pixel SP, the transistor can be used as a switching transistor. In this case, even if the second active layer 201 included in the second type transistor OT1 contains an oxide semiconductor, the mobility can be further improved by including a material with high conductivity as a metal component or by adjusting the content ratio of the metals contained in the oxide semiconductor.

[0073] Here, the seventh insulating film 127 can function as the second gate insulating film for each of the second type transistors OT1 and OT2.

[0074] Meanwhile, the display device according to the embodiments disclosed herein may include a first oxide semiconductor transistor OT1 and a second oxide semiconductor transistor OT2 with different layer structures. The second type transistors OT1 and OT2 include an oxide semiconductor layer as an active layer.

[0075] The second oxide semiconductor transistor OT2 of the second type of transistor may include a third active layer 202, a third gate electrode 211 overlapping the third active layer 202, a seventh insulating film 127 between the third active layer 202 and the third gate electrode 211, and a fifth source-drain electrode 225 and a sixth source-drain electrode 226 connected to the opposite side of the third active layer 202 and separated from each other. As shown in FIG4, the third active layer 202 of the second oxide semiconductor transistor OT2 is located in the same layer as the second active layer 201 of the first oxide semiconductor transistor OT1, and the third gate electrode 211 is located in the same layer as the second gate electrode 210, such that at least one layer of the second oxide semiconductor transistor OT2 and the first oxide semiconductor transistor OT1 can be formed in the same process to optimize the process.

[0076] However, in the second oxide semiconductor transistor OT2, the third light-shielding pattern 191 for preventing light from entering from below the substrate 111 is located further away from the substrate 111 than the second light-shielding pattern 171 of the first oxide semiconductor transistor OT1, and the third light-shielding pattern 191 overlaps with the third active layer 202 and is sandwiched between the sixth insulating film 126.

[0077] The third light-shielding pattern 191 of the second oxide semiconductor transistor OT2 is connected to an extension of the fifth source-drain electrode 225, which extends beyond the third active layer 202 and is subjected to the same potential as the fifth source-drain electrode 225. Therefore, the potential of the third light-shielding pattern 191 can be stabilized.

[0078] Meanwhile, the second oxide semiconductor transistor OT2 is driven by a single gate electrode, which is the opposite of the dual-gate structure of the first oxide semiconductor transistor OT1. Therefore, compared to the first oxide semiconductor transistor OT1, the second oxide semiconductor transistor OT2 can ensure a certain range until the drain current Ids saturates based on the gate voltage Vgs variation. Since a gradual expression can be achieved within a certain range of Vgs-Ids variation, the second oxide semiconductor transistor OT2 can be used as the driving transistor in the sub-pixel.

[0079] The first oxide semiconductor transistor OT1 and the second oxide semiconductor transistor OT2 may each contain a metal with hydrogen-trapping function in the second gate electrode 210 and the third gate electrode 211, respectively. The second gate electrode 210 and the third gate electrode 211 are perpendicularly adjacent to the second active layer 201 and the third active layer 203, for example, to prevent hydrogen from transferring to the second active layer 201 and the third active layer 202. For example, the second gate electrode 210 and the third gate electrode 211 may contain titanium (Ti). To improve conductivity, the second gate electrode 210 and the third gate electrode 211 may contain a three-layer stacked structure of titanium (Ti) layer / aluminum (Al) layer / titanium (Ti) layer. Furthermore, to prevent hydrogen from transferring to the third active layer 202, the third light-shielding pattern 191, perpendicularly adjacent to the third active layer 203, may be formed of a metal with hydrogen-trapping function. The third light-shielding pattern 191 may contain titanium.

[0080] The first storage electrode 172 and the second storage electrode 181 included in the storage capacitor STC can be formed together with the electrodes included in the first type transistor LT and the second type transistors OT1 and OT2 disposed on the substrate 111. In an example example, the first storage electrode 172 is disposed on the same layer as the first gate electrode 173 of the first type transistor LT and uses the same material. However, this disclosure is not limited thereto.

[0081] Meanwhile, the second-type transistors OT1 and OT2, which incorporate oxide semiconductors, tend to have conductive regions expanded by hydrogen ions. The second-type transistors OT1 and OT2 have a second active layer 201 and a third active layer 202, a second gate electrode 210 and a third gate electrode 211 disposed on multiple layers, and a second light-shielding pattern 171 and a third light-shielding pattern 191. In particular, when hydrogen remains in the seventh insulating film 127 and the sixth insulating film 126 of adjacent second active layers 201 and third active layers 202, hydrogen components may flow into the active layers of the oxide semiconductor. When hydrogen ions remaining in the insulating films of adjacent active layers flow into the active layers of the second-type transistors OT1 and OT2, the conductive region of the active layer expands, and the effective channel length shortens. Furthermore, when the effective channel length in the transistor shortens, the threshold voltage may shift in the negative direction, making the transistor's off-state characteristics unstable.

[0082] For example, residual hydrogen in the insulating film may originate from plasma gas used in the conductive fabrication of the active layer, including the oxide semiconductor layer, or residual components of the etching solution used in the contact hole formation process, which remain in the insulating film.

[0083] In the sub-pixel SP circuit, the transistor arrangement area is small, and hydrogen may be captured by the second gate electrode 210 and the third gate electrode 211 and the third light-shielding pattern 191 that is perpendicular to the second active layer 201 and the third active layer 202 and is captured to the third active layer 202.

[0084] However, the circuit configuration is integrated and densely arranged in the gate driver (GIP), and the arrangement density of the second type transistor OT1 or OT2 using an oxide semiconductor layer as the active layer is lower than that of the first type transistor LT compared to a structure using polysilicon as the active layer. In this case, the horizontal flow of hydrogen through the insulating film may be difficult to be adequately blocked by the third light-shielding pattern 191 of the second gate electrode 210 and the third gate electrode 211 or the second type transistor OT2 or the third type transistor OT3.

[0085] The display device according to the present disclosure embodiment may be further configured with a first electrode pattern 211 and / or a second electrode pattern 192 such that the first electrode pattern 211 and / or the second electrode pattern 192 overlap with the area of ​​the first gate electrode 173 that occupies the main area in the gate driver (GIP) of the first type transistor LT, thereby capturing hydrogen and preventing hydrogen from diffusing horizontally through the insulating film. This can prevent hydrogen from diffusing to the second type transistor OT1 or OT2 of the adjacent first type transistor LT.

[0086] The second electrode pattern 192 overlaps with the first gate electrode 173 of the first-type transistor LT. The second electrode pattern 192 is disposed on the same layer as the third light-shielding pattern 191. The third light-shielding pattern 191 is disposed below the sixth insulating film 126. The second electrode pattern 192 and the third light-shielding pattern 191 are located below the second active layer 201 and the third active layer 202. The first electrode pattern 212 overlaps with the first gate electrode 173 of the first-type transistor LT and is located on the same layer as the second gate electrode 210 and the third gate electrode 211. The second gate electrode 210 and the third gate electrode 211 are located above the seventh insulating film 127 above the second active layer 201 and the third active layer 202. The second electrode pattern 192 and the first electrode pattern 212 contact the sixth insulating film 126 and the seventh insulating film 127 closest to the second active layer 201 and the third active layer 202, thereby blocking hydrogen that is horizontally transported through the sixth insulating film 126 and the seventh insulating film 127.

[0087] The bottom surface of the first electrode pattern 212 can contact the seventh insulating film 127. The upper surface of the second electrode pattern 192 is in contact with the sixth insulating film 126.

[0088] The vertical structure in Figure 4 will be described in detail below.

[0089] The substrate 111 can be made of a flexible plastic material, thus possessing flexibility. For example, the substrate 111 can comprise a first substrate 111a and a second substrate 111c made of organic materials, the first substrate 111a and the second substrate 111c overlapping each other and sandwiched between an inorganic interlayer film 111b. The first substrate 111a and the second substrate 111c can comprise different organic films of the same or different types, such as PET (polyethylene terephthalate) and polyimide. In some cases, an adhesive film, such as a pressure-sensitive adhesive (PSA) film, can be included between the first substrate 111a and the second substrate 111c as an interlayer.

[0090] The substrate 111 is used to support and protect the components disposed above the display device 1000.

[0091] In addition to the first transistor T1 and the second transistor T2 shown in Figure 2, various types of transistors included in the compensation circuit CC can be disposed in the active region AA of the substrate 111. Figure 8 shows, as an example, a driving transistor T connected to the light-emitting element ED.

[0092] Multilayer inorganic insulating films 121, 122, 123, 124, 125, 126, 127 and 128 are disposed in the active region AA and the inactive region (see NA in FIG1) of the substrate 111, so that the electrodes located in different layers in the first type transistor LT and the second type transistor OT2 can be insulated from each other.

[0093] The inorganic insulating film may include a first insulating film 121, a second insulating film 122, a third insulating film 123, a fourth insulating film 124, a fifth insulating film 125, a sixth insulating film 126, a seventh insulating film 127, and an eighth insulating film 128.

[0094] A first insulating film 121 is disposed in the active region AA and the inactive region NA on the substrate 111. The first insulating film 121 may be referred to as a buffer layer and can perform the same function as buffer layers known in the art. The first insulating film 121 may be disposed on the substrate 111 to protect the structure located above the substrate 111 from moisture that penetrates through the substrate 111 and to planarize the surface of the substrate 111.

[0095] The first insulating film 121 may be configured adjacent to the edge of the substrate 111, or disposed on the edge of the substrate 111, to prevent moisture from penetrating from the edge of the substrate 111. The first insulating film 121 may be a single-layer inorganic film, or may comprise multiple layers of inorganic films stacked alternately.

[0096] For example, the first insulating film 121 may comprise one or more inorganic films, such as silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiOxNy) film, or may comprise a multilayer of the above inorganic films stacked together.

[0097] The first light-shielding pattern 151 may be disposed on the first insulating film 121 using a conductive metal material. Specifically, the conductive metal material may include at least one aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), niobium (Nd) or titanium (Ti).

[0098] The second insulating film 122 may be disposed on the first insulating film 121 containing the first light-shielding pattern 151. For example, the second insulating film 122 may serve as a buffer layer for a first-type transistor LT containing polycrystalline silicon as an active layer. In this case, the second insulating film 122 is located below the polycrystalline silicon semiconductor layer and may serve as a buffer layer for the polycrystalline silicon semiconductor layer. The second insulating film 122 may contain an inorganic film, such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film of the aforementioned silicon oxide (SiOx) film and silicon nitride (SiNx) film. The first active layer 161 containing polycrystalline silicon is disposed on the second insulating film 122 to overlap with the first light-shielding pattern 151. The first active layer 161 may be formed, for example, by depositing amorphous silicon, then heating it to perform a crystallization process, and then patterning it so that the first active layer 161 has a predetermined width overlapping with the first light-shielding pattern 151.

[0099] The third insulating film 123 is disposed on the second insulating film 122, which includes the first active layer 161. The bottom surface of the first electrode pattern 212 may contact the seventh insulating film 127. The upper surface of the second electrode pattern 192 may contact the sixth insulating film 126. The third insulating film 123 may include one or more inorganic films, such as silicon oxide (SiOx) film, silicon nitride (SiNx) film, and silicon oxynitride (SiOxNy) film.

[0100] The third insulating film 123 and the second insulating film 122 can be selectively removed to form a contact hole, exposing a portion of the upper part of the first light-shielding pattern 151.

[0101] The first gate electrode 173 may be disposed on the third insulating film 123 using a conductive metal material. The first storage electrode 172 and the second light-shielding pattern 171 of the second type transistor OT1 may be disposed on the same layer. Specifically, the conductive metal material may include at least one aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), niobium (Nd), or titanium (Ti).

[0102] The first gate electrode extension 174 is further disposed on the same layer as the first gate electrode 173, and the first gate electrode extension 174 can be connected to the first light-shielding pattern 151 through the contact holes disposed in the second insulating film 122 and the third insulating film 123.

[0103] The first light-shielding pattern 151 and the second light-shielding pattern 171 can prevent light from below the substrate 111 from affecting the first active layer 161 and the second active layer 201, thereby solving the problem caused by photocurrent.

[0104] The first storage electrode 172 may form an electrode of a capacitor contained in the driver of a non-active region or sub-pixel.

[0105] The fourth insulating film 124 may be disposed on the third insulating film 123 to cover the second light-shielding pattern 171, the first storage electrode 172, and the first gate electrode 173. The fourth insulating film 124 may have an insulating function from the active layer or other electrodes subsequently formed.

[0106] The fourth insulating film 124 may contain an inorganic material. The inorganic material may include, for example, a silicon nitride (SiNx) film.

[0107] The second storage electrode 181 may be disposed on the fourth insulating film 124 at a position overlapping with the first storage electrode 172, using a conductive metal material. The conductive metal material may include at least one aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), niobium (Nd), or titanium (Ti).

[0108] The fifth insulating film 125 is formed on the fourth insulating film 124 by an inorganic insulating material, such as a silicon nitride film, a silicon dioxide film, or a silicon oxynitride film, and covers the second storage electrode 181.

[0109] As a hydrogen-trapping metal layer on the fifth insulating film 125, a third light-shielding pattern 191 is disposed at the position of the second oxide semiconductor transistor OT2 of the second type transistor, and a first electrode pattern 192 is disposed at a position overlapping with the first gate electrode 173. The hydrogen-trapping metal may include, for example, at least titanium (Ti). The hydrogen-trapping metal may be formed from a single metal with hydrogen-trapping function or from an alloy containing a hydrogen-trapping metal.

[0110] The sixth insulating film 126 is disposed on the fifth insulating film 125. The third light-shielding pattern 191 and the first electrode pattern 192 can be disposed on the fifth insulating film 125 and can be covered by the sixth insulating film 126.

[0111] The sixth insulating film 126 can function as a buffer layer for the second and third active layers 201 and 202 of the oxide semiconductor. The sixth insulating film 126 can be used to planarize the surface of the region where the first and second active layers 180 are formed on the sixth insulating film 126.

[0112] The sixth insulating film 126 may comprise an inorganic material. This inorganic material may comprise, for example, a silicon oxide (SiOx) film or a multilayer stacked inorganic film. The sixth insulating film 126 closest to the second and third active layers 201 and 202 of the oxide semiconductor preferably comprises a silicon oxide film with a low hydrogen content.

[0113] On the sixth insulating film 126, the second active layer 201 and the third active layer 202 are respectively disposed at positions overlapping with the second light-shielding pattern 171 and the third light-shielding pattern 191. The second and third active layers 201 and 202 comprise, for example, an oxide semiconductor material. The oxide semiconductor material can be formed by combining oxygen with at least one metal, including zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). In some cases, to improve mobility, a metal with high conductivity, such as iron (Fe), can be further added to the oxide semiconductor material.

[0114] More specifically, examples of oxide semiconductor materials included in the second and third active layers 201 and 202 may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), iron indium zinc oxide (FIZO), etc.

[0115] The seventh insulating film 127 has an inorganic insulating film assembly configured to cover the second and third active layers 201 and 202. The seventh insulating film 127 is located on the second and third active layers 201 and can function as the gate insulating film for the second type transistors OT1 and OT2. The seventh insulating film 126, which is closest to the second and third active layers 201 and 202 of the oxide semiconductor, preferably contains a silicon oxide film with a low hydrogen content.

[0116] The second gate electrode 210 and the third gate electrode 211 are respectively disposed on the seventh insulating film 127 at positions overlapping with the channels of the second active layer 201 and the third active layer 202. In addition, in the same process, the first electrode pattern 212 is configured to overlap with the first gate electrode 173 and the first electrode pattern 192 in the same layer.

[0117] The eighth insulating film 128 has an inorganic insulating film assembly configured to cover the second and third gate electrodes 210 and 211 and the first electrode pattern 212.

[0118] Next, contact holes CT3 and CT7 are fabricated by selectively removing the eighth insulating film 128, the seventh insulating film 127, the sixth insulating film 126, the fifth insulating film 125, the fourth insulating film 124, and the third insulating film 123. In the same process, contact holes are formed by selectively removing the eighth insulating film 128, the seventh insulating film 127, the sixth insulating film 126, the fifth insulating film 125, and the fourth insulating film 124, thereby exposing a portion of the upper surface of the second light-shielding pattern 171 and a portion of the upper surface of the first storage electrode 172. In the same process, contact holes are formed by selectively removing the eighth insulating film 128, the seventh insulating film 127, the sixth insulating film 126, and the fifth insulating film 125, thereby exposing a portion of the upper surface of the second storage electrode 181. In the same process, contact holes are formed by selectively removing the eighth insulating film 128, the seventh insulating film 127, and the sixth insulating film 126, thereby exposing a portion of the third light-shielding pattern 191. In the same process, contact holes are formed by selectively removing the eighth insulating film 128 and the seventh insulating film 127, thereby exposing the upper surfaces on both sides of the second active layer 201 and the third active layer 202. In the same process, contact holes are formed by selectively removing the eighth insulating film 128, thereby exposing a portion of the upper surface of the second gate electrode 210.

[0119] The contact holes provided in each insulating film are filled to form a conductive metal material, and the conductive metal material is patterned on the eighth insulating film 128 to form each source-drain electrode 222, 225, 226, 227 and 228 and storage connection electrodes 223 and 224.

[0120] The upper surfaces of both sides of the first active layer 161 can be exposed through the contact holes CT3 and CT7, and connected to the first source-drain electrode 227 and the second source-drain electrode 228.

[0121] The upper surfaces of both sides of the third active layer 202 can be exposed through the contact holes provided in the insulating films 127 and 128, and connected to the fifth and sixth source-drain electrodes 225 and 226.

[0122] Furthermore, the fifth source-drain electrode 225 may be connected to a portion of the upper surface of the third light-shielding pattern 191, which protrudes further from one side of the third active layer 202 and is exposed.

[0123] The upper surfaces of both sides of the second active layer 201 can be exposed through the contact holes provided in the insulating films 127 and 128, and connected to the fourth source-drain electrode 222.

[0124] Furthermore, a portion of the upper surface of the second gate electrode 210 and a portion of the upper surface of the second light-shielding pattern 171 can be interconnected via a connecting electrode 221 and an extension 221ec. The connecting electrode 221 is disposed on the eighth insulating film 128. The extension 221ec is vertically disposed in contact holes penetrating the third to eighth insulating films 123, 124, 125, 126, 127, and 128. The extension 221ec is directly connected to the connecting electrode 221. The connecting electrode 221 can be integrated into the extension 221ec within the third to eighth insulating films 123, 124, 125, 126, 127, and 128.

[0125] The first storage connection electrode 223 is connected to the lower first storage electrode 172, and the second storage connection electrode 224 is connected to the lower second storage electrode 181.

[0126] Next, we will examine the configuration of the gate driver and its surrounding components in more detail.

[0127] Next, the first type of transistor refers to a transistor that uses polysilicon as the active layer, while the second type of transistor refers to a transistor that uses oxide semiconductor as the active layer. The first type of transistor refers to LT as described in Figure 4, while the second type of transistor may refer to OT1 and OT2 as described in Figure 4.

[0128] Figure 5 shows a plan view of region A in Figure 1. Figure 6 is a cross-sectional view along line segment I-I' in Figure 5. Figure 7 is a cross-sectional view along line segment II-II' in Figure 5. Figure 8 shows an enlarged view of region B in Figure 5. Figure 9 is a cross-sectional view along line segment III-III' in Figure 8. Figure 10 shows a plan view of the first and second electrode patterns and the first and second connection patterns located in the same layer of region A in Figure 1.

[0129] As shown in Figures 1 and 5, the display device according to the present disclosure embodiment may include a substrate 111, which includes an active region AA and a non-active region NA, as well as a first power supply voltage line VSSL and a gate driver (GIP) disposed in the non-active region NA of the substrate 111 and adjacent to each other.

[0130] The first power supply voltage line VSSL provides a low voltage or ground voltage EVSS to the cathode of the light-emitting element ED, and can be located in the area surrounding the active region AA. The first power supply voltage line VSSL can be located between the active region AA and the gate driver (GIP). The first power supply voltage line VSSL can extend from the active region AA and connect to the cathode located in the non-active region NA to provide a low voltage or ground voltage EVSS to the cathode.

[0131] In the display device according to the present disclosure embodiment, the first power supply voltage line VSSL can be formed as a multilayer structure, as shown in FIG5, FIG6 and FIG7. In addition, the metal layer of the multilayer structure includes a second connection pattern 194 and a first connection pattern 272 with hydrogen capture function to prevent hydrogen from diffusing to the adjacent second type transistor (OT: OT1 or OT2).

[0132] Referring to Figures 1 and 2, the active region AA is contained in the sub-pixel SP in the area where multiple gate lines GL and data lines DL intersect, and each sub-pixel SP has a light-emitting element ED, and the first power supply voltage line VSSL can be electrically connected to the cathode of the light-emitting element ED.

[0133] The first power supply voltage line VSSL includes a source-drain metal layer 239, which is located on the same layer as the source-drain electrodes (222, 225, and 226 in FIG. 4) and storage connection electrodes 223 and 224; a second connection pattern 194, located on the same layer as the light-shielding pattern 191, which is located below the active layers 201 and 202 of the oxide semiconductor containing the second type transistor (OT: OT1 or OT2); and a first connection pattern 272, located on the same layer as the gate electrodes 210 and 211, which are located above the active layers 201 and 202 of the semiconductor oxide containing the second type transistor (OT: OT1 or OT2).

[0134] The light-shielding pattern 191 is located below the active layers 201 and 202 of the second-type transistor (OT: OT1 or OT2), and each of the gate electrodes 210 and 211 located above the active layers 201 and 202 contains a hydrogen-trapping metal to prevent hydrogen from diffusing directly into the active layers 201 and 202 of the second-type transistor (OT: OT1 or OT2) in the vertical direction. For example, the light-shielding pattern 191 of the second-type transistor OT may contain titanium, and the gate electrodes 210 and 211 of the second-type transistor OT may contain a multilayer structure of titanium / aluminum / titanium layers. By including a highly conductive metal and the hydrogen-trapping function of the gate electrodes 210 and 211 of the second-type transistor, the mobility of the transistor can be improved.

[0135] The first power supply voltage line VSSL may include a second connection pattern 194 and a first connection pattern 191. The second connection pattern is disposed on the same layer as the light-shielding pattern 191 of the second oxide semiconductor transistor OT2 of the second type transistor OT. The first connection pattern 272 is disposed on the same layer as the gate electrodes 210 and 211 of the second oxide semiconductor transistor OT2 of the second type transistor (OT: OT1 or OT2), and the second connection pattern 194 may contain the same material as the light-shielding pattern 191 of the second type transistor OT. The first connection electrode 272 may contain the same material as the gate electrodes 210 and 211 of the second type transistor (OT: OT1 or OT2). The material of the light-shielding pattern 191 and the gate electrodes 210 and 211 of the second type transistor OT may contain hydrogen-capturing metal, and at least one of the first connection electrode 272 and the second connection pattern 194 may contain hydrogen-capturing metal, thereby enhancing the hydrogen capture function around the active region AA. In other words, for each sub-pixel of the active region AA and the second type of transistor OT contained in the gate driver (GIP), the first power supply voltage line VSSL is a multilayer structure containing hydrogen-capturing metal. The second connection pattern 194 and the first connection pattern 272 can capture hydrogen ions in adjacent insulating films 125, 126, 127, and 128, and prevent lateral diffusion of hydrogen in insulating films 125, 126, 127, and 128.

[0136] The display device according to the present disclosure embodiment further includes a first electrode pattern 212 and a second electrode pattern 192 with hydrogen capture function in the gate driver (GIP), and a first and second connection patterns 272 and 194 included in the multilayer structure of the first power supply voltage line VSSL as shown in FIG10, for capturing hydrogen, thereby preventing hydrogen from being transversely transmitted to the second type transistor OT, and preventing hydrogen from causing changes in the effective channel length.

[0137] Furthermore, the resistance of the first power supply voltage line VSSL can be reduced by electrical connections between conductors in the multilayer structure. As shown in FIG7, the second connection pattern 194 can be connected to the first source-drain metal layer 229 through contact holes CT1 in the sixth to eighth insulating films 126, 127 and 128 within the opening 272a in the first connection pattern 272. Furthermore, the first connection pattern 272 can be connected to the first source-drain metal layer 229 through contact holes CT2 in the eighth insulating film 128. Here, the first source-drain metal layer 229 is connected to the first connection pattern 272 through an extension 229ec1 extending vertically into the contact holes CT2 in the eighth insulating film 128 and through an extension 229ec2 extending vertically into the contact holes CT1 disposed in the sixth to eighth insulating films 126, 127 and 128.

[0138] Meanwhile, the first power supply voltage line VSSL may include not only the first source-drain metal layer 229, but also a second source-drain metal layer 234 overlapping the first source-drain metal layer 229, as shown in Figures 7 and 8. The second source-drain metal layer 234 may be disposed on the first planarization film 131.

[0139] The second source-drain metal layer 234, being electrically connected to the first source-drain metal layer 229, further reduces the resistance of the first power supply voltage line VSSL. Furthermore, when the first source-drain metal layer 229 and the second source-drain metal layer 234 overlap, they effectively shield the upper light-emitting element ED or touch function portion from operation.

[0140] The first source-drain metal layer 229 and the second source-drain metal layer 234 are made of conductive metal materials. For example, the conductive metal materials may include at least one aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), niobium (Nd) or titanium (Ti).

[0141] Additional planarization membranes, embankments, sealing layers, etc., can be added to the sealing layer on the second source-drain metal layer 234.

[0142] Figure 6 shows the arrangement of multiple Type I transistors LT contained in a gate driver (GIP).

[0143] As shown in Figure 6, a plurality of Type I transistors (LTs) are configured along a first direction (X-axis) in a region of the gate driver (GIP). Each Type I transistor (LT) may share a first source-drain electrode 227, a second source-drain electrode 228, and a gate connection metal layer 230.

[0144] The first source-drain electrode 227 and the second source-drain electrode 228, as well as the gate connection metal layer 230, may be parallel in a first direction in the configuration region of the first type transistor LT.

[0145] The first source-drain electrode 227 and the second source-drain electrode 228 can be connected to the first active layer 161 through the contact holes CT3 and CT7 disposed in the insulating films 123, 124, 125, 126, 127 and 128, as shown in Figures 4 and 9.

[0146] As shown in Figures 6 and 10, the first electrode pattern 192 and the second electrode pattern 212 with hydrogen capture function are disposed between the regions where the first source-drain electrode 227 and the second source-drain electrode 228 are disposed, so that the configuration density of the hydrogen capture function electrode in the region of the gate driver (GIP) can be increased.

[0147] In the display device according to the present disclosure embodiment, the source-drain electrodes 222, 225, 226, 227 and 228, storage connection electrodes 223 and 224, and gate connection metal layer 230 of each transistor LT and OT may be located on the same layer as the power supply voltage line.

[0148] As shown in Figure 10, the gate electrode 193 of the second type transistor OT has a hydrogen capture function and can be formed using the same material (such as titanium) and the same process as the first electrode pattern 212.

[0149] Referring to Figures 9 and 10, the first electrode pattern 212 may include a connecting portion 212c on the same layer as the first electrode pattern 212 used for receiving electrical signals. The first electrode pattern 212 and the connecting portion 212c may be integral. The second electrode pattern 192 may include a connecting portion 192c on the same layer as the second electrode pattern 192 used for receiving electrical signals. The second electrode pattern 192 and the connecting portion 192c may be integral.

[0150] The same gate voltage signal can be applied to the first electrode pattern 212, the second electrode pattern 192, and the first type gate electrode 173.

[0151] Furthermore, the second electrode pattern 192 can be formed in the same process as the light-shielding pattern 191 of the second type transistor OT.

[0152] Therefore, when forming the first electrode pattern 212 and the second electrode pattern 192 disposed in the gate driver (GIP), the electrode pattern can be formed together with the transistor in the transistor formation process without adding additional metal, thereby optimizing the process and preventing the emission of harmful gases such as greenhouse gases.

[0153] In the gate driver (GIP), a first type transistor LT is configured to surround a second type transistor OT, and a first electrode pattern 212 and a second electrode pattern 192 of the second type transistor OT are arranged at overlapping horizontally adjacent levels to capture hydrogen and prevent hydrogen from diffusing into the second type transistor LT.

[0154] The first electrode pattern 212 and the second electrode pattern 192 can be configured to overlap the first type gate electrode 173.

[0155] Furthermore, the gate connection metal layer 230 is disposed on the same layer as the first source-drain electrode 227 and the second source-drain electrode 228, extends to one side of the direction intersecting the first direction, and can be connected to the first gate electrode 173, the second electrode pattern 192 and the first electrode pattern 212 through the contact holes CT4, CT5 and CT6 in the insulating layers 124, 125, 126, 127 and 128 in the area that does not overlap with the first source-drain electrode 227 and the second source-drain electrode 228.

[0156] Specifically, the gate connection metal layer 230 is connected to the first gate electrode 173 through contact holes CT4 provided in the insulating films 124, 125, 126, 127 and 128. As shown in FIG9, a portion of the first gate electrode 173 connected to the gate connection metal layer 230 may protrude to one side more than each of the connection portions 212c and 129c of the first electrode pattern 212 and the second electrode pattern 192.

[0157] The gate connection metal layer 230 connects to the connection portion 192c of the second electrode pattern 192 exposed from the first electrode pattern 212 through the contact hole CT5 provided in the insulating films 126, 127 and 128. As shown in FIG9, the connection portion 212c of the first electrode pattern 212 may have an opening in the contact hole CT5, and the second electrode pattern 192 and the connection portion 192c of the gate connection metal layer 230 are connected to each other through the opening.

[0158] The gate connection metal layer 230 is connected to the connection portion 212c of the first electrode pattern 212 through the contact hole CT6 disposed in the eighth insulating film 128. As shown in FIG9, the connection portion 212c of the first electrode pattern 212 connected to the gate connection metal layer 230 can be connected through the contact hole CT6 disposed in a different region from the contact hole CT5, wherein the contact hole CT5 is the connection area between the connection portion 192c of the second electrode pattern 192 and the gate connection metal layer 230.

[0159] The gate connection metal layer 230 can be disposed on the same layer as the first source-drain electrode 227 and the second source-drain electrode 228.

[0160] Meanwhile, the gate driver (GIP) can cover the first type transistor LT and can be further protected by providing a first planarization film 131, a second planarization film 132, a dam 235 and a sealing layer 250.

[0161] As shown in Figures 5 and 10, in the display device according to the present disclosure embodiment, the configuration density of the first type transistor LT in the gate driver (GIP) can be higher than the configuration density of the second type transistor OT.

[0162] For ease of manufacturing, type I transistors LT and type II transistors OT of the same type can be formed close to each other.

[0163] Furthermore, as shown in Figure 5, gate drivers (GIPs) require many transistors that require high operating speeds, which allows for a higher configuration density of type 1 transistors LT with relatively high mobility than that of type 2 transistors OT with relatively low mobility.

[0164] A first electrode pattern 212 and a second electrode pattern 192 with hydrogen-capturing properties can be included in a first type transistor LT located around a second type transistor OT. The second type transistor OT contains a low-density oxide semiconductor to block the lateral diffusion of hydrogen. Specifically, the first electrode pattern 212 and the second electrode pattern 192 are positioned adjacent to the upper and lower portions of the active layer (see 201 and 202 in FIG. 4) of the second type transistor OT, and the second electrode pattern 192 and the first electrode pattern 212 are in direct contact with insulating films 126 and 127. The insulating films 126 and 127 can primarily introduce hydrogen to the active layers 201 and 202 of the second type transistor OT. The first electrode pattern 192 and the second electrode pattern 212 can have a hydrogen-capturing function to effectively block hydrogen diffusion. Therefore, the operational reliability of the second type transistor containing the oxide semiconductor can be improved.

[0165] By including a first type of transistor closer to the substrate and a second type of transistor further away from the substrate and including at least one electrode pattern on the first type of transistor, the technical challenge of the display device of the disclosed embodiment is to capture hydrogen from the adjacent insulating layer through the electrode pattern and prevent hydrogen from diffusing to the active layer of the adjacent second type of transistor.

[0166] The technical challenge of the display device of this disclosed embodiment is to block hydrogen transported horizontally to the second active layer by means of a first type transistor having a first active layer containing polycrystalline silicon and a second active layer containing oxide semiconductor, and an electrode pattern that overlaps with the first gate electrode of the first type transistor and is located in the upper and lower layers of the second active layer in a region where the arrangement density of the second type transistor is greater than that of the first type transistor.

[0167] In the display device of this disclosed embodiment, in order to prevent the active layer of the heterogeneous first-type transistor and the second-type transistor in the gate driver disposed on the substrate from becoming conductive, an electrode pattern is sequentially disposed on the same layer as the light-shielding pattern of the gate electrode and the second-type transistor above the gate electrode of the first-type transistor to capture hydrogen between the first-type transistor and the second-type transistor. This prevents the diffusion of hydrogen from horizontally transferring from the first-type transistor to the second-type transistor, prevents the shift of the critical voltage of the second-type transistor, minimizes the channel length margin of the second-type transistor, and improves driving stability.

[0168] In the display device of this disclosed embodiment, in order to prevent the active layer of the second type transistor in the gate driver of the substrate, which is heterogeneous, from becoming conductive, the electrode pattern of each layer located in the same layer as the gate electrode and light-shielding pattern of the second type transistor is sequentially arranged above the gate electrode of the first type transistor to capture hydrogen between the first type transistor and the second type transistor, thereby preventing the diffusion of hydrogen from the first type transistor to the second type transistor laterally.

[0169] The display device in this disclosed embodiment can electrically connect the electrode patterns disposed on the first type of transistor to each other to stabilize the potential, prevent the flow of hydrogen components, and improve the hydrogen capture effect, thereby ensuring the operational reliability of multiple transistors.

[0170] In the display device of this disclosed embodiment, the electrode pattern on the first type transistor prevents hydrogen diffusion in the second type transistor, which includes an oxide semiconductor, thereby preventing the problem of shortened effective channel length due to hydrogen diffusion. Therefore, it prevents the threshold voltage from shifting in the negative direction due to shortened effective channel length. In this way, the channel length margin of the second type transistor can be minimized, and driving stability can be improved.

[0171] The display device of this disclosed embodiment can further improve the reliability of the transistors disposed in the active layer containing oxide semiconductors in the active region by further including first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region.

[0172] The display device in this disclosed embodiment further includes first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region, thereby using a multi-wire structure to reduce the resistance of the power supply voltage lines.

[0173] The display device of this disclosed embodiment can form first and second connection patterns overlapping the electrode patterns and power supply voltage lines on the same layer as the light-shielding pattern and gate electrode of the second type transistor, thereby achieving device reliability without adding additional materials or manufacturing processes. In other words, the display device of this disclosed embodiment can achieve process optimization. Furthermore, since there are no additional processes, no processes that generate harmful gases are added, thereby reducing greenhouse gas emissions.

[0174] Furthermore, the display device of this disclosed embodiment can reduce the resistance in the power supply voltage line, thereby achieving high efficiency with the same power consumption, minimizing the increase in material costs, and having a sustainable effect, thus providing environmental advantages. Therefore, ESG (Environmental, Social, and Governance) goals can be achieved.

[0175] Figure 11 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0176] The same configuration as described in Figure 4 is omitted.

[0177] The first planarization film 131 may be configured to cover a first type transistor LT using polysilicon as an active layer 161, second type transistors OT1 and OT2 using oxide semiconductors as active layers 201 and 202, and a storage capacitor STC.

[0178] The second type transistors OT1 and OT2, which have different connection structures from the light-shielding patterns 171 and 191, can respectively perform the functions of switching transistors and driving transistors.

[0179] Furthermore, although not shown, the first type transistor LT and the second type transistor OT, which uses oxide semiconductor as the active layer, may be further contained within the non-active region NA. The second source-drain metal layer 234 in the first power supply voltage line VSSL may be configured to overlap with the first type transistor LT. The first power supply voltage line VSSL may be applied such that the driving function of the first type transistor LT can be shielded from the configuration above the light-emitting element ED. The first power supply voltage line VSSL may be configured to surround the active region AA in the non-active region NA and have a certain width, and may overlap with the first type transistor LT disposed in the gate driver GIP in part or all of that width.

[0180] The first power supply voltage line VSSL, to which a low-voltage drive signal is applied, may include a first connecting metal and a second connecting pattern (272 and 194 in Figures 6 and 7) that partially overlap and have a connection structure, and is disposed in the non-active region NA together with a first source-drain metal layer (229 in Figures 6 and 7) located on the same layer as the source-drain electrodes 222, 225, 226, 227 and 228 of the transistor.

[0181] On the first planarization layer 131, the second source-drain metal layers 231, 232 and 223 are configured using a conductive metal material to prevent the storage capacitor STC and the first oxide semiconductor transistor OT1 from being affected by the lower layer configuration and the driving effect of the upper layer configuration.

[0182] Meanwhile, the anode connection electrode 233 is configured to connect a source-drain electrode 226 of the second oxide semiconductor transistor OT2, which serves as a driving transistor in the second source-drain metal layer, so that the light-emitting element ED located above can be connected to the anode 241.

[0183] The second planarization layer 132 is disposed on the second source-drain metal layers 231, 232 and 233.

[0184] The first and second planarization layers 131 and 132 may contain organic materials. The organic materials may include one or more of the following: acrylic resin, phenolic resin, polyimide resin, unsaturated polyester resin, polyamide resin, phenylcyclobutene, polyphenylene ether resin, and polyphenylene sulfide resin.

[0185] In addition, the second planarization layer 132 provides contact holes to expose the anode connection electrode 233, and can be connected to a source-drain electrode 226 of the transistor OT2, which is a driving transistor, through the subsequently configured anode 241 and the anode connection electrode 233.

[0186] One of the anode 241 and cathode 243 of the light-emitting element ED may include a reflective electrode, and the other may include a transparent electrode or a reflective-transparent electrode.

[0187] When the anode 241 includes a reflective electrode, the anode 241 can block light from incident on the lower first and second type transistors T1 and T2. The anode 241 can be composed of, for example, a stacked structure of a first transparent electrode, a reflective electrode, and a second transparent electrode. The second transparent electrode is the uppermost electrode of the anode 241 and can reduce the hole injection barrier at the interface with the intermediate layer EL, which serves as the dielectric layer. Here, the first and second transparent electrodes can be transparent oxide electrodes, such as ITO and IZO. The reflective electrode can contain silver, silver alloys such as silver-palladium-copper (APC, Ag-Pd-Cu), aluminum, or aluminum alloys.

[0188] For example, the anode 241 may be formed of a multilayer structure, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), an APC (silver / palladium / copper) alloy, a stacked structure of APC alloy and ITO (ITO / APC / ITO), and a stacked structure of silver (Ag) and molybdenum / titanium alloy (MoTI), or may contain a single-layer structure composed of a material selected from silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca) or barium (Ba), or an alloy of two or more materials.

[0189] The embankment 135 is disposed around the edge of the anode 241 and extends into the inactive region NA, serving as an embankment pattern 225A in and around the curved region BA, and protecting the area around the curved region BA and the lower connecting pattern 235 in the curved region BA.

[0190] The embankment 135 that exposes the light-emitting area of ​​the anode 241 can be configured in each sub-pixel SP.

[0191] The embankment 135 may contain inorganic or organic materials. The embankment 135 may contain an opaque material (e.g., black) to prevent optical interference between adjacent sub-pixels SP. In this case, the embankment 135 may contain a light-masking material made of at least one of colored pigments, organic black, and carbon.

[0192] The intermediate layer 242 may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The intermediate layer 242 may be formed by configuring a multilayer stack including a hole transport layer, a light-emitting layer, and an electron transport layer, and may be formed as a series structure including charge generation layers between the stacks. The charge generation layers may include, for example, an n-type charge generation layer and a p-type charge generation layer.

[0193] The light-emitting layer in the intermediate layer 242 can vary for each sub-pixel. The light-emitting layer EL can include a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, and a blue light-emitting layer that emits blue light. The red, green, and blue light-emitting layers can be configured on the anode 241 for each sub-pixel SP.

[0194] For example, a red emitting layer can be patterned and configured as a red sub-pixel, a green emitting layer can be patterned and configured as a green sub-pixel, and a blue emitting layer can be patterned and configured as a blue sub-pixel. This disclosure is not limited thereto, and at least two or more organic emitting layers of the red, green, and blue emitting layers can be stacked and configured as a sub-pixel SP.

[0195] The emitting layer EL can be a white emitting layer that emits white light. In this case, the emitting layer EL can be in the form of a common layer, in which one or more layers are jointly configured in the sub-pixel SP, rather than in a patterned form.

[0196] As described above, the light-emitting layer 342 can be configured as a series structure of two or more stacked stacks. In this case, each light-emitting element ED can include a charge-generating layer disposed between the stacks. The charge-generating layer can be a common layer disposed on the entire surface of the active region AA.

[0197] The cathode 243 can be formed by thinning a transparent electrode such as ITO or IZO, or a reflective transparent electrode such as silver, silver alloy, magnesium, magnesium alloy, lanthanum (Yb), or lanthanum alloy. In another embodiment, to increase the transmittance of the penetrating portion TA, the material of the cathode 243 in the penetrating portion TA region can be partially removed, or it can be formed with a thinner thickness. The cathode 243 can be a common layer disposed across all the sub-pixels SP and subjected to the same voltage. For this purpose, the cathode 243 can be configured as a portion extending from the active region AA to the inactive region NA.

[0198] The cathode 243 can be a light-transmitting electrode. The cathode 243 can contain a transparent conductive material (TCO) that allows light to pass through, such as ITO or IZO, or a semi-transparent conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium and silver. When the cathode 243 is formed of a semi-transparent conductive material, the luminous efficiency can be improved by using a microcavity.

[0199] The above description uses a front-emitting light-emitting element (ED) as an example. However, the ED disclosed herein is not limited to this; it can also be a back-emitting light-emitting element (ED), in which light from the intermediate layer 242 is emitted toward the substrate 111. In this case, the anode 241 may contain a transparent or translucent electrode material, while the cathode 243 may contain a reflective electrode material.

[0200] A sealing layer 250 is disposed on the light-emitting element ED. The sealing layer 250 may cover the active region AA and the inactive region NA to prevent oxygen or moisture from penetrating into the light-emitting element ED. If necessary, other layers, such as a capping layer, may be disposed between the sealing layer 250 and the cathode 243.

[0201] The sealing layer 250 may comprise multiple layers. The sealing layer 250 may be formed as a structure having an inorganic thin film comprising an inorganic insulating material and an organic thin film comprising an organic insulating material, stacked alternately. For example, the inorganic insulating material may comprise one or more of silicon oxides, silicon nitrides, and / or silicon nitrides.

[0202] Organic insulating materials may include one or more materials selected from the following combinations: polyester terephthalate, naphthalene polyester terephthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0203] A capping layer (not shown) may be formed on the cathode 243 to protect the cathode 243 of the light-emitting element ED and improve the upward light emission efficiency.

[0204] The display device according to this embodiment improves the stability and reliability of the transistor disposed in the display device by increasing the configuration density of the metal layer having hydrogen capture function and surrounding the transistor containing oxide semiconductor, thereby capturing hydrogen components diffused into the oxide semiconductor layer from the surroundings.

[0205] By including a first type of transistor closer to the substrate and a second type of transistor further away from the substrate than the first type of transistor and including at least one electrode pattern on the first type of transistor, the technical challenge of the display device of the disclosed embodiment is to capture hydrogen from the adjacent insulating film through the electrode pattern and prevent hydrogen from diffusing to the active layer of the adjacent second type of transistor.

[0206] The technical challenge of the display device of this disclosed embodiment is to block hydrogen horizontally transported to the second active layer by means of a first type transistor having a first active layer containing polycrystalline silicon and a second active layer containing oxide semiconductor, and an electrode pattern that overlaps with the first gate electrode of the first type transistor and is located in the upper and lower layers of the second active layer in a region where the arrangement density of the second type transistor is greater than that of the first type transistor.

[0207] In the display device of this disclosed embodiment, in order to prevent the active layer of the second type transistor, which is heterogeneous and disposed in the gate driver of the substrate, from becoming conductive, each electrode pattern located on the same layer as the gate electrode and the light-shielding pattern of the second type transistor is sequentially arranged above the gate electrode of the first type transistor to capture hydrogen between the first type transistor and the second type transistor. This prevents the diffusion of hydrogen horizontally transmitted from the first type transistor to the second type transistor, prevents the critical voltage deviation of the second type transistor, minimizes the channel length margin of the second type transistor, and improves driving stability.

[0208] In the display device of this disclosed embodiment, in order to prevent the active layer of the second type transistor, which is heterogeneous and disposed between the gate driver of the substrate and the second type transistor, from becoming conductive, each electrode pattern located on the same layer as the gate electrode and the light-shielding pattern of the second type transistor is sequentially disposed above the gate electrode of the first type transistor to capture hydrogen between the first type transistor and the second type transistor, thereby preventing the diffusion of hydrogen horizontally transferred from the first type transistor to the second type transistor.

[0209] The display device of this disclosed embodiment can electrically connect the electrode patterns disposed on the first type of transistor to each other to stabilize the potential, prevent the flow of hydrogen components, improve the hydrogen capture effect, and thus ensure the operational reliability of multiple transistors.

[0210] The display device of this disclosed embodiment can prevent hydrogen diffusion in a second type transistor containing an oxide semiconductor by using the electrode pattern on the first type transistor, thereby preventing the problem of shortening of the effective channel length due to hydrogen diffusion. Therefore, it can prevent the threshold voltage from shifting negatively due to the shortening of the effective channel length. This minimizes the channel length margin of the second type transistor and improves driving stability.

[0211] The display device of this disclosed embodiment can further improve the reliability of the transistors comprising the active layer of oxide semiconductor disposed in the active region by further including first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region.

[0212] The display device of this disclosed embodiment further includes first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region, thereby using a multi-wire structure to reduce the resistance of the power supply voltage lines.

[0213] The display device of this disclosed embodiment can form first and second connection patterns overlapping the electrode patterns and power supply voltage lines on the same layer as the light-shielding pattern and gate electrode of the second type transistor, thereby achieving device reliability without adding additional materials or manufacturing processes. In other words, the display device of this disclosed embodiment can achieve process optimization. Furthermore, since there are no additional processes, no processes that generate harmful gases are added, thereby reducing greenhouse gas emissions.

[0214] Furthermore, the display device of this disclosed embodiment can reduce the resistance in the power supply voltage line, thereby achieving high efficiency with the same power consumption, minimizing the increase in material costs, and having a sustainable effect, thus providing environmental advantages. Therefore, ESG (Environmental, Social, and Governance) goals can be achieved.

[0215] By including a first type of transistor closer to the substrate and a second type of transistor further away from the substrate and including at least one electrode pattern on the first type of transistor, the technical challenge of the display device of the disclosed embodiment is to capture hydrogen from the adjacent insulating layer through the electrode pattern and prevent hydrogen from diffusing to the active layer of the adjacent second type of transistor.

[0216] The technical challenge of the display device of this disclosed embodiment is to block hydrogen transported horizontally to the second active layer by means of a first type transistor having a first active layer containing polycrystalline silicon and a second active layer containing oxide semiconductor, and an electrode pattern that overlaps with the first gate electrode of the first type transistor and is located in the upper and lower layers of the second active layer in a region where the arrangement density of the second type transistor is greater than that of the first type transistor.

[0217] In the display device of this disclosed embodiment, in order to prevent the active layer of the heterogeneous first-type transistor and the second-type transistor in the gate driver disposed on the substrate from becoming conductive, an electrode pattern located on the same layer as the light-shielding pattern of the gate electrode and the second-type transistor is sequentially arranged above the gate electrode of the first-type transistor to capture hydrogen between the first-type transistor and the second-type transistor. This prevents the diffusion of hydrogen from horizontally transferring from the first-type transistor to the second-type transistor, prevents the shift of the critical voltage of the second-type transistor, minimizes the channel length margin of the second-type transistor, and improves driving stability.

[0218] In the display device of this disclosed embodiment, in order to prevent the active layer of the second type transistor in the gate driver of the substrate, which is a heterogeneous first type transistor and a second type transistor, from becoming conductive, each electrode pattern located in the same layer as the gate electrode and light-shielding pattern of the second type transistor is sequentially arranged above the gate electrode of the first type transistor to capture hydrogen between the first type transistor and the second type transistor, thereby preventing the diffusion of hydrogen from the first type transistor to the second type transistor laterally.

[0219] The display device in this disclosed embodiment can electrically connect the electrode patterns disposed on the first type of transistor to each other to stabilize the potential, prevent the flow of hydrogen components, and improve the hydrogen capture effect, thereby ensuring the operational reliability of multiple transistors.

[0220] The display device in this disclosed embodiment can be electrically connected to the electrode pattern disposed on the first type of transistor to stabilize the potential, prevent hydrogen flow, and improve the hydrogen capture effect, thereby ensuring the operational reliability of multiple transistors.

[0221] In the display device of this disclosed embodiment, the electrode pattern on the first type transistor prevents hydrogen diffusion in the second type transistor, which includes an oxide semiconductor, thereby preventing the problem of shortened effective channel length due to hydrogen diffusion. Therefore, it prevents the threshold voltage from shifting in the negative direction due to shortened effective channel length. In this way, the channel length margin of the second type transistor can be minimized, and driving stability can be improved.

[0222] The display device of this disclosed embodiment can further improve the reliability of the transistors disposed in the active layer containing oxide semiconductors in the active region by further including first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region.

[0223] The display device in this disclosed embodiment further includes first and second connection patterns that overlap with and are electrically connected to the power supply voltage lines surrounding the active region, thereby using a multi-wire structure to reduce the resistance of the power supply voltage lines.

[0224] The display device of this disclosed embodiment can form first and second connection patterns overlapping the electrode patterns and power supply voltage lines on the same layer as the light-shielding pattern and gate electrode of the second type transistor, thereby achieving device reliability without adding additional materials or processes. In other words, the display device of this disclosed embodiment can achieve process optimization. Furthermore, since there are no additional processes, processes that generate harmful gases are not added, thereby reducing greenhouse gas emissions.

[0225] Furthermore, the display device of this disclosed embodiment can reduce the resistance in the power supply voltage line, thereby achieving high efficiency with the same power consumption, minimizing the increase in material costs, and having a sustainable effect, thus providing environmental advantages. Therefore, ESG (Environmental, Social, and Governance) goals can be achieved.

[0226] The display device according to an embodiment of this disclosure may include a substrate, the substrate including an active region and a non-active region, and power supply voltage lines and gate drivers disposed adjacent to each other in the non-active region of the substrate. The gate driver includes a first type transistor, wherein the first type transistor includes a first active layer on the substrate, a first gate insulating film on the first active layer, and a first gate electrode overlapping the first active layer and located on the first gate insulating film; and a second type transistor, wherein the second type transistor includes a second active layer located further away from the substrate than the first gate electrode, a second gate insulating film on the second active layer, a second gate electrode overlapping the second active layer and located on the second gate insulating film, and a first electrode pattern overlapping the first gate electrode and located on the second gate insulating film.

[0227] The display device according to the present disclosure embodiment may further include a second electrode pattern overlapping the first gate electrode, with a first dielectric insulating film closest to the second active layer sandwiched therebetween. At least the first dielectric insulating film and another dielectric insulating film are disposed between the second active layer and the first gate electrode.

[0228] According to the display device of the present disclosure embodiment, the first electrode pattern and the second electrode pattern may include hydrogen-capturing metal.

[0229] According to the display device of the present disclosure embodiment, the first electrode pattern may include metal located in the same layer as the second gate electrode.

[0230] According to the display device of the present disclosure embodiment, the first electrode pattern may include a stacked structure composed of a first titanium layer, an aluminum layer and a second titanium layer.

[0231] The display device according to the present disclosure embodiment may further include a first light-shielding pattern disposed below and overlapping the first active layer, and a second light-shielding pattern disposed below the first dielectric insulating film and overlapping the second active layer. The second electrode pattern may be located on the same layer as the second light-shielding pattern.

[0232] According to the display device of the present disclosure embodiment, the first light-shielding pattern may have the same potential as the first gate electrode.

[0233] According to the display device of the present disclosure embodiment, the second light-shielding pattern may have the same potential as the source-drain region of the second active layer.

[0234] In a display device according to one embodiment of this disclosure, the first electrode pattern and the second electrode pattern are electrically connected to each other.

[0235] In a display device according to one embodiment of this disclosure, the first electrode pattern may be electrically connected to the first gate electrode.

[0236] In a display device according to one embodiment of this disclosure, the first active layer may contain polycrystalline silicon semiconductor, and the second active layer may contain oxide semiconductor.

[0237] In a display device according to one embodiment of this disclosure, the configuration density of the first type of transistor can be greater than the configuration density of the second type of transistor in the gate driver.

[0238] In a display device according to one embodiment of this disclosure, a second type transistor may be surrounded by a first type transistor in a gate driver.

[0239] In a display device according to one embodiment of the present disclosure, the active area may include a plurality of sub-pixels, and each sub-pixel may include a third type transistor having an active layer comprising an oxide semiconductor.

[0240] In a display device according to one embodiment of the present disclosure, a first type transistor may include a first source-drain electrode and a second source-drain electrode that are separated from each other and connected to a first active layer, a second type transistor may include a third source-drain electrode and a fourth source-drain electrode that are separated from each other and connected to a second active layer, and the first to fourth source-drain electrodes may be located on the same layer as the power supply voltage line.

[0241] The display device according to one embodiment of the present disclosure may further include a first connection pattern configured to overlap with a power supply voltage line, and at least one insulating film sandwiched between the power supply voltage line and the first connection pattern, and a second connection pattern configured to overlap with the power supply voltage line, and a second gate insulating film and at least one dielectric insulating film sandwiched between the first connection pattern and the second connection pattern.

[0242] In a display device according to one embodiment of the present disclosure, the power supply voltage line can be connected to the first connection pattern through the first connection portion in at least one insulating film, and the power supply voltage line can be connected to the second connection pattern through the second connection portion, the second gate insulating film and at least one dielectric insulating film in at least one insulating film.

[0243] In a display device according to one embodiment of the present disclosure, each of the first connection pattern and the second connection pattern may contain a hydrogen-capturing metal.

[0244] A display device according to an embodiment of the present disclosure may include a substrate comprising an active region and a non-active region, a plurality of gate lines and a plurality of data lines intersecting each other in the active region, and a gate driver disposed in the non-active region of the substrate and connected to the plurality of gate lines. The gate driver may include a first type transistor comprising a first active layer on the substrate, a first gate insulating film on the first active layer, and a first gate electrode overlapping the first active layer and located on the first gate insulating film; a second type transistor comprising a second active layer and further away from the substrate than the first gate electrode, a second gate insulating film on the second active layer, and a second gate electrode overlapping the second active layer and located on the second gate insulating film, a first electrode pattern overlapping the first gate electrode and located on the second gate insulating film, a first dielectric insulating film between the second active layer and the first gate electrode; and a second electrode pattern overlapping the first gate electrode and sandwiched between the first dielectric insulating film.

[0245] A display device according to one embodiment of the present disclosure may further include a power supply voltage line adjacent to the gate driver and surrounding the active region in the non-active region.

[0246] In a display device according to one embodiment of the present disclosure, the active area includes sub-pixels located in the area where multiple gate lines and data lines intersect, and each sub-pixel has a light-emitting element at its position.

[0247] The display device according to one embodiment of the present disclosure may further include a first connection pattern configured to overlap with a power supply voltage line, wherein at least one insulating film is sandwiched between the power supply voltage line and the first connection pattern, and a second connection pattern configured to overlap with the power supply voltage line, wherein a second gate insulating film and a first dielectric insulating film are sandwiched between the first connection pattern and the second connection pattern.

[0248] In a display device according to one embodiment of the present disclosure, the power line can be connected to the first connection pattern through a first connection portion disposed in at least one insulating film, and the power line can be connected to the second connection pattern through a second connection portion disposed in at least one insulating film, a second gate insulating film and a first dielectric insulating film.

[0249] In a display device according to one embodiment of the present disclosure, each of the first connection pattern and the second connection pattern may contain a hydrogen-capturing metal.

[0250] In a display device according to one embodiment of this disclosure, each of the first electrode pattern and the second electrode pattern may contain a hydrogen-capturing metal.

[0251] In a display device according to one embodiment of this disclosure, the first electrode pattern may include metal located in the same layer as the second gate electrode.

[0252] The display device according to one embodiment of this disclosure may further include a first light-shielding pattern below and overlapping the first active layer, and a second light-shielding pattern below the first dielectric insulating film and overlapping the second active layer. A second electrode pattern may be located on the same layer as the second light-shielding pattern.

[0253] In a display device according to one embodiment of this disclosure, the first electrode pattern and the second electrode pattern can be electrically connected to each other.

[0254] In a display device according to one embodiment of this disclosure, the first active layer may comprise a polycrystalline silicon semiconductor, and the second active layer may comprise an oxide semiconductor.

[0255] The display device according to one embodiment of the present disclosure may further include a third type transistor located in the active region and including a third active layer located in the same layer as the second active layer.

[0256] A display device according to an embodiment of the present disclosure may include: a gate driver comprising a first type transistor, wherein the first type transistor comprises a first active layer of polysilicon, a first gate insulating film on the first active layer, a first gate electrode overlapping the first gate and located on the first gate insulating film and comprising a hydrogen-harvesting metal, and a first gate electrode on the first gate insulating film, a second type transistor comprising a second active layer of oxide semiconductor, and a second gate insulating film on the second active layer.

[0257] According to one embodiment of the present disclosure, the display device may further include a second electrode pattern above and sandwiched between a first electrode pattern and a second gate insulating film.

[0258] In a display device according to an embodiment of the present disclosure, a first electrode pattern and a second electrode pattern are electrically connected to each other.

[0259] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the appended claims and their equivalents.

[0260] 1000: Display device DL: Data Line GL: Gate line PAD: solder pad GIP: Gate Driver 110: Display panel A, B: Areas 111:Substrate AA: Active Zone NA: Non-active zone SP: Subpixel EVDD: High-potential drive voltage T2: Second transistor ED: Light-emitting element EVSS: Grounding voltage CC: Compensation circuit Cst: Storage capacitor N1: First node T1: First transistor NC: Node Controller STT1: Level NQ: Pull-up node NQB: Drop-down node CL: Clock Line TU: Pull-up transistor OT: Transistor TD: Pull-down transistor VGLT: Gate Low Voltage Terminal 221ec: Extension 221: Connecting electrode 210: Gate electrode 222: Source-Drain Electrode 211: Third gate electrode 212: First electrode pattern 192: Second electrode pattern CT1, CT2, CT3, CT4, CT5, CT6, CT7: Contact holes 121~128: Inorganic insulating film 111:Substrate 111c: Second substrate 111b: Inorganic mesolayer membrane 111a: First substrate 174: First gate electrode extension 151: First light-blocking pattern 161: First Active Layer 173: First gate electrode 202: Third Active Layer 191: Third light occlusion pattern 172: First storage electrode 181: Second storage electrode 201: Second Active Layer 171: Second light-masking pattern OT1: First Oxide Semiconductor Transistor STC: Storage Capacitor OT2: Second Oxide Semiconductor Transistor LT: Type I transistor VSSL: First power voltage line 229: First source-drain metal layer 194: Second connecting pattern 131: First planarization film 132: Second planarization film 135: Embankment 235: Connecting Patterns 250: Sealing layer 234: Second source-drain metal layer 272: First connecting pattern 230: Gate connection metal layer 212c, 192c: Connecting part 272a: Opening 193: Gate electrode 241: Anode 242: Intermediate Layer 243: Cathode 231, 232, 233: Second source-drain metal layer

Claims

1. A display device comprising: a substrate including an active region and a non-active region; and a power supply voltage line and a gate driver disposed on the non-active region of the substrate and adjacent to each other, wherein the gate driver comprises: a first type transistor including a first active layer on the substrate, a first gate insulating film located above the first active layer, and a first gate electrode overlapping the first active layer and located on the first gate insulating film; a second type transistor including a second active layer located further away from the substrate than the first gate electrode, a second gate insulating film located on the second active layer, and a second gate electrode overlapping the second active layer and located above the second gate insulating film; a first electrode pattern overlapping the first gate electrode and located above the second gate insulating film; and a first light-shielding pattern disposed below the first active layer and overlapping the first active layer.

2. The display device according to claim 1 further includes a second electrode pattern, the second electrode pattern overlapping the first gate electrode through a first dielectric insulating film and sandwiched between the first dielectric insulating film, the first dielectric insulating film being the most adjacent to the second active layer, wherein at least the first dielectric insulating film and another dielectric insulating film are disposed between the second active layer and the first gate electrode.

3. The display device according to claim 2, wherein the first electrode pattern and the second electrode pattern comprise a hydrogen-capturing metal.

4. The display device according to claim 1, wherein the first electrode pattern comprises a metal located in the same layer as the second gate electrode.

5. The display device according to claim 1, wherein the first electrode pattern comprises a stacked layer of a first titanium layer, an aluminum layer, and a second titanium layer.

6. The display device according to claim 2 further includes a second light-shielding pattern disposed below the first dielectric insulating film and overlapping the second active layer, wherein the second electrode pattern is located in the same layer as the second light-shielding pattern.

7. The display device according to claim 1, wherein the potential of the first light-shielding pattern is the same as the potential of the first gate electrode.

8. The display device according to claim 6, wherein the potential of the second light-shielding pattern is the same as the potential of a source-drain region of the second active layer.

9. The display device according to claim 2, wherein the first electrode pattern is electrically connected to the second electrode pattern.

10. The display device according to claim 1, wherein the first electrode pattern is electrically connected to the first gate electrode.

11. The display device according to claim 1, wherein: the first active layer comprises a polysilicon semiconductor, and the second active layer comprises an oxide semiconductor.

12. The display device according to claim 11, wherein in the gate driver, the arrangement density of the first type of transistor is greater than the arrangement density of the second type of transistor.

13. The display device according to claim 11, wherein in the gate driver, the second type transistor is surrounded by the first type transistor.

14. The display device according to claim 1, wherein: The active region includes a plurality of sub-pixels, and each of the sub-pixels contains a third-type transistor having an active layer comprising an oxide semiconductor.

15. The display device according to claim 1, wherein: The first type of transistor includes a first source-drain electrode and a second source-drain electrode, which are separate from each other and connected to the first active layer. The second type of transistor includes a third source-drain electrode and a fourth source-drain electrode, which are separate from each other and connected to the second active layer. The first source-drain electrode, the second source-drain electrode, the third source-drain electrode and the fourth source-drain electrode are located on the same layer as the power supply voltage line.

16. The display device according to claim 15 further includes a first connection pattern disposed overlapping the power supply voltage line, and at least one insulating film sandwiched between the power supply voltage line and the first connection pattern, and a second connection pattern disposed overlapping the power supply voltage line, and the second gate insulating film and at least one dielectric insulating film sandwiched between the first connection pattern and the second connection pattern.

17. The display device according to claim 16, wherein: The power supply voltage line is connected to the first connection pattern through a first connection portion in at least one layer of insulating film, and the power supply voltage line is connected to the second connection pattern through a second connection portion in at least one layer of insulating film, the second gate insulating film, and at least one layer of dielectric insulating film.

18. The display device according to claim 16, wherein each of the first connection pattern and the second connection pattern comprises a hydrogen-capturing metal.

19. A display device comprising: a substrate including an active region and a non-active region, wherein a plurality of gate lines and a plurality of data lines are located in the active region and intersect each other; and a gate driver disposed in the non-active region of the substrate and connected to the gate lines, wherein the gate driver comprises: a first type transistor including a first active layer on the substrate, a first gate insulating film located on the first active layer, and a first gate electrode overlapping the first active layer and located on the first gate insulating film; and a second type transistor. It includes a second active layer located further away from the substrate than the first gate electrode, a second gate insulating film located on the second active layer, a second gate electrode overlapping the second active layer and located on the second gate insulating film, a first electrode pattern overlapping the first gate electrode and located on the second gate insulating film, a first dielectric insulating film located between the second active layer and the first gate electrode, and a second electrode pattern overlapping the first gate electrode, with the first dielectric insulating film sandwiched therebetween.

20. The display device according to claim 19 further includes a power supply voltage line adjacent to the gate driver and surrounding the active region in the non-active region.

21. The display device according to claim 20, wherein: The active region comprises sub-pixels in areas where multiple gate lines intersect with data lines, and each sub-pixel has a light-emitting element; and the power supply voltage line is electrically connected to the cathode electrode of the light-emitting element.

22. The display device according to claim 20 further includes a first connection pattern disposed overlapping the power supply voltage line and having at least one insulating film sandwiched between the power supply voltage line and the first connection pattern, and a second connection pattern disposed overlapping the power supply voltage line and having the second gate insulating film and the first dielectric insulating film sandwiched between the first connection pattern and the second connection pattern.

23. The display device according to claim 22, wherein: The power supply voltage line is connected to the first connection pattern through a first connection portion provided in at least one insulating film, and the power supply voltage line is connected to the second connection pattern through a second connection portion provided in at least one insulating film, the second gate insulating film, and the first dielectric insulating film.

24. The display device according to claim 22, wherein each of the first connection pattern and the second connection pattern comprises a hydrogen-added metal.

25. The display device according to claim 19, wherein each of the first electrode patterns and the second electrode pattern comprises a hydrogen-added metal.

26. The display device according to claim 19, wherein the first electrode pattern comprises a metal located on the same layer as the second gate electrode layer.

27. The display device according to claim 19 further comprises: a first light-shielding pattern located below and overlapping the first active layer; and a second light-shielding pattern located below the first dielectric insulating film and overlapping the second active layer, wherein the second electrode pattern is located on the same layer as the second light-shielding pattern.

28. The display device according to claim 19, wherein the first electrode pattern is electrically connected to the second electrode pattern.

29. The display device according to claim 19, wherein: the first active layer comprises a polysilicon semiconductor, and the second active layer comprises an oxide semiconductor.

30. The display device according to claim 19 further includes a third type transistor, the third type transistor including a third active layer located in the active region of the same layer as the second active layer.

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