Semiconductor device and communication method thereof

Abstract

In one or more embodiments, the semiconductor device includes processing circuitry and N signal paths corresponding to N communication channels. The processing circuitry is configured to acquire channel defect information, which indicates L defective channels or NL functional channels among the N communication channels; employ a remapping configuration corresponding to a flit protocol format with M rows and N data units, and a flit reassembly format with M+R rows and NL data units; acquire a target flit in the flit protocol format, and transmit the data units of the target flit through the NL functional channels based on the flit reassembly format; or receive the data units of the target flit through the NL functional channels based on the flit reassembly format, and acquire the target flit in the flit protocol format.

Description

Technical Field

[0001] This invention relates to semiconductors, and more particularly to semiconductor devices and communication methods thereof. Prior Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have driven the development of multiple generations of IC devices. Each generation of ICs features smaller and more complex circuitry than its predecessor. For example, throughout the history of IC development, functional density (i.e., the number of interconnects per die area) has generally increased, while geometric dimensions (i.e., the smallest components (or lines) that can be manufactured using a process) have decreased. This scaling down process typically offers advantages through increased production efficiency and reduced associated costs. Consequently, these advancements have increased the complexity of handling and manufacturing IC devices.

[0003] In some applications, semiconductor devices (e.g., IC devices) comprise multiple semiconductor wafers or circuit modules packaged within an IC package. Different wafers or circuit modules may be designed by different IC design companies and / or manufactured using different manufacturing technologies (or nodes). This allows the overall design of the semiconductor device to be broken down into smaller projects, accelerating the design process and / or optimizing each wafer for its corresponding function. In some applications, semiconductor wafer circuit modules within a semiconductor device are configured to transmit and receive data from another semiconductor wafer circuit module through corresponding die-to-die (D2D) communication paths to work collaboratively. When such D2D communication paths in a semiconductor device become defective after the semiconductor device is installed in the electronic device, it is not feasible to remove the IC package to repair the defective communication paths. In some applications, such as automobiles, defective communication paths can lead to safety or reliability issues, affecting normal vehicle operation and / or potentially causing serious data loss or fatal accidents. Summary of the Invention

[0004] According to some embodiments disclosed herein, a semiconductor device is provided, including processing circuitry and N signal paths corresponding to N communication channels, where N is a positive integer. In some embodiments, the processing circuitry is coupled to the N signal paths and configured to acquire channel defect information, which indicates L defective channels out of the N communication channels, or NL functional channels out of the N communication channels, where L is 0 or a positive integer. The processing circuitry is configured to, based on L being greater than 0 and based on the channel defect information, employ a remapping configuration corresponding to the mapping relationship between the Flit protocol format and the Flit reconstructed format, where the Flit protocol format has N data units in M ​​rows and the Flit reconstructed format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. The processing circuit is configured to obtain the target flit in the flit protocol format based on L being greater than 0 and based on the remapping configuration, and transmit the data unit of the target flit through NL functional channels based on the flit reassembly format; or receive the data unit of the target flit through NL functional channels based on the flit reassembly format and obtain the target flit in the flit protocol format.

[0005] According to some embodiments disclosed herein, a communication method is provided, executed in a processing circuit of a semiconductor device, comprising acquiring channel defect information, wherein the channel defect information indicates L defective channels out of N communication channels accessible by the processing circuit, or NL functional channels out of N communication channels, where N is a positive integer and L is 0 or a positive integer. The method includes, based on L being greater than 0 and based on the channel defect information, employing a remapping configuration corresponding to the mapping relationship between the flit protocol format and the flit reconstructed format, wherein the flit protocol format has N data units in M ​​rows, and the flit reconstructed format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. The method includes, based on L being greater than 0 and based on the remapping configuration, acquiring a target flit in the flit protocol format, and transmitting the data units of the target flit through the NL functional channels based on the flit reconstructed format; or, based on the flit reconstructed format, receiving the data units of the target flit through the NL functional channels, and acquiring the target flit in the flit protocol format.

[0006] According to other embodiments disclosed herein, a semiconductor device is provided, comprising a dynamic remapping circuit, a protocol circuit, and a front-end circuit, configured to transmit or receive data units of a target flit through N communication channels, where N is a positive integer. In some embodiments, the dynamic remapping circuit is coupled to the protocol circuit and the front-end circuit, and the dynamic remapping circuit is configured to acquire channel defect information, which indicates L defective channels out of the N communication channels, or NL functional channels out of the N communication channels, where L is 0 or a positive integer. The dynamic remapping circuit is configured to employ a remapping configuration corresponding to the mapping relationship between the flit protocol format and the flit reassembled format, based on L being greater than 0 and based on the channel defect information, where the flit protocol format has N data units in M ​​rows, and the flit reassembled format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. The dynamic remapping circuit is configured to receive the target flit in the flit protocol format from the protocol circuit based on L being greater than 0 and based on the remapping configuration, and transmit the data unit of the target flit through NL functional channels based on the flit reassembly format; or to receive the data unit of the target flit through NL functional channels based on the flit reassembly format and transmit the target flit in the flit protocol format to the protocol circuit. Simple Explanation of the Diagram

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a block diagram of a semiconductor device according to various embodiments. Figure 2 is a protocol stack diagram of various embodiments of the die-to-die (D2D) interconnect protocol. Figure 3 is a functional block diagram of physical layer circuit examples according to various embodiments. Figure 4 is a flowchart illustrating the various operations performed through the first and second processing circuits according to various embodiments. Figure 5A is a diagram illustrating an example of a flow control unit (flit) protocol format based on the Universal Chiplet Interconnect Express (UCIe) standard according to various embodiments. Figure 5B is a diagram illustrating an example of a flit recombination format derived from the flit protocol format of Figure 5A based on a first-level mapping scheme according to various embodiments. Figure 5C is a diagram illustrating an example of a flit recombination format derived from the flit protocol format of Figure 5A based on a second-mapping scheme according to various embodiments. Figure 6A is a block diagram of a shift register group for converting data units in the flit protocol format of Figure 5A to the flit reconstructed format of Figure 5B, according to various embodiments. Figure 6B is a block diagram of the control logic of the shift register group in Figure 6A according to various embodiments, and of the component register examples of the shift register group in Figure 6A. Figure 7A is a diagram of a repair register for storing data units corresponding to target flits of defective channels (lanes) according to various embodiments. Figures 7B and 7C are diagrams of various multiplexer examples that can be used in conjunction with the repair register in Figure 7A to convert data units in the flit protocol format in Figure 5A to the flit reconstructed format in Figure 5C, according to various embodiments. Figure 8 is a flowchart of communication methods according to various embodiments. Implementation

[0008] To achieve the various features of the provided object, this disclosure will provide many different embodiments or examples. The specific examples of elements and layouts described below are for simplification purposes. Of course, these are merely examples and not intended to be limiting. For example, the formation of a first feature beyond or on a second feature may include embodiments where the first and second features are formed through direct contact, and may include embodiments where additional features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, this disclosure may repeat figures and / or letters in various examples. This repetition is for simplicity and clarity and does not define the relationships between the various embodiments and / or configurations discussed.

[0009] In addition, spatial terms may be used here, such as “at the bottom of,” “below,” “lower,” “above,” “upper,” etc., to describe the relationship between an element or feature and another element or feature depicted in the figure. Apart from the orientations shown in the figure, spatial terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and spatial descriptions used herein may be translated according to their meaning. Furthermore, the term “formed by” may mean “comprising” or “consisting of.” In this disclosure, “one of A, B, and C” means “A, B, and / or C” (A; B; C; A and B; A and C; B and C; A, B, and C), and does not mean one of the elements from A, one of the elements from B, and one of the elements from C, unless otherwise stated.

[0010] In some embodiments, data communication between two semiconductor wafers or circuit modules is implemented based on a communication lane. Within each transmission session, data units (e.g., bytes) of a flow control unit (flit) are transmitted in one or more sessions or cycles (e.g., rows) across multiple lanes. A communication standard paradigm for such applications is the Universal Chipplet Interconnect Express (UCIe) standard. In some embodiments, the communication lane is configured with redundant lanes that can be used in the event that one or more communication lanes are defective.

[0011] In some embodiments, defective channels are identified, and the data width (e.g., the number of channels used for transmission) is dynamically adjusted. In one or more embodiments of this disclosure, by dynamically adjusting the flit format, fewer communication channels are used in die-to-die (D2D) communication to avoid defective communication channels, thereby protecting the reliability of data transmission. In some embodiments, the communication method of dynamically adjusting the flit format to utilize fewer communication channels, as provided in this disclosure, can be applied not only to D2D communication but also to other types of multi-channel communication between chips, processing circuit modules, IC devices, etc. In some embodiments, the communication method of dynamically adjusting the flit format to utilize fewer communication channels, as provided in this disclosure, can be used alone or in conjunction with channel repair based on redundant channels.

[0012] Figure 1 is a block diagram of a semiconductor device 100 according to various embodiments. In some embodiments, the semiconductor device 100 is an IC device comprising elements packaged in an integrated circuit (IC) package. The semiconductor device 100 includes a first processing circuit 110 and a second processing circuit 120. In some embodiments, the first processing circuit 110 is a semiconductor wafer or processing circuit module in the semiconductor device 100. In some embodiments, the second processing circuit 120 is another semiconductor wafer or another processing circuit module in the semiconductor device 100. In some embodiments, the semiconductor device 100 includes one or more additional wafers or circuit modules not shown in Figure 1. In some embodiments, the first processing circuit 110 and the second processing circuit 120 within the IC package of the semiconductor device 100 are semiconductor wafers, also referred to as "chiplets". In some embodiments, the first processing circuit 110 and the second processing circuit 120 are a first chip and a second chip, and are configured based on 2D packaging technology (e.g., the first chip and the second chip are mounted on a common packaging substrate), 2.5D packaging technology (e.g., the first chip and the second chip are mounted on a common interposer on the packaging substrate), or 3D packaging technology (e.g., the first chip and the second chip are stacked on top of each other and mounted on a packaging substrate with or without an interposer), and are electrically coupled to each other.

[0013] In some embodiments, the first processing circuit 110 and the second processing circuit 120 correspond to a semiconductor wafer having digital circuitry, analog circuitry, mixed-mode circuitry, and / or memory formed on a semiconductor wafer. In some embodiments, each of the first processing circuit 110 and the second processing circuit 120 corresponds to one or more central processing units (CPUs), application processors (APs), systems on chips (SOCs), application-specific integrated circuits (ASICs), dynamic random access memory (DRAM) wafers, static random access memory (SRAM) wafers, micro-electro-mechanical systems (MEMS) wafers, etc.

[0014] In the example of Figure 1, the first processing circuit 110 includes a D2D communication interface 112, and the second processing circuit 120 includes a D2D communication interface 122. In some embodiments, the first processing circuit 110 and the second processing circuit 120 are configured to communicate with each other in the semiconductor device 100 through the D2D communication interfaces 112 and 122. In some embodiments, the communication between the D2D communication interfaces 112 and 122 is based on a D2D interconnect protocol, such as a protocol based on the UCIe standard, a protocol based on the Bunch of Wires (BoW) standard, a proprietary protocol, etc.

[0015] Figure 2 is a protocol stack diagram of a D2D interconnect protocol 200 according to various embodiments. In some embodiments, the D2D interconnect protocol 200 is illustrated as a non-limiting example. In some embodiments, the D2D interconnect protocol corresponds to a protocol stack that does not include all protocol layers in the protocol stack diagram. In some embodiments, the D2D interconnect protocol corresponds to a protocol stack that includes one or more additional protocol layers in the protocol stack diagram. In some embodiments, as a non-limiting example, the D2D interconnect protocol 200 corresponds to a UCIe-based D2D interconnect protocol. In some embodiments, the D2D interconnect protocol 200 can be used to implement communication between chips in an IC device. In some embodiments, the D2D interconnect protocol 200 can be used to implement communication between processing circuit modules in a chip, or between IC devices.

[0016] In Figure 2, the D2D interconnect protocol 200 includes a protocol layer 210, a D2D adapter 220, and a physical layer 230. Protocol layer 210 and D2D adapter 220 are configured to communicate with each other through a flow control unit (flit) aware D2D interface 215. D2D adapter 220 and physical layer 230 are configured to communicate with each other through a raw D2D interface 225. In some embodiments, protocol layer 210 corresponds to a communication protocol based on the Peripheral Component Interconnect Express (PCIe) standard, the Compute Express Link (CXL) standard, or a proprietary communication standard.

[0017] In Figure 2, the D2D adapter 220 corresponds to the operation of bridging data to / from the protocol layer 210 and the physical layer 230, enabling the physical layer 230 to operate with different types of communication protocols of the protocol layer 210. In some embodiments, the D2D adapter 220 is configured to manage data transmission between the protocol layer 210 and the physical layer 230, including data format conversion, link state management, error correction management, retry management, parameter adjustment, arbitration, and / or multiplexing between two or more protocols supported by the protocol layer 210.

[0018] In some embodiments, the semiconductor wafer includes protocol circuitry configured to perform the operations of the D2D adapter 220 and the protocol layer 210. In some embodiments, the D2D interconnect protocol does not define a D2D adapter, but rather defines a protocol layer that combines the operations of the D2D adapter 220 and the protocol layer 210 in Figure 2.

[0019] In some embodiments, physical layer 230 is configured to transmit and receive electronic signals to perform data transfer with another semiconductor device or processing circuit module through multiple signal paths. In some embodiments, each signal path is configured to carry information of one data unit (e.g., a byte) and is referred to as a "communication channel" or "lane". In Figure 2, physical layer 230 includes physical layer logic 232, an electronic / analog front end 234, and sidebands 236. In some embodiments, the electronic / analog front end 234 is configured to transmit and receive flit to / from another semiconductor chip or processing circuit module, and the sidebands 236 are configured to transmit and receive control information to / from another semiconductor chip or processing circuit module. In some embodiments, the front end 234 and sideband 236 of the electronic / analog circuit include conductive terminals (e.g., bumps), transmitters and / or receivers coupled to the conductive terminals, and multiplexers coupled to the transmitters and / or receivers for selectively reconfiguring the pin configuration of the conductive terminals for repairing one or more defective channels.

[0020] In some embodiments, based on the UCIe standard, the electronic / analog front-end 234 is configured to communicate via 64 data channels for transmission, 64 data channels for reception, one valid data channel for transmission, one valid data channel for reception, two clock channels for transmitting differential clock signals, two clock channels for receiving differential clock signals, one tracking signal channel for transmission, and one tracking signal channel for reception. In some embodiments, based on the UCIe standard, the electronic / analog front-end 234 is further configured to communicate via redundant channels for channel repair when needed, including four redundant data channels for transmission, four redundant data channels for reception, one redundant valid data channel for transmission, one redundant valid data channel for reception, one redundant clock channel for transmission, and one redundant clock channel for reception.

[0021] In some embodiments, based on the UCIe standard, sideband 236 may be configured to communicate via a data channel for transmission, a data channel for reception, a clock channel for transmission, and a clock channel for reception. In some embodiments, based on the UCIe standard, sideband 236 is further configured to communicate via redundant channels for channel repair when needed, including a redundant data channel for transmission, a redundant data channel for reception, a redundant clock channel for transmission, and a redundant clock channel for reception.

[0022] In some embodiments, the entity layer logic 232 is configured to coordinate the operation of the electronic / analog front-end 234 and sideband 236 to perform operations including link initialization, link training, channel repair, channel reversal, data scrambling or descrambling, sideband training, and sideband transmission. In some embodiments, redundancy is achieved by configuring multiple channels to skip defective channels and reuse / remap other functional channels along with one or more redundant channels to compensate for the deficiencies of defective channels. In some embodiments, a series of shuffling multiplexer settings are required to shift or redirect data paths to remanded channels.

[0023] However, some cases of channel repair based on redundant channels are not feasible. In some examples, the implemented semiconductor wafer does not have redundant channels for channel repair. In some examples, the semiconductor wafer has used all available redundant channels for channel repair, and still has one or more defective channels. In such cases, according to one or more embodiments of this disclosure, by dynamically adjusting the flit format for D2D communication using fewer communication channels to avoid defective communication channels, the reliability of data transmission can still be protected. In some embodiments, communication based on dynamically adjusting the flit format to utilize fewer communication channels, as shown in this disclosure, can be used not only for D2D communication, but also for any multi-channel communication between wafers, processing circuit modules, IC devices, etc. In some embodiments, communication based on dynamically adjusting the flit format to utilize fewer communication channels, as provided in this disclosure, can be used alone or in conjunction with channel repair based on redundant channels.

[0024] Figure 3 is a functional block diagram of the physical layer circuit 300 according to various embodiments. In some embodiments, the physical layer circuit 300 is configured to implement the operation of the physical layer 230 in Figure 2. In some embodiments, the physical layer circuit 300 is part of a processing circuit (e.g., a semiconductor wafer) and is configured to communicate with another processing circuit (e.g., another semiconductor wafer) based on a D2D interconnect protocol as illustrated in Figure 2.

[0025] In Figure 3, the physical layer circuit 300 includes a physical layer logic circuit 310 corresponding to physical layer logic 232, a front-end circuit 320 corresponding to the electronic / analog front-end 234, and a sideband circuit 330 corresponding to the sideband 236. In Figure 3, the physical layer logic circuit 310 is configured to communicate with the protocol circuit 303 (e.g., corresponding to the protocol layer 210 in Figure 2, directly or indirectly through the D2D adapter 220) (as shown by arrow 302).

[0026] In Figure 3, the front-end circuitry 320 includes multiple signal paths coupled to multiple conductive terminals 322 (e.g., bumps), and these signal paths correspond to multiple data channels, clock channels, and signal channels (collectively referred to as communication channels 324) for D2D communication. In some embodiments, the communication channels 324 include at least N communication channels serving as data channels, where N is a positive integer. In some embodiments, the front-end circuitry 320 is configured to communicate with another processing circuitry 305 (e.g., another semiconductor chip) through the data channels and associated clock and signal channels (as indicated by arrow 304).

[0027] In Figure 3, the sideband circuit 330 also includes multiple signal paths coupled to multiple conductive terminals 332 (e.g., bumps), and these signal paths correspond to one or more sideband data channels, sideband clock channels, and sideband signal channels (collectively referred to as sideband communication channels 334) for control information related to D2D communication through the front-end circuit 320. In some embodiments, the sideband circuit 330 is configured to communicate with another processing circuit 305 (as indicated by arrow 306) through one or more sideband data channels and associated sideband clock and signal channels via a control interface.

[0028] In some embodiments, the data units of a flit are transmitted or received in accordance with the flit protocol format. In some embodiments, the data units of a flit are configured in N vertical columns corresponding to N communication channels and M horizontal columns corresponding to M transmit or receive sessions or cycles, wherein the M transmit or receive sessions or cycles are performed by the N communication channels. In some embodiments, each data unit corresponds to a byte.

[0029] In Figure 3, the physical layer logic circuit 310 includes a dynamic remapping circuit 312 and a channel defect detection circuit 314. In some embodiments, the dynamic remapping circuit 312 is coupled to the protocol processing circuit 303, the front-end circuit 320, the sideband circuit 330, coupled through the front-end circuit 320 to the communication channel 324, and coupled through the sideband circuit 330 to the sideband communication channel 334. In some embodiments, the dynamic remapping circuit 312 is configured to acquire channel defect information indicating L defective channels out of N communication channels, or NL functional channels out of N communication channels, where L is 0 or a positive integer. In this example, two communication channels 326 are defective (e.g., L=2 in Figure 3). In some embodiments, the dynamic remapping circuit 312 is configured to acquire channel defect information from the channel defect detection circuit 314. In some embodiments, channel defect information is generated by channel defect detection circuit 314, or received by channel defect detection circuit 314 from another processing circuit 305 via sideband communication channel 334 through control interface (e.g., sideband circuit 330).

[0030] In some embodiments, based on L being greater than 0 and based on channel defect information, the dynamic remapping circuit 312 employs a remapping configuration corresponding to the mapping relationship between a flit protocol format with M rows and N data units and a flit reassembly format with M+R rows and NL data units, where M is a positive integer and R is a positive integer representing additional rows used for channel repair. In some embodiments, N represents the number of communication channels per transmission session / cycle based on the flit protocol format, and M represents the number of rows or transmission sessions / cycles based on the flit protocol format. In some embodiments, data units are transmitted in each communication channel per transmission session / cycle. In some embodiments, R represents the number of additional rows corresponding to the number of additional transmission sessions / cycles, where the additional transmission sessions / cycles can be used to compensate for the insufficient transmission capacity caused by L defective channels. In some embodiments, each data unit corresponds to a byte, and N ranges from 32 to 128, M ranges from 1 to 8, and R ranges from 1 to 4. In some embodiments, based on the UCIe standard, each data unit corresponds to a byte, where N is 64, M is 4, and R is 1.

[0031] In some embodiments, based on L being greater than 0 and based on the remapping configuration, the dynamic remapping circuit 312 is configured to obtain the target flit in the flit protocol format and, based on the flit reassembly format, transmit the data units of the target flit to another processing circuit 305 through NL functional channels. In some embodiments, based on L being greater than 0 and based on the remapping configuration, the dynamic remapping circuit 312 is configured to receive the data units of the target flit from another processing circuit 305 through NL functional channels based on the flit reassembly format and obtain the target flit for the protocol circuit 303 based on the flit protocol format. In some embodiments, based on the UCIe standard, the target flit corresponds to a 256-byte flit.

[0032] In some embodiments, according to the first mapping scheme, the mapping relationship corresponds to sequentially mapping N data units in M ​​columns of the Flit protocol format to NL data units in M+R columns of the Flit reconstructed format. In some embodiments, according to the second mapping scheme, the mapping relationship corresponds to mapping NL data units in M ​​columns of the Flit protocol format corresponding to NL functional channels to NL data units in M ​​columns of the Flit reconstructed format (total) based on the original columns and channel allocation in the Flit protocol format, and mapping M×L data units in the Flit protocol format corresponding to L defective channels to a maximum of R additional columns in the Flit reconstructed format.

[0033] In some embodiments, with L set to 0 (i.e., indicating no defective channels), transmission can be performed based on the flit protocol format without arbitrary remapping configuration.

[0034] Figure 4 is a process flow diagram 400 of various operations performed through the first processing circuit 402 and the second processing circuit 406 according to various embodiments. In some embodiments, the first processing circuit 402 and the second processing circuit 406 correspond to the semiconductor wafer or processing circuit incorporated in Figure 3 as the physical layer circuit 300 and the protocol circuit 303. In some embodiments, the first processing circuit 402 and the second processing circuit 406 correspond to the semiconductor wafer or processing circuit incorporated in Figure 3 as the processing circuit 305.

[0035] In Figure 4, at stage 410, the first processing circuit 402 receives data transmissions from the second processing circuit 406 based on the D2D interconnect protocol. In this example, data transmissions are performed in a flit based on the flit protocol format layout and on N communication channels. In some embodiments, the first processing circuit 402 detects some corrupted or undecodeable flits from stage 410. Therefore, at stage 412, the first processing circuit 402 sends a data retransmission request to the second processing circuit 406, requesting the retransmission of the corrupted flits. In stage 414, in response to the data retransmission request, the second processing circuit 406 performs data retransmission based on the D2D interconnect protocol. In some embodiments, at least k (k is a positive integer) data retransmissions in stage 414 are performed based on the D2D interconnect protocol.

[0036] In Figure 4, after stage 414, although a retransmission was performed in stage 414, the first processing circuit 402 still cannot receive or decode all the damaged flits. Then, in stage 422, the first processing circuit 402 transmits a defect detection mode request to the second processing circuit 406, requesting the transmission of the defect detection mode. In some embodiments, the defect detection mode includes one or more test flits for identifying one or more defective communication channels among N communication channels. In stage 424, the second processing circuit 406 transmits one or more test flits to the first processing circuit 402 through the N communication channels. Furthermore, in stage 424, the first processing circuit 402 receives one or more test flits from the second processing circuit 406 through the N communication channels.

[0037] In stage 430, the first processing circuit 402 identifies L defective channels or NL functional channels out of N communication channels based on one or more received test flits. In stage 442, the first processing circuit 402 transmits channel defect information to the second processing circuit 406 through its control interface (e.g., sideband circuit 330 and sideband communication channel 334). Furthermore, the second processing circuit 406 receives the channel defect information from the first processing circuit 402 through its control interface. In some embodiments, the channel defect information indicates L defective channels or NL functional channels.

[0038] In stage 444, the first processing circuit 402 and the second processing circuit 406 perform data transmission based on the flit reconstruction format determined according to the channel defect information shown in Figure 3.

[0039] Figure 5A is a diagram of the flit protocol format 500A based on the UCIe standard according to various embodiments. In Figure 5A, the flit protocol format 500A includes 256 data units (e.g., bytes, data units B00 to B255) arranged in 4 rows and 64 columns. In Figure 5A, each column of data units corresponds to a data unit transmitted or received by a corresponding communication channel. For example, data units B00, B64, B128, and B192 according to the FLIT protocol format 500A will be transmitted or received through communication channel 0; data units B01, B65, B129, and B193 according to the FLIT protocol format 500A will be transmitted or received through communication channel 1; data units B02, B66, B130, and B194 according to the FLIT protocol format 500A will be transmitted or received through communication channel 2; and data units B63, B127, B191, and B255 according to the FLIT protocol format 500A will be transmitted or received through communication channel 63.

[0040] Figure 5B is a diagram of a flit reconstructed format 500B derived from the flit protocol format 500A in Figure 5A, based on a first-remapping scheme according to various embodiments. In Figure 5B, communication channels 1, 2, 4, and 5 are identified as defective channels (marked with "x"). According to the first-remapping scheme, data units are reconstructed by sequentially shifting the data units of the target flit to functional channels and skipping defective channels. For example, compared to flit protocol format 500A, data unit B01 is shifted from row 0 of communication channel 1 to row 0 of communication channel 3 in flit reconstructed format 500B, and data unit B02 is shifted from row 0 of communication channel 2 to row 0 of communication channel 6. Therefore, at least 16 data units B240~B255 are shifted from row 3 to an additional row (row 4 in Figure 5C) for channel repair.

[0041] Figure 5C is a diagram of a flit reconstructed format 500C derived from the flit protocol format 500A in Figure 5A, based on a second remapping scheme according to various embodiments. In Figure 5C, communication channels 1, 2, 4, and 5 are identified as defective channels (marked with "x"). According to the second remapping scheme, data units are reconstructed by moving data units allocated in defective channels to one or more additional rows (e.g., row 0 in Figure 5C). For example, compared to flit protocol format 500A, data units in all functional channels are configured based on the original rows and channel allocations of the flit protocol format in the flit reconstructed format 500C (e.g., moving all row allocations by 1 without changing the row order, and the same applies to channel allocations). Furthermore, skipped data units (e.g., data units corresponding to rows 0-3 and channels 1, 2, 4, and 5 in the Flit protocol format 500A) are added to a new row (e.g., row 0 in Figure 5C). In this non-limiting example, additional rows are transmitted or received before rows based on the original rows and channel allocations. In some embodiments, one or more additional rows for channel repair are transmitted or received before or after rows based on the original rows and channel allocations.

[0042] In some embodiments, the first mapping scheme in Figure 5B and the second mapping scheme in Figure 5C can be summarized as converting a Flit protocol format with M rows and N data units to a Flit reassembly format with M+R rows and NL data units, where L represents the number of defective channels and R represents the number of additional channels. In Figure 5B, N is 64, M is 4, and R is 1. In some embodiments, N ranges from 32 to 128, M ranges from 1 to 8, and R ranges from 1 to 4.

[0043] Figure 6A is a block diagram of a shift register group 600 for converting data units in the flit protocol format 500A of Figure 5A to the flit reconstructed format 500B of Figure 5B, according to various embodiments. In some embodiments, the shift register group 600 is incorporated into the dynamic remapping circuit 312 of Figure 3, or into the physical layer logic circuit 310 of Figure 3, and is accessed by the dynamic remapping circuit 312.

[0044] In Figure 6A, each block (e.g., blocks 602 and 604) represents a component register configured to store bits. In some embodiments, for a communication channel configured to transmit a data unit of one byte (e.g., 8 bits) in a transmission session, flit is stored in 8 sets of shift registers, and as a non-limiting example, each set of shift registers is based on shift register group 600.

[0045] In Figure 6A, arrows pointing to or away from each of the component registers (e.g., arrows 605 and 607) indicate the direction of data shifting between component registers. In Figure 6A, cross symbols (e.g., cross symbol 608) indicate that the corresponding component register is mapped to a defective channel. Furthermore, the shift register group 600 for converting data units from the flit protocol format 500A to the flit reconstructed format 500B can be arranged in 5 rows (rows 612, 614, 616, 618, 622, corresponding to rows 0, 1, 2, 3, and 4 in Figure 5B, respectively) and 64 columns (corresponding to the 64 channels in Figure 5B, e.g., columns 631-636 and 641-646). In some embodiments, the dynamic remapping circuit 312 in Figure 3 prepares the data units of the target flit in several sets of shift registers, the number of which is determined by the number of bits in each data unit of the target flit. In some embodiments, during each transmission session, the physical layer logic circuit 310 in Figure 3 transmits the data units stored in one row of the shift register set 600 at a time through the communication channel of the front-end circuit 320. For example, to transmit the data units of the target flit allocated in the 5 rows of Figure 6A, 5 transmission sessions must be performed.

[0046] In some embodiments, according to the first mapping scheme in Figure 5B, in the first stage, based on the row and channel allocation of the flit protocol format 500A, registers at rows 612, 614, 616, and 618 store the data values ​​of specific bit positions of the data units of the target flit. For example, component register 602 is located at channel 631, row 614, and therefore stores bits from data unit B64 in Figure 5A; component register 604 is located at channel 632, row 614, and therefore stores bits from data unit B65 in Figure 5A. Furthermore, in some embodiments, a component register located at an additional row 622 stores defective data values ​​(e.g., 0).

[0047] In some embodiments, during the second stage, the data values ​​stored in rows 612-618 are shifted and / or bypassed to skip the component registers corresponding to the defective channels (channels marked with cross symbols, including channels 632, 633, 635, and 636). In some embodiments, as the number of defective channels decreases, a portion of the data unit of the target flit is moved out of rows 612-618 and into an additional row 622. In some embodiments, skipped registers are ignored during transmission, and the data values ​​stored in these registers thus become irrelevant. In some embodiments, the skipped registers store defective values ​​(e.g., 0). Therefore, the defective value (of a specific element of the data unit of the target flit) is changed from being stored in flit protocol format 500A to being stored in flit reconstructed format 500B.

[0048] Figure 6B is a block diagram of the control logic 650 of the shift register group 600 in Figure 6A according to various embodiments, and the component register 660 of the shift register group 600 in Figure 6A. In some embodiments, the control logic 650 is incorporated into the dynamic remapping circuit 312 in Figure 3.

[0049] In Figure 6B, component register 660 includes register 662, shift multiplexer 664, shift mask selector 665, bypass multiplexer 666, and bypass mask selector 667. Component register 660 in Figure 6B also includes a data input terminal D and a data output terminal Q. In some embodiments, data input terminal D is coupled to the data output terminal of a component register in a previous stage (refer to the data shift direction in Figure 6A), and data output terminal Q is coupled to the data input terminal of a component register in a subsequent stage (refer to the data shift direction in Figure 6A).

[0050] In some embodiments, register 662 includes a D-type flip-flop that includes a data input terminal D', a data output terminal Q', and a clock terminal coupled to a clock signal CLK. In Figure 6B, shift multiplexer 664 is configured to selectively provide a signal from data input terminal D or data output terminal Q' to data input terminal D' based on a signal from shift mask selector 665, and bypass multiplexer 666 is configured to selectively provide a signal from data input terminal D' or data output terminal Q' to data output terminal Q based on a signal from bypass mask selector 667.

[0051] In some embodiments, control logic 650 is configured to set the modes of shift masks smask0, smask1, smask2, smask3, smask4, and smask5, and the modes of bypass masks bpmask0, bpmask1, bpmask2, bpmask3, and bpmask4, based on the identified defective channels. In Figure 6B, “[n]” represents a specific channel n of the communication channel associated with component register 660. In some embodiments, control logic 650 is further configured to control shift mask selector 665 and bypass mask selector 667 to output appropriate masking signals to the corresponding shift multiplexer 664 and bypass multiplexer 666, based on the shift mask mode and bypass mask mode, during each clock cycle of clock signal CLK.

[0052] In a non-limiting example based on the examples in Figures 5B and 6A, control logic 650 acquires channel defect information indicating the pattern of the defective channel, and control logic 650 identifies a set of shift masks and a set of bypass masks associated with the pattern of the defective channel. In this non-limiting example, the pattern of the defective channel is {0110110000 . . . 0000}, which is a 64-bit binary number where 1 indicates a defective channel and 0 indicates a functional channel. In this non-limiting example, the set of shift masks associated with the pattern of the defective channel includes a set of 64 bit values ​​as shown in Table I (including shift mask identifiers and a corresponding bitmap, where 1 indicates shift and 0 indicates no shift). Displacement mask identification code Shift mask bit mapping smask0 0000000000. . . 0000 smask1 0000011111. . . 1111 smask2 0000111111. . . 1111 smask3 0011111111. . . 1111 smask4 0111111111. . . 1111 smask5 1111111111. . . 1111 Table I In this non-limiting embodiment, a set of bypass masks associated with the pattern of the defective channel comprises a set of 64 bit values ​​as shown in Table II (including a bypass mask identifier and a corresponding bit mapping, where 1 indicates bypass and 0 indicates no bypass). Bypass mask identification code Bypass masking bit mapping bpmask0 0000000000. . . 0000 bpmask1 0000010000. . . 0000 bpmask2 0000110000... 0000 bpmask3 0010110000... 0000 bpmask4 0110110000. . . 0000 Table II

[0053] In this non-limiting example, based on the masking order (including rows and corresponding masking order) shown in Table III, the applicable shift mask and the applicable bypass mask are selected and updated in each clock cycle. Horizontal Masking order Column 0 (Column 612 in Figure 6A) Displacement mask [12 smask0 (in this disclosure, it may be marked as (×12)), smask1, smask2, smask3, smask4, smask0 (until reset)], and Bypass mask [bpmask0 (×13), bpmask1, bpmask2, bpmask3, bpmask4 (until reset)] Column 1 (Column 614 in Figure 6A) Shift mask [smask0 (×8), smask1, smask2, smask3, smask4, smask5 (×4), smask0 (until reset)], and Bypass mask [bpmask0 (×9), bpmask1, bpmask2, bpmask3, bpmask4 (until reset)] Column 2 (Column 616 in Figure 6A) Shift mask [smask0 (×4), smask1, smask2, smask3, smask4, smask5 (×8), smask0 (until reset)], and Bypass mask [bpmask0 (×5), bpmask1, bpmask2, bpmask3, bpmask4 (until reset)] Column 3 (Column 618 in Figure 6A) Shift mask [smask1, smask2, smask3, smask4, smask5 (×12), smask0 (until reset)], and Bypass mask [bpmask0, bpmask1, bpmask2, bpmask3, bpmask4 (until reset)] Column 4 (Column 622 in Figure 6A) Displace mask [smask5 (×16), smask0 (until reset)], and Bypass mask [bpmask4 (until reset)] Table III

[0054] The circuit examples in Figures 6A and 6B are merely non-limiting examples. The number of component registers and masking modes is determined based on the number of repairable defective channels and the number of flit formats to be transmitted. Furthermore, the non-limiting examples in Figures 6A and 6B correspond to converting flit from flit protocol format to flit reconstructed format for transmission. In some embodiments, shift register group 600 can be used to convert flit from flit reconstructed format to flit protocol format for reception. In the example of Figure 6B, data is shifted in the opposite data shift direction and / or with an appropriate shift mask.

[0055] Figure 7A is a diagram of a repair register 700 for storing data units corresponding to the target flit of a defective channel, according to various embodiments. In some embodiments, the repair register 700 is incorporated into the dynamic remapping circuit 312 in Figure 3, or into the physical layer logic circuit 310 in Figure 3, and is accessible by the dynamic remapping circuit 312.

[0056] In Figure 7A, each block represents a set of repair registers used to store data units assigned to a defective channel in a specific row. For example, repair register FL0 / R0 stores data units in the first defective channel (e.g., channel 1 in Figure 5C) and the first row (e.g., row 0). Similarly, repair registers FL0 / R1, FL0 / R2, and FL0 / R3 store data units in the second to fourth rows (e.g., rows 1 to 3) of the first defective channel (e.g., channel 1 in Figure 5C). Repair registers FL1 / R0, FL1 / R1, FL1 / R2, and FL1 / R3 store data units in the first to fourth rows (e.g., rows 0 to 3) of the second defective channel (e.g., channel 2 in Figure 5C). Repair registers FL2 / R0, FL2 / R1, FL2 / R2, and FL2 / R3 store data units in the first to fourth rows (e.g., rows 0-3) of the third defective channel (e.g., channel 4 in Figure 5C). Repair registers FL3 / R0, FL3 / R1, FL3 / R2, and FL3 / R3 store data units in the first to fourth rows (e.g., rows 0-3) of the fourth defective channel (e.g., channel 5 in Figure 5C). The number of repair registers 700 is determined based on the number of communication channels and rows in a flit, and the number of channels that can be repaired. In this non-limiting example, to repair up to four defective channels, based on a flit protocol format with 64 channels and four rows, 16 data bits (e.g., bytes) are reserved in the repair registers for storing data units from the defective channels.

[0057] In this non-limiting example, based on the second mapping scheme in Figure 5C, 20 of the 64 communication channels are designated as repair channels and configured to transmit data units from defective channels in the general rows (rows 1-4 in Figure 5C) in an additional row (row 0 in Figure 5C), and store them in the repair register 700. In this non-limiting example, 20 repair channels are used because 16 data units (from 4 rows and 4 defective channels) are to be transmitted in the additional row, and all defective channels (a total of 4) may fall into the repair channels. In some embodiments, the 4 defective channels are configured to transmit preset data (e.g., 0).

[0058] Figure 7B is a diagram of a multiplexer 710 according to various embodiments. The multiplexer 710 is configured to select data paths for communication channels not used as repair channels. In Figure 7B, the multiplexer 710 is configured to selectively couple a data path to an output terminal 712 for one of the communication channels. In some embodiments, for transmitting a flit based on the flit reassembly format 500C in Figure 5C, 44 multiplexers based on multiplexer 710 are configured for each of the 44 communication channels not used as repair channels. In some embodiments, the number of communication channels not used as repair channels is configured based on the number of repairable defective channels planned by the circuit designer.

[0059] In Figure 7B, multiplexer 710 is configured to select a data path from multiple raw data paths 714 and preset data 716. In some embodiments, based on transmitting the first row according to the flit reassembly format 500C in Figure 5C, multiplexer 710 is configured to receive preset data 716 (e.g., 0). In some embodiments, based on transmitting the second to fifth rows according to the flit reassembly format 500C in Figure 5C, multiplexer 710 is configured to couple multiple register sets that store data units of the first to fourth rows in the flit protocol format 500A in Figure 5A, thus effectively corresponding to the second to fifth rows based on the flit reassembly format 500C in Figure 5C. In some embodiments, multiplexer 710 is also configured to receive preset data 716 (e.g., 0) based on a corresponding channel that is a defective channel. In some embodiments, the multiplexer 710 is coupled to selection logic 720, which is configured to control the selection of various data paths. In some embodiments, selection logic 720 is part of the dynamic remapping circuitry 312 in Figure 3.

[0060] Figure 7C is a diagram of a multiplexer 730 according to various embodiments. The multiplexer 730 is configured to select a data path for a communication channel used as a repair channel. In Figure 7C, the multiplexer 730 is configured to selectively couple a data path to an output 732 for one of the communication channels configured as a repair channel. In some embodiments, 20 multiplexers based on the multiplexer 730 are configured for each of the 20 communication channels used as repair channels to transmit a flit based on the flit reconstruction format 500C in Figure 5C. In some embodiments, the multiplexer 730 is coupled to selection logic 720 configured to control the selection of various data paths. In some embodiments, the selection logic 720 determines which 16 of the 20 repair channels will be used for repair based on whether any of the 20 repair channels are defective.

[0061] In Figure 7C, multiplexer 730 is configured to select a data path from multiple raw data paths 734, preset data 736, and multiple repair data paths 738. In some embodiments, based on transmitting the first row according to the flit reconstruction format 500C in Figure 5C, multiplexer 730 is configured to be coupled to a corresponding register storing the data units of the defective channel in register 700 in Figure 7A. In some embodiments, based on transmitting the second to fifth rows according to the flit reconstruction format 500C in Figure 5C, multiplexer 730 is configured to be coupled to multiple registers that respectively store the data units of the first to fourth rows in the flit protocol format 500A in Figure 5A, thus effectively corresponding to the second to fifth rows based on the flit reconstruction format 500C in Figure 5C. In some embodiments, the multiplexer 730 is also configured to receive preset data 736 (e.g., 0) based on whether the corresponding channel is a defective channel or not used for repair during the transmission of the first row.

[0062] In some embodiments, the original data path 714 in Figure 7B or the original data path 734 in Figure 7C includes four different data paths corresponding to four rows (e.g., rows 0-3 in Figure 5A, or rows 1-4 in Figure 5C). In some embodiments, the repair data path 738 in Figure 7C includes five different data paths corresponding to up to five different groups from the repair register 700. In some embodiments, each register group for storing data units from a specific defective channel and a specific row is coupled to five different multiplexers for 20 multiplexers of 20 repair channels to provide alternative data paths in the event that up to four of the 20 repair channels are defective.

[0063] The circuit examples in Figures 7A to 7C are merely non-limiting examples. The number of repair registers and the number and type of multiplexers are determined based on the number of repairable defective channels transmitted and the flit format. Furthermore, the non-limiting examples illustrated in Figures 7A to 7C correspond to converting flit from the flit protocol format to the flit reassembly format for transmission. In some embodiments, corresponding multiplexers 710 and 730 with signals in opposite directions can be used to pass received data units to the repair register 700 (e.g., from the first row in Figure 5C) based on the flit reassembly format 500C, and to pass tables (e.g., from the second to fifth rows in Figure 5C) based on the flit protocol format 500A. Then, based on the flit protocol format 500A, the data units in the repair register 700 are moved to appropriate positions in the table to store the data units corresponding to the defective channels.

[0064] Figure 8 is a flowchart of a communication method 800 according to some embodiments. In some embodiments, various operations of the communication method 800 are performed by processing circuitry (e.g., a semiconductor wafer or semiconductor circuit module) of a semiconductor device (e.g., an IC package). In some embodiments, the processing circuitry corresponds to the physical layer logic circuitry 310 in Figure 3, the circuit examples in Figures 6A to 6B, and / or the circuit examples in Figures 7A to 7C. As shown in Figure 8, the communication method 800 includes operations 810 to 834.

[0065] In operation 810, the processing circuit acquires channel defect information, which indicates L defective channels out of N communication channels accessible to the processing circuit, or NL functional channels out of N communication channels. In some embodiments, N is a positive integer, and L is 0 or a positive integer. In some embodiments, the processing circuit acquires the channel defect information by generating the channel defect information (e.g., through the channel defect detection circuit 314) or by receiving channel defect information from another processing circuit of the semiconductor device (e.g., another semiconductor chip or another circuit module).

[0066] In operation 820, based on L being greater than 0 and based on channel defect information, the processing circuit employs a remapping configuration corresponding to the mapping relationship between the flit protocol format and the flit reconstructed format. The flit protocol format has M rows of N data units, and the flit reconstructed format has M+R rows of NL data units. In some embodiments, M is a positive integer, and R is a positive integer.

[0067] In some embodiments, according to the first mapping scheme in Figures 5B and 6A to 6B, the mapping relationship corresponds to sequentially mapping N data units in M ​​rows of the Flit protocol format to NL data units in M+R rows of the Flit reconstructed format. In some embodiments, according to the second mapping scheme in Figures 5C and 7A to 7C, the mapping relationship corresponds to mapping NL data units in M ​​rows of the Flit protocol format corresponding to NL functional channels to NL data units in M ​​rows of the Flit reconstructed format, based on the original rows and channel allocation in the Flit protocol format. The mapping relationship further corresponds to mapping M×L data units in the Flit protocol format corresponding to L defective channels to a maximum of R additional rows in the Flit reconstructed format.

[0068] In operation 832, in order to transmit one or more target flits, based on L being greater than 0 and based on the remapping configuration, the processing circuit obtains the target flit in the flit protocol format, and transmits the data units of the target flit through NL functional channels based on the flit reassembly format.

[0069] In operation 834, in order to receive one or more target flits, based on L being greater than 0 and based on the remapping configuration, the processing circuit receives the data units of the target flits through NL functional channels based on the flit reassembly format and obtains the target flits in the flit protocol format.

[0070] In some embodiments, each data unit corresponds to one byte. In some embodiments, N ranges from 32 to 128, M ranges from 1 to 8, and R ranges from 1 to 4. In some embodiments, the target flit contains 256 bytes, and N is 64, M is 4, and R is 1.

[0071] In some embodiments, described from the perspective of the first processing circuit 402 based on stages 424, 430, and 442 in Figure 4, the communication method 800 further includes receiving one or more test fragments from another processing circuit through N communication channels, and identifying L defective channels or NL functional channels among the N communication channels based on the received one or more test fragments. In some embodiments, the communication method 800 further includes transmitting channel defect information to other processing circuits through a control interface, the channel defect information indicating L defective channels or NL functional channels.

[0072] In some embodiments, based on stages 424 and 442 in Figure 4, and described from the perspective of the second processing circuit 406, the communication method 800 further includes transmitting one or more test flits to another processing circuit through N communication channels. In some embodiments, the communication method 800 further includes receiving channel defect information from other processing circuits through a control interface, the channel defect information indicating L defective channels or NL functional channels.

[0073] In some embodiments, a semiconductor device includes processing circuitry and N signal paths corresponding to N communication channels, where N is a positive integer. In some embodiments, the processing circuitry is coupled to the N signal paths and configured to acquire channel defect information, which indicates L defective channels out of the N communication channels, or NL functional channels out of the N communication channels, where L is 0 or a positive integer. The processing circuitry is configured to, based on L being greater than 0 and based on the channel defect information, employ a remapping configuration corresponding to the mapping relationship between the Flit protocol format and the Flit reconstructed format, where the Flit protocol format has M rows of N data units and the Flit reconstructed format has M+R rows of NL data units, where M is a positive integer and R is a positive integer. The processing circuit is configured to, based on L > 0 and based on a remapping configuration, obtain the target flit in the flit protocol format, and transmit the data units of the target flit through NL functional channels based on the flit reconstructed format; or, based on the flit reconstructed format, receive the data units of the target flit through NL functional channels and obtain the target flit in the flit protocol format. In some embodiments, the processing circuit is configured to sequentially map N data units in M ​​rows of the flit protocol format to NL data units in M+R rows of the flit reconstructed format. In some embodiments, the processing circuit is configured to, based on the original rows and channel allocation in the flit protocol format, map NL data units in M ​​rows of the flit protocol format corresponding to NL functional channels to NL data units in M ​​rows of the flit reconstructed format; and map M×L data units in the flit protocol format corresponding to L defective channels to up to R additional rows of the flit reconstructed format. In some embodiments, the processing circuitry is further configured to receive one or more test flits from another processing circuitry via N communication channels; based on the received one or more test flits, identify L defective channels or NL functional channels from the N communication channels; and transmit channel defect information to another processing circuitry via a control interface, the channel defect information indicating L defective channels or NL functional channels. In some embodiments, the processing circuitry is further configured to transmit one or more test flits to another processing circuitry via N communication channels; and receive channel defect information from another processing circuitry via a control interface, the channel defect information indicating L defective channels or NL functional channels. In some embodiments, each of the data units corresponds to a byte; N ranges from 32 to 128; M ranges from 1 to 8; and R ranges from 1 to 4. In some embodiments, each of the data units corresponds to a byte; the target flit comprises 256 bytes; N is 64; M is 4; and R is 1.

[0074] In some embodiments, a communication method, executed in a processing circuit of a semiconductor device, includes acquiring channel defect information, which indicates L defective channels out of N communication channels accessible by the processing circuit, or NL functional channels out of N communication channels, where N is a positive integer and L is 0 or a positive integer. The method includes, based on L being greater than 0 and based on the channel defect information, employing a remapping configuration corresponding to the mapping relationship between a flit protocol format and a flit reconstructed format, where the flit protocol format has N data units in M ​​rows and the flit reconstructed format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. The method includes, based on L being greater than 0 and based on the remapping configuration, acquiring a target flit in the flit protocol format, and transmitting the data units of the target flit through the NL functional channels based on the flit reconstructed format; or, based on the flit reconstructed format, receiving the data units of the target flit through the NL functional channels and acquiring the target flit in the flit protocol format. In some embodiments, the mapping relationship corresponds to sequentially mapping N data units in M ​​rows of the flit protocol format to NL data units in M+R rows of the flit reconstructed format. In some embodiments, the mapping relationship corresponds to mapping NL data units in M ​​rows of the flit protocol format corresponding to NL functional channels to NL data units in M ​​rows of the flit reconstructed format based on the original rows and channel allocation in the flit protocol format; and mapping M×L data units in the flit protocol format corresponding to L defective channels to up to R additional rows in the flit reconstructed format. In some embodiments, the method further includes receiving one or more test flits from another processing circuit through N communication channels; identifying L defective channels or NL functional channels from the N communication channels based on the received one or more test flits; and transmitting channel defect information to another processing circuit through a control interface, the channel defect information indicating L defective channels or NL functional channels. In some embodiments, the method further includes transmitting one or more test flits to another processing circuit via N communication channels; and receiving channel defect information from the other processing circuit via a control interface, the channel defect information indicating L defective channels or NL functional channels. In some embodiments, each of the data units corresponds to a byte; N ranges from 32 to 128; M ranges from 1 to 8; and R ranges from 1 to 4. In some embodiments, each of the data units corresponds to a byte; the target flit comprises 256 bytes; N is 64; M is 4; and R is 1.

[0075] In some embodiments, a semiconductor device includes a dynamic remapping circuit, a protocol circuit, and a front-end circuit, configured to transmit or receive data units of a target flit through N communication channels, where N is a positive integer. In some embodiments, the dynamic remapping circuit is coupled to the protocol circuit and the front-end circuit, and the dynamic remapping circuit is configured to acquire channel defect information, which indicates L defective channels out of the N communication channels, or NL functional channels out of the N communication channels, where L is 0 or a positive integer. The dynamic remapping circuit is configured to, based on L being greater than 0 and based on the channel defect information, employ a remapping configuration corresponding to the mapping relationship between the flit protocol format and the flit reassembled format, where the flit protocol format has N data units in M ​​rows, and the flit reassembled format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. The dynamic remapping circuit is configured to receive the target flit in the flit protocol format from the protocol circuit based on L being greater than 0 and based on the remapping configuration, and transmit the data units of the target flit through NL functional channels based on the flit reassembly format; or, based on the flit reassembly format, receive the data units of the target flit through NL functional channels and transmit the target flit in the flit protocol format to the protocol circuit. In some embodiments, the dynamic remapping circuit is configured to sequentially map N data units in M ​​rows of the flit protocol format to NL data units in M+R rows of the flit reassembly format. In some embodiments, the dynamic remapping circuit is configured to map NL data units in M ​​rows of the flit protocol format corresponding to NL functional channels to NL data units in M ​​rows of the flit reconstructed format based on the original row and channel allocation in the flit protocol format; and to map M×L data units in the flit protocol format corresponding to L defective channels to up to R additional rows in the flit reconstructed format. In some embodiments, the semiconductor device further includes a control interface; and a channel defect detection circuit configured to receive one or more test flits from another processing circuit via N communication channels; identify L defective channels or NL functional channels from the N communication channels based on the received one or more test flits; and transmit channel defect information to the other processing circuit via the control interface, the channel defect information indicating L defective channels or NL functional channels.In some embodiments, each of the data units corresponds to a byte; N ranges from 32 to 128; M ranges from 1 to 8; and R ranges from 1 to 4.

[0076] The foregoing outlines the features of many embodiments, thus enabling those skilled in the art to better understand the embodiments disclosed herein. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made to the structures herein without departing from the spirit and scope of this disclosure.

[0077] 100: Semiconductor devices 110,402: First processing circuit 120,406: Second processing circuit 112,122: D2D communication interface 200:D2D Interconnection Protocol 210: Agreement Layer 215:flit Perceptual D2D Interface 220:D2D Adapter 225: Original D2D Interface 230: Entity Layer 232: Entity Layer Logic 234: Electronic / Analog Front End 236: Sideband 300: Physical layer circuit 302, 304, 306, 605, 607: Arrows 303: Protocol Circuit / Protocol Processing Circuit 305: Another processing circuit / processing circuit 310: Physical layer logic circuits 312: Dynamic remapping circuit 314: Channel Defect Detection Circuit 320: Front-end circuit 322, 332: Conductive terminals 324: Communication Channel 326: Two communication channels 330: Sideband Circuit 334: Sideband Communication Channel 400: Processing Flowchart 410,412,414,422,424,430,442,444: Stages 500A:flit protocol format 500B, 500C: flit recombinant format 600: Shift register group 602, 604: Block / Component Temporary Register 608: Cross symbol 650: Control Logic 660: Component temporary register 662: Temporary Register 664: Shift Multiplexer 665: Shift Mask Selector 666: Bypass Multiplexer 667: Bypass Mask Selector 700: Temporary Register 710, 730: Multiplexer 712, 732: Output terminals 714,734: Path to original data 716,736: Preset data 720: Selection Logic 738: Repair data path 800: Communication Method 810, 820, 832, 834: Operations CLK: Clock signal D, D': Data input terminals Q, Q': Data output end

Claims

1. A semiconductor device, comprising: One processing circuit; And N signal paths, corresponding to N communication channels, where N is a positive integer; wherein, the above processing circuit is coupled to the above N signal paths, and the above processing circuit is configured to: obtain channel defect information, the channel defect information indicating L defective channels among the above N communication channels, or NL functional channels among the above N communication channels, where L is 0 or a positive integer; based on L being greater than 0 and based on the above channel defect information, adopt a remapping configuration corresponding to one of the mapping relationships between a flow control unit protocol format and a flow control unit reconfiguration format, the flow control unit protocol format having N data units in M ​​rows, and the flow control unit reconfiguration format having NL data units in M+R rows, where M is a positive integer and R is a positive integer; and based on L being greater than 0 and based on the above remapping configuration: Obtain a target flow control unit in the above flow control unit protocol format, and based on the above flow control unit reconfiguration format, transmit multiple data units of the target flow control unit through the above NL functional channels; or based on the above flow control unit reconfiguration format, receive the above data units of the target flow control unit through the above NL functional channels, and obtain the target flow control unit in the above flow control unit protocol format.

2. The semiconductor device as claimed in claim 1, wherein the processing circuitry is configured to sequentially map the N data units of the M rows in the flow control unit protocol format to the NL data units of the M+R rows in the flow control unit reconfiguration format.

3. The semiconductor device as claimed in claim 1, wherein the processing circuitry is configured to: map NL data units of M rows in the flow control unit protocol format corresponding to the NL functional channels to NL data units of M rows in the flow control unit reconfiguration format based on a plurality of original rows and channel assignments in the flow control unit protocol format; and map M data units of the flow control unit protocol format corresponding to the L defective channels to a maximum of R additional rows in the flow control unit reconfiguration format.

4. The semiconductor device as claimed in claim 1, wherein the processing circuitry is further configured to: receive one or more test flow control units from another processing circuitry via the N communication channels; identify the L defective channels or the NL functional channels from the N communication channels based on the received test flow control units; and transmit channel defect information to the other processing circuitry via a control interface, the channel defect information indicating the L defective channels or the NL functional channels.

5. The semiconductor device as claimed in claim 1, wherein the processing circuit is further configured to: transmit one or more test flow control units to another processing circuit through the N communication channels; and receive channel defect information from the other processing circuit through a control interface, the channel defect information indicating the L defective channels or the NL functional channels.

6. The semiconductor device as claimed in claim 1, wherein: Each of the above data units corresponds to a tuple; N ranges from 32 to 128; M ranges from 1 to 8; and R ranges from 1 to 4.

7. The semiconductor device as claimed in claim 1, wherein: Each of the above data units corresponds to a byte; the above target flow control unit comprises 256 bytes; N is 64; M is 4; and R is 1.

8. A communication method performed on a processing circuit of a semiconductor device, the communication method comprising: The system obtains channel defect information, which indicates L defective channels out of N communication channels accessible by the processing circuit, or NL functional channels out of the N communication channels, where N is a positive integer and L is 0 or a positive integer. Based on L being greater than 0 and based on the channel defect information, a remapping configuration is adopted, corresponding to a mapping relationship between a flow control unit protocol format and a flow control unit reconfiguration format. The flow control unit protocol format has N data units in M ​​rows, and the flow control unit reconfiguration format has NL data units in M+R rows, where M is a positive integer and R is a positive integer. Based on L being greater than 0 and based on the remapping configuration: A target flow control unit in the flow control unit protocol format is obtained, and based on the flow control unit reconfiguration format, multiple data units of the target flow control unit are transmitted through the NL functional channels; or based on the flow control unit reconfiguration format, the data units of the target flow control unit are received through the NL functional channels, and the target flow control unit in the flow control unit protocol format is obtained.

9. A semiconductor device comprising: a dynamic remapping circuit; a protocol circuit; and a front-end circuit configured to transmit or receive a plurality of data units of a target flow control unit through N communication channels, where N is a positive integer; wherein the dynamic remapping circuit is coupled to the protocol circuit and the front-end circuit, and the dynamic remapping circuit is configured to: acquire channel defect information, the channel defect information indicating L defective channels among the N communication channels, or NL functional channels among the N communication channels, where L is 0 or a positive integer; based on L being greater than 0 and based on the channel defect information, employ a remapping configuration corresponding to a mapping relationship between a flow control unit protocol format and a flow control unit reconfiguration format, the flow control unit protocol format having N data units in M ​​rows, and the flow control unit reconfiguration format having NL data units in M+R rows, where M is a positive integer and R is a positive integer; and based on L being greater than 0 and based on the remapping configuration: The system receives the target flow control unit in the flow control unit protocol format from the aforementioned protocol circuit, and transmits the target flow control unit's data unit through the aforementioned NL functional channels based on the aforementioned flow control unit reconfiguration format; or receives the target flow control unit's data unit through the aforementioned NL functional channels based on the aforementioned flow control unit reconfiguration format, and transmits the target flow control unit in the aforementioned flow control unit protocol format to the aforementioned protocol circuit.

10. The semiconductor device as claimed in claim 9 further comprises: a control interface; and a channel defect detection circuit configured to: receive one or more test flow control units from another processing circuit via the N communication channels; identify the L defective channels or the NL functional channels from the N communication channels based on the received test flow control units; and transmit channel defect information to the other processing circuit via the control interface, the channel defect information indicating the L defective channels or the NL functional channels.

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