Semiconductor device and method for manufacturing the same

Abstract

This invention provides a semiconductor device. The semiconductor device includes a substrate, a first well, two first source / drain regions, a first gate dielectric layer, and a first gate. The first well is disposed in the substrate. The two first source / drain regions are disposed in the first well and are separated from each other. The first gate dielectric layer is disposed on the substrate. The first gate dielectric layer has a multilayer structure. The first gate is disposed on the first gate dielectric layer. At least a portion of the first gate dielectric layer covers the two first source / drain regions.

Claims

1. A semiconductor device, comprising: substrate; The first well is disposed in the substrate; Two first source / drain regions are located in the first well and are separated from each other; A first gate dielectric layer is disposed on the substrate, wherein the first gate dielectric layer has a multilayer structure; a first gate is disposed on the first gate dielectric layer, wherein at least a portion of the first gate dielectric layer covers the two first source / drain regions; a second well is disposed on the substrate and adjacent to the first well; two second source / drain regions are disposed in the second well and separated from each other; a second gate dielectric layer is disposed on the substrate; And a second gate, disposed on the second gate dielectric layer, wherein the second gate dielectric layer exposes the upper surface of the two second source / drain regions; The first well, the two first source / drain regions, the first gate dielectric layer, and the first gate corresponding to a first transistor; the second well, the two second source / drain regions, the second gate dielectric layer, and the second gate corresponding to a second transistor; wherein the semiconductor device further includes a transistor arrangement, the transistor arrangement being composed of a combination of a first bonding unit and a second bonding unit, the first bonding unit including a first transistor adjacent to a first side and a second transistor adjacent to a second side, the second side being relative to the first side; the second bonding unit including a first transistor adjacent to the second side and a second transistor adjacent to the first side.

2. The semiconductor device as claimed in claim 1, wherein the multilayer structure comprises one or more nitride layers and one or more oxide layers.

3. The semiconductor device as claimed in claim 1, wherein the first gate dielectric layer and the first gate are stacked on the substrate along a first direction, and at least a portion of the first gate dielectric layer overlaps the two first source / drain regions in the first direction.

4. The semiconductor device as claimed in claim 1, wherein the doping concentration of the first well is different from the doping concentration of the second well.

5. The semiconductor device as claimed in claim 1, wherein the first well and the second well have a first conductivity type, the two first source / drain regions and the two second source / drain regions have a second conductivity type, and the first conductivity type is different from the first conductivity type.

6. The semiconductor device as claimed in claim 1, wherein the two first source / drain regions and the two second source / drain regions are connected to each other, with the adjacent first source / drain region and second source / drain region being connected to each other.

7. The semiconductor device as claimed in claim 1 further includes a drain contact and a source contact, wherein the drain contact is disposed on the first source / drain region of the two first source / drain regions that is farther away from the second well, and the source contact is disposed on the second source / drain region of the two second source / drain regions that is farther away from the first well.

8. The semiconductor device as claimed in claim 7, wherein at least a portion of the first gate dielectric layer is adjacent to the drain contact; and the second gate dielectric layer is separated from the source contact.

9. The semiconductor device of claim 1, wherein the first gate dielectric layer has a body, and wings extend from both sides of the body to form wings, wherein each wing has an arcuate profile on its upper side, the arcuate profile extending outward from the body.

10. The semiconductor device as claimed in claim 1, wherein the first bonding unit and the second bonding unit are arranged in an alternating or repeating manner.

11. The semiconductor device as claimed in claim 1, wherein the number of transistors arranged is a plurality of transistors, the plurality of transistors arranged to form a transistor array.

12. The semiconductor device of claim 1, wherein the first transistor of the first bonding unit and the first transistor of the second bonding unit share a drain contact, and the second transistor of the first bonding unit and the second transistor of the second bonding unit are electrically connected to different source contacts.

13. A method for manufacturing a semiconductor device, comprising: Provide a substrate; A first well is formed, and the first well is disposed in the substrate; Two first source / drain regions are formed, the two first source / drain regions being disposed in the first well and separated from each other; a first gate dielectric layer is formed, the first gate dielectric layer being disposed on the substrate, wherein the first gate dielectric layer is a multilayer structure; a first gate is formed, the first gate being disposed on the first gate dielectric layer, wherein at least a portion of the first gate dielectric layer covers the two first source / drain regions; a second well is formed, the second well being disposed on the substrate and adjacent to the first well; two second source / drain regions are formed, the two second source / drain regions being disposed in the second well and separated from each other; A second gate dielectric layer is formed, and the second gate dielectric layer is disposed on the substrate; And a second gate is formed, the second gate being disposed on the second gate dielectric layer, wherein the second gate dielectric layer exposes the upper surface of the two second source / drain regions; The first well, the two first source / drain regions, the first gate dielectric layer, and the first gate corresponding to a first transistor; the second well, the two second source / drain regions, the second gate dielectric layer, and the second gate corresponding to a second transistor; wherein the semiconductor device further includes a transistor arrangement, the transistor arrangement being composed of a combination of a first bonding unit and a second bonding unit, the first bonding unit including a first transistor adjacent to a first side and a second transistor adjacent to a second side, the second side being relative to the first side; the second bonding unit including a first transistor adjacent to the second side and a second transistor adjacent to the first side.

14. A method of manufacturing a semiconductor device as claimed in claim 13, wherein the first well and the second well have a first conductivity type, and the two first source / drain regions and the two second source / drain regions have a second conductivity type, the second conductivity type being different from the first conductivity type.

15. The method of manufacturing a semiconductor device as claimed in claim 13 further includes forming a drain contact and a source contact, wherein the drain contact is disposed on the first source / drain region of the two first source / drain regions that is farther away from the second well, and the source contact is disposed on the second source / drain region of the two second source / drain regions that is farther away from the first well.

16. A method of manufacturing a semiconductor device as claimed in claim 15, wherein at least a portion of the first gate dielectric layer is adjacent to the drain contact; and the second gate dielectric layer is separated from the source contact.

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