Superconducting parametric interferometers for isolation and directional amplification

Abstract

The present invention provides an apparatus comprising a superconducting parametric interference circuit, the superconducting parametric interference circuit including a signal input port and a signal output port, and a first parametric mixer circuit and a second parametric mixer circuit coupled in parallel between the signal input port and the signal output port. The signal input port is configured to receive an input signal having a first frequency. The first parametric mixer circuit is configured to convert the input signal into a first output signal having a second frequency, and the second parametric mixer circuit is configured to convert the input signal into a second output signal having the second frequency. The superconducting parametric interference circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency, and to provide isolation between the signal input port and a signal present at the signal output port.

Description

Technical Field

[0001] This disclosure is generally about quantum computing, and more specifically, about microwave isolators and isolation techniques used in conjunction with, for example, superconducting quantum computing systems. Prior Technology

[0002] Superconducting quantum computing systems are implemented using circuit quantum electrodynamics (QED) devices. These QED devices utilize the quantum dynamics of the electromagnetic fields in a superconducting circuit, including superconducting qubits, to generate and process quantum information. Generally, a superconducting qubit is an electronic circuit implemented using components such as superconducting tunneling junctions (e.g., Josephson junctions), inductors, and / or capacitors. When cooled to cryogenic temperatures, these electronic circuits behave as quantum mechanical anharmonic (nonlinear) oscillators with quantized states. Additionally, flux-tunable qubits can be implemented using superconducting quantum interference devices (SQUIDs) to flux-tune the transition frequencies of the qubits.

[0003] In quantum computing systems implementing superconducting qubits, the quantum chip includes cryogenic hardware comprising microwave components for controlling and reading out the quantum states of the superconducting qubits. For example, the cryogenic hardware includes qubit readout hardware configured to read out and amplify weak signals from the superconducting qubits while protecting their quantum states from noise and interference from other components in the quantum computing system. For instance, non-reciprocal microwave devices, such as ferrite-based microwave isolators, are commonly used in the readout signal path of a mixing chamber in a cryostat (dilution freezer) to isolate the superconducting qubits. However, in the microwave range (e.g., 1 to 10 GHz), the use of such ferrite-based components in the mixing chamber of a quantum computing system is problematic because these components tend to be very large, require extensive shielding to prevent any stray magnetic field leakage, and also have unusually high losses. Because quantum computing systems scale up to hundreds or thousands of superconducting qubits, the use of ferrite-based isolation components limits system expansion and integration. Summary of the Invention

[0004] The exemplary embodiments disclosed herein include superconducting parametric interferometer circuits and techniques for providing isolation and directional amplification in quantum computing systems.

[0005] For example, one exemplary embodiment includes an apparatus comprising a superconducting parametric interferometry circuit including a signal input port and a signal output port, and a first parametric mixer circuit and a second parametric mixer circuit coupled in parallel between the signal input port and the signal output port. The signal input port is configured to receive an input signal having a first frequency. The first parametric mixer circuit is configured to convert the input signal into a first output signal having a second frequency, and the second parametric mixer circuit is configured to convert the input signal into a second output signal having the second frequency. The superconducting parametric interferometry circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency, and to provide isolation between the signal input port and a signal present at the signal output port.

[0006] Advantageously, the superconducting parametric interferometer circuit can operate in a continuous wave mode to provide broadband isolation or broadband directional amplification in, for example, a qubit readout signal chain, rather than using ferrite-based isolation devices.

[0007] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the superconducting parameter interference circuit includes an interference isolator circuit configured to provide unity gain for the output signal and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

[0008] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the superconducting parameter interference circuit includes an interference directional amplifier circuit configured to provide an amplified output signal having one of the second frequencies at the signal output port, and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

[0009] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first parameter mixer circuit and the second parameter mixer circuit each include a parameter frequency converter circuit configured to perform one of the following: up-converting the first frequency to the second frequency; and down-converting the first frequency to the second frequency.

[0010] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first parameter mixer circuit and the second parameter mixer circuit each include a parameter amplifier circuit.

[0011] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first parameter mixer circuit is driven by a first pump signal, and the second parameter mixer circuit is driven by a second pump signal, wherein the first pump signal and the second pump signal have one of the following: the same frequency, the same phase, and a phase offset.

[0012] Another exemplary embodiment includes an apparatus comprising a superconducting interferometric isolation circuit, the superconducting interferometric isolation circuit including a signal input port, a signal output port, a frequency conversion circuit, and a delay circuit. The signal input port is configured to receive an input signal having a first frequency. The frequency conversion circuit includes a first-parameter frequency converter circuit and a second-parameter frequency converter circuit cascaded in series. The delay circuit is coupled in parallel with the frequency conversion circuit. The delay circuit is configured to delay the input signal to generate a first output signal having the first frequency and a first phase. The frequency conversion circuit is configured to generate a second output signal having the first frequency and a second phase. The superconducting interferometric isolation circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the first frequency, and to provide isolation between the signal input port and a signal present at the signal output port.

[0013] In another exemplary embodiment, as may be combined with the foregoing paragraphs, the delay circuit includes a passive delay line.

[0014] In another exemplary embodiment, as may be combined with the foregoing paragraphs, the delay circuit includes a passive filter circuit.

[0015] In another exemplary embodiment, as can be combined with the foregoing paragraphs, one of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency up-converter circuit, and the other of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency down-converter circuit.

[0016] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first parameter frequency converter circuit is driven by a first pump signal, and the second parameter frequency converter circuit is driven by a second pump signal, wherein the first pump signal and the second pump signal have one of the following: the same frequency, the same phase, and a phase offset.

[0017] Another exemplary embodiment includes an apparatus comprising a superconducting parametric interferometry circuit, the superconducting parametric interferometry circuit including a first hybrid coupler, a second hybrid coupler, a first parametric mixer circuit, and a second parametric mixer circuit. The first hybrid coupler includes a signal input port configured to receive an input signal having a first frequency, and the second hybrid coupler includes a signal output port. The first parametric mixer circuit and the second parametric mixer circuit are coupled in parallel between the first hybrid coupler and the second hybrid coupler. The first hybrid coupler is configured to divide the input signal into a first input signal having the first frequency and a second input signal having the first frequency. The first parametric mixer circuit is configured to convert the first input signal into a first output signal having a second frequency. The second parametric mixer circuit is configured to convert the second input signal into a second output signal having the second frequency. The second hybrid coupler is configured to combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency.

[0018] Another exemplary embodiment includes an apparatus comprising a superconducting interferometric isolation circuit, the superconducting interferometric isolation circuit including a first hybrid coupler, a second hybrid coupler, a frequency conversion circuit, and a delay circuit. The first hybrid coupler includes a signal input port configured to receive an input signal having a first frequency. The second hybrid coupler includes a signal output port. The frequency conversion circuit includes a first-parameter frequency converter circuit and a second-parameter frequency converter circuit cascaded in series. The delay circuit is coupled in parallel with the frequency conversion circuit between the first hybrid coupler and the second hybrid coupler. The delay circuit is configured to delay the input signal to generate a first output signal having the first frequency and a first phase, and the frequency conversion circuit is configured to generate a second output signal having the first frequency and a second phase. The second hybrid coupler is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the first frequency.

[0019] Another exemplary embodiment includes a system comprising a quantum processor and a readout signal path. The quantum processor includes qubits. The readout signal path is configured to transmit signals read from one or more of the qubits of the quantum processor. The readout signal path includes a superconducting parametric interference circuit, which includes a signal input port, a signal output port, a first parameter mixer circuit, and a second parameter mixer circuit. The signal input port is configured to receive an input signal having a first frequency, wherein the input signal includes a readout signal from at least one qubit. The first parameter mixer circuit and the second parameter mixer circuit are coupled in parallel between the signal input port and the signal output port. The first parameter mixer circuit is configured to convert the input signal into a first output signal having a second frequency. The second parameter mixer circuit is configured to convert the input signal into a second output signal having the second frequency. The superconducting parametric interference circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency, and provides isolation between the signal input port and a signal present at the signal output port.

[0020] Other embodiments will be described in the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0021] Figures 1A, 1B and 1C schematically illustrate components for constructing a superconducting parametric interferometer circuit according to an exemplary embodiment of the present disclosure.

[0022] Figure 2 schematically illustrates a Josephson junction traveling wave parameter circuit that can be used to implement an interference configuration of a broadband isolator and a directional quantum-limited amplifier according to an exemplary embodiment of this disclosure.

[0023] Figure 3A schematically illustrates a dual-port SQUID-based parametric frequency mixer circuit that can be used to implement a superconducting parametric interferometer circuit according to an exemplary embodiment of this disclosure.

[0024] Figure 3B schematically illustrates a dual-port SQUID-based parametric frequency mixer circuit that can be used to implement a superconducting parametric interferometer circuit according to another exemplary embodiment of this disclosure.

[0025] Figure 4 schematically illustrates a superconducting parametric interferometer circuit configured to provide directional amplification according to an exemplary embodiment of this disclosure.

[0026] Figure 5 schematically illustrates a superconducting parametric interferometer circuit configured to provide isolation according to an exemplary embodiment of this disclosure.

[0027] Figure 6 schematically illustrates a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure.

[0028] Figure 7 schematically illustrates a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure.

[0029] Figures 8A and 8B illustrate simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide directional amplification according to an exemplary embodiment of this disclosure.

[0030] Figures 9A and 9B illustrate simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide isolation according to an exemplary embodiment of this disclosure.

[0031] Figure 10 illustrates the simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure.

[0032] Figure 11 illustrates the simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure.

[0033] Figure 12 schematically illustrates a readout circuit system of a quantum processing system according to an exemplary embodiment of the present disclosure, which may implement a superconducting parametric interferometer circuit in the qubit readout signal path to provide directional amplification and isolation.

[0034] Figure 13 schematically illustrates a quantum computing system according to an exemplary embodiment of this disclosure.

[0035] Figure 14 schematically illustrates an exemplary architecture for managing a quantum computing platform and performing quantum information processing according to an exemplary embodiment of the present disclosure. Implementation

[0036] The exemplary embodiments of superconducting parametric interferometer circuits disclosed herein for use with quantum computing systems are described in further detail below. Specifically, the exemplary superconducting parametric interferometer circuits disclosed herein include parametric interferometer circuits implemented at least in part using parametric frequency mixing circuits (e.g., parametric amplifier circuits, parametric frequency converter circuits) and configured to provide isolation (instead referred to herein as "interference isolator circuits" or "interference isolators"), and superconducting parametric interferometer circuits configured to provide directional amplification (instead referred to herein as "interference directional amplifier circuits" or "interference directional amplifiers"). Generally, a parametric frequency mixing circuit is a type of circuit configured to convert energy from one frequency to another using nonlinear elements (e.g., Josephson junctions). Furthermore, an interferometer is a device configured to induce constructive interference and / or destructive interference of, for example, microwave signals. The exemplary superconducting parametric interferometer circuits are implemented using interference configurations of various components such as microwave hybrid couplers and superconducting parametric frequency mixing circuits to achieve broadband interference isolation and broadband interference directional amplification.

[0037] For example, an exemplary embodiment of a superconducting parametric interferometer circuit may be implemented using an interferometric configuration of a Josephson junction traveling-wave circuit (JJTWPC), such as a Josephson traveling-wave amplifier (JTWPA) circuit and a Josephson traveling-wave frequency converter (JTWFC) circuit, where the JTWPA and JTWFC circuits are specific types of JJTWPC. In other embodiments, the superconducting parametric interferometer circuit may be implemented using an interferometric configuration of a SQUID-based parametric amplifier or a SQUID-based parametric frequency converter.

[0038] In some embodiments, the superconducting parametric interferometer circuit can be configured as an interferometric isolator circuit to provide isolation between cryogenic components in a cryogenic system. For example, the superconducting parametric interferometer circuit can be implemented in a qubit readout signal chain and configured to provide broadband isolation between the superconducting qubits of the quantum processor and the readout circuitry system when the quantum states of the superconducting qubits are read and measured individually or in a multiplexed configuration. In other embodiments, the superconducting parametric interferometer circuit can be configured as an interferometric directional amplifier circuit (e.g., a directional quantum confinement amplifier (QLA)) to amplify low-power signals in cryogenic environments. For example, the superconducting parametric interferometer circuit can be implemented as a QLA in a qubit readout signal chain and configured to provide broadband directional amplification to amplify the qubit readout signal with a good signal-to-noise ratio, thereby allowing for higher fidelity qubit measurements and lower power qubit measurements. Furthermore, the broadband interferometric directional amplifier circuit implemented in the qubit readout signal chain not only provides amplification but also provides isolation between the superconducting qubit and the readout circuit system. Advantageously, operating the superconducting parametric interferometer circuit in continuous wave operation mode enables broadband isolation and directional amplification, for example, in the qubit readout signal chain, to be achieved in the multiplexed superconducting quantum operation readout signal chain, rather than using ferrite-based isolation devices.

[0039] It should be understood that the various features shown in the accompanying drawings are schematic illustrations not drawn to scale. Furthermore, the same or similar element symbols are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each in the drawings. Additionally, the term "illustrative" as used herein means "serving as an example, example, or illustration." Any embodiment or design described herein as "illustrative" should not be construed as superior or more advantageous than other embodiments or designs.

[0040] Furthermore, it should be understood that the phrase "configured as" used in conjunction with circuits, structures, elements, components, or the like that perform one or more functions or otherwise provide some functionality is intended to encompass embodiments of such circuits, structures, elements, components, or the like implemented in hardware, software, and / or combinations thereof, including implementations of hardware, wherein the hardware may include quantum circuit elements (e.g., quantum processors, qubits, Josephson junction devices, Josephson parameter converters (JPCs), quantum-limited amplifiers (QLAs), qubit coupler circuit systems, Josephson multipole multiband isolator circuits, etc.), discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application-specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.), one or more integrated circuits and / or combinations thereof. Therefore, by way of example only, when circuits, structures, elements, components, etc. are defined as being configured to provide specific functionality, it is intended to cover, but not limited to, embodiments of circuits, structures, elements, components, etc., consisting of elements, processing devices, and / or integrated circuits that enable them to perform specific functions when in an operational state (e.g., connected or otherwise deployed in a system, powered, receiving input, and / or generating output), as well as embodiments when circuits, structures, elements, components, etc. are in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered, not receiving input, and / or not generating output) or in a partially operational state.

[0041] As mentioned above, the exemplary superconducting parametric interferometer circuits disclosed herein are implemented using interferometric configurations of various components, such as microwave hybrid couplers and superconducting parametric circuits, to achieve broadband isolation and directional amplification. For example, Figures 1A, 1B, and 1C schematically illustrate components for constructing a superconducting parametric interferometer circuit according to exemplary embodiments of this disclosure. Specifically, according to exemplary embodiments of this disclosure, Figure 1A schematically illustrates a hybrid coupler 100, Figure 1B schematically illustrates a parametric frequency converter 110, and Figure 1C schematically illustrates a parametric amplifier 120; these components are used to implement various interferometric configurations of broadband isolators and directional quantum-confined amplifiers.

[0042] Referring to Figure 1A, the hybrid coupler 100 includes passive microwave circuitry that can be configured to operate as a power divider or power combiner. Specifically, the hybrid coupler 100 includes a four-port 90-degree (orthogonal) hybrid coupler comprising a first port P1, a second port P2, a third port P3, and a fourth port P4. In some embodiments, the hybrid coupler 100 is configured as a power divider for equally splitting the power of an input microwave signal applied to a given input port into two microwave signals, which are then... The phase difference is output from the two output ports. For example, assuming a microwave signal is input to the first port P1 (where the fourth port P4 is terminated), the hybrid coupler 100 splits the power of the input microwave signal into two microwave signals output from the second port P2 and the third port P3, where the two output signals each have the same power (e.g., 50% of the input power), but... The phase difference.

[0043] In other embodiments, the hybrid coupler 100 is configured as a power combiner for combining microwave signals input to two ports of the hybrid coupler 100 and outputting a combined signal from at least one of the ports. For example, suppose a first microwave signal and a second microwave signal are input to a second port P2 and a third port P3, respectively. Depending on the respective phases of the input first and second microwave signals, the signals will be combined (via constructive or destructive interference) and output from a first port P1 or a fourth port P4, or distributed between the first port P1 and the fourth port P4.

[0044] As explained in further detail below, the exemplary superconducting parametric interferometer circuit is configured to (i) implement an actuator of hybrid coupler 100 as a power divider at the input of the superconducting parametric interferometer circuit, and (ii) implement an actuator of hybrid coupler 100 as a power combiner at the output of the superconducting parametric interferometer circuit. Hybrid coupler 100 can be designed to provide wideband operation using microwave engineering techniques well known to those skilled in the art. It should be noted that although the exemplary embodiments disclosed herein are discussed in the context of using a 0-degree hybrid coupler, other embodiments use other equivalent microwave power dividers or couplers (such as 180-degree hybrid couplers). In such cases, the phase requirements of the exemplary superconducting parametric interferometer circuit will vary depending on the type of hybrid coupler used to achieve the necessary signal phase at the port for constructive and destructive interference to realize the desired circuit functionality.

[0045] Next, referring to Figure 1B, the parameter frequency converter 110 is a circuit configured to use a nonlinear procedure (i.e., a parameter frequency mixing procedure) to convert an input signal at one frequency into an output signal at another frequency. The parameter frequency converter 110 includes a first port P1, a second port P2, and a control port (referred to herein as the pump port). The pump port receives signals containing a pump frequency... (or angular frequency) The pump signal is a microwave frequency-modulated (tone) pump signal, wherein the pump signal is configured to modulate the properties of the nonlinear element of the parameter frequency converter 110 to execute the parameter frequency conversion program. The parameter frequency converter 110 can be configured as a frequency up converter circuit or a frequency down converter circuit.

[0046] For example, assuming it has frequency (or angular frequency) The microwave input signal is applied to the first port P1 and has a frequency. The pump signal is applied to the pump port. Depending on whether the parameter frequency converter 110 is configured as a frequency up-converter or a frequency down-converter, the parameter frequency converter 110 will output a frequency... (or angular frequency) The signal is either up-converted or down-converted. Furthermore, depending on the type of parametric frequency mixing performed by the parametric frequency converter 110 (e.g., three-wave mixing or four-wave mixing), the up-converted signal will have a frequency... (for three-wave mixing) or (Used for four-wave mixing). On the other hand, for a downconverter configuration, the downconverted signal will have a frequency... (for three-wave mixing) or (Used for four-wave mixing)

[0047] Furthermore, in all configurations, the frequency conversion procedure of the parameter frequency converter 110 causes the phase of the pump signal to be assigned to the up-converted or down-converted signal. Specifically, the phase of the up-converted or down-converted signal is phase-shifted proportionally to the phase of the pump signal.

[0048] Although Figure 1B illustrates an exemplary embodiment in which the parametric frequency converter 110 includes a single pump port, depending on the specific implementation, the parametric frequency converter may operate using more than one pump port, allowing the parametric frequency converter 110 to have more than one pump port. Furthermore, the method of injecting or coupling the pump signal into the parametric frequency converter 110 will depend on the specific implementation, such as a separate circuitry for a SQUID, such as a duplexer, directional coupler, or flux bias line. As explained in further detail below, the parametric frequency converter 110 can be implemented using various circuit architectures, including but not limited to traveling wave frequency converter (TWFC) circuitry or SQUID-based parametric frequency mixer circuitry, exemplary embodiments of which will be described in further detail below in conjunction with Figures 2, 3A, and 3B.

[0049] Next, referring to Figure 1C, the parametric amplifier 120 is a circuit configured to amplify an input signal through a parametric frequency mixing procedure, which is executed by modulating the nonlinear components of the parametric amplifier 120 using a pump signal. The parametric amplifier 120 includes a first port P1, a second port P2, and a control port (or pump port). The parametric amplifier 120 receives an input signal, for example, at the first port P1, and outputs an amplified signal from the second port P2, wherein the pump signal applied to the pump port provides power for amplifying the input signal. Furthermore, as a result of the parametric frequency mixing and amplification procedure, the parametric amplifier 120 generates an amplified idler signal, which, along with the amplified signal, is output from the second port P2.

[0050] More specifically, assuming frequency (or angular frequency) The microwave input signal is applied to the first port P1 and has a frequency. The pump signal is applied to the pump port. The parameter amplifier 120 will generate a frequency with the input signal. The amplified output signal, and the signal with frequency (or angular frequency) The idler signal (or idler frequency modulation) is generated as a result of a nonlinear amplification process. Furthermore, depending on the type of parametric frequency mixing performed by the parametric amplifier 120 (e.g., three-wave mixing or four-wave mixing), the resulting idler signal will have a frequency... (for three-wave mixing) or (For four-wave mixing). In addition, the phase of the pump signal is assigned to the idler signal (or idler frequency modulation), wherein the idler signal is phase-shifted in proportion to the frequency of the pump signal.

[0051] Although Figure 1C illustrates an exemplary embodiment in which the parametric amplifier 120 includes a single pump port, depending on the specific implementation, the parametric amplifier may operate using more than one pump frequency modulation, such that the parametric amplifier 120 may have more than one pump port. Furthermore, the method of injecting or coupling the pump signal into the parametric amplifier 120 will depend on the specific implementation, such as a duplexer, directional coupler, or separate circuitry for the flux bias line, as explained in further detail below. The parametric amplifier 120 may be implemented using various circuit architectures, including but not limited to Josephson traveling wave parametric amplifier (JTWPA) circuits or SQUID-based parametric amplifiers, exemplary embodiments of which will be described in further detail below in conjunction with Figures 2, 3A, and 3B.

[0052] Figure 2 schematically illustrates a Josephson junction traveling-wave parameter circuit according to an exemplary embodiment of the present disclosure, which can be used to implement an interference configuration of a broadband isolator and a directional quantum-limited amplifier. Specifically, Figure 2 schematically illustrates a Josephson junction traveling-wave parameter circuit 200, which can be configured to operate as a Josephson traveling-wave parameter amplifier (JTWPA) circuit or a Josephson traveling-wave frequency converter (JTWFC). The Josephson junction traveling-wave parameter circuit 200 includes an input port PIN, an output port POUT, and a nonlinear transmission line comprising a series of unit cells 2101, 2102, 2103, ..., 210i (collectively referred to as unit cell 210). Each unit cell 2101, 2102, 2103, ..., 210i of the nonlinear transmission line includes individual Josephson junctions J1, J2, J3, ..., Ji and individual capacitors C1, C2, C3, ..., Ci. Josephson junctions J1, J2, J3, ..., Ji are connected in series between the input port PIN and the output port POUT. In each unit cell 210, individual capacitors C1, C2, C3, ..., Ci provide capacitance to the ground GND node, and individual Josephson junctions J1, J2, J3, ..., Ji provide both inductance and nonlinearity.

[0053] Additionally, the Josephson junction traveling-wave parameter circuit 200 includes a dispersive element 220 (e.g., a dispersive resonator) configured to add dispersion along the transmission line, thereby conserving energy and momentum simultaneously during amplification or frequency conversion procedures. In some embodiments, as shown in FIG2, the dispersive element 220 includes a microwave LC resonator circuit comprising a capacitor Cr and an inductor Lr connected in parallel, and a coupling capacitor Cc coupling the LC resonator to the nonlinear transmission line of the Josephson junction traveling-wave parameter circuit 200. Although FIG2 shows a single dispersive element 220 for ease of illustration, the Josephson junction traveling-wave parameter circuit 200 includes multiple implementations of the dispersive element 220 positioned at various points along the nonlinear transmission line. For example, in some embodiments, every nth unit cell (e.g., n=3) contains an implementation of the dispersive element 220. The dispersive resonator is configured to maintain phase matching to cancel the phase difference between different modes propagating in the Josephson junction traveling-wave parameter circuit 200. Typically, the dispersive element 220, which includes an LC resonator and an associated coupling capacitor Cc, is designed to set the desired frequency range to achieve phase matching and cancel the dispersion along the transmission line of the Josephson junction traveling wave parameter circuit 200.

[0054] Figure 2 schematically illustrates an exemplary operating mode of the Josephson junction traveling wave parameter circuit 200 when configured as JTWPA. Specifically, Figure 2 schematically illustrates the input signal 230 and pump signal 240 applied to the input port PIN, and a plurality of output signals from the output port POUT, including an amplified output signal 231, an output pump signal 241, and an idler signal 250. The input signal 230 includes a signal frequency (denoted as ). The pump signal 240 includes a microwave signal with a pump frequency (denoted as...). The microwave signal provides a signal frequency for use in signaling. The power of the input signal 230 is amplified. In some embodiments, the directional coupler 225 is used to couple the input signal 230 and the pump signal 240 to the input port PIN. The idler signal 250 has an idler frequency (denoted as...). The microwave signal is generated as a result of a nonlinear amplification process. For example, as mentioned above, for a four-wave mixing process, the idler signal 250 has a frequency that serves as the input signal frequency. and pump signal frequency Frequency of the function ,as follows: .

[0055] When configured as JTWPA, the Josephson junction traveling wave parameter circuit 200 receives the input signal 230 and the pump signal 240, and amplifies the input signal 230 by acquiring power from the self-pump signal 240. For example, in a four-wave mixing process, two pump photons are converted to signals at the signal frequency. The new photon and the frequency of the idler wave The new photon. This is schematically shown in Figure 2, where the amplified output signal 231 is represented by an arrow thicker than the arrow representing the input signal 230, and where the input pump signal 240 is represented by an arrow thicker than the arrow representing the output pump signal 241.

[0056] The Josephson interface traveling-wave parameter circuit 200 can be configured to operate as a Josephson traveling-wave frequency converter circuit by changing certain parameters and utilizing a pump frequency selected to achieve frequency conversion (e.g., converting the input signal frequency to the output idler frequency). For example, the Josephson traveling-wave frequency converter circuit can be configured to perform four-wave mixing and frequency upconversion, wherein the frequency of the input pump signal (e.g., pump signal 240, FIG. 2) is... and the frequency of the idler signal (e.g., idler signal 250, Figure 2). It has the following relationship: This is related to the frequency at which the JTWPA circuit operates. Slightly different.

[0057] Figure 3A schematically illustrates a dual-port SQUID-based parametric frequency mixer circuit that can be used to implement a superconducting parametric interferometer circuit according to an exemplary embodiment of the present disclosure. Specifically, Figure 3A schematically illustrates a parametric frequency mixer circuit 300, which includes a first port P1, a second port P2, a pump port, a first linear circuit 301, a second linear circuit 302, a DC-SQUID 303, and a coupling inductor LC disposed adjacent to the DC-SQUID 303. The DC-SQUID 303 includes a superconducting loop that includes two Josephson junctions, including a first Josephson junction J1 and a second Josephson junction J2. In some embodiments, linear circuits 301 and 302 include a passive filter circuit that jointly implements a bandpass filter.

[0058] Linear circuits 301 and 302 are filter networks that perform parameter coupling via modulation of DC-SQUID 303 by applying a pump signal to the pump port to induce parameter frequency mixing and thereby perform parameter amplification or parameter frequency conversion, depending on the circuit configuration. The pump signal (e.g., a continuous pump signal frequency with a DC offset for three-wave mixing) is applied to the pump port, and in response, a coupling inductor LC (which is positioned adjacent to and near DC-SQUID 303) generates a magnetic flux bias through the superconducting loop of DC-SQUID 303. The magnetic flux bias modulates the inductance of the Josephson junction and thus achieves parametric frequency mixing with the input signal applied to the first port P1, resulting in parametric amplification or parametric frequency conversion of the input signal, depending on the configuration of the parametric frequency mixing circuit 300.

[0059] Figure 3B schematically illustrates a dual-port SQUID-based parametric frequency mixer circuit that can be used to implement a superconducting parametric interferometer circuit according to another exemplary embodiment of this disclosure. Specifically, Figure 3B schematically illustrates a parametric frequency mixer circuit 310, which includes a first port P1, a second port P2, a pump port, a first passive filter circuit 311, a second passive filter circuit 312, a DC-SQUID 313, and a coupling inductor LC disposed adjacent to the DC-SQUID 313. The first passive filter circuit 311 includes an inductor L1, capacitors C1, C2, and C3, and an LC resonator 311-1. The second passive filter circuit 312 includes an inductor L2, capacitors C4, C5, and C6, and an LC resonator 312-1. Figure 3B illustrates an exemplary embodiment in which the first passive filter circuit 311 and the second passive filter circuit 312 jointly implement a multipole reactive inverting bandpass filter. The first passive filter circuit 311 and the second passive filter circuit 312 are parametrically coupled by the pump signal applied to the pump port via DC-SQUID modulation, as can be easily understood by those familiar with this technology.

[0060] In some embodiments, the directional amplifier circuit can be implemented using an interferometric configuration consisting of an actuator of hybrid coupler 100 and parametric amplifier 120. For example, FIG4 schematically illustrates a superconducting parametric interferometer circuit configured to provide directional amplification according to an exemplary embodiment of the present disclosure. Specifically, FIG4 schematically illustrates an interferometric directional amplifier circuit 400, which includes a first hybrid coupler 410-1, a second hybrid coupler 410-2, a first parametric amplifier 420-1, and a second parametric amplifier 420-2. In the exemplary embodiment of FIG4, the first hybrid coupler 410-1 and the second hybrid coupler 410-2 each include a 90-degree hybrid coupler. The first parametric amplifier 420-1 and the second parametric amplifier 420-2 are implemented using the same parametric amplifier circuit architecture and are nominally identical. The first parametric amplifier 420-1 and the second parametric amplifier 420-2 can be implemented using any suitable parametric amplifier architecture (such as those discussed herein).

[0061] The interference directional amplifier circuit 400 includes a first port P1, a second port P2, a third port P3, and a fourth port P4. In the exemplary embodiment shown in FIG4, the interference directional amplifier circuit 400 operates essentially as a dual-port circuit by using the first port P1 as a signal input port and the second port P2 as an output port, wherein the third port P3 and the fourth port P4 are isolated by respective terminals T2 and T1 (e.g., 50 Ohm terminals). The first parametric amplifier 420-1 and the second parametric amplifier 420-2 are coupled in parallel between the first hybrid coupler 410-1 and the second hybrid coupler 410-2. Specifically, the first parametric amplifier 420-1 is located in the first branch B1 of the interference directional amplifier circuit 400 (e.g., In the branch), the second parameter amplifier 420-2 is placed in the second branch B2 of the interference directional amplifier circuit 400 (e.g., In the branch), the first branch B1 and the second branch B2 are coupled in parallel between the first hybrid coupler 410-1 and the second hybrid coupler 410-2.

[0062] As further schematically shown in Figure 4, the first parametric amplifier 420-1 is driven by the first pump signal Pump_1, and the second parametric amplifier 420-2 is driven by the second pump signal Pump_2. In some embodiments, the first pump signal Pump_1 and the second pump signal Pump_2 have the same pump frequency. and phase shift For example, in the exemplary embodiment of Figure 4, the second pump signal Pump_2 includes the pump frequency. and phase And the first pump signal Pump_1 contains the same pump frequency. and phase ,in This indicates the phase offset (or phase difference) between the first pump signal Pump_1 and the second pump signal Pump_2. In an exemplary embodiment where the first parametric amplifier 420-1 and the second parametric amplifier 420-2 each implement 4-wave mixing, the phase difference between the first pump signal Pump_1 and the second pump signal Pump_2... Set as, for example or At that time, interference-oriented amplification is achieved. On the other hand, in an exemplary embodiment where the first parameter amplifier 420-1 and the second parameter amplifier 420-2 each implement three-wave mixing, when the phase difference between Pump_1 and Pump_2... Set as, for example (where Pump_1 and Pump_2 are in phase), achieving interference-directed amplification.

[0063] In the exemplary operating mode, the interference directional amplifier circuit 400 of Figure 4 is configured to (i) receive a frequency at the first (input) port P1. The input signal S_In, (ii) is amplified by the first parameter amplifier 420-1 and the second parameter amplifier 420-2 to generate an idler signal, and (iii) the constructive interference of the idler signal generates a frequency at the second (output) port P2. The idler signal (Idler_Out) is amplified, and (iv) the input signal is dissipated at the third (isolation) port P3 via terminal T2 and amplified again. More specifically, the interference directional amplifier circuit 400 operates as follows.

[0064] Having frequency The input signal S_In is input to the first (input) port P1, and the first hybrid coupler 410-1 splits the input signal S_In into a first signal Signal_1 and a second signal Signal_2, wherein Signal_1 and Signal_2 each have approximately 50% of the power of the input signal S_In, but The phase difference. The first signal Signal_1 (has (phase) from the first hybrid coupler 410-1 The branch is applied to the first branch B1, while the second signal Signal_2 (with...) (phase) from the first hybrid coupler 410-1 The branch is applied to the second branch B2.

[0065] The first signal Signal_1 is input to the first parametric amplifier 420-1, which generates and outputs a first idler signal Idler_1 (and an amplified signal Signal_1A). The second signal Signal_2 is input to the second parametric amplifier 420-2, which generates and outputs a second idler signal Idler_2 (and an amplified signal Signal_2A). Through parametric amplification by the first and second parametric amplifiers 420-1 and 420-2, the phases of the first idler Idler_1 and the second idler Idler_2 will depend, respectively, on the phases of Signal_1 and Signal_2, and the phase offset between the first pump signal Pump_1 and the second pump signal Pump_2.

[0066] Specifically, the phases of the first idler Idler_1 and the second idler Idler_2 will each depend at least partially on the conjugate of the first signal Signal_1 and the second signal Signal_2, thereby corresponding to the conjugate (negative) phases of the first signal Signal_1 and the second signal Signal_2, respectively. Specifically, in the exemplary embodiment of Figure 4, since Signal_1 has... The phase of the first parameter amplifier 420-1 will therefore be... The conjugate (negative) phase is assigned to the first idler signal Idler_1. On the other hand, since Signal_2 has The phase of the second parameter amplifier 420-2 will therefore The combined (negative) phase is assigned to the second idler wave Idler_2.

[0067] Furthermore, the phase difference between the first idler signal Idler_1 and the second idler signal Idler_2 will depend at least in part on the phase difference between the first pump signal Pump_1 and the second pump signal Pump_2. The type of frequency mixing performed by the first parametric amplifier 420-1 and the second parametric amplifier 420-2. Specifically, as mentioned above, for 3-wave mixing, the parametric amplifier imparts a phase shift proportional to 1 times the phase of the pump signal to the idler signal, while for 4-wave mixing, the parametric amplifier imparts a phase shift proportional to 2 times the phase of the pump signal to the idler signal.

[0068] In the exemplary embodiment of the interference directional amplifier circuit 400 in Figure 4, it is assumed that the first parameter amplifier 420-1 and the second parameter amplifier 420-2 perform 4-wave mixing, and there is a frequency difference between the first pump signal Pump_1 and the second pump signal Pump_2. The phase difference. In this case, the first idler wave Idler_1 will have the phase difference given by the amplification of Signal_1. Phase shift (i.e., no phase shift) (this is because the conjugate (negative) phase of the first signal Signal_1 is However, it will have a phase offset from the first pump signal Pump_1. bestow it The phase shift. Therefore, the first idler wave Idler_1 applied to the second hybrid coupler 410-2 will essentially have The phase of.

[0069] In addition, the second idler wave Idler_2 will have the amplification given by Signal_1. The phase, which has The phase of Signal_1 is the conjugate (negative) phase. Furthermore, the second pump signal Pump_2 will not effectively change the phase of the second idler Idler_2. Therefore, the second idler Idler_2 applied to the second hybrid coupler 410-2 will have... Phase shift.

[0070] The second hybrid coupler 410-2 combines the first idler Idler_1 and the second idler Idler_2 at the second (output) port P2 via constructive interference. More specifically, the first idler Idler_1 (having...) The phase of the second hybrid coupler 410-2 will be transmitted via the second hybrid coupler 410-2. The branch is transmitted to the second (output) port P2, so that the phase of the first idler wave Idler_1 remains unchanged and is maintained. The second idle wave Idler_2 (with) The phase of the second hybrid coupler 410-2 will be transmitted via the second hybrid coupler 410-2. The branch is transmitted to the second (output) port P2, where the phase of the second idler wave Idler_2 is shifted. This effectively offsets Phase, such that the second idler wave Idler_2 will have at the second (output) port P2 The phase. At the second (output) port P2, the first idler Idler_1 and the second idler Idler_2 will have essentially the same phase (e.g., (phase) and thus through constructive interference combination to generate Idler_Out at the second (output) port P2.

[0071] It should be noted that at the third port P3 (which is isolated by terminal T2), the first idler Idler_1 and the second idler Idler_2 will be at or near the position of the terminal. The phase shift causes destructive interference between Idler_1 and Idler_2 at port P3. More specifically, the first idler wave Idler_1 (with...) (phase) via the second hybrid coupler 410-2 The branch transmission to the third port P3 causes a further phase shift in Idler_1. Furthermore, the second idler wave Idler_2 is transmitted via the second hybrid coupler 410-2. The branch transmission is sent to the third port P3, enabling Idler_2 to... The phase is not shifted. Therefore, at the third port P3, the first idler signal Idler_1 ( (phase) and the second idler signal Idler_2 ( (phase) has at or near The phase shift causes destructive interference between the first idler signal Idler_1 and the second idler signal Idler_2 at the third port P3.

[0072] Furthermore, at the second (output) port P2, the amplified signal Signal_1A (output from the first parametric amplifier 420-1) and the amplified signal Signal_2A (output from the second parametric amplifier 420-2) will have signals at or near the level of... The phase shift causes destructive interference between the amplified signals Signal_1A and Signal_2A at the second (output) port P2. More specifically, the amplified signal Signal_1A (with...) (phase) via the second hybrid coupler 410-2 The branch transmits to the second (output) port P2, ensuring that the phase of Signal_1A remains unchanged. On the other hand, the second amplified signal Signal_2A (with...) (phase) via the second hybrid coupler 410-2 The tributary is transmitted to the second (output) port P2, so that Signal_2A has at the second (output) port P2. Therefore, at the third port P3, the first amplified signal Signal_1A and the second amplified signal Signal_2A will have a phase at or near the phase. The phase mismatch causes destructive interference between Signal_1A and Signal_2A at the second (output) port P2. On the other hand, at the third (isolation) port P3, the first amplified signal Signal_1A and the second amplified signal Signal_2A will each have their own... The phase of the signal is used to constructively interfere to generate an amplified version of the input signal, which is terminated via terminal T2.

[0073] Furthermore, when a frequency is applied at the second (output) port P2 When the signal is transmitted, the interference directional amplifier provides isolation in the reverse direction (e.g., isolation in the transmission direction S12). Specifically, as schematically shown in Figure 4, when the frequency is... When the signal is applied to the second (output) port P2, the second hybrid coupler 410-2 will equally divide the signal into two branches on the first branch B1 and the second branch B2. Two signals with a phase difference. The first hybrid coupler 410-1 receives and equally divides each of the two signals from the first branch B1 and the second branch B2, and (i) constructively interferometrically combines the signals at the fourth (isolation) port P4, wherein the signals have a frequency The signal is dissipated by terminal T1, and (ii) at the first (input) port P1, a destructive interference cancellation signal is generated, thereby eliminating or significantly suppressing any signal power output from the first (input) port P1. Similarly, the mismatched reflection terminals at the inputs of the first parametric amplifier 420-1 and the second parametric amplifier 420-2 are connected to the fourth (isolation) port P4, and are attributed to the difference between the reflected signals at the first (input) port P1. The phase mismatch is canceled out at the first (input) port P1 via destructive interference.

[0074] It should be noted that the interference directional amplifier circuit 400 in Figure 4 operates in a similar manner to that described above in the exemplary embodiment, in which the first parametric amplifier 420-1 and the second parametric amplifier 420-2 are configured to perform four-wave mixing and are of the same frequency and phase (i.e., The first pump signal Pump_1 and the second pump signal Pump_2 drive the circuit. Furthermore, the interference directional amplifier circuit 400 in Figure 4 operates in a similar manner to that described above in the exemplary embodiment, where the first parametric amplifier 420-1 and the second parametric amplifier 420-2 are configured to perform three-wave mixing and are driven by signals having the same frequency and the same phase (i.e., ...). The first pump signal Pump_1 and the second pump signal Pump_2 drive the pump.

[0075] Next, in some embodiments, the broadband isolator circuit can be implemented using an interferometric configuration consisting of hybrid coupler 100 and an execution entity of parameter frequency converter 110. For example, FIG5 schematically illustrates a superconducting parameter interferometer circuit configured to provide isolation according to an exemplary embodiment of the present disclosure. Specifically, FIG5 schematically illustrates an interferometric isolator circuit 500, which includes a first hybrid coupler 510-1, a second hybrid coupler 510-2, a first parameter frequency converter 520-1, and a second parameter frequency converter 520-2. In the exemplary embodiment of FIG5, the first hybrid coupler 510-1 and the second hybrid coupler 510-2 each include a 90-degree hybrid coupler. The first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are implemented using the same parameter frequency converter circuit architecture and are nominally identical. In some embodiments, the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 can be implemented using any suitable parameter frequency architecture (such as those discussed herein).

[0076] The interference isolator circuit 500 includes a first port P1, a second port P2, a third port P3, and a fourth port P4. In the exemplary embodiment shown in FIG5, the interference isolator circuit 500 operates essentially as a dual-port circuit by using the first port P1 as a signal input port and the second port P2 as an output port, wherein the third port P3 and the fourth port P4 are isolated by respective terminals T2 and T1 (e.g., 50 Ohm terminals). A first parameter frequency converter 520-1 and a second parameter frequency converter 520-2 are coupled in parallel between a first hybrid coupler 510-1 and a second hybrid coupler 510-2. Specifically, the first parameter frequency converter 520-1 is located in the first branch B1 (e.g., 0-degree branch) of the interference isolator circuit 500, while the second parameter frequency converter 520-2 is located in the second branch B2 (e.g., ...) of the interference isolator circuit 500. In the branch), the first branch B1 and the second branch B2 are coupled in parallel between the first hybrid coupler 510-1 and the second hybrid coupler 510-2.

[0077] As further schematically shown in Figure 5, the first parameter frequency converter 520-1 is driven by the first pump signal Pump_1, and the second parameter frequency converter 520-2 is driven by the second pump signal Pump_2. In some embodiments, the first pump signal Pump_1 and the second pump signal Pump_2 have the same pump frequency. and the phase shift between them (or phase difference). For example, in the exemplary embodiment of Figure 5, the second pump signal Pump_2 includes the pump frequency. and phase And the first pump signal Pump_1 contains the same pump frequency. and phase ,in This indicates the phase offset (or phase difference) between the first pump signal Pump_1 and the second pump signal Pump_2. In an exemplary embodiment where the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 each implement 4-wave mixing, the phase difference between the first pump signal Pump_1 and the second pump signal Pump_2... Set as, for example At that time, interference isolation is achieved. On the other hand, in an exemplary embodiment where the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 each perform three-wave mixing, when the phase difference between the first pump signal Pump_1 and the second pump signal Pump_2 is... Set as, for example At that time, an intervention and isolation agreement was reached.

[0078] In the exemplary operating mode, the interference isolator circuit 500 of Figure 5 is configured to (i) receive a frequency at the first (input) port P1. The input signal S_In, (ii) is up-converted or down-converted by the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 to change the frequency of the input signal S_In. And generate individual up-frequency or down-frequency signals (indicated as Up / Dn), (iii) generate a frequency signal at the second (output) port P2 by constructive interference of the Up / Dn signal. The frequency-converted output signal (Up / Dn_Out), (iv) dissipates the input signal S_In at the third (isolation) port P3 via the terminal T2. More specifically, the interference isolator circuit 500 operates as follows.

[0079] Having frequency The input signal S_In is input to the first (input) port P1, and the first hybrid coupler 510-1 splits the input signal S_In into a first signal Signal_1 and a second signal Signal_2, wherein Signal_1 and Signal_2 each have approximately 50% of the power of the input signal S_In, but The phase difference. The first signal Signal_1 (has (phase) from the first hybrid coupler 510-1 The branch is applied to the first branch B1, while the second signal Signal_2 (with...) (phase) from the first hybrid coupler 510-1 The branch is applied to the second branch B2.

[0080] The first signal Signal_1 is input to the first parameter frequency converter 520-1, which generates and outputs a frequency. The first frequency conversion signal is Up / Dn_1. The second signal, Signal_2, is input to the second parameter frequency converter 520-2, which generates and outputs a frequency... The second frequency-converted signal is Up / Dn_2. It should be noted that, depending on the configuration of the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2, after frequency conversion, signals at Signal_1 and Signal_2 frequencies can be used. A certain residual frequency component is maintained. In an exemplary embodiment where the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are configured as frequency upconversion converters, the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will be upconverted signals, which have (i) (for three-wave mixing) or (ii) (used for four-wave mixing) frequency On the other hand, in an exemplary embodiment where the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are configured as frequency downconverters, the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will be downconverted signals, which have (i) (for three-wave mixing) or (ii) (used for four-wave mixing) frequency .

[0081] Furthermore, the phases of the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will depend on the phases of the first input signal Signal_1 and the second input signal Signal_2, and the phases of the first and second pump signals Pump_1 and Pump_2, respectively. More specifically, the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will have phases corresponding to the phases of the respective first input signal Signal_1 and the second input signal Signal_2. Additionally, the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will have... (for three-wave mixing) or Additional phase shift (for four-wave mixing), where This represents the phase difference between the first pump signal Pump_1 and the second pump signal Pump_2 discussed above.

[0082] By way of example, assuming that in the exemplary embodiment of Figure 5, the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 perform 4-wave mixing, and there is a frequency between the first pump signal Pump_1 and the second pump signal Pump_2. The phase difference. In this case, the first frequency-converted signal Up / Dn_1 will have The phase shift is determined by the phase offset of the first pump signal Pump_1 relative to the second pump signal Pump_2. Assigned. The first frequency-converted signal Up / Dn_1 will be based on Signal_1. Phase and have The phase, and the second frequency-converted signal Up / Dn_2 will be based on Signal_2. Phase and have The phase. Furthermore, since the first parameter frequency converter 520-1 assigns the phase of the first pump signal Pump_1 to the phase of the first frequency-converted signal Up / Dn_1, the first frequency-converted signal Up / Dn_1 will have... The phase shift of the phase.

[0083] In this case, it will have The first frequency-converted signal Up / Dn_1 of the phase is applied to the second hybrid coupler 510-2, thereby converting the phase of the signal into a frequency-converted signal Up / Dn_1. The second frequency-converted signal Up / Dn_2, representing the phase of the first frequency-converted signal, is applied to the second hybrid coupler 510-2. The second hybrid coupler 510-2 combines the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 at the second (output) port P2 via constructive interference. More specifically, the first frequency-converted signal Up / Dn_1 (with...) (phase) via the second hybrid coupler 510-2 The branch is transmitted to the second (output) port P2, so that the phase of the first frequency-converted signal Up / Dn_1 remains unchanged and is maintained. The second frequency-converted signal Up / Dn_2 (has...) The initial phase) via the second hybrid coupler 510-2 The branch is transmitted to the second (output) port P2, where the phase of Up / Dn_2 is further shifted. This causes the second frequency-converted signal Up / Dn_2 to have at the second (output) port P2. The phase. At the second (output) port P2, the first idler signal Idler_1 and the second idler signal Idler_2 will have essentially the same phase (e.g., The phase of the signal is converted, and thus, through constructive interference combination, a frequency-converted output signal Up / Dn_Out is generated at the second (output) port P2. In some embodiments, as is known in the art, the frequency-converted output signal Up / Dn_Out has unity gain and some minimum power loss due to the Manley-Rowe energy relationship of the parameter device with nonlinear reactive elements. In this regard, the interference isolator circuit 500 of FIG5 is configured to operate as an isolator that transmits the frequency-converted signal Up / Dn_Out corresponding to the input signal S_In, but with a frequency modulation that is either up-converted or down-converted.

[0084] It should be noted that at the third port P3 (which is isolated by terminal T2), the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will be at or near the specified position. The phase shift causes disruptive interference between Up / Dn_1 and Up / Dn_2 at port P3. More specifically, the first frequency-converted signal Up / Dn_1 (with... The initial phase) via the second hybrid coupler 510-2 The branch transmission to the third port P3 causes a further phase shift in the first frequency-converted signal Up / Dn_1. , thus leading to The phase of the signal. Furthermore, the second frequency-converted signal Up / Dn_2 (with...) The initial phase) via the second hybrid coupler 510-2 The branch transmission is sent to the third port P3, so that the second frequency-converted signal Up / Dn_2... The phase is not shifted. Therefore, at port P3, the first frequency-converted signal Up / Dn_1 ( (phase) and the second frequency-converted signal Up / Dn_2 ( (phase) has at or near phase difference ( - This causes destructive interference between the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 at the third port P3.

[0085] Furthermore, at the second (output) port P2, the residual first signal Signal_1 (output from the first parameter frequency converter 520-1) and the residual second signal Signal_2 (output from the second parameter frequency converter 520-2) will have a state at or near the value of the first signal Signal_1 (output from the first parameter frequency converter 520-1) and the second signal Signal_2 (output from the second parameter frequency converter 520-2). The phase shift causes destructive interference between the residual first signal Signal_1 and the residual second signal Signal_2 at the second (output) port P2. More specifically, the residual Signal_1 (with...) (phase) via the second hybrid coupler 510-2 The branch is transmitted to the second (output) port P2, so that the phase of the residual Signal_1 remains unchanged. On the other hand, the phase of the residual Signal_2 (with...) (phase) via the second hybrid coupler 510-2 The branch is transmitted to the second (output) port P2, so that the residual Signal_2 has at the second (output) port P2. Therefore, at port P3, the residual signals Signal_1 and Signal_2 will be at or near the phase. The phase mismatch causes destructive interference between the residual signals Signal_1 and Signal_2 at the second (output) port P2. On the other hand, at the third (isolation) port P3, the residual signals Signal_1 and Signal_2 will each have their own... The phase of the signal is used to constructively interfere to generate a non-amplified version of the input signal S_In, which is terminated via terminal T2.

[0086] Furthermore, when a frequency is applied at the second (output) port P2 When a signal is transmitted, the interference isolator circuit 500 provides isolation in the reverse direction (e.g., isolation in the transmission direction S12). Specifically, as schematically shown in Figure 5, when a frequency is... When the signal is applied to the second (output) port P2, the second hybrid coupler 510-2 will equally divide the signal into two signals with a 90° phase difference on the first branch B1 and the second branch B2. The first hybrid coupler 510-1 receives and equally divides each of the two signals from the first branch B1 and the second branch B2, and (i) constructively interferometrically combines the signals at the fourth (isolation) port P4, wherein the signals have a frequency The signal is dissipated by terminal T1, and (ii) at the first (input) port P1, a destructive interference cancellation signal is generated, thereby eliminating or significantly suppressing any signal power output from the first (input) port P1. Similarly, the mismatched reflections at the inputs of the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are terminated at the fourth (isolation) port P4, and are destructively cancelled at the first (input) port P1 due to the 180° phase mismatch between the reflected signals at the first (input) port P1.

[0087] It should be noted that the interference isolator circuit 500 in Figure 5 operates in a similar manner to that described above in the exemplary embodiment, in which the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are configured to perform three-wave mixing and are composed of components having the same frequency and The first pump signal Pump_1 and the second pump signal Pump_2 are driven by phase offset. In this case, the first frequency-converted signal Up / Dn_1 will have The phase shift is determined by the phase offset of the first pump signal Pump_1 relative to the second pump signal Pump_2. Therefore, the first frequency-converted signal Up / Dn_1 and the second frequency-converted signal Up / Dn_2 will have the same phase and, through constructive interference combination at the second (output) port P2, simultaneously possess... The phase difference is thus canceled out at the third (isolation) port P3 by destructive interference.

[0088] Figure 6 schematically illustrates a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure. Specifically, Figure 6 schematically illustrates an interferometric isolator circuit 600, which includes a first hybrid coupler 610-1, a second hybrid coupler 610-2, a first parametric frequency converter 620-1, a second parametric frequency converter 620-2, and a delay line 630. In some embodiments, the first hybrid coupler 610-1 and the second hybrid coupler 610-2 each comprise a 90-degree hybrid coupler, but in other embodiments, the first hybrid coupler 610-1 and the second hybrid coupler 610-2 may be implemented using, for example, a 180-degree hybrid coupler. In some embodiments, the first parametric frequency converter 620-1 and the second parametric frequency converter 620-2 may be implemented using any suitable parametric frequency architecture (such as those discussed herein).

[0089] As further shown in Figure 6, the interference isolator circuit 600 includes a first port P1, a second port P2, a third port P3, and a fourth port P4. In some embodiments, the interference isolator circuit 600 operates essentially as a dual-port circuit by using the first port P1 as a signal input port and the second port P2 as an output port, wherein the third port P3 and the fourth port P4 are isolated by respective terminals T2 and T1 (e.g., 50 Ohm terminals). The interference isolator circuit 600 is configured to have a frequency at the first (input) port P1. The input signal S_In is transmitted to the second (output) port P2, which has a frequency The output signal S_Out (allows unit S21 transmission) simultaneously suppresses or blocks signals with frequency. The signal is transmitted from the second (output) port P2 to the first (input) port P1 (blocking S12 transmission), thereby providing non-reciprocal signal transmission between the first port P1 and the second port P2.

[0090] As schematically illustrated in Figure 6, the interference isolator circuit 600 includes a cascaded (or series) connection of a first parameter frequency converter 620-1 and a second parameter frequency converter 620-2, wherein the output of the first parameter frequency converter 620-1 is coupled to the input of the second parameter frequency converter 620-2. A delay line 630 is coupled in parallel with the cascaded first parameter frequency converter 620-1 and second parameter frequency converter 620-2 between a first hybrid coupler 610-1 and a second hybrid coupler 610-2. Specifically, the delay line 630 is located in the first branch B1 of the interference isolator circuit 600 (e.g., In the second branch (B2) of the interference isolator circuit 600, the cascaded first-parameter frequency converter 620-1 and second-parameter frequency converter 620-2 are located (e.g., In the branch), the first branch B1 and the second branch B2 are coupled in parallel between the first hybrid coupler 610-1 and the second hybrid coupler 610-2.

[0091] In some embodiments, the first parameter frequency converter 620-1 includes a parameter frequency up-converter, while the second parameter frequency converter 620-2 includes a parameter frequency down-converter. In other embodiments, the first parameter frequency converter 620-1 includes a parameter frequency down-converter, while the second parameter frequency converter 620-2 includes a parameter frequency up-converter. The first parameter frequency converter 620-1 and the second parameter frequency converter 620-2 can be implemented using any suitable parameter frequency converter architecture (such as those discussed herein). In some embodiments, a filter may be disposed in a second branch B2 between the first parameter frequency converter 620-1 and the second parameter frequency converter 620-2 to filter spurious tone resulting from parameter frequency conversion.

[0092] As further schematically shown in Figure 6, the first parameter frequency converter 620-1 is driven by the first pump signal Pump_1, and the second parameter frequency converter 620-2 is driven by the second pump signal Pump_2. In some embodiments, the first pump signal Pump_1 and the second pump signal Pump_2 have the same pump frequency. and phase shift (or phase difference). For example, the first pump signal Pump_1 contains the pump frequency. and phase Furthermore, the second pump signal Pump_2 contains the same pump frequency. and phase ,in Indicates the phase offset (or phase difference) between Pump_1 and Pump_2. The first parameter frequency converter 620-1 and the second parameter frequency converter 620-2 can perform 4-wave mixing or 3-wave mixing, wherein the phase offset... An appropriate phase is selected to implement interference isolation.

[0093] More specifically, cascading the first-parameter frequency converter 620-1 and the second-parameter frequency converter 620-2 to provide back-to-back parameter frequency up-conversion and frequency down-conversion allows the second branch B2 of the interference isolator circuit 600 to generate a signal with the same frequency as the input signal S_In. The phase of the signal, as well as the phase controlled by the first pump signal Pump_1 and the second pump signal Pump_2, ensures proper phasing in conjunction with the phase of the signal output of the first branch B1 of the interference isolator circuit 600, so as to achieve constructive interference at the second (output) port P2 and thereby generate an output signal S_Out with the same frequency as the input signal S_In. The delay line 630 in the first branch B1 is configured to provide phase balance between the two branches B1 and B2 of the interference isolator circuit 600 by matching the phase slope of the cascaded parameter up-conversion / down-conversion converter within a given frequency band of the signal of interest.

[0094] More specifically, in some embodiments, the interference isolator circuit 600 is configured to operate as follows. Having a frequency The input signal S_In is input to the first (input) port P1, and the first hybrid coupler 610-1 splits the input signal S_In into a first signal Signal_1 and a second signal Signal_2, wherein Signal_1 and Signal_2 each have approximately 50% of the power of the input signal S_In, but The phase difference. The first signal Signal_1 (has (phase) from the first hybrid coupler 610-1 The branch is applied to the first branch B1, while the second signal Signal_2 (with...) (phase) from the first hybrid coupler 610-1 The branch is applied to the second branch B2.

[0095] In the first branch B1, the first signal Signal_1 propagates along delay line 630, and delay line 630 outputs a signal Signal_1D containing a group-delayed version of Signal_1. Delay line 630 can be implemented using suitable techniques known to those skilled in the art. For example, delay line 630 can be a passive LC network implemented using a cascade of lumped inductors L and capacitors C, or a transmission line with distributed inductance and capacitance per unit length. In all cases, delay line 630 is designed to impart a group delay to the first signal Signal_1 in specified time increments to produce a group-delayed signal Signal_1D with the desired delay required to implement interference isolation.

[0096] In the second branch B2, it has The second phase signal, Signal_2, is input to the first parameter frequency converter 620-1. Assume the first parameter frequency converter 620-1 is a frequency up-conversion converter performing 4-wave mixing and the first pump signal, Pump_1, is... Then the first parameter, frequency converter 620-1, will generate a frequency... as well as The frequency signal after phase upconversion (because Frequency signal after upsampling The phase will be Signal_2. (Phase). Next, assuming that the second parameter frequency converter 620-2 is a frequency downconverter that performs 4-wave mixing, the second parameter frequency converter 620-2 will downconvert the frequency signal and then upconvert it. To generate Signal_2D, which has frequency The frequency signal is down-converted. This is because the second pump signal, Pump_2, is phase-shifted. This is caused by driving the second parameter frequency converter 620-2. In addition to the phase shift of the phase, the Signal_2D signal will also be based on the up-converted frequency signal. (Output from the first parameter frequency converter 620-1) Phase and have The phase, as discussed above.

[0097] Due to the frequency conversion of the cascaded parameters in the second branch B2, the signal Signal_2D will have a frequency and The total phase shift. The signal Signal_2D is applied from the second branch B2 to the second hybrid coupler 610-2 and via the second hybrid coupler 610-2. The branch is transmitted to the second (output) port P2, where the phase of Signal_2D is further shifted. This ensures that Signal_2D will have at the second (output) port P2. (or effectively) (phase)

[0098] On the other hand, signal Signal_1D is applied from the first branch B1 to the second hybrid coupler 610-2, and via the second hybrid coupler 610-2... The branch transmits to the second (output) port P2. Assume delay line 630 is configured to assign a constant group delay (matching the slope and frequency of the second branch B2) to the first signal Signal_1 to output a signal with, for example... If the group-delayed signal Signal_1D is a group-delayed signal, then signals Signal_1D and Signal_2D will have essentially the same phase at the second (output) port P2 (e.g., ), and therefore at the second (output) port P2, a constructive interference combination is used to generate a frequency The output signal is S_Out. It should be noted that the term "group delay" refers to the time delay incurred by the different frequency components of the input signal as it passes through delay line 630 (or filter 730 in Figure 7). Group delay indicates how much the envelope of the signal is delayed by delay line 630 (or filter 730 in Figure 7). Unlike frequency-varying phase delay, group delay is a total time delay concentrated across the entire spectrum of the signal's frequency components.

[0099] It should be noted that at port P3 (which is isolated by terminal T2), signals Signal_1D and Signal_2D will be at or near [position missing]. The phase shift causes destructive interference between signals Signal_1D and Signal_2D at port P3. More specifically, the first signal Signal_1D (with...) The initial phase) via the second hybrid coupler 610-2 The branch transmission to the third port P3 causes a further phase shift in Signal_1D. , thus leading to The phase of the signal. Furthermore, the second signal Signal_2D (with...) The initial phase) via the second hybrid coupler 610-2 The tributary transmission is sent to the third (isolated) port P3, enabling Signal_2D to... The phase is not shifted. Therefore, at the third (isolation) port P3, the first signal Signal_1D ( (phase) and the second signal Signal_2D ( (phase) has at or near phase difference ( - This causes destructive interference between Signal_1D and Signal_2D at the third (isolation) port P3.

[0100] Further attention should be paid to when there is a frequency When a signal is applied to the second (output) port P2, the signal is dissipated in the fourth (isolation) port P4 in the same manner as described above for the exemplary embodiments of Figures 4 and 5. Therefore, when a signal is input to the second (output) port, the interference isolator circuit 600 provides non-reciprocal transmission and thus provides isolation between the first port P1 and the second port P2.

[0101] Figure 7 schematically illustrates a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure. Specifically, Figure 7 schematically illustrates an interferometric isolator circuit 700 that is similar in architecture and operation to the interferometric isolator circuit 600 of Figure 6 discussed above, except that the interferometric isolator circuit 700 implements a filter 730 instead of a delay line. The filter 730 may be a unity-gain bandpass filter containing a bandwidth compatible with the intended operating frequency range. The filter 730 may be configured to have, for example, a group delay that provides the desired signal delay in the first branch B1 to generate a signal Signal_1D with the desired phase shift required to implement interferometric isolation, as discussed above.

[0102] It should be understood that the exemplary superconducting parametric interferometer circuits described herein are configured to provide wideband directional amplification and wideband isolation. Generally, the bandwidth of a given superconducting parametric interferometer circuit is set by the bandwidth of individual circuit components, and therefore the total bandwidth is limited by the circuit component with the smallest bandwidth. In the exemplary superconducting parametric interferometer circuits shown, for example, in Figures 4, 5, 6, and 7, the passive hybrid coupler can be designed to provide a wideband response using accepted microwave engineering techniques, and therefore, the passive hybrid coupler does not need to limit the bandwidth. In this regard, bandwidth-limiting components are typically parametric circuit components, such as parametric amplifiers and parametric frequency converters. However, parametric amplifiers and parametric frequency converters can be designed to provide wideband operation within the target operating frequency range using currently best available techniques known to those skilled in the art.

[0103] In the illustrative configuration of Figure 4, the interference directional amplifier circuit 400 can be implemented as a quantum-confined amplifier for various applications. In practice, it is assumed that the noise added by an amplifier with given parameters is quantum-confined in the best case, as has been confirmed using currently state-of-the-art superconducting parameter amplifiers. When used in the configuration shown in Figure 4, the added noise can be shown to be quantum-confined at the second (output) port P2 during amplification. Although each of the first parameter amplifiers 420-1 and the second parameter amplifier 420-2 in the first branch B1 and the second branch B2 adds noise due to amplification, this noise is distributed between the second port P2 and the third port P3. Therefore, the overall interference directional amplifier circuit 400 is still quantum-confined. In this respect, the illustrative interference directional amplifier circuit 400 can be implemented as a quantum-confined amplifier in a qubit readout chain.

[0104] It should be further understood that the illustrative interferometric isolator circuits 500, 600, and 700 of Figures 5, 6, and 7 can be used as isolators in the qubit readout chain of a superconducting quantum system. Depending on the given configuration of the interferometric isolator circuit used, the interferometric isolator circuit can be implemented instead of a passive ferrite-based isolator in the qubit readout chain. In the case where the interferometric isolator 500 of Figure 5 is used for isolation in the qubit readout chain, since the qubit readout signal is converted to a different frequency (e.g., idler frequency) by means of a parametric frequency converter, downstream components (e.g., amplifiers, filters, etc.) will be configured to process the frequency-converted signal. In addition, in order to combine the interferometric isolator circuit with other circuits used in the readout chain, additional filtering can be implemented to effectively cascade the interferometric isolator circuit device and downstream components.

[0105] It should be noted that the exemplary superconducting parametric interferometer circuits implemented using Josephson junction traveling-wave parameter circuits (e.g., JTWPA) described herein can be fabricated using a basic three-layer process. The passive microwave component of the hybrid coupler can be implemented in the same three-layer process, in a separate microwave monolithic integrated circuit (MMIC) process, or as a discrete component. In the most compact implementation of a given superconducting parametric interferometer circuit, the entire circuit can be fabricated on a single wafer. Alternatively, a given superconducting parametric interferometer circuit can be fabricated as a multi-wafer module or as a discrete component on a printed circuit board, wherein the hybrid coupler and the "on-wafer" Josephson junction traveling-wave parameter circuit are fabricated "off-wafer" separately.

[0106] The exemplary superconducting parameter interferometer circuits shown in Figures 4, 5, 6, and 7 schematically illustrate operation using at least two pump signals. As mentioned above, depending on the given circuit configuration, the pump signals have the same frequency but may have different phases. In this regard, in some embodiments, the given superconducting parameter interferometer circuit can be operated using a common pump drive, while using a local static phase shift to generate a phase difference, thereby simplifying the pump feed network. In practice, the given superconducting parameter interferometer circuit can be operated using two pump signals by using a common RF signal generator and an RF pump I / O line that extends through a cryostat to the given superconducting parameter interferometer circuit to feed a single RF pump signal, which is split at this end into two pump signals with the same frequency and the desired phase shift to drive the parametric amplifier or frequency converter of the given superconducting parameter interferometer circuit.

[0107] Furthermore, it should be noted that the exemplary superconducting parametric interferometer circuits shown in Figures 4, 5, 6, and 7 can be cascaded with filters, duplexers, and / or other passive microwave circuits configured to remove unwanted frequency components that could adversely affect downstream components. For example, filters, duplexers, and / or other passive microwave circuits can be used to remove pump-modulated frequencies, pump-modulated harmonics, and / or sideband frequency components (e.g., intermodulation components) generated and transmitted (or leaked due to non-idealities) by parametric frequency mixing operations performed by components of the superconducting parametric interferometer circuit, thereby suppressing the power of pump-modulated frequencies, pump-modulated harmonics, and / or sideband frequency components to prevent these unwanted frequency components from being transmitted to downstream circuitry.

[0108] Figures 8A and 8B illustrate simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide directional amplification according to an exemplary embodiment of this disclosure. Specifically, Figures 8A and 8B illustrate simulated scattering parameter waveforms of a simulated interferometric directional amplifier circuit having a circuit architecture based on the exemplary interferometric directional amplifier circuit 400 of Figure 4, wherein the first parametric amplifier 420-1 and the second parametric amplifier 420-2 are implemented using JTWPA. Figure 8A illustrates a simulated S21 waveform 800 based on power in dB (y-axis) as a function of frequency in GHz (x-axis), and Figure 8B illustrates a simulated S12 waveform 810 based on power in dB (y-axis) as a function of frequency in GHz (x-axis).

[0109] The simulated S21 waveform in Figure 8A is based on an input signal S_In (applied to the first (input) port P1) with a frequency of 4.0 GHz to 10.0 GHz and an amplified idler signal Idler_Out (at the second (output) port P2) with a frequency of 6.8 GHz to 12.8 GHz. This is achieved by using a pump frequency of 8.4 GHz and a phase shift of... The first pump signal Pump_1 and the second pump signal Pump_2 drive the first parametric amplifier 420-1 and the second parametric amplifier 420-2. The analog S21 waveform 800 in Figure 8A illustrates the interferometric directional amplifier circuit with a peak gain (e.g., better than about 15 dB) for the amplified idler signal Idler_Out in the range of 9.5 GHz to 12.8 GHz, where the gain is relatively stable.

[0110] Figure 8B illustrates the simulated S12 waveform 810, showing the isolation provided by the interference directional amplifier circuit in response to an input signal S_In applied to the second (output) port P2 at frequencies from 4.0 GHz to 10.0 GHz. Figure 8B shows that the power transfer (S12) of the input signal S_In from the second port P2 to the first port P1 is highly suppressed, for example, better than 20 dB from 5.6 GHz to 10 GHz. As mentioned above, the input signal S_In applied to the second (output) port P2 is essentially dissipated in the fourth (isolation) port P4, thereby providing high isolation in the opposite direction to that from the second (output) port P2 to the first (input) port P1.

[0111] Next, Figures 9A and 9B illustrate simulated scattering parameter waveforms of a superconducting parametric interferometer circuit configured to provide isolation according to an exemplary embodiment of this disclosure. Specifically, Figures 9A and 9B illustrate simulated scattering parameter waveforms of a simulated interferometric isolator circuit having a circuit architecture based on the exemplary interferometric isolator circuit 500 of Figure 5, wherein the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2 are implemented using a JTWFC configured to provide frequency upscaling. Figure 9A illustrates a simulated S21 waveform 900 based on power in dB (y-axis) as a function of frequency in GHz (x-axis), and Figure 9B illustrates a simulated S12 waveform 910 based on power in dB (y-axis) as a function of frequency in GHz (x-axis).

[0112] The simulated S21 waveform 900 in Figure 9A is based on an input signal S_In with a frequency of 4.0 GHz to 10.0 GHz (applied to the first (input) port P1) and an up-converted output signal with a frequency of 9.75 GHz to 15.75 GHz (output from the second (output) port P2). This is due to the use of a pump frequency of 2.75 GHz and a phase shift of... The first pump signal Pump_1 and the second pump signal Pump_2 drive the first parameter frequency converter 520-1 and the second parameter frequency converter 520-2. The analog S21 waveform 900 in Figure 9A illustrates that the interference isolation circuit provides near unity gain for the up-converted output signal in the range of 12.0 GHz to 14.0 GHz.

[0113] Figure 9B illustrates the simulated S12 waveform 910, showing the isolation provided by the interference isolator circuit in response to an input signal S_In applied to the second (output) port P2 at a frequency of 4.0 GHz to 10.0 GHz. Figure 9B shows that the power transfer (S12) of the input signal S_In from the second (output) port P2 to the first (input) port P1 is highly suppressed, for example, better than 20 dB from 5.5 GHz to 10 GHz. As mentioned above, the input signal S_In applied to the second (output) port P2 is essentially dissipated in the fourth (isolation) port P4, thereby providing high isolation in the opposite direction to that from the second (output) port P2 to the first (input) port P1.

[0114] Next, Figure 10 illustrates a simulated scattering parameter waveform 1000 of a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure. Specifically, Figure 10 illustrates simulated scattering parameter waveforms S21 and S12 for a simulated interferometric isolator circuit having a circuit architecture based on the exemplary interferometric isolator circuit 600 with delay line 630 of Figure 6, wherein the first parametric frequency converter 620-1 and the second parametric frequency converter 620-2 include a frequency up-converter and a frequency down-converter implemented using a SQUID-based parametric frequency converter (e.g., based on the architecture shown in Figure 3B).

[0115] More specifically, Figure 10 illustrates the analog S21 waveform of the signal power transmitted at the second (output) port P2. This waveform is obtained by applying an input signal S_In with a frequency of 4.5 GHz to 5.5 GHz to the first (input) port P1, while simultaneously driving the first parametric frequency converter 620-1 and the second parametric frequency converter 620-2 using a first pump signal Pump_1 and a second pump signal Pump_2 with the same pump frequency and a phase offset of ϕ = 270°. The analog S21 waveform illustrates that the interference isolation circuit provides unity gain (close to 0 dB) for the transmission of the input signal S_In from the first (input) port P1 to the second (output) port P2 within a bandwidth BW of approximately 4.95 GHz to approximately 5.15 GHz of the input signal S_In. In this case, the bandwidth BW is set by the bandwidth of the SQUID-based parametric frequency converter.

[0116] Additionally, Figure 10 illustrates the analog S12 waveform of the signal power output at the first (input) port P1, which is obtained by applying an input signal S_In with a frequency of 4.5 GHz to 5.5 GHz to the second (output) port P2. The analog S12 illustrates an isolation of approximately 15 dB or better, provided by an interference isolator circuit within a bandwidth BW of approximately 4.95 GHz to approximately 5.15 GHz for the input signal S_In applied to the second (output) port P2. As mentioned above, the input signal S_In applied to the second (output) port P2 is substantially dissipated in the fourth (isolation) port P4, thereby providing high isolation in the direction opposite to that from the second (output) port P2 to the first (input) port P1.

[0117] Next, Figure 11 illustrates simulated scattering parameter waveforms 1100 of a superconducting parametric interferometer circuit configured to provide isolation according to another exemplary embodiment of this disclosure. Specifically, Figure 11 illustrates simulated scattering parameter waveforms S21 and S12 for an analog interferometric isolator circuit having a circuit architecture based on the exemplary interferometric isolator circuit 700 with filter 730 of Figure 7, wherein the first parametric frequency converter 620-1 and the second parametric frequency converter 620-2 include a frequency up-converter and a frequency down-converter implemented using a SQUID-based parametric frequency converter (e.g., based on the architecture shown in Figure 3B).

[0118] More specifically, Figure 11 illustrates a simulated S21 waveform of the signal power transmitted at the second (output) port P2. This waveform is obtained by applying an input signal S_In with a frequency of 4.5 GHz to 5.5 GHz to the first (input) port P1, while simultaneously driving a first parametric frequency converter 620-1 and a second parametric frequency converter 620-2 with the same pump frequency and a phase offset of ϕ = 270° using a first pump signal Pump_1 and a second pump signal Pump_2. The simulated S21 waveform illustrates that the interference isolation circuit provides near unity gain (e.g., near 0 dB) for the transmission of the input signal S_In from the first (input) port P1 to the second (output) port P2 within a bandwidth BW of approximately 4.85 GHz to approximately 5.15 GHz of the input signal S_In.

[0119] Additionally, Figure 11 illustrates the analog S12 waveform of the signal power output at the first (input) port P1, which is obtained by applying an input signal S_In with a frequency of 4.5 GHz to 5.5 GHz to the second (output) port P2. The analog S12 illustrates an isolation of approximately 15 dB or better, provided by an interference isolator circuit within a bandwidth BW of approximately 4.85 GHz to approximately 5.15 GHz for the input signal S_In applied to the second (output) port P2. As mentioned above, the input signal S_In applied to the second (output) port P2 is substantially dissipated in the fourth (isolation) port P4, thereby providing high isolation in the direction opposite to that from the second (output) port P2 to the first (input) port P1.

[0120] Figure 12 schematically illustrates a readout circuit system of a quantum processing system according to an exemplary embodiment of the present disclosure, which may implement a superconducting parametric interferometer circuit in the qubit readout signal path to provide directional amplification and isolation. More specifically, Figure 12 schematically illustrates a qubit readout circuit system 1200 of a quantum computing system configured to read out the quantum state of at least one superconducting qubit. For example, the qubit readout circuit system 1200 includes a qubit resonator device 1202 comprising a superconducting qubit 1204, a readout resonator 1206, and a Purcell filter 1208, configured to perform dispersive qubit readout operation, selected as appropriate.

[0121] The qubit readout circuit system 1200 further includes a control circuit system configured to generate an RF readout control signal (RF_RO) using a dispersive readout scheme to read out the state of the superconducting qubit 1204. This dispersive readout scheme enables quantum nondestructive measurement of the state of the superconducting qubit 1204 to maintain the state of the superconducting qubit 1204. For example, the qubit readout circuit system 1200 includes a control signal chain that includes a waveform generator 1210 (or pulse envelope generator), which includes a digital-to-analog (DAC) circuit system 1211, a low-pass filter circuit system 1212, a first I / Q mixer 1213 (up-converter or down-converter mixer), and a local oscillator (LO) signal generator 1214.

[0122] Additionally, the qubit readout circuit system 1200 includes a readout signal chain comprising an interference isolator circuit 1220, an interference directional quantum confinement amplifier (QLA) 1221, a filter 1222, a high electron mobility transistor (HEMT) amplifier 1223, a second I / Q mixer 1224, and an analog-to-digital converter (ADC) circuit system 1225 that outputs a digital readout signal to a hardware- or software-based discriminator to determine the readout state of the superconducting qubit 1204.

[0123] Waveform generator 1210 is configured to generate and output analog I and Q control signals with a given type of pulse envelope (e.g., Gaussian square pulse envelope) in response to a readout control signal for use in qubit state readout. The analog I and Q control pulses are filtered by low-pass filter circuitry 1212. The filtered analog I and Q control pulses, together with the LO signal (LO_RO) generated by LO signal generator 1214, are applied to a first I / Q mixer 1213 to generate the RF readout control pulse RF_RO. Specifically, I / Q mixer 1213 is configured to mix the analog I and Q control pulses with the LO_Q signal at a given LO frequency (e.g., 7 GHz) to perform I / Q modulation and up-conversion and / or down-conversion using known techniques (e.g., single-sideband modulation) to generate the RF readout control pulse RF_RO.

[0124] An RF readout control signal RF_RO is applied to the input port of the Passell filter 1208 and then coupled to the readout resonator 1206. The readout resonator 1206 is capacitively coupled to the superconducting qubit 1204, thereby providing a qubit / resonator system. In some embodiments, the readout resonator 1206 comprises a coplanar waveguide resonator. For readout operation, in some embodiments, the center frequency of the RF readout control signal RF_RO corresponds to the resonant frequency of the readout resonator 1206 to perform dispersive qubit readout operation. In other embodiments, the frequency of RF_RO may not resonate with the readout resonator 1206, yet still provide information about the qubit state.

[0125] In the dispersion mechanism of qubit resonator coupling, the RF readout control signal RF_RO (with the necessary frequency modulation, pulse envelope shape, and pulse duration) interacts with the given qubit resonator device 1202 in such a way that the resulting readout signal RO reflected from the readout resonator 1206 is generated. The readout signal RO contains information related to the qubit state (e.g., phase and / or amplitude). In other words, the dispersion readout procedure generates an RF readout signal RO with a state-related phasor response, which is analyzed to distinguish the quantum states of the superconducting qubit 1204.

[0126] The readout signal RO output from the self-readout resonator 1206 is coupled to the Passell filter 1208 and then applied to the readout signal chain. For example, the Passell filter 1208 is designed to pass at the frequency of the readout signal RO while blocking energy transmission at the qubit frequency to enhance qubit lifetime and perform other functions as understood by those skilled in the art. The readout signal RO output is coupled to the readout signal chain, where the readout signal RO flows through the interference isolator circuit 1220 and is applied to the input port of the interference orientation QLA 1221 that amplifies the readout signal RO. The amplified readout signal RO output from the interference orientation QLA 1221 is transmitted along the signal chain including the filter 1222 and another isolator circuit of choice, amplified by the HEMT amplifier 1223, and applied to the input of the second I / Q mixer 1224. The second I / Q mixer 1224 mixes the RF readout signal RO and the LO_RO signal to perform a down-conversion operation, wherein the RF readout signal RO is down-converted and split into analog I and Q signals. The analog I and Q signals are input to the ADC circuit system 1225 and sampled by the ADC circuit system 1225 to generate separate digital I and Q signals indicating the amplitude and phase of the readout signal RO. The discriminator analyzes the digital I and Q signals to identify the measured quantum state of the superconducting quantum bit 1204 based on the amplitude and phase components of the readout signal RO.

[0127] It should be understood that Figure 12 is an illustrative, non-limiting embodiment of a high-level schematic diagram of a readout control circuitry system. The qubit readout circuitry system 1200 and the readout signal chain can be implemented using other components and configurations. For example, in some embodiments, when the Passell filter 1208 is not implemented, a circulator or feed line can be implemented in Figure 12 instead of the Passell filter 1208. Furthermore, a frequency multiplexing readout system (which implements frequency domain multiplexing) can be used to extend the readout chain in a quantum computing system to read the quantum states of superconducting qubits in a relatively large superconducting quantum computer. In a frequency multiplexing readout system, multiple readout resonators (with different resonant frequencies) are coupled to individual qubits and co-coupled to a communication bus. The communication bus is configured to allow the transmission of multiple readout signals with readout frequencies matching the resonant frequencies of the readout resonators, and thus the quantum states of multiple qubits can be read out simultaneously using a single input and a single output line.

[0128] In the exemplary embodiment of Figure 12, the interference isolator circuit 1220 can be implemented using any of the exemplary interference isolator circuits discussed herein (e.g., Figures 5, 6, or 7). Additionally, the interference-oriented QLA 1221 can be implemented using any of the exemplary interference-oriented amplifier circuits discussed herein (e.g., Figure 4). While the exemplary embodiment of Figure 12 illustrates implementations of both the interference isolator circuit 1220 and the interference-oriented QLA 1221, in other embodiments, the qubit readout circuitry system 1200 can implement the interference isolator circuit 1220 in conjunction with any suitable quantum-confining amplifier, such as a JTWPA, instead of the interference-oriented QLA 1221. Furthermore, in some embodiments, because the interference-oriented QLA 1221 provides both isolation and quantum-confining amplification, the interference-oriented QLA 1221 can be implemented alone without requiring a separate isolation circuit (e.g., the interference isolator circuit 1220) upstream of the interference-oriented QLA 1221.

[0129] Figure 13 schematically illustrates a quantum computing system 1300 including a quantum computing platform 1310, a control system 1320, and a quantum processor 1330. In some embodiments, the quantum computing platform 1310 implements a software platform configured to program a quantum computer to execute quantum computing algorithms 1312, which are implemented using, for example, quantum circuits that define computational routes consisting of coherent quantum operations on quantum data (such as qubits). Additionally, in some embodiments, the control system 1320 includes a multi-channel arbitrary waveform generator 1322 and a qubit readout circuitry system 1324. The quantum processor 1330 includes one or more solid-state quantum chips, comprising, for example, a superconducting qubit array 1332, and a network 1334 of qubit drive lines, coupler flux bias control lines, qubit state readout lines, pump control lines, and other circuitry QED components that may be required for a given application or quantum system configuration. The qubit readout circuit system 1324 may include interference isolator circuits and / or interference directional amplifier circuits in each of a plurality of qubit readout signal chains, which are implemented to read out the state of the qubits of the superconducting qubit array 1332, as described above in Figure 12.

[0130] In some embodiments, the control system 1320 and the quantum processor 1330 are housed in a dilution cryogenic system 1340, which generates cryogenic temperatures sufficient to operate the components of the control system 1320 for quantum computing applications. For example, the quantum processor 1330 may need to be cooled to near absolute zero, such as 10 to 15 milliklvin (mK), to allow superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution cryogenic system 1340 includes a multi-stage dilution cryostat, wherein the components of the control system 1320 can be maintained at different cryogenic temperatures as needed. For example, while the quantum processor 1330 may need to be cooled to, for example, 10 to 15 mK, depending on the configuration of the quantum computing system, the circuit components of the control system 1320 may operate at cryogenic temperatures greater than 10 to 15 mK (e.g., cryogenic temperatures in the range of 3K to 4K).

[0131] In some embodiments, the superconducting qubit array 1332 includes a quantum system of superconducting qubits, superconducting qubit couplers, and other components typically used to support quantum processing using qubits. The number of superconducting qubits in the superconducting qubit array 1332 can be on the order of tens, hundreds, thousands, or more. A network 1334 of qubit drive lines, coupler flux bias control lines, qubit state readout lines, etc., is configured to apply microwave control signals to the superconducting qubits and coupler circuit system in the superconducting qubit array 1332 to perform various types of gate operations, such as single-gate operations, entangled gate operations, error correction operations, etc., and to read the quantum state of the superconducting qubits. For example, when executing a quantum information processing algorithm, microwave control pulses are applied to the qubit drive lines of individual superconducting qubits to change the quantum state of the superconducting qubits (e.g., changing the quantum state of a given qubit between the ground state and an excited state, or changing it to a superposition state).

[0132] Furthermore, as mentioned above, the state readout line includes a readout resonator coupled to each individual superconducting qubit. The state of a given superconducting qubit can be determined using the readout port of the readout resonator via microwave transmission or reflection measurement. The state of the superconducting qubit is read out after the execution of a quantum algorithm. In some embodiments, as mentioned above, a dispersive readout operation is performed, wherein the state (e.g., ground state or excited state) of a given superconducting qubit is read out by utilizing a change in the resonant frequency of a given readout resonator coupled to a given superconducting qubit.

[0133] A network 1334 of qubit drive lines, coupler flux bias control lines, qubit state readout lines, etc., is coupled to a control system 1320 via a suitable hardware input / output (I / O) interface. This interface couples I / O signals between the control system 1320 and the quantum processor 1330. For example, the hardware I / O interface may include various types of hardware and components, such as RF cables, wiring, RF components, optical fibers, heat exchangers, filters, amplifiers, isolators, etc.

[0134] In some embodiments, when various gate operations are performed to execute a given quantum information processing algorithm, a multi-channel arbitrary waveform generator (AWG) 1322 and other suitable microwave pulse signal generators are configured to generate microwave control pulses applied to qubit drive lines and coupler drive lines to control the operation of superconducting qubits and associated qubit coupler circuitry. In some embodiments, the multi-channel AWG 1322 includes a plurality of AWG channels that control individual superconducting qubits within the superconducting qubit array 1332 of the quantum processor 1330. In some embodiments, each AWG channel includes a fundamental frequency signal generator, a digital-to-analog converter (DAC) stage, a filter stage, a modulation stage, an impedance matching network, and a phase-locked loop system to generate local oscillator (LO) signals (e.g., quadrature LO signals LO_I and LO_Q) for the respective modulation stages of the respective AWG channels.

[0135] In some embodiments, the multi-channel AWG 1322 includes an orthogonal AWG system configured to process quadrature signals, wherein the quadrature signals include in-phase (I) signal components and quadrature (Q) signal components. In each AWG channel, a baseband signal generator is configured to receive baseband data as input (e.g., from a quantum computing platform) and generate digital quadrature signals I and Q representing the input baseband data. In this process, the baseband data input to the baseband signal generator for a given AWG channel is separated into two quadrature digital components, including an in-phase (I) baseband component and a quadrature (Q) baseband component. The baseband signal generator for a given AWG channel generates the necessary digital quadrature baseband IQ signals required to generate an analog waveform (e.g., a sinusoidal voltage waveform) with a target center frequency, which is configured to operate or otherwise control a given qubit coupled to the output of the given AWG channel.

[0136] The DAC stage for a given AWG channel is configured to convert a digital baseband signal (e.g., a digital IQ signal output from a baseband signal generator) into an analog baseband signal (e.g., analog baseband signals I(t) and Q(t)). The filter stage for a given AWG channel is configured to filter the IQ analog signal components output from the DAC stage to generate a filtered analog IQ signal. The modulation stage for a given AWG channel is configured to perform analog IQ signal modulation (e.g., single-sideband (SSB) modulation) by mixing the filtered analog signals I(t) and Q(t) output from the filter stage with quadrature LO signals (e.g., in-phase LO signals (LO_I) and quadrature-phase LO signals (LO_Q)) to generate and output an analog RF signal (e.g., a SSB-modulated RF output signal).

[0137] In some embodiments, the qubit readout circuit system 1324 includes: a microwave pulse signal generator configured to apply microwave frequency modulation to a given readout resonator line of a given superconducting qubit to perform a readout operation to read out the state of the given superconducting qubit; and a circuit system configured to process the readout signal generated by the readout resonator line to determine the state of the given superconducting qubit using techniques known to those skilled in the art. In some embodiments, the qubit readout circuit system 1324 is implemented based on the exemplary readout circuit system shown in FIG. 12.

[0138] The quantum computing platform 1310 includes a software and hardware platform comprising various software layers configured to perform various functions, including but not limited to generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into a quantum combination language, implementing and utilizing a suitable quantum instruction set architecture (ISA), and performing calibration operations to calibrate quantum circuit elements and gate operations. Additionally, the quantum computing platform 1310 includes a hardware architecture such as a processor and memory, configured to control the execution of quantum applications and interfacing with the control system 1320 to (i) generate digital control signals, which are converted by the control system 1320 into analog microwave control signals to control the operation of the quantum processor 1330 when executing a given quantum application, and (ii) acquire and process digital signals received from the control system 1320, which represent the processing results generated by the quantum processor 1330 when executing various gate operations of a given quantum application.

[0139] In some exemplary embodiments, the quantum computing platform 1310 in FIG13 may be implemented using any suitable computing system architecture (e.g., as shown in FIG14) configured to implement methods supporting quantum computing operations by executing computer-readable program instructions embodied on a computer program product including one or more computer-readable storage media having such computer-readable program instructions for causing a processor to perform the control methods discussed herein.

[0140] The various forms disclosed herein are described by descriptive text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). Depending on the technology involved, operations may be performed in a different order than shown in a given flowchart, relative to any flowchart. For example, also depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or in a manner that at least partially overlaps in time.

[0141] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any group of one or more storage media (also referred to as “mediums”) commonly included in a group of one or more storage devices, which commonly include machine-readable program code corresponding to instructions and / or data for performing computer operations specified in a given CPP requirement. “Storage device” is any tangible means capable of retaining and storing instructions for use by a computer processor. Without limitation, computer-readable storage media may be electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, mechanical storage media, or any suitable combination of the foregoing. Some known types of storage devices that include such media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital discs (DVDs), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or dimples / pads formed in the main surface of the disc), or any suitable combination of the foregoing. The term computer-readable storage media as used in this disclosure should not be construed as storing data in the form of transient signals, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. Those skilled in the art will understand that data typically moves at random points in time during the normal operation of the storage device (such as during access, defrauding, or garbage collection), but this does not make the storage device transient, as the data is not transient when it is stored.

[0142] The computing environment 1400 in Figure 14 contains an example of an environment for executing at least some of the computer program code (block 1426) involved in executing quantum computing algorithms (e.g., quantum computing algorithm 1312, Figure 13). In addition to block 1426, the computing environment 1400 includes, for example, a computer 1401, a wide area network (WAN) 1402, an end-user device (EUD) 1403, a remote server 1404, a public cloud 1405, and a private cloud 1406. In this embodiment, computer 1401 includes processor set 1410 (including processing circuitry 1420 and cache 1421), communication mesh architecture 1411, volatile memory 1412, persistent storage 1413 (including operating system 1422 and block 1426, as identified above), peripheral device set 1414 (including user interface (UI) device set 1423, storage 1424 and Internet of Things (IoT) sensor set 1425) and network module 1415. Remote server 1404 includes remote database 1430. Public cloud 1405 includes gateway 1440, cloud coordination process module 1441, host physical machine set 1442, virtual machine set 1443 and container set 1444.

[0143] Computer 1401 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other portable computer, mainframe computer, quantum computer or any other form of computer or mobile device that is known or to be developed in the future, capable of running programs, accessing networks or querying databases, such as remote database 1430. As is fully understood in the field of computer technology, and depending on the technology, the performance of a computer implementation method may be distributed across multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 1400, the detailed discussion focuses on a single computer, specifically computer 1401, to keep the presentation as simple as possible. Computer 1401 may reside in the cloud, even if it is not shown in the cloud in Figure 14. On the other hand, except to any extent that can be definitively indicated, computer 1401 does not need to be in the cloud.

[0144] Processor set 1410 includes one or more computer processors of any type, known or to be developed in the future. Processing circuitry system 1420 may be distributed over multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry system 1420 may implement multiple processor threads and / or multiple processor cores. Cache 1421 is memory located within one or more processor chip packages and is typically used for data or code that should be readily accessible by the threads or cores running on processor set 1410. Cache memory is typically organized into multiple tiers depending on its relative proximity to the processing circuitry system. Alternatively, some or all of the cache used for the processor set may be located "off-chip". In some computing environments, processor set 1410 may be designed to use qubits and perform quantum operations.

[0145] Computer-readable program instructions are typically loaded onto computer 1401 to cause the processor set 1410 of computer 1401 to perform a series of operational steps and thereby affect the computer-implemented method, such that the instructions executed thereby will perform the methods specified in the flowcharts and / or descriptions of the computer-implemented method included in this document (collectively, the "method of the invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 1421 and other storage media discussed below. The program instructions and associated data are accessed by processor set 1410 to control and direct the execution of the method of the invention. In computing environment 1400, at least some of the instructions for executing the method of the invention may be stored in block 1426 of persistent storage 1413.

[0146] The communication mesh architecture 1411 is a signal transmission path that allows various components of computer 1401 to communicate with each other. Typically, this mesh architecture consists of switches and conductive paths, such as switches and conductive paths forming buses, bridges, physical input / output ports, and the like. Other types of signal communication paths, such as fiber optic communication paths and / or wireless communication paths, can be used.

[0147] Volatile memory 1412 is any type of volatile memory known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, but this is not necessary unless explicitly indicated. In computer 1401, volatile memory 1412 is located in a single package and inside computer 1401, but alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 1401.

[0148] Persistent storage 1413 is any form of non-volatile storage for a computer, known or to be developed in the future. Non-volatile means that the stored data is maintained regardless of whether the computer 1401 is powered or the persistent storage 1413 is powered directly. Persistent storage 1413 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, deleted, and overwritten. Some common forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 1422 may take several forms, such as various known dedicated operating systems, or open-source portable operating system interfaces employing a kernel. The code included in block 1426 typically includes at least some of the computer code involved in performing the methods of the present invention.

[0149] Peripheral device set 1414 includes a collection of peripheral devices for computer 1401. Data communication connections between peripheral devices and other components of computer 1401 can be implemented in various ways, such as Bluetooth connectivity, Near Field Communication (NFC) connectivity, cable connections (such as Universal Serial Bus (USB) cables), plug-in connections (e.g., Secure SD cards), connections via local area networks, and even connections via wide area networks such as the Internet. In various embodiments, UI device set 1423 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 1424 is external storage such as an external hard drive, or insertable storage such as an SD card. Storage 1424 may be persistent and / or volatile. In some embodiments, storage 1424 may take the form of a quantum computing storage device for storing data in qubit form. In embodiments requiring computer 1401 to have a large amount of storage (e.g., computer 1401 locally stores and manages a large database), this storage may then be provided by peripheral storage devices designed for storing extremely large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 1425 comprises sensors that can be used in Internet of Things (IoT) applications. For example, one sensor may be a thermometer, and another sensor may be a motion detector.

[0150] Network module 1415 is a collection of computer software, hardware, and firmware that allows computer 1401 to communicate with other computers via WAN 1402. Network module 1415 may include: hardware, such as a modem or Wi-Fi transceiver; software for packetizing and / or depacketizing data transmitted over a communication network; and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 1415 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software Defined Networking (SDN), the control and forwarding functions of network module 1415 are executed on physically separate devices, such that the control functions manage several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 1401 from an external computer or external storage device via a network adapter card or network interface included in network module 1415.

[0151] WAN 1402 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology known or to be developed in the future for transmitting computer data. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in an area such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0152] End-user device (EUD) 1403 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 1401), and may take any of the forms described above in connection with computer 1401. EUD 1403 typically receives helpful and useful information from the operation of computer 1401. For example, in the hypothetical scenario where computer 1401 is designed to provide recommendations to an end-user, these recommendations would typically be communicated to EUD 1403 via WAN 1402 from network module 1415 of computer 1401. In this way, EUD 1403 may display or otherwise present recommendations to the end-user. In some embodiments, EUD 1403 may be a user terminal device, such as a simplified user terminal, a multi-function user terminal, a mainframe computer, a desktop computer, etc.

[0153] Remote server 1404 is any computer system that provides at least some data and / or functionality to computer 1401. Remote server 1404 can be controlled and used by the same entity operating computer 1401. Remote server 1404 refers to one or more machines that collect and store helpful and useful data for use by other computers such as computer 1401. For example, in the hypothetical scenario where computer 1401 is designed and programmed to provide recommendations based on historical data, this historical data can then be provided from remote database 1430 of remote server 1404 to computer 1401.

[0154] The public cloud 1405 is any computer system available to multiple entities that provide on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without requiring direct active management by the user. Cloud computing typically utilizes resource sharing to achieve harmony and economies of scale. Direct and active management of the computing resources of the public cloud 1405 is performed by the computer hardware and / or software of the cloud coordination process module 1441. The computing resources provided by the public cloud 1405 are typically implemented by virtual computing environments running on various computers constituting the host entity machine set 1442, which is the total range of physical computers in and / or available to the public cloud 1405. Virtual computing environments (VCEs) typically take the form of virtual machines from the virtual machine set 1443 and / or containers from the container set 1444. It should be understood that such VCEs can be stored as images and can be transferred between and among various physical machine hosts, either as images or after individualization of the execution of the VCE. The cloud coordination process module 1441 manages the transmission and storage of images, deploys new VCE instances, and manages the active instances deployed by VCE. The gateway 1440 is a collection of computer software, hardware, and firmware that allows the public cloud 1405 to communicate via WAN 1402.

[0155] Here is a further explanation of Virtual Computing Environments (VCEs). A VCE can be stored as an "image." New active execution instances of a VCE can be individualized from an image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space execution instances, called containers. From the perspective of the program running within it, these isolated user-space execution instances typically behave like a real computer. A computer program running on a regular operating system can utilize all the resources of that computer, such as connectivity, files and folders, network sharing, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container; this feature is called containerization.

[0156] Aside from the fact that computing resources are only available to a single enterprise, private cloud 1406 is similar to public cloud 1405. While private cloud 1406 is depicted as communicating with WAN 1402, in other embodiments, private cloud may be completely disconnected from the internet and accessible only via a local / private network. A hybrid cloud is composed of multiple clouds of different types (e.g., private, group, or public cloud types) typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable coordinated processes, management, and / or data / application portability across the multiple constituent clouds. In this embodiment, both public cloud 1405 and private cloud 1406 are parts of a larger hybrid cloud.

[0157] Various embodiments of the present disclosure have been described for illustrative purposes, but such descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles, practical applications, or technical improvements to technologies found in the market, and to enable others skilled in the art to understand the embodiments disclosed herein.

[0158] 100: Hybrid Coupler 110: Parameter Frequency Converter 120: Parameter Amplifier 200: Josephson junction traveling wave parameter circuit 210: Unit cell 2101: Unit cell 2102: Unit cell 2103: unit cell 210i: unit cell 220: Dispersion element 225: Directional Coupler 230: Input signal 231: Amplified output signal 240: Pump signal 241: Output pump signal 250: Idle signal 300: Parameter Frequency Mixer Circuit 301: First Linear Circuit 302: Second Linear Circuit 303: DC-SQUID 310: Parameter-frequency mixer circuit 311: First Passive Filter Circuit 311-1: LC Resonator 312: Second Passive Filter Circuit 312-1: LC Resonator 313:DC-SQUID 400: Interference Directional Amplifier Circuit 410-1: First Hybrid Coupler 410-2: Second Hybrid Coupler 420-1: First-parameter amplifier 420-2: Second-parameter amplifier 500: Interference Isolator Circuit 510-1: First Hybrid Coupler 510-2: Second Hybrid Coupler 520-1: First Parameter Frequency Converter 520-2: Second Parameter Frequency Converter 600: Interference Isolator Circuit 610-1: First Hybrid Coupler 610-2: Second Hybrid Coupler 620-1: First Parameter Frequency Converter 620-2: Second Parameter Frequency Converter 630: Delay Line 700: Interference Isolator Circuit 730: Filter 800: Simulate S21 waveform 810: Simulate S12 waveform 900: Simulate S21 waveform 910: Simulate S12 waveform 1000: Simulated scattering parameter waveform 1100: Simulated scattering parameter waveform 1200: Quantum Bit Readout Circuit System 1202: Quantum bit resonator device 1204: Superconducting qubit 1206: Readout Resonator 1208: Passell filter 1210: Waveform Generator 1211: Digital-to-Analog Circuit System 1212: Low-pass filter circuit system 1213: First I / Q Mixer 1214: Local Oscillator Signal Generator 1220: Interference Isolator Circuit 1221: Interferometric Directional Quantum Confinement Amplifier 1222: Filter 1223: High Electron Mobility Transistor Amplifier 1224: Second I / Q Mixer 1225: Analog-to-Digital Converter Circuit System 1300: Quantum Computing System 1310: Quantum computing platform 1312: Quantum Computation Algorithm 1320: Control System 1322: Multi-channel arbitrary waveform generator 1324: Quantum Bit Readout Circuit System 1330: Quantum Processor 1332: Superconducting qubit array 1334: Network 1340: Dilution Refrigeration System 1400: Computing Environment 1401: Computer 1402: Wide Area Network 1403: End-user device 1404: Remote Server 1405: Public Cloud 1406: Private Cloud 1410: Processor Set 1411: Communication Mesh Architecture 1412: Volatile Memory 1413: Persistent Storage 1414: Peripheral Device Collection 1415: Network Module 1420: Processing circuit system 1421: Cache 1422: Operating System 1423: User Interface Device Set 1424: Storage 1425: IoT Sensor Set 1426: Block 1430: Remote Database 1440: Gate 1441: Cloud-based coordination process module 1442: Host Entity Machine Assembly 1443: Virtual Machine Set 1444:Container set B1: First Branch B2: Second Branch BW: Bandwidth C: Capacitor C1: Capacitor C1: Capacitor C2: Capacitor C2: Capacitor C3: Capacitor C3: Capacitor C4: Capacitor C5: Capacitor C6: Capacitor CC: Coupling capacitor Ci: Capacitor Cr: Capacitor Idler_1: First idler signal Idler_2: Second idler signal Idler_Out: Amplified idler signal J1: Josephson Interface J2: Josephson Interface J3: Josephson Interface Ji: Josephson Interface L: Inductor L1: Inductor L2: Inductor LC: Coupled Inductor Lr: Inductor P1: First Port P2: Second Port P3: Third Port P4: Fourth Port PIN: Input port POUT: Output port Pump: Pump port Pump_1: First pump signal Pump_2: Second pump signal RO: Readout signal S12: Transmission direction / simulated scattering parameter waveform S21: Simulated scattering parameter waveform Signal_1: First signal Signal_1A: Amplified signal Signal_1D: Signal Signal_2: Second signal Signal_2A: Amplified signal Signal_2D: Signal S_In: Input signal S_Out: Output signal T1: Terminal T2: Terminal Up / Dn_1: First frequency-converted signal Up / Dn_2: Second frequency-converted signal Up / Dn_Out: Frequency-converted output signal

Claims

1. An apparatus for quantum computing, comprising: a superconducting parametric interference circuit, comprising: a signal input port and a signal output port, the signal input port being configured to receive an input signal having a first frequency; a first parameter mixer circuit and a second parameter mixer circuit, which are coupled in parallel between the signal input port and the signal output port; wherein the first parameter mixer circuit is configured to convert the input signal into a first output signal having a second frequency, and the second parameter mixer circuit is configured to convert the input signal into a second output signal having the second frequency; and wherein the superconducting parametric interference circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency, and provides isolation between the signal input port and a signal present at the signal output port. The superconducting parameter interference circuit includes an interference isolator circuit configured to provide unity gain for the output signal and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

2. The apparatus of claim 1, wherein the superconducting parameter interferometry circuit includes an interferometric directional amplifier circuit configured to provide an amplified output signal having the second frequency at the signal output port, and to provide isolation by dissipating the signal present at the signal output port in a terminal of the superconducting parameter interferometry circuit.

3. The apparatus of claim 1, wherein the first parameter mixer circuit and the second parameter mixer circuit each include a parameter frequency converter circuit configured to perform one of the following: up-converting the first frequency to the second frequency; and down-converting the first frequency to the second frequency.

4. The apparatus of claim 3, wherein the parameter frequency converter circuit includes a Josephson traveling wave frequency converter circuit.

5. The apparatus of claim 1, wherein the first parameter mixer circuit and the second parameter mixer circuit each include a parameter amplifier circuit.

6. The apparatus of claim 5, wherein the parametric amplifier circuit includes a Josephson traveling wave parametric amplifier circuit.

7. The apparatus of claim 1, wherein the first parameter mixer circuit is driven by a first pump signal and the second parameter mixer circuit is driven by a second pump signal, wherein the first pump signal and the second pump signal have one of the following: the same frequency, the same phase and a phase offset.

8. An apparatus for quantum computing, comprising: a superconducting interference isolation circuit, including: a signal input port and a signal output port, the signal input port being configured to receive an input signal having a first frequency; a frequency conversion circuit including a first-parameter frequency converter circuit and a second-parameter frequency converter circuit cascaded in series; and a delay circuit coupled in parallel with the frequency conversion circuit; wherein the delay circuit is configured to delay the input signal to generate a first output signal having the first frequency and a first phase, and the frequency conversion circuit is configured to generate a second output signal having the first frequency and a second phase; and wherein the superconducting interference isolation circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the first frequency, and provides isolation between the signal input port and a signal present at the signal output port. The superconducting parameter interference circuit includes an interference isolator circuit configured to provide unity gain for the output signal and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

9. The apparatus of claim 8, wherein the delay circuit includes a passive delay line.

10. The apparatus of claim 8, wherein the delay circuit includes a passive filter circuit.

11. The apparatus of claim 8, wherein one of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency up-converter circuit, and the other of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency down-converter circuit.

12. The apparatus of claim 8, wherein the first parameter frequency converter circuit is driven by a first pump signal and the second parameter frequency converter circuit is driven by a second pump signal, wherein the first pump signal and the second pump signal have one of the following: the same frequency, the same phase and a phase offset.

13. An apparatus for quantum computing, comprising: a superconducting parametric interference circuit, comprising: a first hybrid coupler and a second hybrid coupler, the first hybrid coupler including a signal input port configured to receive an input signal having a first frequency, and the second hybrid coupler including a signal output port; and a first parameter mixer circuit and a second parameter mixer circuit coupled in parallel between the first hybrid coupler and the second hybrid coupler; wherein the first hybrid coupler is configured to divide the input signal into a first input signal having the first frequency and a second input signal having the first frequency; wherein the first parameter mixer circuit is configured to convert the first input signal into a first output signal having a second frequency, and the second parameter mixer circuit is configured to convert the second input signal into a second output signal having the second frequency; and wherein the second hybrid coupler is configured to combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency. The superconducting parameter interference circuit includes an interference isolator circuit configured to provide unity gain for the output signal and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

14. The apparatus of claim 13, wherein the first hybrid coupler and the second hybrid coupler each include a passive 90-degree hybrid coupler.

15. The apparatus of claim 13, wherein the interference isolator circuit provides isolation between the signal input port and the signal present at the signal output port by dissipating a signal present at the signal output port at a first terminal of one of the first hybrid couplers.

16. The apparatus of claim 13, wherein the superconducting parameter interference circuit includes an interference directional amplifier circuit configured to provide an amplified output signal at the signal output port and to provide isolation between the signal input port and the signal present at the signal output port by dissipating a signal present at the signal output port at a first terminal of one of the first hybrid couplers.

17. The apparatus of claim 13, wherein the first parameter mixer circuit and the second parameter mixer circuit each include a parameter frequency converter circuit configured to perform one of the following: up-converting the first frequency to the second frequency; and down-converting the first frequency to the second frequency.

18. The apparatus of claim 13, wherein the first parameter mixer circuit and the second parameter mixer circuit each include a parameter amplifier circuit.

19. The apparatus of claim 13, wherein the first parameter mixer circuit is driven by a first pump signal and the second parameter mixer circuit is driven by a second pump signal, wherein the first pump signal and the second pump signal have one of the following: the same frequency, the same phase and a phase offset.

20. An apparatus for quantum computing, comprising: a superconducting interference isolation circuit including: a first hybrid coupler and a second hybrid coupler, the first hybrid coupler including a signal input port configured to receive an input signal having a first frequency, and the second hybrid coupler including a signal output port; a frequency conversion circuit including a first-parameter frequency converter circuit and a second-parameter frequency converter circuit cascaded in series; and a delay circuit coupled in parallel with the frequency conversion circuit between the first hybrid coupler and the second hybrid coupler; wherein the delay circuit is configured to group delay the input signal to generate a first output signal having the first frequency and a first phase, and the frequency conversion circuit is configured to generate a second output signal having the first frequency and a second phase; and wherein the second hybrid coupler is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the first frequency. The superconducting parameter interference circuit includes an interference isolator circuit configured to provide unity gain for the output signal and to provide isolation by dissipating the signal present at the signal output port in one of the terminals of the superconducting parameter interference circuit.

21. The apparatus of claim 20, wherein the delay circuit comprises one of: a passive delay line and a passive filter circuit.

22. The apparatus of claim 20, wherein: One of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency up-converter circuit, and the other of the first parameter frequency converter circuit and the second parameter frequency converter circuit includes a parameter frequency down-converter circuit; the first parameter frequency converter circuit is driven by a first pump signal, and the second parameter frequency converter circuit is driven by a second pump signal; and the first pump signal and the second pump signal have one of the following: the same frequency and the following: the same phase and a phase offset.

23. A quantum computing system comprising: a quantum processor including qubits; a readout signal path configured to transmit signals read from one or more of the qubits of the quantum processor, the readout signal path including a superconducting parameter interference circuit, the superconducting parameter interference circuit including: a signal input port and a signal output port, the signal input port being configured to receive an input signal having a first frequency, the input signal including a readout signal from at least one qubit; a first parameter mixer circuit and a second parameter mixer circuit coupled in parallel between the signal input port and the signal output port; The first parameter mixing circuit is configured to convert the input signal into a first output signal having a second frequency, and the second parameter mixing circuit is configured to convert the input signal into a second output signal having the second frequency; the superconducting parameter interferometry circuit is configured to constructively combine the first output signal and the second output signal at the signal output port to generate an output signal having the second frequency, and to provide isolation between the signal input port and a signal present at the signal output port; the superconducting parameter interferometry circuit includes an interferometric isolator circuit configured to provide unity gain of the output signal, and to provide isolation by dissipating the signal present at the signal output port in a terminal of the superconducting parameter interferometry circuit.

24. The system of claim 23, wherein the superconducting parameter interference circuit includes an interference-oriented quantum confinement amplifier circuit configured to provide an amplified output signal at the signal output port.

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