Display device and manufacturing method thereof

Abstract

The display device of one embodiment includes a first display element, a second display element, a partition, a first sealing layer, and a second sealing layer. The first display element includes a first lower electrode, a first upper electrode, and a first organic layer. The second display element includes a second lower electrode, a second upper electrode, and a second organic layer. The partition is disposed between the first and second display elements. The first sealing layer covers the first display element. The second sealing layer covers the second display element. The first sealing layer has a first end portion located above the partition. The second sealing layer has a second end portion located above the partition. The first and second ends overlap in the thickness direction of the first and second sealing layers.

Description

Technical Field

[0001] This invention relates to a display device and a method for manufacturing the same. Prior Technology

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. For these display devices, a technology is needed to improve yield or increase reliability. Summary of the Invention

[0003] Generally, the display device of the embodiment includes a first display element, a second display element, a partition, a first sealing layer, and a second sealing layer. The first display element includes a first lower electrode, a first upper electrode opposite to the first lower electrode, and a first organic layer located between the first lower electrode and the first upper electrode, emitting light upon application of voltage. The second display element includes a second lower electrode, a second upper electrode opposite to the second lower electrode, and a second organic layer located between the second lower electrode and the second upper electrode, emitting light upon application of voltage. The partition is disposed between the first display element and the second display element. The first sealing layer covers the first display element. The second sealing layer covers the second display element. The first sealing layer has a first end located above the partition. The second sealing layer has a second end located above the partition. In the thickness direction of the first sealing layer and the second sealing layer, the first end and the second end overlap.

[0004] Furthermore, generally speaking, the manufacturing method of the display device in the embodiment includes the following steps: forming a first lower electrode and a second lower electrode in the display area; forming a partition between the first lower electrode and the second lower electrode; forming a first laminated film in the display area comprising a first organic layer that emits light according to the application of voltage and a first upper electrode covering the first organic layer; forming a first insulating layer in the display area covering the first laminated film; forming a first sealing layer by first etching the first insulating layer, having a first end located above the partition and covering a first display element composed of the first lower electrode, the first organic layer and the first upper electrode; and forming a first sealing layer by second etching the first laminated film. The portion of the first stacked film exposed from the first sealing layer is removed; after the second etching, a second stacked film comprising a second organic layer that emits light according to the application of voltage and a second upper electrode covering the second organic layer is formed in the display area; a second insulating layer covering the second stacked film is formed in the display area; by the third etching of the second insulating layer, a second sealing layer is formed having a second end overlapping the first end in the thickness direction of the first sealing layer and covering a second display element composed of the second lower electrode, the second organic layer and the second upper electrode; by the fourth etching of the second stacked film, the portion of the second stacked film exposed from the second sealing layer is removed.

[0005] Depending on the implementation, the yield or reliability of the display device can be improved. Simple Explanation of the Diagram

[0006] Figure 1 is a diagram showing an example of the configuration of a display device in one embodiment. Figure 2 is a schematic top view showing an example of the layout of subpixels in one implementation. Figure 3 is a schematic cross-sectional view of the display device along line III-III in Figure 2. Figure 4 is a schematic top view of a partition and sealing layer in one embodiment. Figure 5 is a schematic cross-sectional view of the display device along line VV in Figure 4. Figure 6 is a schematic cross-sectional view of the display device along line VI-VI in Figure 4. Figure 7 is a schematic cross-sectional view of the display device along line VII-VII in Figure 4. Figure 8A is a schematic cross-sectional view showing the manufacturing process of a display device in one embodiment. Figure 8B is a schematic cross-sectional view of the process following Figure 8A. Figure 8C is a schematic cross-sectional view of the process following Figure 8B. Figure 8D is a schematic cross-sectional view of the process following Figure 8C. Figure 8E is a schematic cross-sectional view of the process following Figure 8D. Figure 8F is a schematic cross-sectional view of the process following Figure 8E. Figure 8G is a schematic cross-sectional view of the process following Figure 8F. Figure 8H is a schematic cross-sectional view of the process following Figure 8G. Figure 9A is a schematic cross-sectional view showing the manufacturing method of the display device of the comparative example. Figure 9B is a schematic cross-sectional view of the process following Figure 9A. Figure 9C is a schematic cross-sectional view of the process following Figure 9B. Implementation

[0007] The diagram is shown on one side, and several implementation forms are explained on the other.

[0008] The disclosure is merely one example. Any appropriate modifications that can be readily conceived by those skilled in the art to ensure the essence of the invention are naturally within the scope of this invention. Furthermore, while the drawings make the explanation clearer, and although there are instances where the width, thickness, shape, etc., of each part are shown in a patterned manner compared to the actual form, this is merely one example and does not limit the interpretation of the invention. Also, in this specification and the accompanying drawings, for the attached figures, the same reference numerals are used for constituent elements that perform the same or similar functions as described above, and repeated detailed descriptions are appropriately omitted.

[0009] Furthermore, in the diagram, for ease of understanding, the mutually orthogonal X-axis, Y-axis, and Z-axis are shown. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane that includes the X-direction and the Y-direction. Also, the view of various elements parallel to the Z-direction is called a top view.

[0010] The display devices in each embodiment are organic electroluminescent display devices with organic light-emitting diodes (OLEDs) as display elements, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle machines, tablet terminals, smartphones, portable telephone terminals, and wearable terminals.

[0011] Figure 1 is a diagram showing an example of the configuration of the display device DSP of this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the substrate 10 and the display area DA are rectangular when viewed from above. However, the shape of the substrate 10 and the display area DA when viewed from above is not limited to a rectangle, and may also be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA has a plurality of pixels PX arranged in a matrix in the X and Y directions. Pixel PX includes a plurality of subpixels SP displaying different colors. In this embodiment, it is assumed that pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, pixel PX may also include subpixels SP of other colors such as white, either together with or in place of subpixels SP1, SP2, and SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements made of thin-film transistors.

[0015] In the display area DA, there are a plurality of scan lines G supplying scan signals to the pixel circuit 1 of each sub-pixel SP, a plurality of signal lines S supplying image signals to the pixel circuit 1 of each sub-pixel SP, and a plurality of power lines PL. In the example of Figure 1, the scan lines G extend in the X direction and the signal lines S extend in the Y direction, but this is not limited to this example.

[0016] The gate electrode of pixel switch 2 is connected to scan line G. One of the source electrode and drain electrode of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of driving transistor 3 and capacitor 4. In driving transistor 3, one of the source electrode and drain electrode is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0017] Furthermore, the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] Figure 2 is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Figure 2, subpixels SP2 and SP3 are arranged in the X direction along with subpixel SP1. Furthermore, subpixels SP2 and SP3 are arranged in the Y direction.

[0019] When subpixels SP1, SP2, and SP3 are arranged in this layout, rows of subpixels SP2 and SP3 arranged alternately in the Y direction and rows of multiple subpixels SP1 arranged repeatedly in the Y direction are formed in the display area DA. These rows are arranged alternately in the X direction. Furthermore, the layout of subpixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0020] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel apertures AP1, AP2, and AP3 in subpixels SP1, SP2, and SP3, respectively. In the example of Figure 2, the area of ​​pixel aperture AP1 is larger than the area of ​​pixel aperture AP2, and the area of ​​pixel aperture AP2 is larger than the area of ​​pixel aperture AP3. That is, among subpixels SP1, SP2, and SP3, subpixel SP1 has the largest aperture ratio, and subpixel SP3 has the smallest aperture ratio.

[0021] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0022] The portion of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel opening AP1 constitutes the display element DE1 (first display element) of the sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel opening AP2 constitutes the display element DE2 (second display element) of the sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel opening AP3 constitutes the display element DE3 (third display element) of the sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include the capping layer described later. Rib layer 5 surrounds each of the display elements DE1, DE2, and DE3.

[0023] The relationship between the areas of display elements DE1, DE2, and DE3 is the same as the relationship between the areas of pixel apertures AP1, AP2, and AP3. That is, display element DE1 has the largest area, and display element DE3 has the smallest area. However, the relationship between the areas of display elements DE1, DE2, and DE3 and the relationship between the areas of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0024] A conductive partition 6 is disposed on the rib layer 5. The partition 6 overlaps the rib layer 5 and has the same planar shape as the rib layer 5. That is, the partition 6 has openings in the sub-pixels SP1, SP2, and SP3 respectively. From another viewpoint, the rib layer 5 and the partition 6 appear as a grid when viewed from above, surrounding each of the display elements DE1, DE2, and DE3. The partition 6 serves as a wiring to supply a common voltage to the upper electrodes UE1, UE2, and UE3.

[0025] Figure 3 is a schematic cross-sectional view of the display device DSP along line III-III in Figure 2. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits or wirings such as pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by the circuit layer 11.

[0026] Lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. Rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of FIG3, the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0027] The partition 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. Consequently, the two ends of the upper portion 62 protrude beyond the sides of the lower portion 61. This type of partition 6 can also be described as suspended.

[0028] In the example of Figure 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Also, in the example of Figure 3, the two ends of the bottom layer 63 protrude from the side of the shaft layer 64.

[0029] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and faces lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and faces lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and faces lower electrode LE3. Upper electrodes UE1, UE2, and UE3 contact the lower part 61 of partition 6.

[0030] Display element DE1 includes a capping layer CP1 disposed on the upper electrode UE1. Display element DE2 includes a capping layer CP2 disposed on the upper electrode UE2. Display element DE3 includes a capping layer CP3 disposed on the upper electrode UE3. The capping layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the light extraction efficiency emitted by the organic layers OR1, OR2, and OR3.

[0031] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as stacked film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as stacked film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as stacked film FL3.

[0032] Sealing layers SE11, SE12, and SE13 are respectively disposed on sub-pixels SP1, SP2, and SP3. Sealing layer SE11 continuously covers display element DE1 and the surrounding partition 6. Sealing layer SE12 continuously covers display element DE2 and the surrounding partition 6. Sealing layer SE13 continuously covers display element DE3 and the surrounding partition 6.

[0033] Resin layer RS1 covers sealing layers SE11, SE12, and SE13. Resin layer RS1 is covered by sealing layer SE2. Resin layer RS2 covers sealing layer SE2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the surrounding area SA.

[0034] Alternatively, a cover component such as a polarizing plate, touch panel, protective film, or glass cover can be further disposed above the resin layer RS2. Such a cover component can also be attached to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0035] An organic insulating layer 12 is formed from an organic insulating material such as polyimide. Rib layers 5 and sealing layers SE11, SE12, SE13, and SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, rib layer 5 is formed from silicon oxynitride, and sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride. Resin layers RS1 and RS2 are formed from resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0036] The lower electrodes LE1, LE2, and LE3, for example, have a reflective layer formed of silver and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0037] The upper electrodes UE1, UE2, and UE3 are formed from metallic materials such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0038] Organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including light-emitting layers. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the Z direction. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called cascaded structure containing a plurality of light-emitting layers.

[0039] The capping layers CP1, CP2, and CP3, for example, have a laminated structure with a plurality of overlapping transparent layers. These transparent layers may comprise layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. Alternatively, at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0040] The partition 6 has a bottom layer 63 and a axial layer 64 formed of metallic materials. For example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. Alternatively, the axial layer 64 can be formed of an insulating material.

[0041] For example, the upper part 62 of the partition 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. For example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys can be used as the metallic material forming the lower layer. For example, ITO or IZO can be used as the conductive oxide forming the upper layer. Alternatively, the upper part 62 may also have a single-layer structure of a metallic material. Furthermore, the upper part 62 may also include a layer formed of an insulating material.

[0042] A common voltage is supplied to the partition 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 of the contact lower part 61. The pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively supply the lower electrodes LE1, LE2, and LE3 with pixel voltages corresponding to the image signals of the signal line S.

[0043] Organic layers OR1, OR2, and OR3 emit light according to the applied voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the emitting layer of organic layer OR3 emits light in the red wavelength range.

[0044] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Furthermore, the display device DSP can also include a layer containing quantum dots, which are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0045] Figure 4 is a schematic top view of the partition 6 and the sealing layers SE11, SE12, and SE13. In this example, the sealing layer SE11 is continuously formed over a plurality of sub-pixels SP1 arranged in the Y direction. On the other hand, the sealing layer SE12 is formed one sub-pixel SP2 at a time. Similarly, the sealing layer SE13 is formed one sub-pixel SP3 at a time.

[0046] Each side of the outer shape of sealing layers SE11, SE12, and SE13 overlaps with the partition plate 6. In the following description, the portion of sealing layer SE11 that lies above the partition plate 6 along its outer shape is referred to as end E1 (first end). The portion of sealing layer SE12 that lies above the partition plate 6 along its outer shape is referred to as end E2 (second end). The portion of sealing layer SE13 that lies above the partition plate 6 along its outer shape is referred to as end E3 (third end).

[0047] In the example of Figure 4, the ends E1 and E2 of adjacent sealing layers SE11 and SE12 overlap in the Z direction. Furthermore, the ends E1 and E3 of adjacent sealing layers SE11 and SE13 overlap in the Z direction. Moreover, the ends E2 and E3 of adjacent sealing layers SE12 and SE13 overlap in the Z direction. Here, the Z direction corresponds to the thickness direction of sealing layers SE11, SE12, and SE13.

[0048] Furthermore, the relationship between ends E1, E2, and E3 is not limited to the example in Figure 4. For instance, a portion of end E1 may not overlap with ends E2 or E3. Similarly, a portion of end E2 may not overlap with ends E1 or E3. Moreover, a portion of end E3 may not overlap with ends E1 or E2.

[0049] Figure 5 is a schematic cross-sectional view of the display device DSP along line VV in Figure 4. Figure 6 is a schematic cross-sectional view of the display device DSP along line VI-VI in Figure 4. Figure 7 is a schematic cross-sectional view of the display device DSP along line VII-VII in Figure 4. In these figures, substrate 10, circuit layer 11, resin layer RS1, sealing layer SE2, and resin layer RS2 are omitted.

[0050] As shown in Figure 5, the end E1 of the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is located between the end E2 of the partition 6 and the sealing layer SE12 in the Z direction. Furthermore, a gap GP1 (first gap) is formed between the upper part 62 of the partition 6 and the end E1 in the Z direction. The gap GP1 is, for example, a void. Alternatively, a laminated film FL1 may be disposed in at least a portion of the region corresponding to the gap GP1 shown in the figure.

[0051] In the example of Figure 5, a laminated film FL2 is disposed between the sealing layer SE12 and the upper part 62. Furthermore, in the Z direction, a gap GP2 (second gap) is formed between end E1 and end E2. For example, as shown in Figure 3, at least a portion of the gap GP2 is filled by the resin layer RS1. Alternatively, the laminated film FL2 can also be disposed in at least a portion of the region corresponding to the gap GP2 shown in the figure.

[0052] In the example of Figure 5, portions of ends E1 and E2 are in contact with each other above the partition 6. In another example, the laminated film FL2 may be positioned between the ends E1 and E2 depicted as being in contact in the figure.

[0053] As shown in Figure 6, the end E1 of the partition 6 located between sub-pixels SP1 and SP3 is situated in the Z direction between the partition 6 and the end E3 of the sealing layer SE13. In the cross-section of Figure 6, a gap GP1 is also formed between the upper part 62 and the end E1.

[0054] In the example of Figure 6, a laminated film FL3 is disposed between the sealing layer SE13 and the upper portion 62. Furthermore, in the Z direction, a gap GP3 (third gap) is formed between end portion E1 and end portion E3. For example, as shown in Figure 3, at least a portion of the gap GP3 is filled by the resin layer RS1. Alternatively, the laminated film FL3 may be disposed in at least a portion of the region corresponding to the gap GP3 shown in the figure.

[0055] In the example of Figure 6, portions of ends E1 and E3 are in contact with each other above the partition 6. In another example, the laminated film FL3 may be positioned between the ends E1 and E3 depicted as being in contact in the figure.

[0056] As shown in Figure 7, the end portion E2 of the partition 6 located between sub-pixels SP2 and SP3 is situated between partition 6 and end portion E3 in the Z direction. Furthermore, a gap GP4 (fourth gap) is formed between the upper portion 62 and end portion E2 in the Z direction. The gap GP4 is, for example, a void. Alternatively, a laminated film FL2 may be disposed in at least a portion of the region corresponding to the gap GP4 shown in the figure.

[0057] In the example of Figure 7, a laminated film FL3 is also disposed between the sealing layer SE13 and the upper part 62. Furthermore, in the Z direction, a gap GP5 (the fifth gap) is formed between end E2 and end E3. Similar to gaps GP2 and GP3 shown in Figure 3, at least a portion of the gap GP5 is filled by the resin layer RS1. Alternatively, the laminated film FL3 can also be disposed in at least a portion of the area corresponding to the gap GP5 shown in the figure.

[0058] In the example of Figure 7, portions of ends E2 and E3 are in contact with each other above the partition 6. In another example, the laminated film FL3 may be positioned between the ends E2 and E3 depicted as being in contact in the figure.

[0059] As shown in Figures 5 to 7, sealing layer SE11 has a thickness T1, sealing layer SE12 has a thickness T2, and sealing layer SE13 has a thickness T3. Furthermore, partition 6 has a height H. Additionally, height H is equivalent to the distance from the upper surface of rib 5 to the upper surface of upper part 62.

[0060] For example, the thicknesses T1, T2, and T3 are equal (T1=T2=T3). Also, the thicknesses T1, T2, and T3 are greater than or equal to the height H (T1, T2, and T3 ≥ H). Thus, when the sealing layers SE11, SE12, and SE13 are relatively thick, the display elements DE1, DE2, and DE3 and their surrounding partition 6 can be well covered by the sealing layers SE11, SE12, and SE13.

[0061] Furthermore, the relationship between thicknesses T1, T2, T3 and height H is not limited to the example shown here. For instance, at least two of the thicknesses T1, T2, and T3 may be different. Also, at least one of the thicknesses T1, T2, and T3 may not reach the height H.

[0062] The overlap widths W1 of ends E1 and E2 as shown in Figure 5, W2 of ends E1 and E3 as shown in Figure 6, and W3 of ends E2 and E3 as shown in Figure 7 are, for example, 1 μm or more, and more specifically, 2 μm or more. These widths W1, W2, and W3 are all less than the width of partition 6 (the width of the upper part 62). Widths W1, W2, and W3 may be equal or different.

[0063] Next, an example of a manufacturing method for a display device DSP will be described. Figures 8A to 8H are schematic cross-sectional views of the manufacturing process of a display device DSP. In Figures 8A to 8H, focus is placed on sub-pixels SP1, SP2, and SP3, and components below the organic insulating layer 12 are omitted.

[0064] When forming the display device DSP, a circuit layer 11 and an organic insulating layer 12 are first formed on the substrate 10. Next, as shown in FIG8A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0065] Next, as shown in Figure 8B, rib layer 5 and partition 6 are formed. The pixel openings AP1, AP2, and AP3 of rib layer 5 can be set after the partition 6 is formed or before the partition 6 is formed.

[0066] After forming the rib layer 5 and the partition 6, the process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that display element DE1 is formed first, followed by display element DE2, and finally display element DE3. However, the formation order of display elements DE1, DE2, and DE3 is not limited to this example.

[0067] When forming the display element DE1, as shown in FIG8C, a multilayer film FL1 and an insulating layer IL1 (first insulating layer) covering the multilayer film FL1 are first formed. As shown in FIG3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The insulating layer IL1 is a layer used to form the sealing layer SE11 and is formed of an inorganic insulating material. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed by vapor deposition. Alternatively, the insulating layer IL1 can be formed by CVD (Chemical Vapor Deposition).

[0068] For example, the laminated film FL1 and the insulating layer IL1 are formed on the display area DA and the surrounding area SA. The laminated film FL1 is divided into multiple parts by suspended partitions 6. The insulating layer IL1 continuously covers each of the divided parts of the laminated film FL1 and the partitions 6.

[0069] Next, the laminated film FL1 and the insulating layer IL1 are patterned. In this patterning, as shown in FIG8C, a resist R1 is disposed on the insulating layer IL1. The resist R1 covers a portion of the sub-pixel SP1 and the surrounding partition 6.

[0070] Subsequently, a first etching of the insulating layer IL1 and a second etching of the laminated film FL1 are performed sequentially. In the first etching, the portion of the insulating layer IL1 exposed from the resist R1 is removed. Thereby, as shown in FIG8D, a sealing layer SE11 having an end E1 located above the partition 6 is formed. The first etching is, for example, a dry etching.

[0071] In the second etching, the portion of the stacked film FL1 exposed from the sealing layer SE11 is removed. For example, the second etching includes wet etching or dry etching of the capping layer CP1, the upper electrode UE1, and the organic layer OR1 in sequence.

[0072] In the second etching, the multilayer film FL1 located on the partition 6 can also be removed. This forms the aforementioned gap GP1 between the end E1 and the partition 6. On the other hand, since the multilayer film FL1, which contacts the lower electrode LE1 through the pixel opening AP1, is completely covered by the sealing layer SE11, it will not be eroded by the second etching. Thus, the multilayer film FL1 remaining on the sub-pixel SP1 and the lower electrode LE1 constitute the display element DE1.

[0073] After the first and second etchings, the resist R1 is removed. Then, as shown in Figure 8E, a multilayer film FL2 and an insulating layer IL2 (the second insulating layer) covering the multilayer film FL2 are formed. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2. The insulating layer IL2 is used to form the sealing layer SE12 and is formed from an inorganic insulating material. The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed by vapor deposition. Alternatively, the insulating layer IL2 can be formed by CVD.

[0074] For example, the laminated film FL2 and the insulating layer IL2 are formed integrally in the display area DA and the peripheral area SA. The laminated film FL2 is divided into a plurality of parts by suspended partitions 6. The laminated film FL2 may also be divided at the end E1, but is not limited to this example. The insulating layer IL2 continuously covers each of the divided parts of the laminated film FL2 and the partitions 6. For example, at least a portion of the gap GP1 remains as a void after the formation of the laminated film FL2 and the insulating layer IL2.

[0075] Next, the laminated film FL2 and the insulating layer IL2 are patterned. In this patterning, as shown in FIG8E, a resist R2 is disposed on the insulating layer IL2. The resist R2 covers a portion of the sub-pixel SP2 and the surrounding partition 6. A portion of the resist R2 is located above the end point E1.

[0076] Subsequently, a third etching of the insulating layer IL2 and a fourth etching of the laminated film FL2 are performed sequentially. In the third etching, the portion of the insulating layer IL2 exposed from the resist R2 is removed. Thus, as shown in FIG8F, a sealing layer SE12 having an end E2 located above the partition 6 is formed. The third etching is, for example, a dry etching.

[0077] In the fourth etching, the portion of the stacked film FL2 exposed from the sealing layer SE12 is removed. For example, the fourth etching includes wet etching or dry etching of the capping layer CP2, the upper electrode UE2, and the organic layer OR2 in sequence.

[0078] In the fourth etching, the deposited film FL2 located above end E1 can also be removed. This forms the aforementioned gap GP2 between end E1 and end E2. Although not shown in the cross-section of FIG8F, the gap GP4 shown in FIG7 is also formed by the fourth etching.

[0079] Because the stacked film FL2, which contacts the lower electrode LE2 through the pixel opening AP2, is completely covered by the sealing layer SE12, it will not be eroded by the fourth etching. Thus, the stacked film FL2 remaining in the sub-pixel SP2 and the lower electrode LE2 together form the display element DE2. After the third and fourth etchings, the resist R2 is removed.

[0080] After the third and fourth etching steps, the resist R2 is removed. Then, as shown in Figure 8G, a multilayer film FL3 and an insulating layer IL3 (the third insulating layer) covering the multilayer film FL3 are formed. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3. The insulating layer IL3 is used to form the sealing layer SE13 and is formed from an inorganic insulating material. The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed by vapor deposition. Alternatively, the insulating layer IL3 can be formed by CVD.

[0081] For example, the laminated film FL3 and the insulating layer IL3 are formed integrally on the display area DA and the peripheral area SA. The laminated film FL3 is divided into multiple parts by suspended partitions 6. The laminated film FL3 may also be divided at the ends E1 and E2, but is not limited to this example. The insulating layer IL3 continuously covers each of the divided parts of the laminated film FL3 and the partitions 6.

[0082] Next, the laminated film FL3 and the insulating layer IL3 are patterned. In this patterning, as shown in FIG8G, resist R3 is disposed on the insulating layer IL3. Resist R3 covers a portion of the sub-pixel SP3 and the surrounding partition 6. A portion of resist R3 is located above the end point E1. Although not shown in the cross-section of FIG8G, a portion of resist R3 is located above the end point E2 at the boundary between sub-pixels SP2 and SP3.

[0083] Subsequently, a fifth etching of the insulating layer IL3 and a sixth etching of the laminated film FL3 are performed sequentially. In the fifth etching, the portion of the insulating layer IL3 exposed from the resist R3 is removed. Thus, as shown in FIG8H, a sealing layer SE13 having an end E3 located above the partition 6 is formed. The fifth etching is, for example, a dry etching.

[0084] In the sixth etching, the portion of the stacked film FL3 exposed from the sealing layer SE13 is removed. For example, the sixth etching includes wet or dry etching of the capping layer CP3, the upper electrode UE3, and the organic layer OR3 in sequence.

[0085] During the sixth etching, the deposited film FL3 located below end E3 may also be etched. This forms the aforementioned gap GP3 between end E1 and end E3. Although not shown in the cross-section of Figure 8H, the gap GP5 shown in Figure 7 is also formed by the fourth etching.

[0086] Because the stacked film FL3, which contacts the lower electrode LE3 through the pixel opening AP3, is completely covered by the sealing layer SE13, it will not be eroded by the 6th etching. Thus, the stacked film FL3 remaining in the sub-pixel SP3 and the lower electrode LE3 together form the display element DE3. After the 5th and 6th etchings, the resist R3 is removed.

[0087] After forming display elements DE1, DE2, and DE3, resin layer RS1, sealing layer SE2, and resin layer RS2 as shown in FIG3 are formed sequentially. As described above, resin layer RS1 can also fill at least a portion of the gaps GP2, GP3, and GP5.

[0088] Based on the above embodiment, the yield and reliability of the display device's DSP can be improved. This effect will be explained below.

[0089] Figures 9A to 9C are schematic cross-sectional views showing the manufacturing method of the display device in a comparative example with this embodiment. The manufacturing process of the display device DSP is the same as that shown in Figures 8A to 8H. Figure 9A shows the state immediately after the first and second etchings, Figure 9B shows the state immediately after the third and fourth etchings, and Figure 9C shows the state immediately after the fifth and sixth etchings.

[0090] The cross-section of Figure 9A is roughly the same as that of Figure 8D. However, in Figure 9A, the widths of the resist R1 and the sealing layer SE11 are smaller than those in Figure 8D. Therefore, the width of the end E1 located above the partition 6 is also smaller than that in Figure 8D.

[0091] In this comparative example, when forming the display element DE2 and the sealing layer SE12, the resist R2 is disposed in a manner that does not overlap with the end E1. In this case, the insulating layer IL2 covering the end E1 is completely removed in the third etching. Therefore, the end E1 may be etched in the third etching. When the end E1 is etched, as shown in FIG9B, the end E1 recedes toward the pixel opening AP1.

[0092] Furthermore, in this comparative example, when forming the display element DE3 and the sealing layer SE13, the resist R3 is disposed in a manner that does not overlap with the ends E1 and E2. In this case, the insulating layer IL3 covering the ends E1 and E2 is completely removed in the fifth etching. Therefore, in the fifth etching, the ends E1 and E2 may be etched. When end E1 is etched, as shown in FIG9C, end E1 recedes further toward the pixel opening AP1. Also, when end E2 is etched, end E2 recedes toward the pixel opening AP2.

[0093] In Figure 9C, end E1 separates from partition 6, exposing the multilayer film FL1, which constitutes display element DE1, from the sealing layer SE11. If this sealing failure occurs, moisture can seep into the multilayer film FL1, potentially corroding it. As a result, display defects in display element DE1 may occur. If the sealing layer SE12 is severely eroded during the fifth etching, display element DE2 will also experience the same problem.

[0094] On the other hand, in this embodiment, a portion of the end E1 of the sealing layer SE11 overlaps with the end E2 of the sealing layer SE12. In this case, during the third or fifth etching, the portion of the end E1 is protected by the sealing layer SE12 (insulating layer IL2).

[0095] Furthermore, in this embodiment, another portion of the end E1 of the sealing layer SE11 overlaps with the end E3 of the sealing layer SE13. In this case, during the fifth etching, the other portion of the end E1 is protected by the sealing layer SE13 (insulating layer IL3).

[0096] Furthermore, in this embodiment, a portion of the end E2 of the sealing layer SE12 overlaps with the end E3 of the sealing layer SE13. In this case, during the fifth etching, the portion of the end E2 is protected by the sealing layer SE13 (insulating layer IL3).

[0097] Because of these circumstances, according to this embodiment, the retraction of ends E1 and E2 shown in the comparative example is suppressed. As a result, the yield of the display device DSP can be improved, and the reliability of the display device DSP can be enhanced.

[0098] Based on the display device and manufacturing method described above as embodiments of the present invention, all display devices and manufacturing methods that can be appropriately designed, modified and implemented by those skilled in the art, as long as they contain the spirit of the present invention, also fall within the scope of the present invention.

[0099] Within the scope of the present invention, various variations will be conceived by those skilled in the art, and such variations are also understood to be within the scope of the present invention. For example, those skilled in the art may appropriately add or reduce constituent elements, modify the design, add or omit processes, or change conditions in relation to the above embodiments, as long as they possess the spirit of the present invention, they are also included within the scope of the present invention.

[0100] Furthermore, it should be understood that other effects and functions obtained by means of the embodiments described above, as understood from the description in this specification, or as can be reasonably conceived by those skilled in the art, can of course be obtained by this invention. [Cross-reference to related applications]

[0101] This application claims priority based on Japanese Patent Application No. 2024-043751, filed on March 19, 2024, and incorporates all the contents described in that Japanese patent application.

[0102] 1: Pixel circuit 2: Pixel switch 3: Driving transistor 4: Capacitor 5: Rib layer 6: partition 10:Substrate 11: Circuit Layer 12: Organic insulating layer 61: Lower part 62: Upper part 63: Bottom layer 64: Axis Layer AP1, AP2, AP3: Pixel apertures CP1, CP2, CP3: Cap layer DA: Display area DE, DE1, DE2, DE3: Display elements DSP: Display device E1, E2, E3: Ends FL1, FL2, FL3: Stacked films G: Scan line GP1, GP2, GP3, GP4, GP5: Gap H: Height IL1, IL2, IL3: Insulating layers LE1, LE2, LE3: Lower electrodes OR1, OR2, OR3: Organic layer PL: Power cord PX: pixel R1, R2, R3: Corrosion resist RS1, RS2: Resin layer S: Signal line SA: Surrounding Area SE2, SE11, SE12, SE13: Sealing layer SP: Pixels SP1, SP2, SP3: Subpixels T1, T2, T3: Thickness UE1, UE2, UE3: Upper electrode W1, W2, W3: Width

Claims

1. A display device comprising: a first display element including a first lower electrode, a first upper electrode opposite to the first lower electrode, and a first organic layer located between the first lower electrode and the first upper electrode and emitting light upon application of a voltage; a second display element including a second lower electrode, a second upper electrode opposite to the second lower electrode, and a second organic layer located between the second lower electrode and the second upper electrode and emitting light upon application of a voltage; a partition disposed between the first display element and the second display element; a first sealing layer covering the first display element; and a second sealing layer covering the second display element; wherein the first sealing layer has a first end portion located above the partition; and the second sealing layer has a second end portion located above the partition; wherein the first end portion and the second end portion overlap in the thickness direction of the first sealing layer and the second sealing layer.

2. The display device of claim 1, wherein the first end is located between the partition and the second end in the thickness direction; and a first gap is formed between the partition and the first end in the thickness direction.

3. The display device as requested in item 2, wherein the first gap is a void.

4. The display device of claim 2, wherein a second gap is formed between the first end and the second end in the thickness direction.

5. The display device of claim 4 further comprises: a resin layer covering the first sealing layer and the second sealing layer; and the resin layer filling at least a portion of the second gap.

6. The display device of any one of claims 1 to 5, wherein the first sealing layer and the second sealing layer are in contact above the partition.

7. The display device according to any one of claims 1 to 5, wherein the area of ​​the first display element is greater than the area of ​​the second display element.

8. The display device according to any one of claims 1 to 5, wherein the partition comprises a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion.

9. The display device according to any one of claims 1 to 5, wherein the first sealing layer and the second sealing layer are formed of inorganic insulating material.

10. The display device according to any one of claims 1 to 5, wherein the thickness of the first sealing layer and the second sealing layer is greater than the height of the partition.

11. A method for manufacturing a display device, comprising the steps of: forming a first lower electrode and a second lower electrode in a display area; forming a partition between the first lower electrode and the second lower electrode; forming a first laminated film in the display area comprising a first organic layer that emits light upon application of voltage and a first upper electrode covering the first organic layer; forming a first insulating layer in the display area covering the first laminated film; forming a first sealing layer having a first end located above the partition and covering a first display element composed of the first lower electrode, the first organic layer and the first upper electrode by a first etching of the first insulating layer; removing a portion of the first laminated film exposed from the first sealing layer by a second etching of the first laminated film; and forming a second laminated film in the display area comprising a second organic layer that emits light upon application of voltage and a second upper electrode covering the second organic layer after the second etching. A second insulating layer covering the second stacked film is formed in the display area; a second sealing layer is formed by a third etching of the second insulating layer, having a second end overlapping the first end in the thickness direction of the first sealing layer, and covering a second display element composed of the second lower electrode, the second organic layer, and the second upper electrode; and a portion of the second stacked film exposed from the second sealing layer is removed by a fourth etching of the second stacked film.

12. A method for manufacturing a display device as claimed in claim 11, wherein in the second etching, the portion of the first laminated film located above the partition is removed, thereby forming a first gap between the partition and the first end in the thickness direction.

13. The method of manufacturing the display device as claimed in claim 12, wherein the first gap remains as a void after the second sealing layer is formed.

14. A method for manufacturing a display device as claimed in claim 12, wherein in the fourth etching, the portion of the second laminated film located above the first end is removed, thereby forming a second gap between the first end and the second end in the thickness direction.

15. The method of manufacturing the display device according to claim 14 further includes the steps of: forming a resin layer covering the first sealing layer and the second sealing layer; and filling at least a portion of the second gap with the resin layer.

16. A method of manufacturing a display device according to any one of claims 11 to 15, wherein the first sealing layer and the second sealing layer are in contact above the partition.

17. A method of manufacturing a display device according to any one of claims 11 to 15, wherein the area of ​​the first display element is larger than the area of ​​the second display element.

18. A method of manufacturing a display device according to any one of claims 11 to 15, wherein the partition comprises a conductive lower portion and an upper portion having an end portion protruding from the side of the lower portion.

19. A method for manufacturing a display device according to any one of claims 11 to 15, wherein the first sealing layer and the second sealing layer are formed of inorganic insulating material.

20. A method for manufacturing a display device according to any one of claims 11 to 15, wherein the thickness of the first sealing layer and the second sealing layer is greater than the height of the partition.

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