Semiconductor devices and methods of fabricating the same

Abstract

A semiconductor device includes a first transistor disposed on a first side of a substrate. The semiconductor device includes a first interconnect structure disposed above the first transistor on the first side. The semiconductor device includes a memory element disposed on a second side of the substrate opposite to the first side, wherein the memory element includes at least one capacitor. The semiconductor device includes a through-hole structure extending through the substrate and electrically coupling the memory element to the first interconnect structure.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a cross-sectional view of an example semiconductor device according to some embodiments of the present disclosure. Figures 2, 3, 4, 5 and 6 each illustrate a portion of an example semiconductor device shown in one or more of Figures 1, 7, 8, 9 and 10 according to some embodiments of the present disclosure. Figure 11 illustrates a portion of an example semiconductor device shown in Figure 12 according to some embodiments of the present disclosure. Figure 13 illustrates a flowchart of an example method for manufacturing an example semiconductor device according to some embodiments of the present disclosure. Figure 14 illustrates a flowchart of an example method for implementing one or more steps of the flowchart of Figure 13 according to some embodiments of the present disclosure. Figure 15 illustrates a portion or integral of an example semiconductor device according to some embodiments of the present disclosure. Figures 16, 17, 18, 19, 20, 21, 22 and 23 respectively illustrate cross-sectional views of portions or the entirety of the example semiconductor device of Figure 15 during various manufacturing stages of the method shown in the flowchart of Figure 13 and / or Figure 14, according to some embodiments of this disclosure. Figures 16, 17, 18, 19, 20, 21, 22, and 23 respectively illustrate partial or overall cross-sectional views of the example semiconductor device of Figure 15 according to some embodiments of the present disclosure during various manufacturing stages of the method shown in the flowchart of Figure 13 and / or Figure 14. Figures 24 and 25 respectively illustrate flowcharts of example methods for implementing one or more steps of the flowchart of Figure 13 according to some embodiments of the present disclosure. Figures 26 and 27 respectively illustrate cross-sectional views of portions or the entirety of the example semiconductor device of Figure 15 during various manufacturing stages of the method shown in the flowchart of Figure 24, according to some embodiments of this disclosure. Figure 28A illustrates a cross-sectional view of a portion of the example semiconductor device of Figure 15 during the manufacturing stage of the method shown in the flowchart of Figure 25, according to some embodiments of the present disclosure. Figure 28B illustrates a top view of the example semiconductor device of Figure 28A according to some embodiments of the present disclosure. Figure 29A illustrates a cross-sectional view of a portion of the example semiconductor device of Figure 15 according to some embodiments of the present disclosure during the manufacturing stage of the method shown in the flowchart of Figure 25. Figure 29B illustrates a top view of the example semiconductor device of Figure 28A according to some embodiments of the present disclosure. Figure 30A illustrates a cross-sectional view of a portion of the example semiconductor device of Figure 15, according to some embodiments of the present disclosure, during the manufacturing stage of the method shown in the flowchart of Figure 25. Figure 30B illustrates a top view of the example semiconductor device of Figure 28A, according to some embodiments of the present disclosure. Figures 31 through 33 respectively illustrate overall cross-sectional views of the example semiconductor device of Figure 15 during various manufacturing stages of the method shown in the flowchart of Figure 25, according to some embodiments of the present disclosure. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0007] In modern semiconductor device manufacturing processes, a large number of semiconductor devices, such as field-effect transistors (FETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as fin-based transistors (often called "FinFETs"), offer higher device density and improved performance compared to planar transistors. Some advanced non-planar transistor device architectures, such as nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, etc.), can further improve device performance. Generally, nanostructure transistors include gate structures surrounding one or more nanostructures to improve control over channel current.

[0008] Given the formation method of nanostructured transistors, these transistors generally allow for more efficient formation of interconnect structures on both the front and back sides of a device. In contrast, planar transistor device architectures typically require the corresponding interconnect structures to be formed only above the top surface of the transistor (e.g., part of what is commonly referred to as a back-end-of-line (BEOL) route). In existing technologies, various memory cells in a memory device can be integrated with such nanostructured transistors in the BEOL route on the front side of the memory device, where the transistor serves as the logic device (e.g., a driver) of the memory device. In this respect, the various components of the memory device are formed in the same space (e.g., the BEOL route), making it increasingly challenging to increase device density on the front side.

[0009] This disclosure provides various embodiments of a semiconductor device (e.g., a memory device) including a logic portion and a memory portion. In various embodiments, the logic portion, including a plurality of transistors serving as logic devices, may be formed on a front side (e.g., a first side) of a substrate; the memory portion, including a plurality of memory cells, may be formed at least partially on a rear side (e.g., a second side) of the substrate opposite the front side. This configuration allows for a more compact design of the disclosed semiconductor device. Therefore, the dimensions (e.g., gate pitch) of the transistors in the logic portion can be further reduced, and more space can be provided on the rear side for forming additional components and / or devices, which can be coupled to the front-side components and / or devices via various interconnect structures, such as through-substrate-via (TSV) structures. Additionally, the disclosed rear-side integration techniques can also provide additional routing options for the memory device. The memory device disclosed herein can further integrate higher density memory cells within the same area.

[0010] Figure 1 illustrates a cross-sectional view of a portion or the entirety of an example semiconductor device 100A (or memory device) according to some embodiments of the present disclosure. The semiconductor device 100A (or simply "device") includes a substrate 102 having a front side 102F (e.g., a first side) and a rear side 102B (e.g., a second side) opposite the front side 102F. The device 100A includes a plurality of frontside transistors 10 (FSTs) and a plurality of frontside interconnect structures 15 (FSLs) disposed above (or on) the front side 102F, wherein at least some portions of the FSLs 15 are electrically coupled to the FSTs 10. In the depicted embodiment, the FSLs 15 are disposed above (or on) the FSTs 10 along a vertical direction (e.g., the Z-axis). In the embodiment depicted in Figure 1, the FSTs 10 are configured as logic devices (e.g., drivers) constituting the logic portion of the device 100A.

[0011] As used herein, the term "electrical coupling" may be used interchangeably with "physical coupling" or "operational ground coupling". The term "electrical coupling" may be used to describe any direct electrical connection between two components without any intermediary components; or it may be used to describe any indirect electrical connection between two components with one or more intermediary components.

[0012] As depicted in Figure 1, the bottom portion of the FST 10 (e.g., near the substrate 102) is embedded (or encapsulated) in an isolation structure 108 disposed above the substrate 102, and the top portion of the FST 10 (e.g., away from the substrate 102) is embedded in an interlayer dielectric (ILD) layer 117. The isolation structure 108 is used to electrically isolate adjacent active structures (e.g., adjacent stacks of adjacent fin structures or nanostructure channel layers) from each other. The isolation structure 108 may include oxides such as silicon oxide, nitrides, low-k dielectric materials (e.g., dielectric materials having a dielectric constant less than that of silicon oxide (approximately 3.9), such as silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silica glass (BPSG), silica-free glass (USG), other suitable materials, or combinations thereof.

[0013] As depicted in Figure 1, device 100A may include a plurality of FSTs 10 arranged along a first lateral direction (e.g., the Y-axis) in the fin structure. Referring to Figure 2, each FST 10 includes a plurality of nanostructures 13 stacked along a vertical direction. The nanostructures 13 include semiconductor material and are configured as a plurality of channels of the FSTs 10. In this disclosure, the nanostructures 13 may also be referred to as semiconductor layers 13 or channel layers 13. Although the nanostructures 13 are depicted as nanosheets in this embodiment, the nanostructures 13 may also be formed as other types of structures, such as nanorods or nanowires.

[0014] Nanostructure 13 may comprise any suitable semiconductor material, such as silicon (Si), silicon-germanium (SiGe), compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), any other suitable material, or combinations thereof. In some embodiments, nanostructure 13 is substantially free of any dopant (e.g., p-type or n-type dopant). In some embodiments, nanostructure 13 is intentionally doped. For example, nanostructure 13 may be doped with p-type dopant such as boron (B), aluminum (Al), indium (In), gallium (Ga), other p-type dopant, or combinations thereof. Alternatively, nanostructure 13 may be doped with n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), other n-type dopant, or combinations thereof. Source (S), Drain (D).

[0015] Referring to Figure 2, the FST 10 includes source features 14S and drain features 14D (hereinafter collectively referred to as source / drain features 14), each electrically coupled to one end of the nanostructure 13. Thus, each source / drain feature 14 extends vertically over the entire stack of nanostructures 13. In embodiments where the FST 10 is configured as an n-type device, the source / drain features 14 may comprise Si doped with the n-type dopant described herein. In embodiments where the FST 10 is configured as a p-type device, the source / drain features 14 may comprise SiGe doped with the p-type dopant described herein. In some embodiments, each source feature 14S is a common source feature shared by two adjacent FST 10s disposed along a first lateral direction (see Figures 10 and 12).

[0016] Referring again to Figure 2, FST 10 includes an active gate structure 16 having at least a bottom (or lower) portion surrounding each nanostructure 13. In this respect, the bottom portion of the active gate structure 16 is staggered with the stack of nanostructures 13. Furthermore, the active gate structure 16 includes a top (or upper) portion disposed above the topmost nanostructure 13 in the stack. In some embodiments, the active gate structure 16 includes a gate dielectric layer and a gate metal layer above the gate dielectric layer (not depicted separately in Figure 2).

[0017] The gate dielectric layer may comprise any suitable dielectric material, such as a high-k dielectric material (e.g., a dielectric constant greater than that of silicon oxide (approximately 3.9)). Examples of high-k dielectric materials include metal oxides or metal silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb, any other suitable material, or combinations thereof. Alternatively, the gate dielectric layer may comprise silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate dielectric layer may comprise a stack of multiple different dielectric materials.

[0018] Gate metal may comprise a stack of multiple metallic materials. For example, gate metal may comprise at least a work function layer (not depicted separately) and a conductive fill layer (not depicted separately) disposed above the work function layer. The work function layer may comprise a p-type work function layer, an n-type work function layer, multiple layers thereof, any other suitable material, or a combination thereof. The work function layer may also be referred to as work function metal. Examples of work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable materials, or combinations thereof. The conductive fill layer may comprise any suitable conductive material, such as polysilicon, tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), other suitable conductive materials, or combinations thereof (or alloys thereof). The active gate structure 16 may further include additional layers, such as an adhesive layer (or bonding layer), a cover layer, a barrier layer, other suitable layers, or combinations thereof.

[0019] Referring to Figure 2, FST 10 includes an internal spacer 11 that intervenes along a first lateral direction between a portion of the active gate structure 16 and the source / drain feature 14. FST 10 further includes gate spacers 17, each extending along a sidewall of the top portion of the active gate structure 16. The internal spacer 11 and gate spacer 17 may each comprise any dielectric material, such as silicon oxide, silicon nitride, silicon oxycarbonitride, other suitable materials, or combinations thereof. The internal spacer 11 and gate spacer 17 may each comprise multiple layers of different dielectric materials. The internal spacer 11 and gate spacer 17 may comprise (multiple) the same or different dielectric materials.

[0020] Referring again to Figure 2, FST 10 further includes various contact features electrically coupled to at least one of source feature 14S, drain feature 14D, and active gate structure 16 (e.g., its conductive fill layer). In the depicted embodiment, FST 10 includes source / drain contacts 18 electrically coupled to at least one of the source / drain features 14. Source / drain contacts 18 may include a conductive fill layer (not depicted separately) having a conductive material such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof). Source / drain contacts 18 may include a barrier layer (not depicted) separating the conductive fill layer from surrounding components. The barrier layer may include Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. The source / drain contact 18 may further include a metal silicate layer (not depicted) disposed between the conductive fill layer and the underlying source / drain feature 14. The metal silicate layer may include, for example, NiSi.

[0021] Referring together to Figures 1 and 3, FSL 15 includes multiple dielectric layers (e.g., intermetallic dielectric (IMD) layers) embedding vertical conductive features (or interconnect conductive features), such as vias, and horizontal conductive features, such as metal (or conductive) lines. For example, FSL 15 may include IMD layers 120 and 122 vertically stacked above IMD layer 117. FSL 15 may include vias V0 and metal lines M0 embedded in IMD layer 120, wherein via V0 interconnects a portion of FST 10 to metal line M0. FSL 15 may further include vias V1 and metal lines M1 embedded in IMD layer 122, wherein via V1 interconnects metal lines M0 to metal lines M1. In some embodiments, each of IMD layers 120, 122 includes multiple dielectric layers, each dielectric layer encapsulating vias (e.g., vias V0, V1, etc.) or metal lines (e.g., metal lines M0, M1, etc.).

[0022] Each front-side IMD layer and its corresponding embedded conductive feature can be collectively referred to as a front-side metallization layer. For example, IMD layer 120, via V0, and metal line M0 can be collectively referred to as the zeroth front-side metallization layer; IMD layer 122, via V1, and metal line M1 can be collectively referred to as the first front-side metallization layer; and so on. Referring to Figure 3, an additional front-side metallization layer including conductive features (such as VX-1, MX-1, VX, and MX) can be formed above IMD layer 122 on the front side 102F.

[0023] ILD / IMD layers 117, 120, and 122 may each comprise an oxide, such as silicon oxide, a low-k dielectric material, such as silicon phosphorus glass (PSG), borosilicate glass (BSG), borosilicate glass, silica-free glass (USG), other suitable dielectric materials, or combinations thereof. In some embodiments, ILD / IMD layers 117, 120, and 122 comprise the same composition as isolation structure 108. Various conductive features V0, V1, M0, and M1 embedded in the corresponding ILD / IMD layers 117, 120, and 122 each comprise a conductive fill layer (not depicted separately) having a conductive material, such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations (or alloys) thereof. In some embodiments, each conductive feature includes a barrier layer (not depicted) separating the conductive fill layer from the surrounding ILD / IMD layers. The barrier layer may include Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof.

[0024] Referring to Figure 1, device 100A further includes a plurality of backside interconnect structures 20 (BSLs) and at least one backside memory element 40 (BSM) above (or on) the rear side 102B. Each BSM 40 is embedded in and electrically coupled to a portion of the BSL 20 along a vertical direction. For example, the top portion of the BSM 40 (e.g., at a location close to the substrate 102) is electrically coupled to a first portion of the BSL 20, and the bottom portion of the BSM 40 (e.g., at a location away from the substrate 102) is electrically coupled to a second portion of the BSL 20, wherein the second portion is below the first portion. In some embodiments, device 100A may optionally include a backside transistor 60 (BST) embedded in the BSL 20 and electrically coupled in series to one of the BSMs 40. As will be described in detail below, the BST 60 may differ structurally and / or functionally from the FST 10.

[0025] Referring together to Figures 1 and 4, the structure of BSL 20 may be similar to that of FSL 15. For example, BSL 20 includes multiple IMD layers 140, 144, 148, and 152 stacked above the rear side 102B. In this respect, IMD layers 140-152 are disposed below FST 10 and are perpendicular to FSL 15 in the vertical direction. BSL 20 may include vias BV0 and metal lines BM0 embedded in IMD layer 140, wherein via BV0 interconnects a portion of the front-side components (e.g., through-substrate-via structure (TSV) 190) to metal line BM0. BSL 20 may include vias BV1 and metal lines BM1 embedded in IMD layer 144, wherein via BV1 interconnects metal lines BM0 to metal lines BM1. Similarly, metal line BMX-1 can be embedded in IMD layer 148, and metal line BMX can be embedded in IMD layer 152, wherein via BVX interconnects metal line BMX-1 to metal line BMX. In some embodiments, each IMD layer 140-152 includes multiple dielectric layers, each dielectric layer encapsulating vias (e.g., vias BV0, BV1, and BVX, etc.) and corresponding metal lines (e.g., metal lines BMO, BM1, BMX-1, and BMX, etc.). Referring to Figure 4, an additional rear metallization layer including conductive features (such as BVX+1, BMX+1, BVX+2, and BMX+2, etc.) can be formed above IMD layer 152 on rear side 102B.

[0026] In this embodiment, device 100A further includes a TSV 190 having at least a portion extending through substrate 102 to electrically couple a component disposed on front side 102F to a component disposed on rear side 102B. In the depicted embodiment, TSV 190 electrically couples the top portion of BSL 20 (e.g., via BV0) to FSL 15 (e.g., metal line M0). In this regard, TSV 190 may extend through at least substrate 102, isolation structure 108, ILD layer 117, and IMD layer 120. TSV 190 may also be referred to as an interconnect conductive feature.

[0027] In some embodiments, TSV 190 has a structure and composition similar to the vias of FSL 15, such as vias V0 and V1 (or vias of BSL 20). For example, TSV 190 includes a conductive fill layer 192 having a conductive material such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof). In some embodiments, TSV 190 further includes a barrier layer 194 separating the conductive fill layer 192 from surrounding components. Barrier layer 194 may include Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. In some instances, TSV 190 may be formed as a monolithic structure extending from substrate 102 to metal line M0.

[0028] Each rear IMD layer and its corresponding conductive feature embedded therein are collectively referred to as a rear metallization layer. For example, IMD layer 140, via BV0, and metal line BM0 are collectively referred to as the zeroth rear metallization layer; IMD layer 144, via BV1, and metal line BM1 are collectively referred to as the first rear metallization layer; referring to Figure 4, an additional rear metallization layer including conductive features (such as BVX+1, BMX+1, BVX+2, and BMX+2) can be formed above IMD layer 152 on rear side 102B. In some embodiments, IMD layers 140-152 may include the same structure and composition as ILD / IMD layers 117, 120, and 122 described herein, and the conductive features embedded in IMD layers 140-152 (e.g., BV0, BMO, BV1, BMO, etc.) may include the same composition and structure as the conductive features embedded in IMD layers 120 and 122 (e.g., V0, M0, V1, M1, etc.).

[0029] In some embodiments, the series-coupled BSM 40 and BST 60 form a backside memory cell (BSMC) with a 1T1C structure, such as BSMC1 and BSMC2 depicted in Figure 1. In this respect, BSM 40 is configured as a capacitor (C) of the BSMC, and BST 60 is configured as a transistor (T) of the BSMC. ​​In some embodiments, BSM 40 serves as a memory cell of the BSMC, while BST 60 serves as a switch to allow access to BSM 40 in the BSMC (e.g., programming, reading, erasing, etc.). In some embodiments, BSM 40 and BST 60 are electrically coupled via a portion of BSL 20, such as the metal line BMX-1 depicted in Figure 1.

[0030] In this embodiment, BST 60 includes a metal oxide-based semiconductor material as the transistor channel, which differs from the channel of FST 10. Functionally, if BST 60 is connected in series to BSM 40, as depicted in Figures 1 and 2, then BST 60 is configured as the transistor portion of a BSMC. ​​In contrast, if FST 10 is not connected in series (but for example, in parallel) to BSM 40, then FST 10 can be configured as a logic device on the front side 102F (e.g., as part of the logic portion of the device depicted in Figures 1 and 2). Alternatively, if FST 10 is connected in series to BSM 40 via at least TSV 190, then FST 10 can be configured as the transistor portion of a memory cell (e.g., a cross-substrate memory cell described below), as described in detail below with reference to Figures 8 through 10 and 12.

[0031] As described herein, the entire 1T1C structure is formed on the rear side 102B and electrically coupled to BSL 20, which is then coupled to FSL 15 via TSV 190. In this respect, the BSMC constituting at least a portion of the memory portion of device 100A is provided integrally on the rear side 102B, thereby improving the space utilization of the rear side 102B and allowing more devices with reduced dimensions (e.g., devices for the logic and / or memory portions of 100A) to be formed on the front side 102F. For example, as will be described in detail below, additional memory cells can be formed on the front side 102F and BSM 40 can be formed on the rear side 102B. Thus, a greater device density can be achieved on both sides of device 100A. Furthermore, placing at least a portion of the memory portion on the rear side 102B allows for additional routing from the rear side 102B, thereby increasing the flexibility of the device's routing options and relaxing the design rules for the front-side components (e.g., FST 10 and FSL 15).

[0032] Depending on the type of materials(s) used in BSM 40, the BSMC may include dynamic random-access memory (DRAM) cells, magnetoresistive random-access memory (MRAM) cells, resistive random-access memory (ReRAM) cells, ferroelectric random-access memory (FeRAM) cells, similar, or other suitable types of memory cells that have been developed, are under development, or will be developed. In some embodiments, device 100A may include two or more BSMCs of the same or different types, each BSMC including at least BSM 40. In some embodiments, referring to Figure 1, the rear memory cells BSMC1 and BSMC2 are formed in the same IMD layer, for example, IMD layer 42.

[0033] In some embodiments, referring to Figures 1 and 5, the BSM 40 is configured as a capacitor having a metal-insulator-metal (MIM) structure. In this respect, the BSM 40 generally includes a bottom electrode 44 (e.g., a first metal layer), a top electrode 48 (e.g., a second metal layer), and a dielectric layer 46 (e.g., an insulating layer) sandwiched vertically between the bottom electrode 44 and the top electrode 48. The BSM 40 may further include a first via 50 and a second via 52, the first via electrically coupling the bottom electrode 44 to a portion of the BSL 20 below the BSM 40, and the second via electrically coupling the top electrode 48 to a portion of the BSL 20 above the BSM 40.

[0034] The bottom electrode 44 and top electrode 48 may comprise iron (Fe), W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof). In some embodiments, the bottom electrode 44 and top electrode 48 may comprise metals doped with dopants (or impurities). The dielectric layer 46 may comprise any suitable dielectric material, such as silicon dioxide, ZrO, TiO2, MgO, the high-k dielectric materials described herein, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, or the like. The first via 50 and the second via 52 may have the same composition and structure as the vias V0 and V1 described herein.

[0035] In embodiments where the BSMC is an MRAM cell, the bottom electrode 44 and the top electrode 48 may each comprise a ferromagnetic material having, for example, Fe doped with Co, boron (B), nickel (Ni), other suitable dopants, or combinations thereof, and the dielectric layer 46 comprises, for example, magnesium oxide (MgO). In embodiments where the BSMC is an FeRAM cell, the dielectric layer 46 comprises a ferroelectric material. Although not described herein, other capacitor configurations, such as MOS capacitors, may also be applicable to this embodiment of the BSM 40.

[0036] In some instances, referring to Figure 1, BST 60 may include a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS) transistor, a p-channel metal-oxide-semiconductor (PMOS), an n-channel metal-oxide-semiconductor (NMOS), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a fin-like FET (FinFET), a planar MOSFET, a nanosheet / nanowire FET (e.g., a GAA FET), the like, or other suitable types of memory cells that have been developed, are under development, or will be developed. BST 60 may sometimes be referred to as a back-gate transistor. In some embodiments, device 100A may include two or more BSTs 60 of the same or different types, each BST connected in series to a corresponding BSM 40 to form one of the BSMCs. In the depicted embodiment, BST 60 is embedded in IMD layer 61, which may have the same structure and composition as IMD layers 140-152 described herein.

[0037] In some embodiments, referring together to Figures 1 and 6, BST 60 includes a channel layer 62 having a metal-oxide-semiconductor material. BST 60 includes a source electrode 64S and a drain electrode 64D (collectively referred to as source / drain electrode 64), each electrode extending vertically from a separate end of the channel layer 62. In some embodiments, at least one of the source / drain electrodes 64 (e.g., drain electrode 64D) is electrically coupled to BSM 40 (e.g., top electrode 48) through a portion of BSL 20 (e.g., metal line BMX-1) and a second via 52. BST 60 further includes a gate dielectric layer 66 overlying the channel layer 62 and a gate electrode 68 disposed above the gate dielectric layer 66. In some embodiments, gate electrode 68 is electrically coupled to a portion of BSL 20 disposed above BST 60 (e.g., metal line BM1). In this embodiment, gate electrode 68 is electrically coupled to FSL 15 through BSL 20 and a portion of TSV 190.

[0038] Channel layer 62 may include one or more metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), tetravalent (IV) tin oxide (SnO2), nickel oxide (NiO), copper oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper indium oxide (CuInO2), strontium copper oxide (SrCu2O2), divalent (II) tin oxide (SnO), other suitable indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO), polycrystalline silicon, amorphous silicon, other suitable materials, or combinations thereof. Channel layer 62 may include n-type channel materials or p-type channel materials. Gate dielectric layer 66 may include any silicon oxide, silicon oxynitride, high-k dielectric materials described herein, other suitable dielectric materials, or combinations thereof. In some embodiments, gate dielectric layer 66 has the same composition as dielectric layer 46 of BSM 40. The source electrode / drain electrode 64 and the gate electrode 68 may each include W, Cu, Co, Ru, Al, Ti, TiN, Ta, TaN, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof).

[0039] Figure 7 illustrates a partial or overall cross-sectional view of an example semiconductor device 100B (or memory device) according to some embodiments of the present disclosure. Semiconductor device 100B (or simply "device") can be used to have a structure similar to device 100A. For example, device 100B includes a plurality of BSMCs, such as BSMC1, BSMC2, and BSMC3, disposed on rear side 102B and configured as the memory portion of device 100B. Each of the BSMCs includes a BSM 40 electrically coupled in series to BST 60 in a 1T1C structure as described herein. Device 100B includes a plurality of FSTs 10 on front side 102F, the FSTs being configured as logic devices in the logic portion of device 100B. Furthermore, each of the BSMCs is electrically coupled to FSL 15 via TSV 190.

[0040] However, the configuration of the BSMCs differs between device 100B and device 100A. For example, BSMC1 and BSMC2 do not extend through the same IMD layer, but rather each extends through (or occupies) IMD layers 61, 148, and 42, while BSMC3 extends through (or occupies) IMD layers 63, 156, and 43. These IMD layers are below IMD layers 61, 148, and 42 (e.g., at a location away from substrate 102). In some instances, placing different memory cells in different IMD layers can improve the utilization of different portions (e.g., horizontal levels) of the rear side 102B, thereby further increasing the device density (e.g., memory devices) on at least the rear side 102B of device 100B. In some instances, by staggering the positioning of the BSMCs on the rear side 102B, the size restrictions on the memory cells can be relaxed, allowing BST 60 and / or BSM 40 to be formed to a larger area, for example, to improve device performance.

[0041] Figure 8 illustrates a partial or overall cross-sectional view of an example semiconductor device 100C (also referred to as a memory device) according to some embodiments of the present disclosure. The semiconductor device 100C (hereinafter referred to as the "device") can be used to have a structure similar to that of device 100A. For example, device 100C includes a plurality of BSMs 40, such as BSM1 and BSM2, disposed on a rear side 102B. Device 100C includes a plurality of FSTs 10 on a front side 102F. Furthermore, device 100C includes a TSV 190, each of the BSLs 20 being electrically coupled to an FSL 15 via the TSV.

[0042] However, the configuration of the memory portion of device 100C differs from that of device 100A. For example, each of the BSMs 40 is series-coupled to one of the FSTs 10, thereby forming a trans-substrate memory cell (TSMC), such as TSMC1 and TSMC2, which serve as the memory portion of device 100C. Each TSMC has a 1T1C structure similar to that of the BSMC in device 100A. In this respect, the capacitor portion of the TSMC is disposed on the rear side 102B, and the transistor portion of the TSMC is disposed on the front side 102F, such that the memory portion of device 100C spans both the front side 102F and the rear side 102B of substrate 102.

[0043] In the depicted embodiment, BSM 40 is electrically coupled to the corresponding FST 10 through portions of BSL 20, TSV 190, and FSL 15. For example, TSMC1 includes BSM 40, which is coupled to portions of BSL 20 (e.g., metal wires BMX-1 and BMO and vias BVX-1 and BV0), which are coupled to metal wire M1 of FSL 15 through portions of TSV 190 and FSL 15 (e.g., vias V0 and V1 and metal wire M0). Metal wire M1 is further coupled to the drain feature 14D of the corresponding FST 10 through other portions of FSL 15 and source / drain contacts 18, thereby establishing a series coupling between BSM 40 and FST 10. Similarly, TSMC2 includes a BSM 40 coupled to a portion of BSL 20, which is coupled to a metal line M0 of FSL 15 via TSV 190. The metal line M0 is further coupled to a drain feature 14D of the corresponding FST 10 via a portion of FSL 15 (e.g., via V0) and S / D contact 18.

[0044] Although not depicted in Figure 8, device 100C may further include various logic devices disposed on the front side 102F, thereby allowing increased device density by utilizing both sides of substrate 102. In some instances, the logic devices may include FST 10 disposed on the front side 102F but not electrically coupled in series to BSM 40.

[0045] Figure 9 illustrates a partial or overall cross-sectional view of an example semiconductor device 100D (also referred to as a memory device) according to some embodiments of the present disclosure. The semiconductor device 100D (hereinafter referred to as the "device") can be used to have a structure similar to that of device 100C. For example, device 100D includes a plurality of TSMCs, such as TSMC1, TSMC2, and TSMC3, configured as the memory portion of device 100D. In this regard, the capacitor portions of each TSMC are disposed on the rear side 102B, and the transistor portions of the TSMCs are disposed on the front side 102F, similar to that depicted in Figure 8. In the depicted embodiment, each of the TSMCs of device 100D includes at least a portion electrically coupled to the BSM 40 corresponding to FST 10 via metal lines M1 of BSL 20, TSV 190, and FSL 15.

[0046] However, the configuration of the TSMCs differs between device 100D and device 100C. For example, instead of being located in the same IMD layer as in the example of device 100C, the BSM 40s of TSMC 1 and TSMC 2 are located in IMD layer 42, while TSMC 3 is located in IMD layer 43 below IMD layer 42 (e.g., at a location away from substrate 102). In contrast, the BSM 40s of both TSMCs in device 100C are located in IMD layer 42. As described herein, placing different memory cells or portions thereof in different IMD layers can improve the utilization of different portions (e.g., horizontal levels) of the rear 102B, thereby further increasing the device density on at least the rear 102B of device 100D. In some instances, by staggering the positioning of the BSM 40s on the rear 102B, the size restrictions on the memory cells can be relaxed, allowing the BSM 40s to be formed over a larger area, for example, to improve device performance.

[0047] Figure 10 illustrates a partial or overall cross-sectional view of an example semiconductor device 100E (also referred to as a memory device) according to some embodiments of the present disclosure. The semiconductor device 100E (hereinafter referred to as the "device") can be used to have a structure similar to that of device 100C. For example, device 100E includes a plurality of TSMCs, such as TSMC1 and TSMC2, configured as the memory portion of device 100E. In this regard, the capacitor portion of each TSMC is disposed on the rear side 102B, and the transistor portion of the TSMC is disposed on the front side 102F, similar to that depicted in Figure 8. In the depicted embodiment, each of the TSMCs of device 100E includes a BSM 40, which is electrically coupled to a corresponding FST 10 via at least a portion of the metal lines M0 of BSL 20, TSV 190, and FSL 15.

[0048] However, unlike device 100C, in addition to TSMC1 and TSMC2, device 100E further includes a plurality of frontside memory cells (FSMCs), such as FSMC1 and FSMC2, configured as the memory portion of device 100E. In the depicted embodiment, each of FSMC1 and FSMC2 includes an FST 10 electrically coupled in series to a corresponding frontside memory element (FSM), wherein the FSM 80 is disposed in the IMD layer 82. Specifically, the FSM 80 is electrically coupled to the drain feature 14D of the corresponding FST 10, thereby establishing a series connection therebetween.

[0049] In some embodiments, FSM 80 has a structure and composition similar to that of BSM 40. For example, referring to Figure 11, FSM 80 includes a MIM capacitor structure having a bottom electrode 84 (e.g., a first metal layer), a top electrode 88 (e.g., a second metal layer), and a dielectric layer 86 (e.g., an insulating layer) sandwiched between the bottom electrode 84 and the top electrode 88 in a vertical direction. FSM 80 may further include a first via 90 that electrically couples the bottom electrode 84 to the portion of FSL 15 below FSM 80 (e.g., vias V0, V1, and VX-1, and metal lines M0, M1, and MX-1); and a second via 92 that electrically couples the top electrode 88 to the portion of FSL 15 above FSM 80 (e.g., metal line MX). Because FSMC has a 1T1C structure, both the transistor and capacitor portions of each FSMC are disposed on the front side 102F.

[0050] Therefore, both the front side 102F and the rear side 102B are used to form the memory portion of device 100E, thereby potentially achieving a greater device density than device 100C. In some instances, although not depicted, TSMC's BSM 40 may be formed in different IMD layers, similar to device 100D, to allow the BSM 40 to be interleaved on the rear side 102B.

[0051] In some embodiments, TSMC1 and adjacent FSMC1 are used to share a common source feature, such as source feature 14S, thereby allowing the front-side device (e.g., FSMC) to have a more compact dimension along a first lateral direction. For example, the cell dimension can be reduced to 1.5 times (P=1.5T) the lateral dimension of FST 10, which contrasts with a cell dimension that is twice (P=2T) the lateral dimension of FST 10 in embodiments where source feature 14S is not shared between adjacent memory cells. To accommodate the sharing of source features, device 100E may further include a dummy gate structure 196 (or inactive gate) disposed between drain features (such as drain feature 14D) of two adjacent FSMCs, wherein the dummy gate structure 196 is grounded (or electrically coupled to a 0V supply voltage). The dummy gate structure 196 may have a similar structure and composition to the active gate structure 16, but is not electrically coupled to any signal line as in the case of the active gate structure 16.

[0052] Figure 12 illustrates a partial or overall cross-sectional view of an example semiconductor device 100F (also referred to as a memory device) according to some embodiments of the present disclosure. The semiconductor device 100F (hereinafter referred to as the "device") can be used to have a structure similar to that of device 100E. For example, device 100F includes a plurality of TSMCs, such as TSMC1 and TSMC2, configured as the memory portion of device 100F. Device 100F further includes a plurality of FSMCs, such as FSMC1 and FSMC2, configured as additional memory portions of device 100F. Furthermore, adjacent FSMCs and TSMCs share common source features, such as source feature 14S, thereby reducing the lateral dimension of the front-side device (e.g., the FSMC) to 1.5T, similar to that depicted in Figure 10.

[0053] However, unlike device 100E, device 100F includes a dielectric structure 198 (or isolation gate) between the drain features 14D of two adjacent FSMCs. In some embodiments, the dielectric structure 198 may be formed as a cut-poly-on-diffusion-edge (CPODE) feature, which generally replaces the active gate structure 16 between the drain features 14D of two adjacent transistors. The dielectric structure 198 may include any dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric structure 198 may be formed in place of the active gate structures 16 after all active gate structures 16 on the front side 102F have been formed. In some embodiments, the dielectric structure 198 and the dummy gate structure 196 each function to electrically isolate adjacent front-side devices (such as FSMC 1 and FSMC 2). In some instances, dielectric structure 198 and dummy gate structure 196 can be used interchangeably.

[0054] Figure 13 illustrates a flowchart of an example method 200 for manufacturing a semiconductor device 300 (e.g., devices 100A-100F) according to some embodiments. It should be noted that method 200 is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that additional steps / operations may be provided before, during, and after method 200 of Figure 13, and only a few other operations may be briefly described herein. In some embodiments, the operations of method 200 are described in detail in the flowcharts shown in Figures 14, 24, and 25. The operations of method 200 may be associated with cross-sectional views of the semiconductor device 300 at various manufacturing stages, as shown in Figures 16 through 33, which will be described in further detail below.

[0055] Briefly, referring to Figure 13, method 200 begins at operation 202, forming a first transistor (or front-side transistor FST, e.g., FST 10, 1000) on the front side (or front side, e.g., 102F, 302F) of a substrate (e.g., substrate 102, 302). Method 200 proceeds to operation 204, forming a first interconnect structure (or front-side interconnect structure FSL, e.g., FSL 15, 1100) on the front side. Method 200 optionally proceeds to operation 206, forming a first memory element (or front-side memory element FSM, e.g., FSM 80, 1200) on the front side. Method 200 proceeds to operation 208, forming a through-substrate via structure (TSV; e.g., TSV 190, 920). Next, method 200 proceeds to operation 210, forming a second interconnect structure (or rear interconnect structure BSL, e.g., BSL 20, 1300) on the rear side (or second side, e.g., rear side 102B) of the substrate opposite the front side. Method 200 may optionally proceed to operation 212, forming a second transistor (or rear transistor BST, e.g., BST 60, 1600) on the rear side. Method 200 proceeds to operation 214, forming a second memory element (or rear memory element BSM, e.g., BSM 40, 1400) on the rear side. In some embodiments, the second memory element is series-coupled to the second transistor on the second side (see Figures 1 and 7). In some embodiments, the second memory element is series-coupled to the first transistor (see Figures 8 to 10 and 12).

[0056] Figure 15 illustrates a perspective view of a portion of an example semiconductor device 300 (or simply "device") according to some embodiments, which includes at least the example frontside transistor 1000 (FST) depicted herein on the front side of device 300. In some embodiments, the FST 1000 is fabricated at operation 202 of method 200, as described in detail in the flowchart shown in Figure 14.

[0057] Device 300 includes a substrate 302 and a plurality of semiconductor layers 306 (e.g., nanostructures 13) on the substrate 302 (e.g., substrate 102). The semiconductor layers 306 may optionally be configured as nanosheets, nanorods, nanowires, or other suitable nanostructures. The semiconductor layers 306 are perpendicularly separated from each other and collectively serve as channels for the FST 1000. Isolation regions / structures 504 (e.g., isolation structure 108) are formed on the sidewalls of protrusions of the substrate 302, with semiconductor layers 306 disposed on the protrusions. Active gate structures 900 (e.g., active gate structure 16) surround each of the semiconductor layers 306 (e.g., the entire periphery of each of the semiconductor layers 306). Source / drain features 802 (e.g., source / drain features 14) (one of which is depicted as shown in Figure 15) are disposed on opposite sides of the active gate structures 900, with gate spacers 702 disposed therebetween. An interlayer dielectric (ILD) 806 is disposed above and may extend below a portion of the source / drain feature 802. The FST 1000 (i.e., device 300) shown in Figure 15 is simplified; therefore, it should be understood that one or more features of the complete FST 1000 may not be shown in Figure 15. For example, another of the source / drain features 802 is not depicted in Figure 15. Furthermore, Figure 15 is provided for reference to illustrate numerous cross-sectional views of the device 300 along line AA' extending in the first lateral direction in subsequent figures.

[0058] In brief, referring to Figure 14, the FST 1000 can be formed by performing sub-operations of operation 202. For example, operation 202 may begin with sub-operation 252, providing a substrate 302 covered by a first semiconductor layer 304 and a second semiconductor layer 306. Next, operation 202 proceeds to sub-operation 254, forming a fin structure 400. Operation 202 proceeds to sub-operation 256, forming an isolation structure 504. Operation 202 proceeds to sub-operation 258, forming a dummy gate structure 600 over the semiconductor fins. Operation 202 proceeds to sub-operation 260, forming internal spacers (e.g., internal spacer 11). Operation 202 proceeds to sub-operation 262, forming source and / or drain features. Operation 202 proceeds to sub-operation 264, removing the dummy gate structure and the first semiconductor layer. Operation 202 proceeds to sub-operation 266, forming an active gate structure. Operation 202 may optionally be performed to sub-operation 268, which replaces some of the active gate structure with a dielectric structure (e.g., dielectric structure 198). Operation 202 may also be performed to sub-operation 270, which forms contact features of components electrically coupled to the FST 1000.

[0059] Referring to Figures 14 and 16, according to various embodiments, at sub-operation 252, a plurality of first semiconductor layers 304 and a plurality of second semiconductor layers 306 are alternately formed on top of each other over the front side 302F of the substrate 302. Such alternating stacks of first semiconductor layers 304 and second semiconductor layers 306 may be formed as a stack over the front side of the substrate 302. It should be understood that FST 1000 may include any number of first semiconductor layers 304 (each serving as a sacrificial layer) and any number of second semiconductor layers 306 (each serving as a channel layer), wherein either one is the top layer, while still within the scope of this disclosure.

[0060] In some embodiments, substrate 302 has substantially the same structure and composition as substrate 102 described herein. In some embodiments, substrate 302 includes an epitaxial layer. For example, semiconductor substrate 302 may have an epitaxial layer of an overlying semiconductor. Furthermore, substrate 302 may include a semiconductor-on-insulator (SOI) structure. For example, substrate 302 may include a buried oxide (BOX) layer formed by processes such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and polishing.

[0061] Semiconductor layers 304 and 306 may have different thicknesses. The first semiconductor layer 304 may have different thicknesses from one layer to another. The second semiconductor layer 306 may have different thicknesses from one layer to another. The first stacked layer may be thicker than the other semiconductor layers 304 and 306. The first semiconductor layer 304 or the second semiconductor layer 306 may be the top layer (or the layer furthest from the semiconductor substrate 302). In an embodiment, the first semiconductor layer 304 may be the bottom layer (or the layer closest to the semiconductor substrate 302).

[0062] Semiconductor layers 304 and 306 have different compositions. In various embodiments, the two semiconductor layers 304 and 306 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In one embodiment, the first semiconductor layer 304 comprises silicon germanium (Si1-xGex), and the second semiconductor layer 306 comprises silicon (Si). In some embodiments, the second semiconductor layer 306 has a composition substantially the same as that of the nanostructure 13 described herein. Either of semiconductor layers 304 and 306 may comprise other materials, for example, compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, any other suitable materials, or combinations thereof. The materials of semiconductor layers 304 and 306 may be selected to provide different oxidation rates and / or etch selectivity.

[0063] Semiconductor layers 304 and 306 can be grown from semiconductor substrate 302. For example, each of semiconductor layers 304 and 306 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD, MOCVD), and / or other suitable growth processes. During epitaxial growth, the crystal structure of semiconductor substrate 302 extends upward, resulting in semiconductor layers 304 and 306 having the same crystal orientation as semiconductor substrate 302.

[0064] Referring to Figures 14 and 17, according to various embodiments, fin structures 400A, 400B, and 400C (collectively referred to as fin structures 400) are formed in the stack of semiconductor layers 304 and 306 at sub-operation 254. Each of the fin structures 400 extends along a first lateral direction and is spaced apart from each other along a second lateral direction perpendicular to the first lateral direction (e.g., the X-axis). Although three fin structures are shown in the embodiment illustrated in Figure 17 (and the following figures), it should be understood that the FST 1000 may include any number of fin structures while still within the scope of this disclosure.

[0065] The fin structure 400 is formed by patterning the stack of semiconductor layers 304 and 306 and the top portion of substrate 302 using techniques such as optical lithography and etching. For example, a mask layer (which may include multiple layers, such as a pad oxide layer and an overlay pad nitride layer) is formed over the topmost second semiconductor layer 306. For example, the pad oxide layer and the pad nitride layer may be formed using thermal oxidation, low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0066] The mask layer can then be patterned using optical lithography. Generally, optical lithography removes a portion of the photoresist material by depositing, irradiating (exposing), and developing the photoresist material (not shown). The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask 402, as shown in Figure 17. After the patterned mask layer, the photoresist material can be removed by suitable methods, such as plasma ashing or resist stripping.

[0067] Subsequently, the exposed portions of semiconductor layers 304 and 306 and substrate 302 are patterned using a patterned mask 402 to form trenches (or openings) 410, thereby defining fin structures 400 between adjacent trenches 410, as shown in Figure 4. The trenches 410 extend continuously along a first lateral direction. When multiple fin structures are formed, this trench 410 can be disposed between any adjacent fin structures. In some embodiments, the fin structures 400 are formed by etching trenches in semiconductor layers 304 and 306 and substrate 302 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), other suitable processes, or combinations thereof. The etching process can be anisotropic.

[0068] Referring to Figures 14 and 18, according to various embodiments, an isolation structure 504 (also referred to as an isolation region) is formed at sub-operation 256. As shown in Figure 18, the isolation structure 504 may be formed between adjacent fin structures 400 and partially embedded in or surrounding the lower portion of adjacent fin structures 400.

[0069] In some embodiments, isolation structure 504 has substantially the same composition as isolation structure 108. Isolation structure 504 may be formed by depositing an insulating material first by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition processes in remote plasma systems followed by curing to transform it into another material, such as oxides), other suitable methods, or combinations thereof. Once the insulating material is formed, an annealing process may be performed. A planarization process, such as chemical mechanical polishing (CMP), or any other suitable process may remove any excess insulating material and form a coplanar top surface of the insulating material and a top surface of the patterned mask 402 (not shown). In some other embodiments, the patterned mask 402 may be removed by a planarization process. Subsequently, the insulating material is recessed to form isolation structure 504, which is sometimes referred to as shallow trench isolation (STI). The isolation structure 504 is recessed, causing the fin structure 400 to protrude from between adjacent isolation structures 504. The isolation structures 504 may be recessed to a position where the top surface 505 of the isolation structure 504 is below the substrate 302. The isolation structures 504 can be recessed using an acceptable etching process, such as an etching process selective for the material of the isolation structure 504. For example, dry etching or wet etching using dilute hydrofluoric acid (DHF) can be performed to recess the isolation structure 504.

[0070] Referring to Figures 14 and 19, according to various embodiments, at sub-operation 258, a plurality of dummy gate structures 600 are formed above the fin structure 400. Each of the dummy gate structures 600 extends continuously along a second lateral direction and is positioned at a location where a movable (e.g., metallic) gate structure may later be formed. Three dummy gate structures 600 are shown in Figure 19, but it should be understood that any number of dummy gate structures 600 may be formed above the fin structure 400.

[0071] Before forming the dummy gate structure 600, an etch stop layer 602 may be formed above the top surface of the fin structure 400. The etch stop layer 602 may comprise silicon oxide or any other suitable material and may be formed by a deposition process, such as CVD, ALD, other suitable processes, or combinations thereof. Next, for example, a dummy gate electrode layer (not depicted) comprising polycrystalline silicon may be deposited as a blanket layer over the etch stop layer 602. In some embodiments, a hard mask 604 is deposited over the dummy gate electrode layer. Then, the dummy gate electrode is formed by first patterning the hard mask 604 using an optical lithography process described herein, and then using the patterned hard mask 604 as an etch mask to etch the dummy gate electrode layer.

[0072] In some embodiments, although not depicted, each of the dummy gate structures 600 further includes a dummy gate dielectric layer (not shown) disposed between the etch stop layer 602 and the dummy gate electrode layer. The dummy gate dielectric layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, multilayers thereof, other suitable dielectric materials, or combinations thereof, and may be formed by thermal oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof.

[0073] Referring to Figures 14 and 20, according to various embodiments, at sub-operation 260, a gate spacer 702 is formed on the opposing sidewalls of the dummy gate structure 600. The gate spacer 702 may comprise any suitable dielectric material as described herein with respect to gate spacer 17. In some embodiments, the gate spacer 702 comprises multiple layers of different dielectric materials. The gate spacer 702 may be formed by first conformally depositing one or more dielectric materials over the dummy gate structure 600. Any suitable deposition method, such as thermal oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof, may be used to deposit the dielectric material. The dielectric material may then be etched using a suitable etching process (such as an anisotropic dry etching process) to form the gate spacer 702 along the opposing sidewalls of the dummy gate structure 600.

[0074] Referring to Figures 14 and 20, according to various embodiments, at sub-operation 262, source / drain features 802 are formed on individual sides of the dummy gate structure 600 in each fin structure 400. The source / drain features 802 can be formed by performing an etching process to remove portions of the fin structure 400 not covered by the dummy gate structure 600 and gate spacer 702. The etching process may include an anisotropic etching process using the dummy gate structure 600 as an etching mask, although any other suitable etching process may also be used. After removing portions of the fin structure 400, source / drain recesses 706 are formed.

[0075] During or after the formation of the source / drain recesses 706, individual end portions of each of the first semiconductor layers 304 may be removed or etched. A "pull-back" process may be used to remove the end portions of the first semiconductor layer 304 to pull the first semiconductor layer 304 back to an initial pull-back distance, such that the end portions of the first semiconductor layer 304 terminate below the gate spacer 702 (e.g., aligned with the gate spacer). It should be understood that the pull-back distance (i.e., the degree to which each of the semiconductor layers 304 has been etched or pulled back) may be increased or decreased arbitrarily. Due to the etch selectivity between the first semiconductor layer 304 and the second semiconductor layer 306, the second semiconductor layer 306 remains substantially intact during this etch process.

[0076] Next, an internal spacer 704 is formed on the exposed end portion of the first semiconductor layer 304 in the source / drain recess 706. The internal spacer 704 may include any suitable dielectric material as described herein with respect to internal spacer 11. The internal spacer 704 may be formed by depositing one or more layers of dielectric material over the exposed end portion of the first semiconductor layer 304 using CVD, ALD, physical vapor deposition (PVD), other suitable methods, or combinations thereof. Subsequently, the dielectric material(s) may be etched using isotropic or anisotropic etching processes to remove excess dielectric material(s) from the sidewalls of the second semiconductor layer 306 and the top surface of the semiconductor substrate 302.

[0077] Subsequently, a source / source feature 802 is formed in the source / drain recess 706 above the internal spacer 704. The source / drain feature 802 may include any suitable semiconductor material as described herein with respect to source / drain feature 14. In some embodiments, the source / drain feature 802 is aligned with the end portions of the internal spacer 704 and the second semiconductor layer 306. The source / drain feature 802 may be formed on the exposed ends of each of the second semiconductor layers 306 using an epitaxial layer growth process. For example, the growth process may include selective epitaxial growth (SEG), CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial processes, or combinations thereof. In some other embodiments, the bottom surface of the source / drain feature 802 may be lower than the top surface of the isolation structure 504.

[0078] In-situ doping (ISD) can be applied to form the doped source / drain features 802, thereby creating the junctions for the FST 1000. For example, when the FST 1000 is configured as an n-type device, the source / drain feature 802 may comprise Si doped with the n-type dopant described herein. When the FST 1000 is configured as a p-type device, the source / drain feature 802 may comprise SiGe doped with the p-type dopant described herein.

[0079] Referring to Figures 14 and 21, according to various embodiments, at sub-operation 264, the dummy gate structure 600 is replaced by the active gate structure 900. Replacing the dummy gate structure 600 includes first forming an ILD layer 806 over the source / drain feature 802. In some embodiments, the ILD layer 806 comprises substantially the same composition as the ILD layer 117 described herein. The ILD layer 806 can be deposited by any suitable method, such as CVD, PECVD, FCVD, other suitable methods, or combinations thereof. Next, a planarization process, such as a CMP process, can be performed to achieve a flat top surface of the ILD layer 806. CMP can also remove the hard mask 604. After performing the planarization process, the top surface of the ILD layer 806 can be substantially flush with or coplanar with the top surface of the dummy gate structure 600.

[0080] Subsequently, still referring to Figure 21, the dummy gate structure 600, etch stop layer 602, patterned mask 402 (if still present), and first semiconductor layer 304 are sequentially removed from device 300 by one or more suitable etching processes, such as wet etching, dry etching, RIE, chemical oxide removal (COR), other suitable processes, or combinations thereof. After removing the dummy gate structure 600, etch stop layer 602, and patterned mask 402 to form a gate trench, the top surface of each of the fin structures 400 (e.g., the top surface of the topmost semiconductor layer 306) is exposed. In addition to the top surface, the sidewalls of each of the fin structures 400 may also be exposed. Next, the first semiconductor layer 304 is removed from each of the fin structures 400 by applying selective etching (e.g., hydrochloric acid (HCl)) to form an opening, while the second semiconductor layer 306 remains substantially intact. After the first semiconductor layer 304 is removed, the individual bottom and top surfaces of each of the second semiconductor layers 306 can be exposed in the opening.

[0081] Referring again to Figures 14 and 21, according to some embodiments, at sub-operation 266, an active gate structure 900 is formed in an opening between the gate trench and the second semiconductor layer 306. Each of the active gate structures 900 includes substantially the same structure and composition as the active gate structure 16 described herein. In various embodiments, the active gate structure 900 may be formed in the exposed cavity left by the dummy gate structure 600 and the first semiconductor layer 304 (i.e., the gate trench and opening between the second semiconductor layers 306). In some embodiments, each of the active gate structures 900 includes a top portion disposed above the second semiconductor layer 306 and a bottom portion interleaved with or surrounding the second semiconductor layer 306.

[0082] The gate dielectric layer (not depicted separately) of the active gate structure 900 can be deposited using any suitable method, such as thermal oxidation, chemical oxidation, CVD, ALD, PVD, other suitable methods, or combinations thereof. The gate metal may comprise a stack of multiple metallic materials, such as a work function metal and a conductive filler layer, each of which can be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof.

[0083] Subsequently, referring to Figure 14, at sub-operation 268, a subset (e.g., one or more) of the active gate structures 900 can be replaced by a dielectric structure (e.g., dielectric structure 912 in Figures 29A and 29B), wherein the dielectric structure is substantially similar to the dielectric structure 198 described herein. In some embodiments, sub-operation 268 is optional, and all active gate structures 900 remain in device 300. The process for forming dielectric structure 912 is described with reference to Figures 28A, 28B, 29A, and 29B.

[0084] In some embodiments, referring to Figures 28A and 28B, a subset of the active gate structure 900 is first removed by a series of optical lithography and etching processes to form a trench 910. Then, referring to Figures 29A and 29B, the trench is filled with one or more dielectric materials described herein with respect to dielectric structure 198. In some embodiments, the trench 910 extends vertically below the front side 302F and into the substrate 302. A planarization process (e.g., CMP process) may then be performed to planarize the top surfaces of the dielectric structures (multiple) with the top surfaces of the remaining active gate structures 900. As described above, the dielectric structure 912 is used to electrically isolate adjacent front-side devices (e.g., FSMC).

[0085] Referring to Figures 14 and 22, according to some embodiments, various contact features, such as source / drain contacts 902 and gate contacts (not depicted), are formed at sub-operation 270. Source / drain contacts 902 are at least disposed in the ILD layer 806 and are used to electrically couple the corresponding source / drain features 802 to the frontside interconnect structure 1100 (FSL). The structure and composition of each source / drain contact 902 may be substantially the same as the structure and composition of the source / drain contacts 18 described herein.

[0086] The source / drain contact 902 can be formed by first patterning an ILD layer 806 disposed above the source / drain feature 802, forming contact trenches, and depositing one or more conductive materials. A barrier layer (not depicted) can be formed in the trenches before depositing the conductive material. The various layers of the source / drain contact 902 can be formed by PVD, CVD, ALD, plating (e.g., electroplating, electroless plating, etc.), other suitable methods, or combinations thereof. In some embodiments, each of the source / drain contacts 902 further includes a silicon layer disposed above the corresponding source / drain feature 802. A planarization process (e.g., CMP process) can then be performed to planarize the top surface of the source / drain contact 902 with the top surface of the active gate structure 900. Although not depicted, gate contacts may also be formed above the active gate structure 900 to electrically couple the active gate structure 900 to the FSL 1100.

[0087] After performing sub-operation 270 of Figure 14, the manufacturing of FST 1000 at operation 202 of method 200 (see Figure 13) can be completed. Next, method 200 proceeds to operation 204 to form FSL 1100 electrically coupled to FST 1000.

[0088] Referring to Figures 13 and 22, according to various embodiments, FSL 1100 has a structure substantially similar to that of FSL 15 described herein, including a number of conductive features (e.g., vias and metal wires) 1002, 1004, 1010 (Figure 23), 1006, and 1008 embedded in the corresponding IMD layers 1001, 1003, 1005, and 1007. Conductive features 1002 and 1006 can be configured as vias similar to vias V0 and V1, respectively, and conductive features 1004 and 1008 can be configured as metal wires similar to metal wires M0 and M1, respectively. The structure and composition of IMD layers 1001-1007 can be substantially the same as those of IMD layers 120 and 122 described herein, and can be formed by any suitable method, such as CVD, PECVD, or FCVD. It should be noted that conductive features 1002, 1004, 1006, and 1008, as well as IMD layers 1001, 1003, 1005, and 1007, are representative structures of FSL 1100 and are not intended to limit FSL 1100 to any particular configuration.

[0089] The conductive features 1002-1008 of the FSL 1100 (and any conductive features subsequently formed thereon) can be formed by at least some of the following processes. As a representative example, a recess can be formed in one of the IMDs by an etching process, such as dry etching, wet etching, RIE, other suitable etching processes, or combinations thereof. Next, the recess is filled with a conductive material, followed by a CMP process to remove any excess conductive material, thereby planarizing the top surface of the conductive features 1002-1008 with the top surface of the corresponding IMD layer. In some instances, the conductive features 1002-1008 can be formed in the corresponding IMD layers 1001-1007 by a damascene process (e.g., dual damascene process, single damascene process, etc.). The resulting conductive features embedded or encapsulated in their corresponding IMD layers are collectively referred to as the metallization layer in the FSL 1100.

[0090] As described above, the conductive features 1002-1008 of the FSL 1100 are configured to electrically couple the FST 1000 to other front-side and / or rear-side devices (e.g., BSM 1400, BSL 1300, etc.) via the TSV 920. Although conductive features 1002-1008 are shown only as being connected to the source / drain features 802 of each FST 1000, it should be understood that at least one conductive feature in the FSL 1100 may be connected to any active gate structure 900 in the FST 1000, while still within the scope of this disclosure.

[0091] Referring to Figures 13 and 23, according to some embodiments, after forming a portion of the FSL 1100 (e.g., an assembly proximate to substrate 302), at operation 206, at least one FSM 1200 is formed to be electrically coupled to the FSL 1100 in a vertical direction. In this regard, for example, the resulting device 300 may have a structure similar to that shown in Figures 10 and 12. In some embodiments, operation 206 is omitted.

[0092] In some embodiments, the FSM 1200 has substantially the same structure and composition as the FSM 80 described herein. In some embodiments, the FSM 1200 is configured as a capacitor 1020 with a MIM structure, which includes a bottom electrode 1019 (or a first metal layer), a top electrode 1021 (or a second metal layer), and a dielectric layer 1023 (e.g., an insulating layer) between the top electrode and the bottom electrode.

[0093] In some embodiments, the conductive features 1002-1008 in the FSM 1200 and FSL 1100 are formed compatiblely. For example, each of the bottom electrode 1019, dielectric layer 1023, and top electrode 1021 can be formed by patterning the IMD layer 1009 to form a trench (not shown) and sequentially forming the bottom electrode 1019, dielectric layer 1023, and top electrode 1021 in the trench. After the FSM 1200 is formed, an additional portion of the FSL 1100 is formed in the device 300, which may include the conductive feature 1026 in the IMD layer 1025 and vias 1022 and 1024 in the IMD layer 1009. The vias 1022 and 1024 electrically couple the bottom electrode 1019 and the top electrode 1021 to portions of the FSL 1100, respectively.

[0094] Referring to Figures 13 and 24 through 31, at operation 208, a TSV 920 is formed in device 300 to electrically couple FSL 1100 to subsequently formed BSL 1300. In some embodiments, referring commonly to Figures 24, 26, and 27, for example, the formation of TSV 920 at operation 208 may be implemented via sub-operations 272, 274, 276, and 278.

[0095] Referring to Figures 24 and 26, according to some embodiments, substrate 302 is flipped and further processed at sub-operation 272. For example, after forming the top metallization layer of FSL 1100 on the front side 302F of substrate 302, a carrier substrate can be attached to the top metallization layer, and then substrate 302 on which the partially completed device 300 is formed is flipped. According to some embodiments, after flipping substrate 302, a polishing process (e.g., CMP process) is performed on the rear side 302B at sub-operation 274.

[0096] Subsequently, still referring to Figures 24 and 26, according to some embodiments, a trench 918 is formed at sub-operation 276, extending from the rear side 302B through the substrate 302 to expose a portion of the FSL 1100. In the depicted embodiments, the trench 918 exposes the metal line 1010 disposed in the IMD layer 1003. In some instances, the trench 918 may extend through a portion of one of the FST 1000. In some instances, the trench 918 may extend through a portion of the device 300 that has no front side device. The trench 918 may be formed by performing a series of optical lithography and etching processes to pattern the substrate 302. In some embodiments, one or more etching processes (e.g., dry etching, wet etching, RIE, etc.) and / or one or more etchants are used to form the trench 918.

[0097] Referring to Figures 24 and 27, according to some embodiments, a TSV 920 is formed in a trench 918 at sub-operation 278. The TSV 920 can be formed by depositing a conductive filler layer 922 in the trench 918 using processes such as CVD, PVD, ALD, plating (e.g., electroplating, electroless plating, etc.), other suitable methods, or combinations thereof. Subsequently, a planarization process (e.g., CMP process) can be performed on the conductive filler layer to make the top surface of the TSV 920 substantially planar with the back side 302B. In some embodiments, a barrier layer 924 is formed in the trench 918 prior to the deposition of the conductive filler layer 922. The barrier layer 924 can be conformally deposited using processes such as CVD, ALD, other suitable methods, or combinations thereof. The planarization process can also remove portions of the barrier layer 924 adjacent to the conductive filler layer 922.

[0098] Alternatively, referring together to Figures 25, 28A, 28B, 29A, 29B, 30A, and 30B, the formation of TSV 920 at operation 208 can be implemented by, for example, sub-operations 282, 284, 286, and 288. Figures 28B, 29B, and 30B, corresponding to Figures 28A, 29A, and 30A respectively, are top views of the device 300 on the front side 302F, depicting the process of forming and replacing dielectric structure 912 according to some embodiments. Although only one of the dielectric structures 912 is shown to be replaced by TSV 920, any suitable number of dielectric structures 912 can be replaced based on various design requirements.

[0099] In the depicted embodiment, TSV 920 replaces one of the dielectric structures 912 formed at sub-operation 268 described herein, which replaces the active gate structure 900. The fabrication process for forming the dielectric structure 912 has been described above with reference to Figures 28A to 29B. Referring to Figures 28B and 29B, the dielectric structure 912 extends parallel to the longitudinal direction of the active gate structure 900. Furthermore, the dielectric structure 912 is separated from adjacent active gate structures 900 by a pitch P1, which is substantially the same as the gate pitch between two adjacent active gate structures 900.

[0100] At sub-operation 282, referring to Figures 30A and 30B, for example, a trench (not depicted) is formed through one of the dielectric structures 912 to expose the substrate 302 by a series of optical lithography and etching processes. In some embodiments, the trench extends below the front side 302F and partially through (or into) the substrate 302. Subsequently, at sub-operation 284, still referring to Figures 30A and 30B, a TSV 920 is formed in the trench. The various layers in the TSV 920 can be formed in the trench by one or more deposition processes, including, for example, CVD, ALD, PVD, plating, other suitable processes, or combinations thereof. The resulting TSV 920 includes a bottom portion that extends into the substrate 302 and is partially embedded in the substrate 302 between the front side 302F and the rear side 302B. In some embodiments, portions of the dielectric structure 912 may be retained along the sidewalls of the top portion 920a. In some embodiments, sub-operations 282 and 284 are performed concurrently with the formation of FSL 1100 during operation 204.

[0101] Referring to Figures 25 and 31, according to some embodiments, substrate 302 is flipped at sub-operation 286 in a manner similar to sub-operation 272. Subsequently, according to some embodiments, at sub-operation 288, the rear side 302B of substrate 302 is polished to expose the TSV 920 formed at sub-operation 284.

[0102] Referring to Figures 13 and 32, continuing with method 200, according to some embodiments, at operation 210, a BSL 1300 is formed on the rear side 302B of device 300. The structure, composition, and manufacturing method of BSL 1300 may be substantially similar to or the same as FSL 1100. For example, BSL 1300 includes a plurality of representative IMD layers 1101, 1103, 1105, 1107, 1129, 1133, 1135, and 1137, as depicted in Figure 32. BSL 1300 further includes a plurality of representative conductive features embedded in the corresponding IMD layers, such as vias 1102 and 1106 and metal lines 1104, 1108, 1142, and 1150.

[0103] Referring to Figures 13 and 32, according to some embodiments, BST 1600 is formed on the rear side 302B and electrically coupled to BSL 1300 at operation 212. In some embodiments, operation 212 is omitted.

[0104] The structure and composition of BST 1600 may be substantially the same as those of BST 60 described herein. For example, BST 1600 includes a channel layer 1136 having a metal-oxide-semiconductor material. BST 1600 includes a source electrode 1140S and a drain electrode 1140D (collectively referred to as source electrode / drain electrode 1140), each extending vertically from a separate end of the channel layer 1136. In some embodiments, at least one of the source electrode / drain electrode 1140 (e.g., drain electrode 1140D) is electrically coupled to a subsequently formed BSM 1400 (e.g., its top electrode) through a portion of BSL 1300 (e.g., metal line 1142). BST 1600 further includes a gate dielectric layer 1134 covering the channel layer 1136 and a gate electrode 1132 disposed above the gate dielectric layer 1134. In some embodiments, gate electrode 1132 is electrically coupled to a portion of BSL 1300 disposed on BST 1600 (i.e., at a location close to substrate 302) (e.g., metal lines 1108 and 1104 and vias 1102 and 1106), and subsequently coupled to FSL 1100 via TSV 920. BST 1600 may be formed by sequentially depositing and patterning individual materials of the various features described herein.

[0105] Referring again to Figures 13 and 32, according to some embodiments, at operation 214, BSM 1400 is formed on the rear side 302B. The structure and composition of BSM 1400 may be substantially the same as those of BSM 40 described herein. For example, BSM 1400 is configured as a capacitor having a MIM structure formed in IMD layer 1135. BSM 1400 may include a bottom electrode 1141, a top electrode 1143, and a dielectric layer 1145 sandwiched between the bottom electrode 1141 and the top electrode 1143. BSM 1400 may be formed in IMD layer 1135 in a manner similar to that of FSM 1200 described herein.

[0106] If BST 1600 is present, BSM 1400 (e.g., its top electrode 1143) is electrically coupled through via 1146 to one of the source electrode / drain electrode 1140 (e.g., drain electrode 1140D) of BST 1600, such that BSM 1400 and BST 1600 are coupled in series to form a backside memory cell (BSMC) with a 1T1C structure, similar to the BSMC described above with reference to Figures 1 and 7. BSM 1400 (e.g., its bottom electrode 1141) is further electrically coupled through via 1148 to the portion of BSL 1300 below BSM 1400 (e.g., conductive feature 1150 in IMD layer 1137).

[0107] In some embodiments, referring to Figure 33, operation 212 is omitted, such that device 300 does not include any rear-side transistor (e.g., BST 1600). In this regard, BSM 1400 may be electrically coupled to one of FST 1000 through portions of BSL 1300 (e.g., metal lines 1108 and 1104 and vias 1102 and 1106), TSV 920, and portions of FSL 1100 (e.g., metal line 1010 and any vias similar to via 1002 in IMD layer 1001), which is further coupled to one of the source / drain features 802 of FST 1000. Thus, BSM 1400 and FST 1000 are configured as trans-substrate memory cells (TSMCs) with a 1T1C structure, similar to the TSMCs described above with reference to Figures 8 through 10 and 12.

[0108] Therefore, this disclosure provides embodiments in which the memory cells (of the memory portion) of a semiconductor device are formed entirely (in the case of BSMC in Figures 1, 2, and 32) or partially (in the case of TSMC in Figures 8 to 10, 12, and 33) on the back side of a substrate, thereby providing more space for additional memory cells in the memory portion of the semiconductor device to be formed on the front side of the substrate and / or logic devices in the logic portion. As a result, various design rules subject to front-side features (e.g., logic devices and corresponding front-side interconnect structures) can be relaxed, allowing front-side features to continue to scale down without violating design rules.

[0109] In one embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first transistor disposed on a first side of a substrate. The semiconductor device includes a first interconnect structure disposed above the first transistor on the first side. The semiconductor device includes a memory element disposed on a second side of the substrate opposite to the first side, wherein the memory element includes at least a capacitor. The semiconductor device includes a through-hole structure extending through the substrate and electrically coupling the memory element to the first interconnect structure.

[0110] In another embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first transistor disposed on a front side of a substrate. The first transistor includes a first semiconductor layer stacked along a vertical direction. The first transistor includes a first source feature and a first drain feature disposed adjacent to the first semiconductor layer, respectively. The first transistor includes a first gate structure interleaved with the first semiconductor layer. The semiconductor device includes a first interconnect conductive feature disposed above the semiconductor layer on the front side, wherein the first interconnect conductive feature is electrically coupled to the first drain feature. The semiconductor device includes a first capacitor disposed on a rear side of the substrate opposite to the front side. The semiconductor device includes a second interconnect conductive feature that electrically couples the first capacitor to the first interconnect conductive feature along a vertical direction, wherein a portion of the second interconnect conductive feature extends through the substrate.

[0111] In another embodiment of this disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stack of semiconductor layers over a substrate. The method includes forming source / drain features respectively adjacent to the semiconductor layers. The method includes forming respective active gate structures interleaved with the semiconductor layers. The method includes forming a first interconnect structure over a first transistor on a front side, wherein at least one of the source / drain features is electrically coupled to the first interconnect structure. The method includes forming a memory element on a rear side of the substrate opposite to the front side. The method includes forming a via structure electrically coupling the memory element to the first interconnect structure, wherein the via structure extends through the substrate.

[0112] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0113] 10: Front Transistor / FST 11: Internal spacers 13: Nanostructure / Semiconductor Layer / Channel Layer 14S: Source Characteristics 14D: Drainage characteristics 14: Source / Drain Characteristics 15: Front-side interconnect structure / FSL 16: Active gate structure 17: Gate spacer 18: Source / Drain Contacts / Contacts 20: Rear Interconnect Structure / BSL 40: Rear Memory Components / BSM 42: IMD layer 43: IMD layer 44: Bottom Electrode 46: Dielectric layer 48: Top electrode 50: First through hole 52: Second through hole 60: Rear Transistor / BST 61: IMD layer 62: Channel Layer 63: IMD layer 64: Source Electrode / Drain Electrode 64D: Drain electrode 64S: Source electrode 66: Gate dielectric layer 68: Gate electrode 80: Front-side memory element / FSM 82: IMD layer 84: Bottom Electrode 86: Dielectric layer 88: Top Electrode 90: First through hole 92: Second through hole 100A, 100B, 100C, 100D, 100E, 100F: Semiconductor devices / assemblies 102:Substrate 102B: Rear side 102F: Front 108: Isolation Structure 117: ILD layer 120: IMD layer 122: IMD layer 140: IMD layer 144: IMD layer 148: IMD layer 152: IMD layer 156: IMD layer 190:TSV 192: Conductive filling layer 194: Barrier Layer 196: Virtual gate structure 198: Dielectric Structure 200: Method 202, 204, 206, 208, 210, 212, 214, 216: Operations 252, 254, 256, 258, 260, 262, 264, 266, 268, 270, 272, 274, 276, 278, 280, 282, 284, 286, 288: sub-operations 300: Semiconductor device / apparatus 302:Substrate 302B: Rear side 302F: Front 304: First semiconductor layer / semiconductor layer 306: Second semiconductor layer / semiconductor layer 400: Fin structure 400A: Fin structure 400B: Fin structure 400C: Fin structure 402: Patterned mask 410: Trench 504: Isolation Structure / Structure 505: Top surface 600: Virtual gate structure 602: Etching stop layer 604: Hard Mask 702: Gate spacer 704: Internal spacers 706: Source / Drain Groove 802: Source / Drain Characteristics 806: Interlayer Dielectric / ILD Layer 900: Active gate structure 902: Source / Drain Contact 910: Trench 912: Dielectric Structure 918: Trench 920:TSV 920a: Top section 922: Conductive filler layer 924: Barrier Layer 1000:FST / Front-side transistor 1001: IMD layer 1002: Conductivity characteristics 1003: IMD layer 1004: Electrical conductivity characteristics 1005: IMD layer 1006: Electrical conductivity characteristics 1007: IMD layer 1008: Conductivity Characteristics 1009: IMD layer 1010: Conductive characteristics / metallic wire 1019: Bottom Electrode 1020: Capacitor 1021: Top Electrode 1022: Through hole 1023: Dielectric layer 1024: Through hole 1025: IMD layer 1026: Electrical conductivity characteristics 1100: Front-side interconnect structure / FSL 1101: IMD layer 1102: Through hole 1103: IMD layer 1104: Metal wire 1105: IMD layer 1106: Through hole 1107: IMD layer 1108: Metal Wire 1129: IMD layer 1132: Gate electrode 1133: IMD layer 1134: Gate dielectric layer 1135: IMD layer 1136: Channel Layer 1137: IMD layer 1140: Source electrode / Drain electrode 1140D: Drain electrode 1140S: Source Electrode 1141: Bottom Electrode 1142: Metal wire 1143: Top Electrode 1145: Dielectric layer 1146: Through hole 1148: Conductive characteristics / via 1150: Metal wire 1200:FSM 1300:BSL 1400:BSM 1600:BST AA': line BM0, BM1, BMX, BMX-1: Metallic wire BV0: Through hole BV1: Through hole BVX: Through Hole BSMC1, BSMC2, BSMC3: Rear memory cells BVX+1, BMX+1, BVX+2, BMX+2, VX-1, MX-1, VX, MX, BV0, BM0, BV1, BM1: Conductivity characteristics M0: Metal wire / conductive feature M1: Metal wire / conductive feature P1: Pitch S: Source D: Jiji TSMC, TSMC1, TSMC2: Cross-substrate memory cells V0: Through-hole / Conductive feature V1: Through-hole / Conductive feature

[0114] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a first transistor disposed on a first side of a substrate; a plurality of first interconnect structures disposed above the first transistor on the first side; a first memory element disposed on a second side of the substrate opposite to the first side, the first memory element including at least a capacitor; a via structure extending through the substrate and electrically coupling the memory element to the first interconnect structures; a second transistor disposed on the first side adjacent to the first transistor; a plurality of third interconnect structures disposed above the second transistor on the first side; and a second memory element disposed above the second transistor on the first side, the third interconnect structures electrically coupling a drain feature of the second transistor to the second memory element.

2. The semiconductor device as claimed in claim 1, wherein the capacitor includes a dielectric layer sandwiched between a bottom electrode and a top electrode.

3. The semiconductor device as claimed in claim 1, wherein the memory element further includes a second transistor connected in series with the capacitor.

4. The semiconductor device as claimed in claim 1, wherein the first transistor comprises: a plurality of nanostructures, a source structure and a drain structure laterally coupled to one end of each of the nanostructures, the drain structure being electrically coupled to the first interconnect structures, and a gate structure surrounding each of the nanostructures.

5. The semiconductor device as claimed in claim 1, wherein the first transistor comprises: a plurality of nanostructures, a source structure and a drain structure laterally coupled to one end of each of the nanostructures, the drain structure being electrically coupled to the first interconnect structures, and a gate structure surrounding each of the nanostructures.

6. A semiconductor device comprising: a first transistor disposed on a front side of a substrate, the first transistor comprising: A plurality of first semiconductor layers are stacked along a vertical direction; a first source feature and a first drain feature are disposed adjacent to the first semiconductor layers, respectively; and a first gate structure is interleaved with the first semiconductor layers; a first interconnect conductive feature is disposed above the first semiconductor layers on the front side and electrically coupled to the first drain feature; a first capacitor is disposed on a rear side of the substrate opposite to the front side; and a second interconnect conductive feature is electrically coupled to the first capacitor along the vertical direction and a portion of the second interconnect conductive feature extends through the substrate. A second transistor includes: a plurality of second semiconductor layers disposed on the front side and stacked along the vertical direction; a second drain feature disposed adjacent to the second semiconductor layers; and a second gate structure interleaved with the second semiconductor layers, wherein the first source feature is a common source feature shared by the first transistor and the second transistor; a third interconnect structure disposed on the front side and electrically coupled to the second drain feature; and a second capacitor disposed on the front side and electrically coupled to the third interconnect structure.

7. The semiconductor device as claimed in claim 6, wherein in a top view of the front side, the second interconnect conductive feature extends parallel to the first gate structure and the second gate structure, and wherein a first pitch between the second interconnect conductive feature and the first gate structure is the same as a second pitch between the first gate structure and the second gate structure.

8. The semiconductor device as claimed in claim 6, wherein the first capacitor configuration is a component of a dynamic random access memory cell, a magnetoresistive random access memory cell, a resistive random access memory cell, or a ferroelectric random access memory cell.

9. A method of manufacturing a semiconductor device, the method comprising the steps of: forming a stack of a plurality of semiconductor layers on a front side of a substrate; forming a plurality of source / drain features respectively adjacent to the semiconductor layers; forming a plurality of active gate structures, each active gate structure interleaved with the semiconductor layers and interposed between the source / drain features to form a first transistor; forming a plurality of first interconnect structures above the first transistor on the front side, at least one of the source / drain features being electrically coupled to the first interconnect structures; forming a memory element on a rear side of the substrate opposite to the front side; and forming a via structure electrically coupling the memory element to the first interconnect structures, the via structure extending through the substrate.

10. The method as described in claim 9, further comprising the step of: forming a plurality of second interconnect structures on the rear side, the second interconnect structures electrically coupling the via structure to the memory element.

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