Device structure and methods for forming the same

Abstract

A device structure can be manufactured by the following steps: forming a metal interconnect structure embedded in a dielectric material layer above a substrate; forming an active metal connection structure, a main dummy metal structure, and a micro dummy metal structure above a topmost dielectric material layer, the topmost dielectric material layer being selected from the dielectric material layers, wherein the height of the micro dummy metal structures is less than the height of the active metal connection structure and the main dummy metal structure; and forming solder pads above the active metal connection structure, the main dummy metal structure, and the micro dummy metal structure, wherein the active metal connection structure and the main dummy metal structure are in contact by the solder pads, and the micro dummy metal structures are not in contact with any solder pads.

Description

Technical Field

[0001] none Prior Technology

[0002] In semiconductor manufacturing, integrating advanced interconnect structures presents significant challenges, particularly in managing stress and preventing defects during the manufacturing process. Copper structures can develop internal stresses during thermal processing, which can often lead to dielectric material cracking and film peeling. Variations in the physical properties of copper structures further complicate stress-related issues, resulting in surface inhomogeneities. Inhomogeneous surfaces can cause difficulties in subsequent processing steps, leading to over-etching and / or exposing copper to plasma, resulting in arcing defects. Problems related to stress and inhomogeneity can degrade the reliability and yield of semiconductor devices, highlighting the need for more effective stress management methods in semiconductor manufacturing processes. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various features disclosed herein can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device and a metal interconnect structure formed in a dielectric material layer, according to an embodiment of the present disclosure. Figures 2A to 2G are sequential vertical cross-sectional views of regions of exemplary structures during the formation of the active metal connection structure, the main dummy metal structure, and the micro dummy metal structure according to the first embodiment of this disclosure. Figure 2H is a top view of the region of an exemplary structure after the formation of the active metal connection structure, the main virtual metal structure, and the micro virtual metal structure according to an embodiment of the present disclosure. Figures 3A to 3G are sequential vertical cross-sectional views of regions of exemplary structures during the formation of the active metal connection structure, the main dummy metal structure, and the micro dummy metal structure according to the second embodiment of this disclosure. Figures 4A to 4F are sequential vertical cross-sectional views of regions of exemplary structures during the planarization of the active metal connection structure, the main dummy metal structure, the micro dummy metal structure, and the formation of the pads, according to embodiments of the present disclosure. Figure 5 is a vertical cross-sectional view of an exemplary structure after the solder pads have been formed. Figure 6A is a vertical cross-sectional view of a region of the reconstituted wafer surrounding a first semiconductor die according to an embodiment of the present disclosure. Figure 6B is a top view of the fabricated reconstituted wafer. Figure 7 is a vertical cross-sectional view of a region of the reconstituted wafer after the formation of the first molding compound matrix, according to an embodiment of the present disclosure. Figure 8 is a vertical cross-sectional view of the region of the reconstituted wafer after the formation of the first bonding level dielectric layer and the first active pad, according to an embodiment of the present disclosure. Figure 9 is a vertical cross-sectional view of a region of the reconstituted wafer after the second semiconductor die is attached to each of the first semiconductor dies, according to an embodiment of the present disclosure. Figure 10A is a vertical cross-sectional view of the region of the reconstituted wafer after the formation of the second molding compound matrix, according to an embodiment of the present disclosure. Figure 10B is a top view of the region of the reconstituted wafer in Figure 10A. Figure 11 is a first flowchart illustrating the steps of forming the device structure according to an embodiment of the present disclosure. Figure 12 is a second flowchart illustrating the steps of forming the device structure according to an embodiment of the present disclosure. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and not limiting. The drawings are not drawn to scale. Elements with the same element symbol refer to the same element and are assumed to have the same material composition and the same thickness range unless explicitly stated otherwise. Unless explicitly disclosed otherwise, it is assumed that all features of the original embodiment exist in any derivative embodiment. Therefore, features described with reference to the relevant embodiments in the drawings and / or specification support the features in the embodiments. Unless explicitly stated otherwise, embodiments in which multiple instances of any said element are repeated are explicitly contemplated. Embodiments in which non-essential elements are omitted are explicitly contemplated, even if such embodiments are not explicitly disclosed but are known in the art.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another, as shown in the accompanying drawings. In addition to the orientations shown in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Unless otherwise expressly stated, it is assumed that each element having the same element symbol has the same material composition and a thickness within the same thickness range.

[0007] According to the present disclosure, a device structure can be manufactured in a manner that addresses the challenges of stress management and defect prevention during the fabrication of copper-containing structures. The process first forms a metal interconnect structure within a dielectric material layer above a substrate. Subsequently, an active metal interconnect structure, a main dummy metal structure, and a micro dummy metal structure can be formed above the topmost dielectric material layer. The height of the micro dummy metal structure is designed to be smaller than that of the active metal interconnect structure and the main dummy metal structure, allowing it to be specifically formed in narrow areas that are too small to accommodate the main dummy metal structure. Various embodiments are designed to promote a more uniform distribution of copper on the semiconductor surface. Therefore, internal stress generated during heat treatment can be reduced, and problems such as dielectric material cracking and peeling can be mitigated.

[0008] A metal structure can be formed by depositing a continuous metal seed layer on a dielectric material layer and then applying a patterned electroplated mask layer. The metal material can be electroplated onto the physically exposed surface of the continuous metal seed layer. After removing the patterned electroplated mask layer and the unmasked portion of the continuous metal seed layer, the remaining portion of the seed layer and the electroplated material constitute an active metal interconnect structure, a main dummy metal structure, and a micro dummy metal structure. The micro dummy metal structure can be electrically isolated from the metal interconnect structure, pads, active metal interconnect structure, and main dummy metal structure, thereby contributing to stress management and reliability of semiconductor devices.

[0009] According to the present disclosure, a device structure with a reduced stress level is provided, including a metal interconnect structure formed within a dielectric material layer. An active metal interconnect structure, a main dummy metal structure, and a micro dummy metal structure may be provided above the dielectric material layer. The micro dummy metal structure is formed in an area too narrow for the main dummy metal structure, contributing to uniform copper distribution and thus helping to reduce stress. Pads may be located above the active metal interconnect structure and the main dummy metal structure, thereby contacting these components, while the micro dummy metal structure remains in contact with the pads, thus ensuring isolation and supporting device reliability.

[0010] According to another embodiment of this disclosure, solder pads can be formed over a metal structure. These solder pads can contact the active metal interconnect structure and the main dummy metal structure, but not the micro-dummy metal structure. This selective contact maintains the structural integrity and reliability of the semiconductor device. Furthermore, the method outlines the formation of an interconnect-level dielectric layer and a bonding-level dielectric layer over the metal structure. The interconnect-level dielectric layer can be planarized to ensure uniformity, and solder pad cavities can be formed via the bonding-level dielectric layer to expose the top surfaces of the active metal interconnect structure and the main dummy metal structure, thereby achieving solder pad formation.

[0011] Embodiments of this disclosure provide a device structure that manages internal stress and mitigates defects such as cracking, spalling, and arcing. Including micro-dummy metal structures in narrow regions where a main dummy metal structure may not be possible is part of this method. By enhancing the uniformity of copper distribution, these micro-dummy metal structures can reduce stress, thereby improving the yield and reliability of semiconductor devices, particularly in applications requiring high-density interconnects and precise stress management in semiconductor manufacturing processes. Various aspects of this disclosure are now described with reference to the accompanying drawings.

[0012] Referring to Figure 1, an exemplary structure is illustrated, including a semiconductor device 320 formed on a semiconductor substrate 309, and a metal interconnect structure 340 formed within a dielectric material layer 330 and covering the semiconductor device 320. The semiconductor device 320 may include field-effect transistors, junction transistors, resistors, capacitors, inductors, diodes, and / or other semiconductor devices known in the art. In one embodiment, the semiconductor device 320 may include a complementary metal-oxide-semiconductor (CMOS) device known in the art. Various semiconductor devices 320 may be electrically isolated from each other by a shallow trench isolation structure 312.

[0013] The dielectric layer 330 may comprise and / or consist of inorganic dielectric materials, such as silicate glass, silicon nitride, silicon carbonitride, silicon oxynitride, and / or dielectric metal oxide materials. The metal interconnect structure 340 may comprise metal wire structures, metal via structures, and / or metal pads. A subset of the metal interconnect structures 340 may serve as a continuous wall structure laterally surrounding the semiconductor device 320 and the remaining metal interconnect structures 340, and may form an edge sealing ring structure 344. In one embodiment, via-level metal interconnect structures and wire-level metal interconnect structures may alternate vertically in a vertical direction. The total number of metal wires within the metal interconnect structure 340 may range from 1 to 20, such as 2 to 10. In one embodiment, the topmost dielectric layer 33T selected from the dielectric layer 330 may comprise a via-level dielectric layer.

[0014] Figures 2A to 2G are sequential vertical cross-sectional views of regions of exemplary structures during the formation of the active metal connection structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366 according to the first embodiment of this disclosure.

[0015] Referring to Figure 2A, the upper region of the exemplary structure of Figure 1 is illustrated in an enlarged view. This upper region includes a metal interconnect structure 340 formed in the topmost dielectric material layer 33T.

[0016] Referring to Figure 2B, a photoresist layer (not shown) can be applied over the top dielectric material layer 33T, and this photoresist layer can be photolithographically patterned to form an opening in a region above a corresponding subset of the metal interconnect structures 340 located within or below the top dielectric material layer 33T. An anisotropic etching process can be performed to form a via cavity 331 through the top dielectric material layer 33T. The top surface of the subset of metal interconnect structures 340 can be exposed below the via cavity 331. The photoresist layer can then be removed, for example, by ashing.

[0017] Referring to Figure 2C, the continuous metal seed layer 368C can be directly deposited on the physically exposed surface of the top dielectric material layer 33T, and directly deposited on the physically exposed top surface segment of a subset of the metal interconnect structure 340. The continuous metal seed layer 368C serves as a conductive substrate, facilitating subsequent copper plating by providing a uniform conductive surface on which copper can be plated. The continuous metal seed layer 368C can be deposited by physical vapor deposition (PVD), which can provide high consistency and thickness uniformity across the different morphologies of the top dielectric material layer 33T and the metal interconnect structure 340. In one embodiment, the continuous metal seed layer 368C may comprise a layer stack including a metal barrier material layer (such as tantalum or tantalum nitride (Ta / TaN)) and an overlying copper layer. The continuous metal seed layer 368C includes a horizontally extending portion and a vertically extending portion. The horizontally extending portion covers the horizontal top surface of the top dielectric material layer 33T, and the vertically extending portion protrudes downward from the horizontally extending portion to the peripheral region of the corresponding via cavity 331. The thickness of the continuous metal seed layer 368C can be in the range of 30 nm to 200 nm, but smaller or larger thicknesses can also be used.

[0018] Referring to Figure 2D, a patterned electroplated mask layer 357 can be formed over a continuous metal seed layer 368C. In one embodiment, the patterned electroplated mask layer 357 can be formed by applying a photoresist layer over the continuous metal seed layer 368C and by photolithography patterning the photoresist layer to form discrete openings therein. The discrete openings in the photoresist layer may include: a first type of opening 361 having regional overlap within a corresponding via cavity 331; a second type of opening 363 having no regional overlap with the via cavity 331 and having a corresponding region larger than any of the first type of opening regions; and a third type of opening 365 having no regional overlap with the via cavity 331 and having a corresponding region smaller than any of the first type of opening 361 regions.

[0019] According to the present disclosure, a first type of opening 361 in the patterned electroplated mask layer 357 may be formed in a region where a first set of pads electrically connected to the metal interconnect structure 340 will subsequently be formed. A second type of opening 363 in the patterned electroplated mask layer 357 may be formed in a region where a second set of pads not electrically connected to the metal interconnect structure 340 will subsequently be formed. Typically, the second type of opening 363 may fill a gap region selected from the first type of opening 361, provided that the second type of opening 363 fits the gap region. A third type of opening 365 in the patterned electroplated mask layer 357 may be formed in the gap selected from the first type of opening 361 and the second type of opening 363, provided that there is sufficient area available for forming the third type of opening 365.

[0020] In illustrative examples, first type openings 361 may have their respective first shapes, which may be rectangular or rounded rectangles. In a plan view (e.g., a top view), the opposite sidewalls of each first shape may be laterally spaced from each other by their respective first lateral dimensions. Each first lateral dimension may be in the range of 5 micrometers to 60 micrometers, although smaller or larger first lateral dimensions may also be used. Second type openings 363 may have their respective second shapes, which may be rectangular or rounded rectangles. In a plan view (e.g., a top view), the opposite sidewalls of each second shape may be laterally spaced from each other by their respective second lateral dimensions. Each second lateral dimension may be in the range of 10 micrometers to 120 micrometers, although smaller or larger second lateral dimensions may also be used. Third type openings 365 may have their respective third shapes, which may be rectangular or rounded rectangles. In a plan view (e.g., a top view), the opposite sidewalls of each third shape may be laterally spaced from each other by their respective third lateral dimensions. Each third lateral dimension may be in the range of 0.3 micrometers to 30 micrometers, for example, 1 micrometer to 10 micrometers, although smaller or larger third lateral dimensions may also be used.

[0021] Typically, the lateral dimension of each opening in the patterned electroplated mask layer 357 can be defined as the maximum lateral spacing between relatively parallel sidewall segments in a plan view (e.g., a top view). When the opening shape in the plan view is rectangular or rounded, the lateral dimension of the shape is equal to the larger of the two lateral spacings between the opposite sidewall segments of the opening in the plan view. When the opening shape in the plan view is circular or elliptical, the lateral dimension of the shape is equal to the diameter or major axis of the opening in the plan view. The lateral dimension of the second type opening 363 can be in the range of 120% to 1000% of the average lateral dimension of the first type opening 361, such as 200% to 500%. The lateral dimension of the third type opening 365 can be in the range of 1% to 90% of the average lateral dimension of the first type opening 361, such as 3% to 50%.

[0022] Referring to Figure 2E, an electroplating process can be performed to electroplat a metallic material, which can be any electroplatable material known in the art. In one embodiment, the electroplated metallic material may be substantially composed of copper. The electroplated metallic material forms electroplated material portions (362M, 364M, 366M). The electroplated material portions (362M, 364M, 366M) are formed in the unmasked areas of the patterned electroplating mask layer 357. The electroplated material portions (362M, 364M, 366M) may contain any electroplatable metal. In one embodiment, the electroplated material portions (362M, 364M, 366M) may be substantially composed of copper.

[0023] The electroplating material portions (362M, 364M, 366M) may include a first type electroplating material portion 362M, a second type electroplating material portion 364M with a height greater than the first type electroplating material portion 362M, and a third type electroplating material portion 366M with a height less than the first type electroplating material portion 362M. The first type electroplating material portion 362M fills the lower portion of the first type opening 361. The second type electroplating material portion 364M fills the lower portion of the second type opening 363. The third type electroplating material portion 366M fills the lower portion of the third type opening 365. The first type electroplating material portion 362M, the second type electroplating material portion 364M, and the third type electroplating material portion 366M are formed simultaneously in a single electroplating process.

[0024] The first height of the top surface of the first type electroplated material portion 362M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 150 nm to 6000 nm, such as 300 nm to 3000 nm, although a smaller or larger first height may also be used. The second height of the top surface of the second type electroplated material portion 364M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 105% to 200% of the first height, such as 110% to 150%, although a smaller or larger second height may also be used. The third height of the top surface of the third type electroplated material portion 366M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 10% to 90% of the first height, such as 30% to 80%, although a smaller or larger third height may also be used.

[0025] Referring to Figure 2F, the patterned electroplated mask layer 357 can be removed by ashing or dissolving in a solvent.

[0026] Referring to Figures 2G and 2H, the unmasked portions of the continuous metal seed layer 368C can be removed by performing an etching process that selectively etches the material of the continuous metal seed layer 368C to etch the material of the topmost dielectric material layer 33T. In cases where the continuous metal seed layer 368C comprises a stack of metal barrier pads composed of TiN or TaN and a copper seed layer, the unmasked portions of the copper seed layer and the metal barrier pad layer can be removed by performing a two-step etching process. First, an isotropic wet etching process using a persulfate-based solution (such as ammonium persulfate) can be used to selectively remove the copper seed layer without etching the material of the metal barrier pad layer. Subsequently, a selective dry etching process using fluorine-based chemicals (such as CxFy or SxFy), such as reactive ion etching (RIE), can be performed to remove the unmasked portions of the metal barrier pad layer. A suitable cleaning process can then be performed to remove any residual material.

[0027] The remaining portion of the continuous metal seed layer 368C includes: a first type metal seed layer 362B, located below the first type electroplated material portion 362M; a second type metal seed layer 364B, located below the second type electroplated material portion 364M; and a third type metal seed layer 366B, located below the third type electroplated material portion 366M. Typically, the remaining portion of the continuous metal seed layer 368C and the electroplated material portions (362M, 364M, 366M) include an active metal connection structure 362, a main dummy metal structure 364, and a micro dummy metal structure 366. Each active metal connection structure 362 includes a stack of the first type metal seed layer 362B and the first type electroplated material portion 362M. Each main dummy metal structure 364 includes a stack of the second type metal seed layer 364B and the second type electroplated material portion 364M. Each micro-virtual metal structure 366 comprises a stack of a third type of metal seed layer 366B and a third type of electroplating material portion 366M.

[0028] Therefore, the active metal interconnect structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366 can be formed above the topmost dielectric material layer 33T selected from the dielectric material layer 330. According to the present disclosure, the height of the micro dummy metal structure 366 is smaller than the height of the active metal interconnect structure 362 and the main dummy metal structure 364. The first type of electroplated material portion 362M can be an active electroplated material portion electrically connected to a corresponding one of the metal interconnect structures 340. The second type of electroplated material portion 364M can be a first dummy electroplated material portion electrically isolated from the metal interconnect structure 340 and having a top surface formed above a horizontal plane, which includes the top surface of the active electroplated material portion (i.e., the first type of electroplated material portion 362M). The third type of electroplated material portion 366M includes a second dummy electroplated material portion electrically isolated from the metal interconnect structure 340 and having a top surface formed below the horizontal plane.

[0029] In one embodiment, each active metal connection 362 contacts a corresponding metal interconnect 340 selected from a subset of metal interconnect structures 340. In one embodiment, the primary dummy metal structure 364 and the micro dummy metal structure 366 do not contact any metal interconnect structure 340. Each of the primary dummy metal structure 364 and the micro dummy metal structure 366 is electrically isolated from the metal interconnect structure 340. In one embodiment, each primary dummy metal structure 364 is electrically isolated from the active metal connection 362, the micro dummy metal structure 366, and any other primary dummy metal structure 364. In one embodiment, each micro dummy metal structure 366 is electrically isolated from the active metal connection 362, the primary dummy metal structure 364, and any other micro dummy metal structure 366.

[0030] The height of the miniature dummy metal structure 366 is less than the height of the active metal connection structure 362 and the main dummy metal structure 364. The height of the main dummy metal structure 364 is greater than the height of the active metal connection structure 362 and the miniature dummy metal structure 366. Each of the main dummy metal structure 364 and the miniature dummy metal structure 366 is completely formed in the region without the through-hole cavity 331.

[0031] Each active metal interconnect 362 includes a respective via portion extending vertically through the topmost dielectric layer 33T and contacting its respective metal interconnect 340. In one embodiment, each of the main dummy metal structure 364 and the micro dummy metal structure 366 is formed entirely above a horizontal plane including the top surface of the topmost dielectric layer 33T. In one embodiment, each of the active metal interconnect 362, the main dummy metal structure 364, and the micro dummy metal structure 366 includes a respective bottom surface located within the horizontal plane including the top surface of the topmost dielectric layer 33T. In one embodiment, each active metal interconnect 362 contacts its respective metal interconnect 340, while the main dummy metal structure 364 and the micro dummy metal structure 366 do not contact any metal interconnect 340.

[0032] Figures 3A to 3G are sequential vertical cross-sectional views of regions of exemplary structures during the formation of the active metal connection structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366, according to the second embodiment of this disclosure.

[0033] Referring to Figure 3A, an exemplary structure is illustrated after the formation of the first patterned electroplated mask layer 353. The exemplary structure illustrated in Figure 3A can be derived from the exemplary structure illustrated in Figure 2C by forming the first patterned electroplated mask layer 353. The opening pattern in the first patterned electroplated mask layer 353 can be the same as the pattern of the third type of opening 365 in the patterned electroplated mask layer 357 described with reference to Figure 2D. Therefore, the first patterned electroplated mask layer 353 does not include the pattern of the first type of opening 361 or the pattern of the second type of opening 363 present in the patterned electroplated mask layer 357 described with reference to Figure 2D.

[0034] Referring to Figure 3B, a first electroplating process can be performed to electroplat a first metallic material, which can be any electroplatable material known in the art. In one embodiment, the first electroplated metallic material may consist primarily of copper. Alternatively, the first electroplated metallic material may comprise non-copper electroplatable materials such as nickel, silver, gold, zinc, cobalt-tungsten (CoW), or cobalt-tungsten-phosphorus (CoWP). In one embodiment, the first metallic material may be selected to provide varying degrees of deformation sensitivity relative to copper for use in the subsequently formed active metallic connection structure. Copper has a relatively low yield strength, typically about 70-100 MPa, indicating a moderate degree of deformation sensitivity under stress. In comparison, the yield strengths of nickel, silver, gold, zinc, CoW, and CoWP are approximately 150-300 MPa, 50-150 MPa, 200-250 MPa, 50-100 MPa, 400-600 MPa, and 400-600 MPa, respectively, indicating different resistance to deformation. The first electroplating material forms the electroplating material portion, referred to herein as the third type electroplating material portion 366M. Measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C, the height of the top surface of the third type electroplating material portion 366M can range from 50 nm to 3000 nm, such as 100 nm to 1500 nm, but smaller or larger heights are also possible.

[0035] Referring to Figure 3C, the first patterned electroplated mask layer 353 can be removed by ashing or dissolving in a solvent.

[0036] Referring to Figure 3D, a second patterned electroplating mask layer 355 can be formed over the continuous metal seed layer 368C and the third type of electroplated material portion 366M. The pattern of the openings in the second patterned electroplating mask layer 355 can be the same as the patterns of the first type of openings 361 and the second type of openings 363 in the patterned electroplating mask layer 357 described with reference to Figure 2D. Therefore, by omitting the pattern of the third type of opening 365, the pattern of the openings in the second patterned electroplating mask layer 355 can be derived from the pattern of the openings in the patterned electroplating mask layer 357 described with reference to Figure 2D. Each third type of electroplated material portion 366M can be covered by the second patterned electroplating mask layer 355.

[0037] Referring to Figure 3E, a second electroplating process can be performed to electroplat a second metallic material. In one embodiment, the second electroplated metallic material may be primarily composed of copper. A first-type electroplated material portion 362M is formed in a first-type opening, and a second-type electroplated material portion 364M is formed in a second-type opening. Therefore, a plurality of electroplating processes are used to form the first-type electroplated material portion 362M, the second-type electroplated material portion 364M, and the third-type electroplated material portion 366M.

[0038] The first height of the top surface of the first type electroplated material portion 362M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 150 nm to 6000 nm, such as 300 nm to 3000 nm, although a smaller or larger first height may also be used. The second height of the top surface of the second type electroplated material portion 364M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 105% to 200% of the first height, such as 110% to 150%, although a smaller or larger second height may also be used. The third height of the top surface of the third type electroplated material portion 366M (measured from a horizontal plane including the topmost surface of the continuous metal seed layer 368C) can be in the range of 10% to 90% of the first height, for example 30% to 80%, but a smaller or larger third height may also be used.

[0039] Referring to Figure 3F, the second patterned electroplated mask layer 355 can be removed by ashing or dissolving in a solvent.

[0040] Referring to Figure 3G, the unmasked portions of the continuous metal seed layer 368C can be removed by performing an etching process that selectively etches the material of the continuous metal seed layer 368C to etch the material of the topmost dielectric material layer 33T. If the continuous metal seed layer 368C comprises a stack of a metal barrier pad layer composed of TiN or TaN and a copper seed layer, the unmasked portions of the copper seed layer and the metal barrier pad layer can be removed by performing a two-step etching process. First, an isotropic wet etching process using a persulfate-based solution (such as ammonium persulfate) can be used to selectively remove the copper seed layer without etching the material of the metal barrier pad layer. Subsequently, a selective dry etching process using fluorine-based chemicals (such as CxFy or SxFy), such as reactive ion etching (RIE), can be performed to remove the unmasked portions of the metal barrier pad layer. A suitable cleaning process can then be performed to remove any residual material.

[0041] The remaining portion of the continuous metal seed layer 368C includes: a first type metal seed layer 362B, located below the first type electroplated material portion 362M; a second type metal seed layer 364B, located below the second type electroplated material portion 364M; and a third type metal seed layer 366B, located below the third type electroplated material portion 366M. Typically, the remaining portion of the continuous metal seed layer 368C and the electroplated material portions (362M, 364M, 366M) include an active metal connection structure 362, a main dummy metal structure 364, and a micro dummy metal structure 366. Each active metal connection structure 362 includes a stack of the first type metal seed layer 362B and the first type electroplated material portion 362M. Each main dummy metal structure 364 includes a stack of the second type metal seed layer 364B and the second type electroplated material portion 364M. Each micro-virtual metal structure 366 comprises a stack of a third type of metal seed layer 366B and a third type of electroplating material portion 366M.

[0042] Therefore, the active metal interconnect structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366 can be formed above the topmost dielectric material layer 33T selected from the dielectric material layer 330. According to the present disclosure, the height of the micro dummy metal structure 366 is smaller than the height of the active metal interconnect structure 362 and the main dummy metal structure 364. The first type of electroplated material portion 362M can be an active electroplated material portion electrically connected to a corresponding one of the metal interconnect structures 340. The second type of electroplated material portion 364M can be a first dummy electroplated material portion electrically isolated from the metal interconnect structure 340 and having a top surface formed above a horizontal plane, which includes the top surface of the active electroplated material portion (i.e., the first type of electroplated material portion 362M). The third type of electroplated material portion 366M includes a second dummy electroplated material portion electrically isolated from the metal interconnect structure 340 and having a top surface formed below the horizontal plane.

[0043] In one embodiment, each active metal connection 362 contacts a corresponding metal interconnect 340 selected from a subset of metal interconnect structures 340. In one embodiment, the primary dummy metal structure 364 and the micro dummy metal structure 366 do not contact any metal interconnect structure 340. Each of the primary dummy metal structure 364 and the micro dummy metal structure 366 is electrically isolated from the metal interconnect structure 340. In one embodiment, each primary dummy metal structure 364 is electrically isolated from the active metal connection 362, the micro dummy metal structure 366, and any other primary dummy metal structure 364. In one embodiment, each micro dummy metal structure 366 is electrically isolated from the active metal connection 362, the primary dummy metal structure 364, and any other micro dummy metal structure 366.

[0044] The height of the miniature dummy metal structure 366 is less than the height of the active metal connection structure 362 and the main dummy metal structure 364. The height of the main dummy metal structure 364 is greater than the height of the active metal connection structure 362 and the miniature dummy metal structure 366. Each of the main dummy metal structure 364 and the miniature dummy metal structure 366 is completely formed in the region without the through-hole cavity 331.

[0045] Each active metal interconnect 362 includes a respective via portion extending vertically through the topmost dielectric layer 33T and contacting its respective metal interconnect 340. In one embodiment, each of the main dummy metal structure 364 and the micro dummy metal structure 366 is formed entirely above a horizontal plane including the top surface of the topmost dielectric layer 33T. In one embodiment, each of the active metal interconnect 362, the main dummy metal structure 364, and the micro dummy metal structure 366 includes a respective bottom surface located within the horizontal plane including the top surface of the topmost dielectric layer 33T. In one embodiment, each active metal interconnect 362 contacts its respective metal interconnect 340, while the main dummy metal structure 364 and the micro dummy metal structure 366 do not contact any metal interconnect 340.

[0046] Figures 4A to 4F are sequential vertical cross-sectional views of regions of exemplary structures during the planarization of the active metal connection structure 362, the main dummy metal structure 364, the micro dummy metal structure 366, and the formation of the pad 388, according to embodiments of the present disclosure.

[0047] Referring to Figure 4A, a connection-level dielectric layer 350 may be formed over the active metal connection structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366. In one embodiment, the connection-level dielectric layer 350 may include at least one connection-level passivation dielectric layer (351, 352) and a connection-level planarization dielectric layer 356. The at least one connection-level passivation dielectric layer (351, 352) may include a stack of a first connection-level passivation dielectric layer 351 and a second connection-level passivation dielectric layer 352. In an illustrative example, the first connection-level passivation dielectric layer 351 may include a silicon nitride layer with a thickness in the range of 10 nm to 200 nm, and the second connection-level passivation dielectric layer 352 may include a silicon carbide nitride layer with a thickness in the range of 10 nm to 200 nm, although each of the first connection-level passivation dielectric layer 351 and the second connection-level passivation dielectric layer 352 may also use a smaller or larger thickness. The interconnect-level planarization dielectric layer 356 comprises a planarizable dielectric material, such as silicate glass. The thickness of the portion of the interconnect-level planarization dielectric layer 356 covering the main dummy metal structure 364 can be in the range of 300 nm to 6,000 nm, such as 600 nm to 3,000 nm, although smaller or larger thicknesses can also be used.

[0048] Referring to Figure 4B, a planarization process (such as chemical mechanical polishing (CMP)) can be performed to remove the portions of the interconnect dielectric layer 350, the active metal interconnect structure 362, and the main dummy metal structure 364 located above a horizontal plane. The horizontal plane may be located above the horizontal plane including the top surface of the micro dummy metal structure 366, and may be located below the horizontal plane including the top surface of the main dummy metal structure 364. The top surfaces of the active metal interconnect structure 362 and the main dummy metal structure 364 may be formed within the same horizontal plane including the top surface of the planarized interconnect dielectric layer 350. The interconnect dielectric layer 350 may laterally surround the active metal interconnect structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366. The top surfaces of the active metal interconnect structure 362 and the main dummy metal structure 364 are physically exposed at the horizontal plane including the top surface of the interconnect dielectric layer 350. The top surface of the miniature virtual metal structure 366 is located below the horizontal plane and is therefore not physically exposed.

[0049] Referring to Figure 4C, a bonding-level dielectric layer 370 may be formed over the interconnect-level dielectric layer 350, the active metal interconnect structure 362, the primary dummy metal structure 364, and the micro dummy metal structure 366. The bonding-level dielectric layer 370 may contain a dielectric material suitable for dielectric-to-dielectric bonding. In one embodiment, the bonding-level dielectric layer 370 comprises a silicate glass material, such as undoped or doped silicate glass. The thickness of the bonding-level dielectric layer 370 may range from 1 micrometer to 15 micrometers, such as 3 micrometers to 8 micrometers, but smaller or larger thicknesses may also be used.

[0050] Referring to Figure 4D, a first photoresist layer (not shown) can be applied to the bonding-level dielectric layer 370 and can be photolithographically patterned to form first discrete openings covering the active metal interconnect structure 362 and the main dummy metal structure 364. Each first discrete opening can have a corresponding shape such as rectangular, rounded rectangle, circular, or elliptical. An anisotropic etching process can be performed to transfer the pattern of the first discrete openings in the photoresist layer to the upper portion of the bonding-level dielectric layer 370. A plate-like cavity 385 can be formed in the upper portion of the bonding-level dielectric layer 370. The first photoresist layer can then be removed, for example, by ashing.

[0051] Referring to Figure 4E, a second photoresist layer (not shown) may be applied over the bonding-level dielectric layer 370 and may be photolithographically patterned to form second discrete openings. Each second discrete opening may have a region overlapping a corresponding plate-shaped cavity 385 and overlapping a corresponding one of the active metal interconnect structure 362 and the main dummy metal structure 364. An anisotropic etching process may be performed to etch the lower portion of the bonding-level dielectric layer 370 unmasked by the first photoresist layer. Vias are formed beneath the plate-shaped cavities 385, such that the top surface segments of the active metal interconnect structure 362 and the main dummy metal structure 364 are physically exposed beneath the via cavities. The second photoresist layer may then be removed, for example, by ashing. Each successive combination of the plate-shaped cavity 385 and at least one underlying via cavity constitutes a pad cavity 387. Typically, the pad cavity 387 can be formed via the bonding-level dielectric layer 370, so that the top surface sections of the active metal connection structure 362 and the main dummy metal structure 364 are exposed below the pad cavity 387.

[0052] Referring to Figure 4F, a metal barrier liner layer may be deposited in the pad cavity 387. This metal barrier liner layer comprises a conductive metal nitride material (such as TiN, TaN, WN, and / or MoN) and at least one metal filler material (such as copper) suitable for metal-to-metal bonding. Excess portions of the metal barrier liner layer and at least one metal filler material may be removed above a horizontal plane, including the top surface of the bonding-level dielectric layer 370, by performing a planarization process (such as chemical mechanical polishing). Each remaining portion of the metal barrier liner layer and at least one metal filler material constitutes a pad 388. Each pad 388 may include a corresponding combination of a metal barrier liner 388B and a metal filler material portion 388M. In one embodiment, each metal filler material portion 388M may include a copper portion. The pad 388 includes: an active pad 388A formed on an active metal connection structure 362; and a dummy pad 388D formed on a primary dummy metal structure 364.

[0053] Typically, solder pads 388 are formed above the active metal interconnect structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366. The active metal interconnect structure 362 and the main dummy metal structure 364 are in contact via solder pads 388. The micro dummy metal structure 366 is not in contact with any solder pads 388. Each micro dummy metal structure 366 is electrically isolated from the metal interconnect structure 340, the solder pads 388, the active metal interconnect structure 362, and the main dummy metal structure 364. Each main dummy metal structure 364 is electrically isolated from the metal interconnect structure 340 and the active metal interconnect structure 362, and contacts the corresponding solder pad 388.

[0054] Referring to Figure 5, an exemplary structure after the formation of the bonding pad 388 is illustrated. In one embodiment, the semiconductor substrate 309 may be provided as a semiconductor wafer, and a plurality of semiconductor dies 300 may be formed on the semiconductor wafer. In this embodiment, a dicing process may be performed to monolithize the semiconductor dies 300.

[0055] Referring to Figures 6A and 6B, a reconstituted wafer comprising a two-dimensional array of a carrier substrate 810 and first semiconductor dies 100 is illustrated. The carrier substrate 810 can be any type of carrier substrate suitable for carrying the semiconductor die array. For example, the carrier substrate 810 can be a glass substrate, a semiconductor substrate, or a conductive substrate. As shown in Figure 6B, the carrier substrate 810 can have a circular shape in a plan view. In other embodiments (not shown), the carrier substrate can have a rectangular shape or any other shape suitable for carrying the semiconductor die array. The first semiconductor die 100 can be any type of semiconductor die known in the art. For example, the first semiconductor die 100 can include logic dies including at least one central processing unit (CPU), at least one graphics processing unit (GPU), at least one neural processing unit (NPU), at least one memory array, and / or any other type of semiconductor device known in the art. The array of first semiconductor dies 100 can be attached to the carrier substrate 810 using an adhesive layer 811. The array of the first semiconductor die 100 can be arranged as a periodic two-dimensional array. The region constituting the smallest repeating unit within the periodic two-dimensional array is referred to here as the unit region.

[0056] In one embodiment, each first semiconductor die 100 may be attached to a carrier substrate 810 via an adhesive layer 811, which may be a thermally degradable adhesive layer, such as a polyimide layer, or a UV-degradable adhesive layer, such as a UV-sensitive tape. The first semiconductor die 100 may include a first semiconductor substrate 109, a first semiconductor device 120 located on the first semiconductor substrate 109, a first metal interconnect structure 180 formed within a first dielectric material layer 160, a first bonding level dielectric layer 190, and a packaging bonding structure 188 formed within the first bonding level dielectric layer 190. The packaging bonding structure 188 serves as a bonding structure for subsequently formed composite dies and can be used for solder-mediated bonding (such as die-bonding, i.e., microbump bonding, or controlled chipping die-bonding, i.e., C4 bonding) or for metal-to-metal bonding. The first grain edge sealing ring structure 170 can extend vertically through the first dielectric material layer 160 and the first bonding level dielectric layer 190, and can laterally surround the entire first metal interconnect structure 180.

[0057] The first semiconductor device 120 may include any semiconductor device known in the art, such as field-effect transistors and passive devices. A first shallow trench isolation structure 112 may be disposed within the first semiconductor substrate 109 such that adjacent pairs of first semiconductor devices 120 are electrically isolated from each other. The first semiconductor die 100 may include a through-substrate via (TSV) structure 114 that extends vertically through the first semiconductor substrate 109 and optionally through a subset of the first dielectric layer 160. The TSV structure 114 may be electrically isolated from the first semiconductor substrate 109 by a dielectric pad 113. A first back-side dielectric layer 117 may be disposed on the back side of the first semiconductor substrate 109. In this embodiment, the TSV structure 114 may extend vertically through the first back-side dielectric layer 117. In one embodiment, the TSV structure 114 may be arranged in a periodic pattern having the same periodicity as the pattern of the first active pad subsequently formed on the first back-side dielectric layer 117. Each sidewall of the first semiconductor die 100 can be physically exposed.

[0058] Referring to Figure 7, a first molding compound can be applied to the gap between adjacent pairs of first semiconductor grains 100. The first molding compound may include an epoxy resin-containing compound that can be hardened (i.e., cured) to provide a dielectric portion with sufficient rigidity and mechanical strength. The first molding compound may include epoxy resin, a hardener, silicon dioxide (as a filler), and other additives. The first molding compound may be provided in liquid or solid form depending on viscosity and flowability. Liquid first molding compounds offer better handleability, good flowability, fewer voids, better filling, and fewer flow marks. Solid molding compounds offer less curing shrinkage, better support, and less grain drift. High filler content (e.g., 85% by weight) in the molding compound can shorten mold time, reduce mold shrinkage, and reduce mold warpage. Uniform filler size distribution in the molding compound can reduce flow marks and enhance flowability. In embodiments where the adhesive layer 811 includes a thermally release material, the curing temperature of the molding compound may be lower than the release (debonding) temperature of the adhesive layer 811. For example, the curing temperature of the first molding compound can be in the range of 125°C to 150°C.

[0059] The first molding compound can be cured at a curing temperature to form a first molding compound matrix 260, which laterally surrounds a two-dimensional array of first semiconductor chips 100. The first molding compound matrix 260 includes a plurality of interconnected first molding compound chip frames. Each first molding compound chip frame is a part of the first molding compound matrix 260, which is located within a repeating cell region of a two-dimensional periodic structure array above the carrier substrate 810. Therefore, each first molding compound chip frame laterally surrounds and embeds a corresponding first semiconductor chip 100.

[0060] The portion of the first molding compound matrix 260 above a horizontal plane, including the top surface of the first semiconductor die 100, can be removed using a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the first molding compound matrix 260 above the horizontal plane. The remaining portion of the first molding compound matrix 260 and the combination of the array of first semiconductor dies 100 constitute a reconstituted wafer. Each portion of the first molding compound matrix 260 within a unit region constitutes a first molding compound die framework. Typically, the first molding compound matrix 260 can be formed around the first semiconductor die 100 such that the top surface of the first molding compound matrix 260 is coplanar with the top dielectric surface of the first semiconductor die 100.

[0061] Referring to Figure 8, a combination of at least one bonding-level dielectric layer 220 and a first bonding pad 228 may be formed over the first semiconductor die 100 and the first molding compound matrix 260. The first bonding pad 228 may include a first active bonding pad 228A electrically connected to a corresponding one of the first metal interconnect structures 180, and may further include a first dummy bonding pad 228D not electrically connected to any other conductive structure. Each first active bonding pad 228A may be formed directly on a corresponding conductive structure (such as a through-substrate via structure 114) within the first semiconductor die 100. Each portion of the exemplary structure within a unit region is referred to herein as a first molding die unit 200, which includes a first die group of portions of the first semiconductor die 100 and the first molding compound matrix 260 and a combination of at least one bonding-level dielectric layer 220, a first active bonding pad 228A, and a first dummy bonding pad 228D located within a unit region.

[0062] Typically, each first dummy pad 228D may have the same material composition as the first active pad 228A, or it may have a different material composition. In one embodiment, all first dummy pads 228D may have the same material composition as the first active pad 228A. In another embodiment, all first dummy pads 228D may have a different material composition than the first active pad 228A. At least one bonding level dielectric layer 220 may comprise a single bonding level dielectric layer 220, or it may comprise a plurality of bonding level dielectric layers 220.

[0063] Referring to Figure 9, a second semiconductor die 300 having a second bonding pad 388 can be bonded to a corresponding one of the first semiconductor dies 100 by metal-to-metal bonding. The second semiconductor die 300 may be identical to the semiconductor die 300 described with reference to Figure 5 and is formed using the processing steps described with reference to Figures 1 through 4F. The bonding pad 388 of the second semiconductor die 300 is hereinafter referred to as the second bonding pad 388. Typically, in embodiments where the first semiconductor die 100 has similar structural elements, each structural element in the second semiconductor die 300 may be referred to hereinafter as a second structural element.

[0064] A plurality of second semiconductor dies 300 may be bonded to a plurality of first semiconductor dies 100. Each second semiconductor die 300 may be bonded to a corresponding first semiconductor die 100 by performing a bonding process in which a second bonding pad 388 of the second semiconductor die 300 is bonded to a first bonding pad 228 in a corresponding cell region containing the first semiconductor die 100 by means of metal-to-metal bonding. In one embodiment, a first active bonding pad 228A may be bonded to a second active bonding pad 388A, and a first dummy bonding pad 228D may be bonded to a second dummy bonding pad 388D.

[0065] Each second semiconductor die 300 may include a second semiconductor substrate 309, a second semiconductor device 320 located on the second semiconductor substrate 309, a second metal interconnect structure 340 formed within a second dielectric material layer 330, a second bonding level dielectric layer 370, and a second bonding pad 388 formed within the second bonding level dielectric layer 370. The second bonding pad 388 can be used for metal-to-metal bonding, such as copper-to-copper bonding. As used herein, metal-to-metal bonding refers to the direct bonding of metal surfaces without the use of an intermediate adhesive or solder. Metal-to-metal bonding can be achieved by performing an annealing process at high temperature, thermoforming and / or diffusion bonding between two metal surfaces in direct contact.

[0066] The second die edge sealing ring structure 344 (also referred to as edge sealing ring structure 344) extends vertically through the second dielectric material layer 330 and the second interconnect dielectric layer 350, and laterally surrounds the entire second metal interconnect structure 340. The second semiconductor device 320 may include any semiconductor device known in the art, such as field-effect transistors and passive devices. The second shallow trench isolation structure 312 may be disposed within the second semiconductor substrate 309, such that adjacent second semiconductor devices 320 are electrically isolated from each other. All sidewalls of the second semiconductor die 300 may be physically exposed.

[0067] The second active pad 388A can be bonded to the first active pad 228A via metal-to-metal bonding (such as copper-to-copper bonding). The second dummy pad 388D can be bonded to the first dummy pad 228D via metal-to-metal bonding (such as copper-to-copper bonding). Furthermore, the horizontal bottom surface of the second bonding level dielectric layer 370 can be bonded to the topmost surface of at least one bonding level dielectric layer 220 via dielectric-to-dielectric bonding (such as silicon oxide-to-silicon oxide bonding).

[0068] In one embodiment, the second semiconductor die 300 includes an edge sealing ring structure 344 that extends continuously along all sidewalls of the second semiconductor die 300. In one embodiment, at least one first dummy pad 228D within a first subset of the first dummy pads 228D overlaps with the edge sealing ring structure 344 in a plan view. Alternatively or additionally, at least one first dummy pad 228D within the first subset of the first dummy pads 228D is at least partially located in a region surrounded by the edge sealing ring structure 344 in a plan view. Alternatively or additionally, at least one first dummy pad 228D within the first subset of the first dummy pads 228D is at least partially located in a frame-shaped region between the periphery of the edge sealing ring structure 344 and the sidewalls of the second semiconductor die 300 in a plan view.

[0069] Referring to Figures 10A and 10B, a second molding compound matrix 460 can be formed around the second semiconductor die 300. Specifically, the second molding compound can be applied to the gap between adjacent pairs of second semiconductor dies 300. The second molding compound can contain any material that can be used as the first molding compound. Typically, the second molding compound and the first molding compound can have the same material composition or can have different material compositions. The second molding compound can be cured at a curing temperature to form a second molding compound matrix 460 that laterally surrounds the second semiconductor die 300 in a two-dimensional array. The second molding compound matrix 460 includes a plurality of interconnected second molding compound die frames. Each second molding compound die frame is a part of the second molding compound matrix 460, which is located within a repeating cell region in a two-dimensional periodic structure array above the carrier substrate 810. Thus, each second molding compound die frame laterally surrounds and embeds into the corresponding second semiconductor die 300.

[0070] A portion of the second molding compound matrix 460 located on a horizontal plane (including the top surface of the second semiconductor die 300) can be removed using a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove the portion of the second molding compound matrix 460 located on a horizontal plane. The remaining portion of the second molding compound matrix 460 and the combination of the array of second semiconductor dies 300 comprise second molding die units 400. Each second molding die unit 400 comprises a second semiconductor die 300 and a portion of the second molding compound matrix 460 located within a unit region. Each portion of the second molding compound matrix 460 located within a unit region constitutes a second molding compound die framework. Typically, the second molding compound matrix 460 can be formed around the second semiconductor die 300 such that the top surface of the second molding compound matrix 460 is coplanar with the top surface of the second semiconductor die 300. Each vertical stack of the first molding die unit 200 and the second molding die unit 400 constitutes a composite die 900. A two-dimensional array of composite dies 900 can be formed above the carrier substrate 810.

[0071] Subsequently, the carrier substrate 810 can be separated from the reconstituted wafer including the two-dimensional array of composite dies 900 by decomposing the adhesive layer 811. The adhesive layer 811 can be decomposed using a thermal annealing process or an ultraviolet irradiation process. Appropriate cleaning processes can be performed to clean the physically exposed surfaces of the first bonding level dielectric layer 190 and the package bonding structure 188.

[0072] The composite die 900 can be separated by dicing along the dicing channel. Each composite die 900 includes components of a first semiconductor die 100; a first molding compound matrix 260 (first molding compound die frame); a combination of at least one bonding level dielectric layer 220, a first active bonding pad 228A, and a first dummy bonding pad 228D; a second semiconductor die 300 including a second bonding pad 388 bonded to the first active bonding pad 228A via metal-to-metal bonding; and a second molding compound matrix 460 (second molding compound die frame). In one embodiment, each composite die 900 may have a pair of first sidewalls parallel to a first horizontal direction hd1 and a pair of second sidewalls parallel to a second horizontal direction hd2, the second horizontal direction hd2 being perpendicular to the first horizontal direction hd1.

[0073] Referring to Figure 11, the first flowchart illustrates the steps involved in forming the device structure.

[0074] Referring to step 1110 and Figures 1 and 2A, a metal interconnect structure 340 embedded in the dielectric material layer 330 can be formed above the substrate.

[0075] Referring to steps 1120 and Figures 2B to 2H and 3A to 3G, an active metal connection structure 362, a main dummy metal structure 364, and a micro dummy metal structure 366 can be formed above the topmost dielectric material layer 33T selected from dielectric material layers 330. The height of the micro dummy metal structure 366 is less than the height of the active metal connection structure 362 and the main dummy metal structure 364.

[0076] Referring to step 1130 and Figures 4A to 10B, solder pads 388 can be formed above the active metal connection structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366. The active metal connection structure 362 and the main dummy metal structure 364 are in contact with the solder pads 388, while the micro dummy metal structure 366 is not in contact with any solder pads 388.

[0077] Referring to Figure 12, the second flowchart illustrates the steps involved in forming the device structure.

[0078] Referring to step 1210 and Figures 1 and 2A, a metal interconnect structure 340 embedded in the dielectric material layer 330 can be formed above the substrate.

[0079] Referring to steps 1220 and Figures 2B and 2C, a continuous metal seed layer 368C can be formed above the dielectric material layer 330.

[0080] Referring to steps 1230 and Figures 2D to 2F and 3A to 3F, at least one electroplating process can be performed using the appropriate electroplating mask layer {357 or (353, 355)} to form electroplated material portions (362M, 364M, 366M). The electroplated material portions (362M, 364M, 366M) include a first type electroplated material portion 362M, a second type electroplated material portion 364M with a height greater than the first type electroplated material portion 362M, and a third type electroplated material portion 366M with a height smaller than the first type electroplated material portion 362M.

[0081] Referring to steps 1240 and Figures 2G, 2H, 3G, and 4A to 10B, the uncovered portions of the electroplated material (362M, 364M, 366M) of the continuous metal seed layer 368C can be removed. The remaining portions of the continuous metal seed layer 368C and the electroplated material portions (362M, 364M, 366M) include: an active metal connection structure 362, containing a first type of electroplated material portion 362M; a main dummy metal structure 364, containing a second type of electroplated material portion 364M; and a micro dummy metal structure 366, containing a third type of electroplated material portion 366M.

[0082] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a device structure is provided, comprising: a metal interconnect structure 340 embedded in a dielectric material layer 330; an active metal connection structure 362, a main dummy metal structure 364, and a micro dummy metal structure 366 located above the topmost dielectric material layer 33T of the dielectric material layer 330, wherein the micro dummy metal structure 366 has a smaller height than the active metal connection structure 362 and the main dummy metal structure 364; and solder pads 388 located above the active metal connection structure 362, the main dummy metal structure 364, and the micro dummy metal structure 366, wherein the active metal connection structure 362 and the main dummy metal structure 364 are in contact by solder pads 388, while the micro dummy metal structure 366 is not in contact with any solder pads 388.

[0083] In one embodiment, each of the active metal interconnect 362, the main dummy metal structure 364, and the micro dummy metal structure 366 includes a corresponding bottom surface located in a horizontal plane, which includes the top surface of the topmost dielectric layer 33T. In one embodiment, each active metal interconnect 362 includes a corresponding via portion extending vertically through the topmost dielectric layer 33T and contacting a corresponding metal interconnect structure 340; and each of the main dummy metal structure 364 and the micro dummy metal structure 366 is located entirely above the horizontal plane, which includes the top surface of the topmost dielectric layer 33T. In one embodiment, the device structure includes a connection-level dielectric layer 350 laterally surrounding the active metal interconnect 362, the main dummy metal structure 364, and the micro dummy metal structure 366, wherein the top surfaces of the active metal interconnect 362 and the main dummy metal structure 364 are located in a horizontal plane, which includes the top surface of the connection-level dielectric layer, and the top surface of the micro dummy metal structure 366 is located below the horizontal plane. In one embodiment, each active metal connection structure 362 is in contact with a corresponding metal interconnect structure 340; and the main dummy metal structure 364 and the micro dummy metal structure 366 are not in contact with any metal interconnect structure 340.

[0084] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Each embodiment described using the term "comprising" also inherently discloses that in some embodiments, the term "comprising" may be replaced by "substantially consisting of" or "consisting of," unless otherwise expressly disclosed herein. When two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising a list of two or more elements is also implicitly disclosed. When the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such elements or such processing steps are not performed are also explicitly considered, provided that the resulting device or apparatus provides an equivalent result. Therefore, when omitting the fact that forming such elements or such processing steps can provide the same or equivalent result, the auxiliary verb "may" used for forming an element or performing a processing step should also be interpreted as "may" or "may, or may not," where equivalent results include slightly better and slightly worse results. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its spirit and scope.

[0085] 33T: Topmost dielectric material layer 100: First semiconductor die 109: First Semiconductor Substrate 112: First shallow trench isolation structure 113: Dielectric Pad 114: Through-substrate via (TSV) structure 117: First back-side dielectric layer 120: First Semiconductor Device 160: First dielectric material layer 170: First grain edge sealing ring structure 180: First metal interconnect structure 188: Package bonding structure 190: First bonding level dielectric layer 200: First molding grain unit 220: Bonding-level dielectric layer 228: First solder pad 228A: First active solder pad 228D: First dummy solder pad 260: First molded plastic matrix 300: Semiconductor die / Second semiconductor die 309: Semiconductor substrate 312: Shallow trench isolation structure 320: Semiconductor device 330: Dielectric material layer 331: Through-hole cavity 340: Metal interconnect structure 344: Edge sealing ring structure 350: Connector-level dielectric layer 351: First interconnect passivation dielectric layer 352: Second interconnect passivation dielectric layer 353: First patterned electroplated mask layer 355: Second patterned electroplated mask layer 356: Connector-level planarization dielectric layer 357: Patterned electroplated masking layer 361: Type I opening 362: Active metal connection structure 362B: Type I metal seed layer 362M: Type I Electroplating Materials 363: Type II opening 364: Main virtual metal structure 364B: Type II metal seed layer 364M: Type II Electroplating Materials 365: Type III Opening 366: Miniature Virtual Metal Structure 366B: Type III metal seed layer 366M: Type III Electroplating Materials 368C: Continuous metal seed layer 370: Bonding-level dielectric layer 385: plate cavity 387: Solder pad cavity 388: Solder pad / Second solder pad 388A: Active solder pad 388B: Metal Barrier Pad 388D: Dummy solder pads 388M: Metal-filled material portion 400: Second molding grain unit 460: Second Molding Plastic Matrix 810: Carrier substrate 811: Adhesive layer 900: Composite grains 1110, 1120, 1130, 1210, 1220, 1230, 1240: Steps hd1: First horizontal direction hd2: Second horizontal direction

Claims

1. A method for forming a device structure, comprising the steps of: forming a plurality of metal interconnect structures embedded in a plurality of dielectric material layers above a substrate; forming a plurality of active metal connection structures, a plurality of main dummy metal structures, and a plurality of micro dummy metal structures above a topmost dielectric material layer, wherein the topmost dielectric material layer is selected from the dielectric material layers, and the height of the micro dummy metal structures is less than the height of the active metal connection structures and the main dummy metal structures; forming a connection level dielectric layer above the active metal connection structures, the main dummy metal structures, and the micro dummy metal structures; The portion of the interconnect dielectric layer, the active metal interconnect structures, and the main dummy metal structures located above a horizontal plane is planarized by performing a chemical mechanical polishing process, wherein the horizontal plane is located above multiple top surfaces of the micro dummy metal structures; and multiple pads are formed above the interconnect dielectric layer, the active metal interconnect structures, the main dummy metal structures, and the micro dummy metal structures, wherein the active metal interconnect structures and the main dummy metal structures are in contact with each other by the pads, and the micro dummy metal structures are not in contact with any pads.

2. The method as described in claim 1, wherein each of the micro-dummy metal structures is electrically isolated from the metal interconnect structures, the pads, the active metal connection structures, and the main dummy metal structures.

3. The method as described in claim 1 further comprises the following steps: depositing a continuous metal seed layer on the dielectric material layers; forming a patterned electroplated mask layer on the continuous metal seed layer; electroplating a metal material on a plurality of physically exposed surfaces of the continuous metal seed layer; and removing the patterned electroplated mask layer and a plurality of unmasked portions of the continuous metal seed layer, wherein the remaining portion of the continuous metal seed layer and the electroplated metal material comprise the active metal connection structures, the main dummy metal structures, and the micro dummy metal structures.

4. The method as described in claim 3 further comprises the following steps: forming a plurality of via cavities via a topmost dielectric material layer selected from the dielectric material layers, wherein a plurality of top surfaces of a subset of metal interconnect structures are exposed below the via cavities, and wherein the continuous metal seed layer is directly deposited on the subset of metal interconnect structures.

5. The method as described in claim 4, wherein: Each of the active metal interconnect structures contacts a corresponding metal interconnect structure selected from the subset of the metal interconnect structures; and the main dummy metal structure does not contact any metal interconnect structure.

6. A method of forming a device structure, comprising the steps of: forming a plurality of metal interconnect structures embedded in a plurality of dielectric material layers over a substrate; depositing a continuous metal seed layer on the dielectric material layers; performing at least one electroplating process using a corresponding electroplating mask layer to form a plurality of electroplated material portions, wherein the electroplated material portions include a plurality of first-type electroplated material portions, a plurality of second-type electroplated material portions having a greater height than the first-type electroplated material portions, and a plurality of third-type electroplated material portions having a smaller height than the first-type electroplated material portions; and removing a plurality of portions of the continuous metal seed layer from which the electroplated material portions are not masked, wherein the remaining portions of the continuous metal seed layer and the electroplated material portions include: Multiple active metal connection structures, including portions of the first type of electroplated material; multiple main virtual metal structures, including portions of the second type of electroplated material; And multiple miniature virtual metal structures, containing these third-type electroplated material components.

7. The method as described in claim 6, wherein the height of the micro-dummy metal structures is less than the height of the active metal connection structures and the main dummy metal structures.

8. The method as described in claim 6, wherein: The first type of electroplating material portions, the second type of electroplating material portions, and the third type of electroplating material portions are formed simultaneously in a single electroplating process; and the lateral dimension of the first type of electroplating material portions is larger than the lateral dimension of the third type of electroplating material portions.

9. The method as described in claim 6, wherein: The first type of electroplated material portions and the second type of electroplated material portions are formed by performing an electroplating process using a patterned electroplating mask layer; and the third type of electroplated material portions are formed by performing an additional electroplating process using an additional patterned electroplating mask layer.

10. A device structure comprising: a plurality of metal interconnect structures embedded in a plurality of dielectric material layers; a plurality of active metal connection structures, a plurality of main dummy metal structures, and a plurality of micro dummy metal structures located above a topmost dielectric material layer, the topmost dielectric material layer being selected from the dielectric material layers, wherein the height of the micro dummy metal structures is less than the height of the active metal connection structures and the main dummy metal structures; A connection-level dielectric layer laterally surrounds the active metal connection structures, the main dummy metal structures, and the micro dummy metal structures, wherein multiple top surfaces of the active metal connection structures and the main dummy metal structures are located within a horizontal plane, the horizontal plane including a top surface of the connection-level dielectric layer, and multiple top surfaces of the micro dummy metal structures are located below the horizontal plane; and multiple solder pads are located above the connection-level dielectric layer, the active metal connection structures, the main dummy metal structures, and the micro dummy metal structures, wherein the active metal connection structures and the main dummy metal structures are in contact with each other via the solder pads, and the micro dummy metal structures are not in contact with any solder pads.

Images