Memory apparatus

Abstract

A memory device. A first selection circuit selects and connects a first global character line decoder to a portion of the first global character lines based on a selected even-numbered memory block. A second selection circuit transmits a first global character line selection signal to the selected even-numbered memory block. A third selection circuit selects and connects a second global character line decoder to a portion of the second global character lines based on a selected odd-numbered memory block. A fourth selection circuit transmits a second global character line selection signal to the selected odd-numbered memory block.

Claims

1. A memory device, comprising: A memory cell array, comprising multiple even-numbered memory blocks and multiple odd-numbered memory blocks; An even-numbered column decoder circuit coupled to the memory cell array includes: a first global character line decoder providing a plurality of first global character line selection signals; a first selection circuit coupled to the first global character line decoder and the plurality of first global character lines, selectively connecting the first global character line decoder to a portion of the first global character lines based on a selected even-numbered memory block; and a second selection circuit coupled to the first global character lines and the even-numbered memory blocks, transmitting the first global character line selection signals to the selected even-numbered memory block based on the selected even-numbered memory block; and an odd-numbered column decoder circuit coupled to the memory cell array includes: a second global character line decoder providing a plurality of second global character line selection signals; A third selection circuit, coupled to the second global character line decoder and multiple second global character lines, selects and connects the second global character line decoder to a portion of the second global character lines based on the selected odd-numbered memory blocks; and a fourth selection circuit, coupled to the second global character lines and the odd-numbered memory blocks, transmits the second global character line selection signals to the selected odd-numbered memory blocks based on the selected odd-numbered memory blocks, wherein the first selection circuit includes: multiple first transmission circuits, respectively coupled to the first global character line decoder and corresponding first global character lines, transmitting the first global character line selection signals to the selected even-numbered memory blocks based on the selected even-numbered memory blocks.

2. The memory device as claimed in claim 1, wherein the second selection circuitry includes: Multiple second transmission circuits are respectively coupled between the corresponding first transmission circuit and the corresponding even-numbered memory blocks, and transmit the first global character line selection signals according to the selected even-numbered memory block, so as to transmit the first global character line selection signals to the selected even-numbered memory block.

3. The memory device as claimed in claim 2, wherein the second selection circuitry further comprises: Multiple third transmission circuits are respectively coupled between the corresponding second transmission circuit and the corresponding even-numbered memory blocks, and transmit the first global character line selection signals according to the selected even-numbered memory block, so as to transmit the first global character line selection signals to the selected even-numbered memory block.

4. The memory device according to any one of claims 2 to 3, wherein each of the first transmission circuits, each of the second transmission circuits, and each of the third transmission circuits comprises: One-block decoder; And a word-line decoder, controlled by the block decoder to transmit the first global word-line selection signals to the selected even-numbered memory block.

5. The memory device as claimed in claim 4, wherein each first character line decoder includes: Multiple first transistors, the control terminals of which are coupled to the even-numbered block decoder, the conduction state of which is controlled by the even-numbered block decoder to transmit the first global character line selection signals.

6. The memory device as claimed in claim 1, wherein the third selection circuitry includes: Multiple fourth transmission circuits are respectively coupled to the second global character line decoder and the corresponding second global character line, and transmit the second global character line selection signals to the second global character line of the selected odd memory block.

7. The memory device as claimed in claim 6, wherein the fourth selection circuitry includes: Multiple fifth transmission circuits are respectively coupled between the corresponding fourth transmission circuit and the corresponding odd memory block, and transmit the second global character line selection signals according to the selected odd memory block, so as to transmit the second global character line selection signals to the selected odd memory block.

8. The memory device as claimed in claim 7, wherein the second selection circuitry includes: Multiple sixth transmission circuits are respectively coupled between the corresponding fifth transmission circuit and the corresponding odd memory block, and transmit the second global character line selection signals according to the selected odd memory block, so as to transmit the second global character line selection signals to the selected odd memory block.

9. The memory device according to any one of claims 6 to 8, wherein each of the fourth transmission circuits, each of the fifth transmission circuits, and each of the sixth transmission circuits comprises: One-block decoder; And a single-line decoder, controlled by the odd-block decoder to transmit the second global character line selection signals to the selected odd-block memory.

10. The memory device as claimed in claim 9, wherein each second character line decoder includes: Multiple second transistors, the control terminals of which are coupled to the odd-numbered block decoder, are controlled by the odd-numbered block decoder to transmit the second global character line selection signals.

11. The memory device as claimed in claim 1, wherein the memory device is a NAND memory device.

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