Semiconductor structure and method of forming the same

Abstract

The disclosed semiconductor structure includes a back-side metal line and a back-side contact structure. The back-side contact structure includes a strip-shaped portion disposed on the back-side metal line, a first via extending from the strip-shaped portion, a second via extending from the strip-shaped portion, and a protrusion disposed between the first and second vias. The semiconductor structure also includes a first source / drain component located above the first via, a second source / drain component located above the second via, and a gate isolation component disposed between the first and second vias. The protrusion extends into the gate isolation component.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a semiconductor structure having a back-side contact structure and a method for forming the same. Prior Technology

[0002] The electronics industry's demand for smaller, faster electronic devices, capable of supporting increasingly complex and sophisticated functions, continues. Consequently, the semiconductor industry's trend towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) persists. To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this development has also increased the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Static random access memory (SRAM) generally refers to any memory or storage that retains stored data only when power is applied. As integrated circuit technology advances to smaller technology nodes, multi-gate structures (e.g., fin-like field-effect transistors (FinFETs) or gate-all-around (GAA) transistors) are integrated into SRAM cells to improve performance. As SRAM cell sizes continue to shrink, the contact structures that functionally connect the transistors within the SRAM cell present additional challenges in reducing resistance (R) and capacitance (C). Summary of the Invention

[0004] A semiconductor structure includes a back-side metal line disposed in a back-side insulating layer and a back-side contact structure. The back-side contact structure includes a strip-shaped portion disposed on the back-side metal line, a first via extending from the strip-shaped portion, a second via extending from the strip-shaped portion, and a protrusion disposed between the first via and the second via. The semiconductor structure further includes a first source / drain component located above the first via, a second source / drain component located above the second via, a gate isolation component disposed between the first via and the second via, and a siliconized component disposed between the first via and the first source / drain component. The protrusion extends into the gate isolation component. The conductivity of the first via is greater than the conductivity of the siliconized component.

[0005] A semiconductor structure includes a back-side insulating layer, a back-side metal line disposed in the back-side insulating layer, a hard mask layer on the back-side insulating layer, and a back-side contact structure disposed above the back-side metal line. The back-side contact structure includes a strip-shaped portion disposed in the hard mask layer, a first via extending from the strip-shaped portion, a second via extending from the strip-shaped portion, and a protrusion disposed along a direction between the first and second vias. The semiconductor structure also includes a first source / drain component above the first via, a second source / drain component above the second via, a gate isolation component disposed along the direction between the first and second source / drain components, an isolation component extending along multiple sidewalls of the first and second vias, a contact etch stop layer above the isolation component, and an interlayer dielectric layer above the contact etch stop layer. The isolation component comprises an oxide-based material. The composition of the contact etch stop layer differs from the composition of the interlayer dielectric layer. The strip-shaped portion of the back contact structure, the first guide hole, the second guide hole, and the protrusion form an M-shape.

[0006] A method for forming a semiconductor structure includes providing a precursor structure. The precursor structure includes a first source / drain component and a second source / drain component located above a front source / drain contact; a first base fin located above the first source / drain component; a second base fin located above the second source / drain component; an isolation component disposed between the first base fin and the second base fin and extending along a plurality of sidewalls of the first base fin and the second base fin; and a gate isolation component disposed between the first base fin and the second base fin. The method further includes depositing a hard mask layer over the isolation component, the first base fin, and the second base fin; forming a patterned photoresist layer over the hard mask layer; using the patterned photoresist layer as an etching mask; etching the precursor structure and the hard mask layer to form a back-side opening of the contact, the back-side opening exposing the isolation component and the gate isolation component; depositing a liner over the back-side opening of the contact; after depositing the liner, performing anisotropic etching to expose the first source / drain component and the second source / drain component; depositing a metal filler in the back-side opening of the contact; and planarizing the metal filler to expose the hard mask layer and form a back-side contact. The isolation component comprises an oxide-based material. A silicon layer is disposed between the first source / drain component and the front source / drain contact. The conductivity of the front source / drain contact is greater than the conductivity of the silicon layer. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present invention. Figure 1 is a circuit diagram of a static random access memory (SRAM) cell according to various forms disclosed herein. Figure 2 is a top view of an SRAM cell based on various configurations disclosed herein. Figure 3 is a partial top view of the front interconnect structure of an SRAM quad-cell, based on various configurations disclosed herein. Figure 4 is a partial cross-sectional view along section A-A' of Figure 3, based on various morphologies disclosed herein. Figure 5 is a partial top view of the back-side interconnect structure of an SRAM quad cell, according to various configurations disclosed herein. Figure 6 is a partial cross-sectional view along section B-B' of Figure 5, based on various morphologies disclosed herein. Figure 7 is a partial cross-sectional view of the back-side connector contact along section C-C' of Figure 5, according to various configurations disclosed herein. Figure 8 is a flowchart illustrating a method for forming a back-side connector contact element according to various forms disclosed herein. Figures 9 through 19 are partial cross-sectional views illustrating the precursor structure undergoing the various steps of the method in Figure 8, according to some embodiments of the present disclosure. Figure 20 is a partial cross-sectional view of a semiconductor structure according to various embodiments disclosed herein, wherein the protruding portion of the back-side connector contact overhangs above the back-side metal line. Figure 21 is a partial top view of the back-side interconnect structure of an SRAM quad cell having the back-side connector contact shown in Figure 20, according to various embodiments of this disclosure. Figure 22 is a partial cross-sectional view of a semiconductor structure according to various embodiments disclosed herein, wherein multiple protrusions of the back-side connector contacts overhang over the back-side metal lines. Figure 23 is a partial top view of the back-side interconnect structure of an SRAM quad cell having the back-side connector contacts shown in Figure 22, according to various embodiments disclosed herein. Figure 24 is a partial cross-sectional view of a semiconductor structure according to various configurations disclosed herein, wherein the back-side connector contact is merged with the front-side common contact. Figure 25 is a partial top view of the back-side interconnect structure of an SRAM quad cell having the back-side connector contacts shown in Figure 24, according to various embodiments of this disclosure. Implementation

[0008] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements so that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or components in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] Furthermore, when using terms such as "approximately" or "around" to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing components having the number as a related part, the number or range of numbers covers a reasonable range including, for example, within + / - 10% of, the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers. When describing various states of a transistor, depending on the context, the source / drain region can refer to the source or drain individually or jointly.

[0011] Static random access memory (SRAM) is a type of semiconductor memory that retains data statically as long as power is applied. Compared to dynamic random access memory (DRAM), SRAM is faster, more reliable, and does not require refreshing. SRAM is widely used in many applications, such as cache memory in computers and as part of the random access memory in digital-to-analog converters on video cards. As integrated circuit technology advances to smaller technology nodes, multi-gate structures (e.g., fin-like field-effect transistors (FinFETs) or gate-all-around (GAA) transistors) are integrated into SRAM cells to improve performance. However, miniaturization puts pressure on electrical wiring. When only front-side interconnects exist, the spacing between contact vias and metal lines becomes extremely tight, and high resistance may occur with the front-side connections of the individual transistor nodes in the SRAM cell. Tight spacing and high contact resistance may lead to increased resistance and capacitance values, which in turn reduces drive current and speed.

[0012] This disclosure provides an SRAM device that includes not only front-side interconnects but also back-side interconnects to improve the performance of the SRAM device. In one embodiment, the source of a pull-down transistor is coupled to a backside ground rail via a backside connector contact to improve pull-down current. The backside connector contact includes a bar portion connected to a backside metal line, a first via and a second via extending from the bar portion toward the source component, and a protrusion disposed between the first via and the second via. The bar portion, the first via, the second via, and the intermediate protrusion give the backside connector contact a shape similar to the letter M. The shape of the backside connector contact is determined by the structure around the backside connector contact and the etching processes used to etch silicon, silicon nitride, and silicon oxide at different rates. The formation of the backside connector contact increases the backside via etching process window and reduces contact resistance.

[0013] Figure 1 illustrates an exemplary type of memory device in which transistors such as planar transistors, FinFET transistors, or GAA transistors can be implemented. In this regard, Figure 1 illustrates a circuit diagram of an exemplary SRAM device, such as a single-port SRAM cell (e.g., a 1-bit SRAM cell) 10. The single-port SRAM cell 10 includes a first through-gate transistor PG1 and a second through-gate transistor PG2, a first pull-up transistor PU1 and a second pull-up transistor PU2, and a first pull-down transistor PD1 and a second pull-down transistor PD2. The gates of the first through-gate transistor PG1 and the second through-gate transistor PG2 are electrically connected to the word line (WL) to determine whether the SRAM cell 10 is selected. In the SRAM cell 10, the first pull-up transistor PU1 and the second pull-up transistor PU2, and the first pull-down transistor PD1 and the second pull-down transistor PD2 form memory bits (e.g., latches or flip-flops) for storing one bit of data. The complementary value of this bit is stored in the first storage node SN1 and the first complementary storage node SNB1. The stored bit can be written to or read from SRAM cell 10 via bit-line (BL) and complementary bit-line (BLB) bars. In this configuration, bit-line BL and complementary bit-line BLB can carry complementary bit-line signals. SRAM cell 10 is powered by a positive power supply voltage Vdd and is also connected to ground potential Vss.

[0014] SRAM cell 10 includes a first inverter 12 formed by a first pull-up transistor PU1 and a first pull-down transistor PD1, and a second inverter 14 formed by a second pull-up transistor PU2 and a second pull-down transistor PD2. As shown in Figure 1, the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1 are coupled together, and the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2 are coupled together. The first inverter 12 and the second inverter 14 are coupled between the positive power supply voltage Vdd and the ground potential Vss. As shown in Figure 1, the first inverter 12 and the second inverter 14 are cross-coupled. That is, the input of the first inverter 12 is coupled to the output of the second inverter 14. Similarly, the second inverter 14 has an input coupled to the output of the first inverter 12. The output of the first inverter 12 is called the first storage node SN1. Similarly, the output of the second inverter 14 is called the first complementary storage node SNB1. In normal operating mode, the first storage node SN1 and the first complementary storage node SNB1 are in opposite logic states (logic high or logic low). By employing two cross-coupled inverters, SRAM cell 10 can use a latched structure to store data, ensuring that the stored data will not be lost as long as it is powered by the positive power supply voltage Vdd, without the need for a refresh cycle.

[0015] Referring now to Figure 2, an exemplary layout of the SRAM cell 10 in Figure 1 is illustrated. Similar to the SRAM cell 10 in Figure 1, the layout in Figure 2 includes six transistors, serving as a first through-gate transistor PG1, a second through-gate transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2. In some embodiments shown in Figure 2, the SRAM cell 10 may be formed above an n-type well 32 (or an N-well 32) sandwiched between two p-type wells 30 and 34 (or P-wells 30 and 34). The N-well 32 and the P-wells 30 and 34 are formed above a substrate. In some embodiments, as shown in Figure 2, the first through-gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second through-gate transistor PG2 may be formed above the P-wells 30 and 34; the first pull-up transistor PU1 and the second pull-up transistor PU2 are formed in the N-well 32. In these embodiments, the first through-gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second through-gate transistor PG2 are all n-type GAA transistors; the first pull-up transistor PU1 and the second pull-up transistor PU2 are both p-type GAA transistors.

[0016] In some embodiments, the SRAM cell 10 includes four fin-shaped vertical stacks, namely a first fin-shaped vertical stack 40, a second fin-shaped vertical stack 42, a third fin-shaped vertical stack 44, and a fourth fin-shaped vertical stack 46. The first fin-shaped vertical stack 40 is formed above the P-well 30 and forms the channel regions for the first through-gate transistor PG1 and the first pull-down transistor PD1. The second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are formed above the N-well 32 and respectively form the channel regions for the first pull-up transistor PU1 and the second pull-up transistor PU2. The fourth fin-shaped vertical stack 46 is formed above the P-well 34 and forms the channel regions for the second pull-down transistor PD2 and the second through-gate transistor PG2. The first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 may each include approximately two to approximately ten channel members. In some embodiments, the first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 each include three channel members. The first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 may each be referred to as an active region.

[0017] In some cases, fin-like vertical stacks can be formed by depositing or epitaxially growing alternating layers of two different semiconductor materials, patterning the alternating layers to form fin-like structures, and selectively removing films formed from one of the two semiconductor materials. For example, alternating layers of silicon (Si) and silicon-germanium (SiGe) can be epitaxially grown on a substrate. This substrate can be a silicon (Si) substrate. The alternating layers can then be patterned to form a fin-like structure comprising alternating stacks of silicon (Si) strips and silicon-germanium (SiGe) strips. In the process of forming the channel regions of transistors in SRAM cells, the channel regions of the fin-like structure can undergo different etching processes to selectively remove the silicon-germanium (SiGe) strips, thereby releasing the silicon (Si) layer as suspended silicon channel components. The channel components can take on different shapes and sizes and can be referred to as nanostructures, nanowires, or nanosheets. These fin-like structures are separated by isolation structures (e.g., shallow trench isolation (STI) structures). In some embodiments, each fin-like vertical stack may include a top formed of alternating layers and a base formed of a substrate. The base of the fin-like vertical stack has a fin shape and may be referred to as a fin structure. The base of the fin-like vertical stack may be substantially embedded in the isolation member, and the top of the base of the fin-like vertical stack may be flush with the top surface of the isolation member. The top of the fin-like vertical stack extends from and rises above the isolation member.

[0018] Referring again to Figure 2. The channel components in the first fin-shaped vertical stack 40 form the channel regions of the first through-gate transistor PG1 and the first pull-down transistor PD1. The channel components in the second fin-shaped vertical stack 42 form the channel region of the first pull-up transistor PU1. The channel components in the third fin-shaped vertical stack 44 form the channel region of the second pull-up transistor PU2. The channel components in the fourth fin-shaped vertical stack 46 form the channel regions of the second pull-down transistor PD2 and the second through-gate transistor PG2. In the illustrated embodiment, the first fin-shaped vertical stack 40 and the fourth fin-shaped vertical stack 46 are used to form an n-type GAA transistor, while the second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are used to form a p-type GAA transistor. In the embodiment shown in Figure 2, the first through-gate transistor PG1, the first pull-down transistor PD1, the second through-gate transistor PG2, and the second pull-down transistor PD2 are n-type GAA transistors, while the first pull-up transistor PU1 and the second pull-up transistor PU2 are p-type GAA transistors. In Figure 2, the first fin-shaped vertical stack 40 and the fourth fin-shaped vertical stack 46 each have a first width W1 along the X direction, and the second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 each have a second width W2 along the X direction. In some embodiments, to achieve better read / write performance, the n-type GAA transistor has a larger channel width than the p-type GAA transistor. That is, the first width W1 can be greater than the second width W2. In some cases, the ratio of the first width W1 to the second width W2 (W1 / W2) is between about 1 and about 5, including between about 1.1 and about 3.0.

[0019] As shown in Figure 2, the channel of the first through-gate transistor PG1 is controlled by gate structure 20, the channels of the first pull-down transistor PD1 and the first pull-up transistor PU1 are controlled by gate structure 24, the channels of the second pull-down transistor PD2 and the second pull-up transistor PU2 are controlled by gate structure 22, and the channel of the second through-gate transistor PG2 is controlled by gate structure 26. Since gate structures 20 and 22 are derived from a single gate structure, they are longitudinally aligned along the X direction. Since gate structures 24 and 26 are derived from a single gate structure, they are longitudinally aligned along the X direction. The first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 extend longitudinally along the Y direction, which is perpendicular to the X direction. In circuit and physical design, the SRAM cell 10 shown in Figure 2 can serve as a repeating cell in an SRAM array. To facilitate signal routing, adjacent SRAM cells 10 in the SRAM array can be mirror-symmetric along their boundaries.

[0020] Figures 3 through 7 illustrate various configurations of the exemplary embodiment, wherein the sources of the second pull-down transistors PD2 of the plurality of SRAM cells are electrically connected to the back-side metal lines through back-side contact elements. In this exemplary embodiment, Figure 3 shows a front top view of a quad-cell 100 comprising four SRAM cells 10. The SRAM cells 10 are indicated by dashed rectangles in Figure 3. For ease of explanation, Figure 3 also includes a first mirror axis MA1 extending along the Y direction and a second mirror axis MA2 extending along the X direction. It can be seen that the SRAM cells located on the other side of the first mirror axis MA1 are mirror-symmetrical to the SRAM cells 10. Similarly, the SRAM cells located on the other side of the second mirror axis MA2 are mirror-symmetrical to the SRAM cells 10. This mirror configuration allows for the merging of pull-up transistors, pull-down transistors, and through-gate transistors to achieve efficient wiring and electrical connections. On the front side, the front interconnect layer in Figure 3 includes butted contacts, such as a first front butted contact 102F, a second front butted contact 104F, and a third front butted contact 106F. The first front butted contact 102F couples the gate structure 24 of the first pull-up transistor PU1 to the source of the second pull-up transistor PU2. In the SRAM cell above SRAM cell 10, the second front butted contact 104F also couples the gate structure of the first pull-up transistor PU1 to the source of the second pull-up transistor PU2. The third front butted contact 106F couples the gate structure 22 of the second pull-up transistor PU2 to the source of the first pull-up transistor PU1. Figure 3 also illustrates a first common contact 130 that couples the drain of the second pull-up transistor PU2 and the drain of the second pull-down transistor PD2 together, a second common contact 132 that couples the sources of two adjacent pull-down transistors together, a third common contact 134 that couples the drain of the pull-up transistor and the drain of the pull-down transistor together, and a fourth common contact 136 that couples the source of the pull-up transistor and the source of the pull-down transistor together.

[0021] Figure 4 shows a partial cross-sectional view along section A-A' of Figure 3. As shown in Figure 4, section A-A' passes through gate structure 24, gate structure 22, a gate structure that is a mirror image of gate structure 22 (relative to the second mirror axis MA2), a gate structure that is a mirror image of gate structure 24 (relative to the second mirror axis MA2), first common contact 130, second common contact 132, third common contact 134, first front abutment contact 102F, second front abutment contact 104F, source 120 of second pull-up transistor PU2, drain 122 of second pull-up transistor PU2, and source 124 of pull-up transistor in SRAM cell above SRAM cell 10. Figure 4 also shows a front interconnect layer disposed above the transistor and a back interconnect layer disposed below the transistor. Figure 4 illustrates the stacking of channel members 1080 in different active regions and how each gate structure (e.g., gate structure 22) surrounds each channel member 1080. Figure 4 also illustrates how the end walls of the channel members 1080 are connected to source / drain components (e.g., source 120, drain 122, and source 124). In some embodiments, the channel member 1080 comprises silicon (Si). The first common contact 130, the second common contact 132, and the third common contact 134 may comprise titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or a combination thereof. In the illustrated embodiment, the first common contact 130, the second common contact 132, and the third common contact 134 are connected to the corresponding source or drain through a silicate layer 139. In some embodiments, the silicate layer 139 may comprise titanium silicate, cobalt silicate, or nickel silicate. In terms of conductivity, the conductivity of the second common contact 132 is greater than that of the silicon layer 139, and the conductivity of the silicon layer 139 is higher than that of the source 137 or the source 138.

[0022] Figure 5 shows a top view of the back side of the quad cell 100. Figure 5 also shows the back side contact 164. The back side contact 164 connects the source of the second pull-down transistor (including the second pull-down transistor PD2) to the back side metal line 172. As shown in Figure 5, the back side contact 164 rests directly on the back side metal line 172. It is worth noting that the sources of the first pull-up transistor PU1, the second pull-up transistor PU2, the first through-gate transistor PG1, and the second through-gate transistor PG2 are not coupled to any conductive components in the back side interconnect layer through any corresponding portion of the back side contact 164. Figure 6 shows a partial cross-sectional view of the quad cell 100 along section B-B' of Figure 5. The mirrored placement of the SRAM cells in quad cell 100 allows the source 137 of the second pull-down transistor PD2 to be placed next to the source 138 of the pull-down transistor in the SRAM cell above SRAM cell 10 (not shown in Figure 6, but shown in Figure 7). In some embodiments shown in Figure 7, sources 137 and 138 are coupled to ground potential Vss not only through a second common contact 132, but also through a back-side contact 164. The additional electrical grounding provided by the back-side contact 164 results in a higher saturation current for the second pull-down transistor PD2. Because the source of the through-gate transistor is not coupled to the additional back-side contact, the saturation current of the through-gate transistor remains at a low level. The larger saturation current of the pull-down transistor helps maintain a beta (β) rate greater than 1 for SRAM cell 10, which gives SRAM cell 10 good read stability. The lower saturation current of the through-gate transistor helps maintain a high alpha (α) rate of the SRAM cell, which gives the SRAM cell 10 good writability. A partial cross-sectional view of Figure 7 illustrates the gate isolation component 121. Referring to Figure 7, the gate isolation component 121 isolates the gate structure 22 from the gate structure in the mirrored SRAM cell located on the other side of the first mirror axis MA1. In some embodiments, the gate isolation component 121 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. In one embodiment, the gate isolation component 121 includes silicon nitride. The back-side contact 164 may include titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or a combination thereof.

[0023] Figure 7 is a partial cross-sectional view of the back-side contact 164 along section C-C' in Figure 5. As shown in Figure 7, section C-C' passes through SRAM cell 10 and the mirrored SRAM cell located on the other side of the second mirror axis MA2. Referring to Figure 7, section C-C' passes through gate structures 26 and 22 in SRAM cell 10 and the corresponding gate structures in the mirrored SRAM cell located on the other side of the second mirror axis MA2. Figure 7 illustrates a back-side metal line 172 disposed in a back-side insulating layer 170. In some embodiments, the back-side metal line 172 may include copper (Cu), cobalt (Co), aluminum (Al), nickel (Ni), or a combination thereof, and the back-side insulating layer 170 may include a low-k dielectric layer with a dielectric constant (k) less than that of silicon dioxide (~3.9). In some cases, the back-side insulating layer 170 may include silicon oxide and may be porous. The back-side contact 164 includes a strip-shaped portion 164B, a first via 164-1 continuously extending from the strip-shaped portion 164B, a second via 164-2 continuously extending from the strip-shaped portion 164B, and an intermediate protrusion 168 continuously extending from the strip-shaped portion 164B. The strip-shaped portion 164B is disposed in the hard mask layer 150. The first via 164-1 extends through the isolation member 103 and the gate spacer 111 and terminates at the source 137 of the second pull-down transistor PD2. The second via 164-2 extends through the isolation member 103 and the gate spacer 111 and terminates at the source 138 of the second pull-down transistor PD2 of the SRAM cell adjacent to the SRAM cell 10. The isolation member 103 is disposed between the active regions and may also be referred to as a shallow trench isolation (STI) member 103. The isolation component 103 is formed of an oxide-based material, such as silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric, or a combination thereof. The intermediate protrusion 168 is located along the X direction between the first via 164-1 and the second via 164-2, and is formed during the partial etching of the gate isolation component 121 during the formation of the back opening of the contact.

[0024] Referring again to Figure 7, a first via 164-1 is electrically coupled to the source 137 through the silicate component 166. Similarly, a second via 164-2 is electrically coupled to the source 138 through the silicate component 166. In some embodiments, the silicate component 166 may include titanium silicate, cobalt silicate, or nickel silicate. A contact etch stop layer (CESL) 109 is deposited over the isolation component 103, the gate spacer 111, and the sources 137 and 138. A first interlayer dielectric (ILD) layer 113 is formed over the CESL 109. The composition of the CESL 109 differs from that of the first ILD layer 113. Along the X direction, the thickness of the first ILD layer 113 is greater than the thickness of the CESL 109. An etch stop layer (ESL) 115 is formed above the first ILD layer 113. As shown in Figure 7, because the first ILD layer 113 needs to accommodate the active region and / or source / drain structures, its thickness along the Z direction is greater than that of the second ILD layer 117. The first ILD layer 113 and the second ILD layer 117 may include materials such as tetraethylorthosilicate (TES) oxide, undoped silicate glass, or doped silicate oxide (e.g., borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon (BSG)) and / or other suitable dielectric materials. CESL 109 and ESL 115 may include silicon nitride. A top ESL 133 is disposed above the second common contact 132 and the second ILD layer 117. A first intermetallic dielectric (IMD) layer 135 is disposed above the top ESL 133. A second IMD layer 144 is disposed above the first IMD layer 135. An ESL 145 is disposed above the second IMD layer 144. A third IMD layer 147 is disposed above the ESL 145. A plurality of first front-side metal lines 143 are disposed in the second IMD layer 144. A first contact via 141 extends from one of the first front-side metal lines 143 to the second common contact 132. A second contact via 149 extends through the third IMD layer 147 and the ESL 145 to couple to one of the front-side metal lines 143. In the illustrated embodiment, the top ESL 133 and ESL 145 may comprise silicon nitride.The first IMD layer 135, the second IMD layer 144, and the third IMD layer 147 may comprise dielectric materials such as tetraethylorthosilicate (TES) oxide, undoped silicate glass, or doped silicate (e.g., borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon (BSG)) and / or other suitable dielectric materials. The first contact via 141, the first front metal line 143, and the second contact via 149 may comprise copper (Cu), cobalt (Co), nickel (Ni), or a combination thereof.

[0025] The second common contact 132 is spaced from the second ILD layer 117, ESL 115, and first ILD layer 113 through the liner 131. The liner 131 may include silicon nitride. A central portion of the second common contact 132 extends downward into the gate isolation member 121, such that this central portion is disposed in the X direction between the source 137 and the source 138. Along the surface away from the gate isolation member 121, the back-side contact 164 is spaced from the isolation member 103, the hard mask layer 150, and the gate spacer 111 through the liner 162. Due to the etch-back process (described in detail below), a portion of the back-side contact 164 surrounding the protrusion 168 contacts the isolation member 103. Furthermore, a portion of the protrusion 168 extends into and contacts the gate isolation member 121. In some embodiments, the liner 162 and the gate isolation member 121 may include silicon nitride.

[0026] As shown in Figure 7, when viewed along the length of the active area (i.e., the Y direction), the strip-shaped portion 164B, the first guide hole 164-1, the second guide hole 164-2, and the protrusion 168 cause the back-side contact member 164 to present an M-shape or a shape similar to the letter M. In other words, it can be said that the back-side contact member 164 presents an M-shape.

[0027] Figure 8 illustrates a flowchart of a method 300 for forming a back-side contact member similar to the back-side contact member 164 described above. Method 300 is illustrative only and is not intended to limit this disclosure beyond the scope explicitly described in method 300. Additional steps may be provided before, during, and after method 300, and some described steps may be replaced, omitted, or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail herein. Method 300 is described below in conjunction with Figures 9 through 19, which are partial cross-sectional and top views of the precursor structure 200 at different manufacturing stages according to various embodiments of method 300. Since the precursor structure 200 will be fabricated into a semiconductor structure, the precursor structure 200 may be referred to herein as a semiconductor structure 200, depending on the context. For the avoidance of doubt, the X, Y, and Z directions in the figures of this disclosure are perpendicular to each other. In this document, unless explicitly described otherwise, the same reference numerals denote the same parts.

[0028] Referring to Figures 8 and 9, method 300 includes block 302, in which a precursor structure 200 is formed. Figure 9 illustrates the precursor structure 200 formed on substrate 101, which includes a front-end-of-line (FEOL) structure, a middle-end-of-line (MEOL) structure, and a back-end-of-line (BEOL) structure formed over substrate 101. In one embodiment, substrate 101 may include silicon (Si). Alternatively or additionally, substrate 101 may include another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide indium (GaInAsP); or combinations thereof. Alternatively, substrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0029] At block 302, an epitaxial stack with alternating semiconductor layers is formed over substrate 101. In some cases, the epitaxial stack may include multiple first semiconductor layers interleaved with multiple second semiconductor layers. The first semiconductor layers may include silicon (Si), and the second semiconductor layers may include silicon-germanium (SiGe). Although not explicitly shown in Figure 9, the precursor structure 200 in Figure 9 includes channel members (similar to channel member 1080 shown in Figure 4) released from the first semiconductor layers when the second semiconductor layers in the channel region are selectively removed. Gate structures are formed to surround each channel member. The end walls of the channel members are connected to source 137 and source 138. In the illustrated embodiment, the transistor is a GAA transistor, and a portion of the epitaxial stack and substrate 101 is patterned to form fin-shaped active regions. Each fin-shaped active region may include a base fin 101B formed by substrate 101 and a top formed by the epitaxial stack. Figure 9 includes a cross-sectional view through source 137 and source 138 in the source / drain regions. As shown in Figure 9, a buffer epitaxial layer 105 is disposed above the top surface of the base fin 101B, and a bottom nitride layer 107 is disposed above the buffer epitaxial layer 105. In some embodiments, the buffer epitaxial layer 105 comprises undoped silicon or undoped germanium, which is used to prevent leakage into the substrate 101. The bottom nitride layer 107 comprises silicon nitride, which is used to control the growth and stress of the source 137 or source 138.

[0030] Sources 137 and 138 can be epitaxially grown from the exposed endwalls of the channel member. In some embodiments, sources 137 and 138 may comprise silicon doped with n-type dopants (e.g., phosphorus (P) and arsenic (As)). After forming sources 137 and 138, a CESL 109 is deposited over the isolation member 103, gate spacer 111, source 137, and source 138. A first ILD layer 113 is then formed over the CESL 109. After a planarization step, an ESL 115 is formed over the planar top surface of the first ILD layer 113, and a second ILD layer 117 is formed over the ESL 115. A gate isolation member 121 is formed to divide the gate structure into two segments. As shown in Figure 9, the gate isolation member 121 also extends along the X direction between the base fins 101B. Using lithography and etching techniques, front contact openings are formed above source electrodes 137 and 138. After forming the substrate 131, a metal filler 132 is deposited above the front contact openings, and a planarization process is performed to form a second common contact 132. It is worth noting that reference numeral 132 is used to denote the metal filler and the second common contact formed by the metal filler. The second common contact is considered part of the MEOL structure. Subsequently, a front BEOL structure is formed above the second common contact 132 and the second IMD layer 117. This front BEOL structure can be a top ESL 133, a first IMD layer 135 above the top ESL 133, a second IMD layer 144 above the first IMD layer 135, an ESL 145 above the second IMD layer 144, and a third IMD layer 147 above the ESL 145. This front-side BEOL structure may also include a plurality of first front-side metal lines 143 disposed in the second IMD layer 144, a first contact guide hole 141 extending between the first front-side metal lines 143 and the second common contact 132, and a second contact guide hole 149 extending through the third IMD layer 147 and ESL 145. The composition of these BEOL structures has been described above and will not be repeated for the sake of brevity.

[0031] Referring to Figures 8, 10, and 11, method 300 includes block 304, in which the precursor structure 200 is flipped and the substrate 101 is thinned. As shown in Figure 10, the precursor structure 200 is flipped at block 304. A combination of grinding and planarization processes is then performed to thin the substrate 101 to expose the isolation member 103 and the base fin 101B. The thinning at block 304 forms a flat back surface 202, which includes the back surfaces of the isolation member 103 and the base fin 101B. In the illustrated embodiment, the thinning at block 304 does not expose the gate isolation member 121. In some alternative embodiments, the thinning at block 304 may expose the bottom of the gate isolation member 121.

[0032] Referring to Figures 8 and 12, method 300 includes block 306, in which an etch mask is formed over the back surface 202 of the precursor structure 200 (as shown in Figure 11). At block 306, a hard mask layer 150 is deposited over the back surface 202 using chemical vapor deposition (CVD). Then, a bottom antireflective coating (BAC) layer 152 is deposited over the hard mask layer 150 using flowable chemical vapor deposition (FCVD) or spin coating. An intermediate layer 154 is deposited over the BARC layer 152 using CVD, FCVD, or spin coating. In some embodiments, the intermediate layer 154 may comprise a silicon-containing inorganic polymer or silicon oxide (e.g., spin-on glass (SOG)). A photoresist layer 158 is then deposited over the intermediate layer 154. BARC layer 152, intermediate layer 154, and photoresist layer 158 can be collectively referred to as three photoresist layers. Then, lithography and etching processes are performed to pattern the photoresist layer 158, forming a patterned photoresist layer 158. As shown in Figure 12, the patterned photoresist layer 158 includes an opening 1580. The patterned photoresist layer 158 will be used as an etching mask in subsequent operations.

[0033] Referring to Figures 8 and 13, method 300 includes block 308, in which a contact back-side opening 160 is formed. At block 308, an etching process 250 is performed to etch the precursor structure 200 using a patterned photoresist layer 158 as an etching mask. The etching process 250 is a dry etching process that etches silicon, silicon nitride, and silicon oxide at different rates. The etching process 250 etches silicon at a first rate, silicon nitride at a second rate, and silicon oxide at a third rate. In the illustrated embodiment, the first rate is greater than the second rate, and the second rate is greater than the third rate. This etch rate configuration of the etching process 250 is not straightforward. As shown in Figures 12 and 13, the etching process 250 needs to etch through the base fin 101B to at least reach the bottom nitride layer 107, while the sidewalls of the base fin 101B are covered by the isolation member 103. This means that etching process 250 is intended to etch the base fin 101B and stop at the bottom nitride layer 107 without substantially damaging the isolation member 103 and the hard mask layer 150. In the illustrated embodiment, the base fin 101B comprises silicon (Si), the isolation member 103 comprises silicon oxide, and the hard mask layer 150 and the bottom nitride layer 107 comprise silicon nitride. In some embodiments, etching process 250 may include the use of a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), oxygen (O2), or hydrogen (H2). In some embodiments shown in Figure 13, etching process 250 destroys the isolation member 103 above the gate isolation member 121 and etches the gate isolation member 121. As shown in Figure 13, a tapered groove 161 may be formed in the gate isolation member 121.

[0034] Referring to Figures 8 and 14, method 300 includes block 310, in which a liner 162 is deposited in the back-side opening 160 of the contact. In some embodiments, the liner 162 may include silicon nitride and may be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD) processes. As shown in Figure 14, the liner 162 is compliantly deposited over the back-side opening 160 of the contact. In the illustrated embodiment, the liner 162 is in contact with a hard mask layer 150, an isolation member 103, a bottom nitride layer 107, a gate spacer 111, and a gate isolation member 121.

[0035] Referring to Figures 8 and 15, method 300 includes block 312, in which anisotropic etching is performed on the substrate 162. At block 310, source 137 and source 138 are not exposed in the contact back opening 160. Anisotropic etching is performed at block 312 to etch the substrate 162 and the remaining bottom nitride layer 107 to expose source 137 and source 138. In some embodiments, the anisotropic etching at block 312 may include the use of a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), or sulfur hexafluoride (SF6)), but is performed at a lower temperature to achieve greater directionality. As shown in Figure 15, upon completion of the operation of block 312, source 137 and source 138 are exposed in the contact back opening 160, while the sidewalls of the contact back opening 160 remain covered by the substrate 162. That is, the liner 162 on the top-facing surface is removed. In Figure 15, the top-facing surface may include the top surface of the hard mask layer 150, the top surface of the isolation member 103 around the tapered recess 161, and the surface of the tapered recess 161.

[0036] Referring to Figures 8 and 16, method 300 includes block 314, in which a metal filler 164 is deposited over a backside opening 160 of the contact. In some embodiments, the metal filler 164 may include titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), or a combination thereof. In an exemplary process, titanium is first deposited on the backside opening 160 of the contact to connect with sources 137 and 138. An annealing process is then performed to promote the reaction between silicon and titanium in sources 137 and 138, forming a silicide component 166. After the silicide component 166 is formed, a selective etching process may be performed to remove unreacted titanium. In some alternative embodiments, excess titanium is not removed. The metal filler 164 is then deposited over the backside opening 160 of the contact using a physical vapor deposition (PVD) or CVD process.

[0037] Referring to Figures 8 and 17, method 300 includes block 316, in which the precursor structure 200 is planarized to form a back-side contact 164. At block 316, a planarization process (e.g., chemical mechanical polishing, CMP) is performed to remove excess metal filler 164 above the hard mask layer 150 to form the back-side contact 164. It is noteworthy that reference numeral 164 is used to denote both the metal filler and the back-side contact. As shown in Figure 17, the hard mask layer 150, the liner 162, and the back-side contact 164 are exposed in the newly formed planar back-side surface. After the operation at block 316 is completed, the back-side contact 164 is substantially formed. As described above in conjunction with Figure 7, the back-side contact element 164 includes a strip-shaped portion 164B, a first guide hole 164-1 continuously extending from the strip-shaped portion 164B, a second guide hole 164-2 continuously extending from the strip-shaped portion 164B, and an intermediate protrusion 168 continuously extending from the strip-shaped portion 164B. When viewed along the length direction of the active area (i.e., the Y direction), the strip-shaped portion 164B, the first guide hole 164-1, the second guide hole 164-2, and the protrusion 168 cause the back-side contact element 164 to present an M-shape or a shape similar to the letter M. The intermediate protrusion 168 is formed when the metal filler 164 fills the tapered groove 161 shown in Figure 15. In terms of conductivity, the back-side contact 164 has a higher conductivity than the silicate component 166, and the silicate component 166 has a higher conductivity than the source 137 or the source 138.

[0038] Referring to Figures 8, 18, and 19, method 300 includes block 318, in which a further BEOL structure is formed. This further BEOL structure includes a back-side insulating layer 170 and back-side metal lines 172 disposed within the back-side insulating layer 170. In some embodiments, the back-side insulating layer 170 may include, for example, tetraethylorthosilicate (TES) oxide, undoped silicate glass, or doped silicate oxide (e.g., borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)) and / or other suitable dielectric materials. The back-side insulating layer 170 may be deposited using FCVD or spin coating. After depositing the back-side insulating layer 170, a back-side line trench is formed in the back-side insulating layer 170 to expose the bottom surface of the strip portion 164B of the back-side contact contact 164. A barrier layer 171 and a metal filler are then deposited over the back-side line trench. A planarization process (e.g., CMP process) is then performed to remove excess metal filler and barrier layer 171 to form a back-side metal line 172. In some embodiments, the barrier layer 171 may include titanium nitride, tantalum nitride, or tungsten nitride. The metal filler for the back-side metal line 172 may include copper (Cu), cobalt (Co), aluminum (Al), nickel (Ni), or a combination thereof. Figure 19 illustrates a partial cross-sectional view of the precursor structure 200 with the back-side interconnect structure at the bottom and the front-side interconnect structure at the top. In the orientation shown in Figure 19, source electrode 137 is disposed above the first guide hole 164-1, and a siliconized component 166 is provided at the interface between source electrode 137 and the first guide hole 164-1. Source electrode 138 is disposed above the second guide hole 164-2, and a siliconized component 166 is provided at the interface between source electrode 138 and the second guide hole 164-2. The second common contact 132 is a front-side source / drain contact, while the back-side contact contact 164 is a back-side source / drain contact.

[0039] Referring again to Figure 19. In the illustrated embodiment, measured from the interface between the strip portion 164B and the back metal line 172, the first via 164-1 and the second via 164-2 have a first depth D1, the intermediate protrusion 168 has a second depth D2, and the strip portion 164B has a third depth D3. The first depth D1 is greater than the second depth D2, and the second depth D2 is greater than the third depth D3. In some cases, the ratio of the second depth D2 to the first depth D1 is between about 0.3 and about 0.8. Because the etching process 250 etches silicon nitride faster than it etches silicon oxide, the ratio of the third depth D3 to the second depth D2 is between about 0.3 and about 0.8. Because the etching process 250 etches silicon faster than it etches silicon oxide, the ratio of the third depth D3 to the first depth D1 is between about 0.15 and about 0.5.

[0040] Figures 20 through 25 illustrate alternative structures for the back-side contact 164 formed using the method 300 described above. Figures 20 through 23 illustrate alternative embodiments in which the back-side contact 164 is not fully connected to the back-side metal wire 172 along the X direction, and at least one protrusion of the back-side contact 164 overhangs the back-side metal wire 172. That is, along the X direction, the size of the strip portion 164B is larger than the size of the back-side metal wire 172. For example, Figure 20 illustrates that the back-side contact 164 includes a first protrusion 1642 that does not perpendicularly overlap with the back-side metal wire 172. Instead, the first protrusion 1642 extends between the insulating member 103 and the back-side insulating layer 170. The sidewalls of the first protrusion 1642 are spaced apart from the hard shielding layer 150 through the liner 162. The first protrusion 1642 (represented by a dashed rectangle in the top view shown in Figure 21) extends in the X direction beyond the edge of the back metal wire 172. For example, Figure 22 illustrates a back contact member 164 including a first protrusion 1642 and a second protrusion 1644 that do not perpendicularly overlap with the back metal wire 172. Instead, both the first and second protrusions 1642 extend in the Z direction (i.e., vertically) between the insulating member 103 and the back insulating layer 170. The sidewalls of either the first or second protrusion 1642 are spaced apart from the rigid shielding layer 150 through the liner 162. The first and second protrusions 1642 (represented by dashed rectangles in the top view shown in Figure 23) extend in the X direction beyond the edge of the back metal wire 172.

[0041] Figure 24 illustrates an alternative embodiment in which the through-back contact 1640 extends through the gate isolation member 121 (as shown in Figure 19) to merge with or engage with the second common contact 132. In this alternative embodiment, the through-back contact 1640 is still M-shaped, but has a different profile than the back contact 164 shown in Figures 19, 20, or 22. As shown in Figure 24, the through-back contact 1640 includes a strip portion 164B disposed in the hard shield layer 150, a fin portion 164F continuously extending from the strip portion 164B, a first short fin 164-3 extending from the fin portion 164F, a second short fin 164-4 extending from the fin portion 164F, and an intermediate platform 1680 disposed on the fin portion 164F. The strip-shaped portion 164B, the first short fin 164-3, the second short fin 164-4, and the intermediate platform 1680 cause the through-through back contact member 1640 to have an M-shape. In some embodiments, the through-through back contact member 1640 includes a first protrusion 1642 and a second protrusion 1644 overhanging above the back metal wire 172. The first protrusion 1642 and the second protrusion 1644 (indicated by dashed rectangles in the top view shown in Figure 25) extend in the X direction beyond the edge of the back metal wire 172.

[0042] In one exemplary embodiment, this disclosure provides a semiconductor structure. The semiconductor structure includes a back-side metal line disposed in a back-side insulating layer and a back-side contact structure. The back-side contact structure includes a strip-shaped portion disposed on the back-side metal line, a first via extending from the strip-shaped portion, a second via extending from the strip-shaped portion, and a protrusion disposed between the first via and the second via. The semiconductor structure further includes a first source / drain component located above the first via, a second source / drain component located above the second via, a gate isolation component disposed between the first via and the second via, and a siliconized component disposed between the first via and the first source / drain component. The protrusion extends into the gate isolation component. The conductivity of the first via is greater than the conductivity of the siliconized component.

[0043] In some embodiments, the semiconductor structure further includes a front contact component disposed above the first source / drain component and the second source / drain component. A portion of the front contact component extends between the first source / drain component and the second source / drain component to connect with a gate isolation component. In some embodiments, a portion of the strip-shaped portion overhangs above a back-side metal line. In some embodiments, the strip-shaped portion of the back-side contact structure, the first via, the second via, and the protrusion form an M-shape. In some embodiments, the semiconductor structure further includes an isolation component extending along a plurality of sidewalls of the first via and a plurality of sidewalls of the second via. A portion of the isolation component is spaced from the first via through a liner, and another portion of the isolation component is connected to the first via. In some embodiments, the isolation component is formed of an oxide-based material. In some embodiments, a portion of the strip-shaped portion is disposed between a back-side insulating layer and the isolation component. In some embodiments, the back-side insulating layer is spaced from the isolation component through a hard mask layer. In some embodiments, the sidewalls of the strip-shaped portion are spaced from the hard mask layer through a liner. In some embodiments, the hard mask layer comprises silicon nitride.

[0044] Another exemplary embodiment disclosed herein relates to a semiconductor structure. The semiconductor structure includes a back-side insulating layer, a back-side metal line disposed in the back-side insulating layer, a hard mask layer on the back-side insulating layer, and a back-side contact structure disposed above the back-side metal line. The back-side contact structure includes a strip-shaped portion disposed in the hard mask layer, a first via extending from the strip-shaped portion, a second via extending from the strip-shaped portion, and a protrusion disposed in one direction between the first and second vias. The semiconductor structure further includes a first source / drain component located above the first via, a second source / drain component located above the second via, a gate isolation component disposed in the direction between the first and second source / drain components, an isolation component extending along multiple sidewalls of the first and second vias, a contact etch stop layer located above the isolation component, and an interlayer dielectric layer located above the contact etch stop layer. The isolation component comprises an oxide-based material. The composition of the contact etch stop layer differs from the composition of the interlayer dielectric layer. The strip-shaped portion of the back contact structure, the first guide hole, the second guide hole, and the protrusion form an M-shape.

[0045] In some embodiments, the protrusion extends partially into the gate isolation member. In some embodiments, a first via is electrically coupled to a first source / drain member through a first silicide member, and a second via is electrically coupled to a second source / drain member through a second silicide member. In some embodiments, the semiconductor structure further includes a front contact member disposed above the first source / drain member and the second source / drain member. A portion of the front contact member extends along the direction between the first source / drain member and the second source / drain member to engage with the gate isolation member. In some embodiments, a portion of the strip-shaped portion overhangs above the back metal line.

[0046] Another exemplary embodiment disclosed herein relates to a method for forming a semiconductor structure. The method includes providing a precursor structure. The precursor structure includes a first source / drain component and a second source / drain component located above a front-side source / drain contact; a first base fin located above the first source / drain component; a second base fin located above the second source / drain component; an isolation component disposed between the first base fin and the second base fin and extending along a plurality of sidewalls of the first base fin and the second base fin; and a gate isolation component disposed between the first base fin and the second base fin. The method further includes depositing a hard mask layer over the isolation component, the first base fin, and the second base fin; forming a patterned photoresist layer over the hard mask layer; using the patterned photoresist layer as an etching mask; etching the precursor structure and the hard mask layer to form a back-side opening of the contact, the back-side opening exposing the isolation component and the gate isolation component; depositing a liner over the back-side opening of the contact; after depositing the liner, performing anisotropic etching to expose the first source / drain component and the second source / drain component; depositing a metal filler in the back-side opening of the contact; and planarizing the metal filler to expose the hard mask layer and form a back-side contact. The isolation component comprises an oxide-based material. A silicon layer is disposed between the first source / drain component and the front source / drain contact. The conductivity of the front source / drain contact is greater than the conductivity of the silicon layer.

[0047] In some embodiments, the etching step of the precursor structure etches silicon at a first rate, etches silicon nitride at a second rate, and etches silicon oxide at a third rate, wherein the first rate is greater than the second rate, and the second rate is greater than the third rate. In some embodiments, the back-side contact element is M-shaped. In some embodiments, the hard mask layer includes silicon nitride. In some embodiments, the etching step of the precursor structure forms a groove in the gate isolation component.

[0048] The components of several embodiments are summarized above to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0049] 10: SRAM cell 12: First Inverter 14: Second Inverter 20, 22, 24, 26: Gate structure 30, 34: P-type well, P-trap 32: n-type well, N-type trap 40, 42, 44, 46: Fin-like vertical stacking 100: Unit 4 101:Substrate 101B: Base fins 102F, 104F, 106F: Front abutment contact element 103: Isolation Components 105: Buffer epitaxial layer 107: Bottom nitride layer 1080: Channel component 109: Contact Etching Stop Layer, CESL 111: Gate spacer 113, 117: Interlayer dielectric layer, ILD layer 115, 145: Etching Stop, ESL 120, 124, 137, 138: Source 121: Gate isolation component 122: Jiji 130, 134, 136: Common contact components 131: Lining 132: Metal filler, common contact 133: Top ESL 135, 144, 147: Intermetallic dielectric layer, IMD layer 139: Silicon layer 141, 149: Contact guide holes 143: Front metal strip 150: Hard mask layer 152: Bottom anti-reflective coating, BARC layer 154: Intermediate Layer 158: Photoresist layer, patterned photoresist layer 1580: Opening 160: Opening on the back side of the contact 161: Conical groove 162: Lining 164: Metal filler, back-side contact element 164-1, 164-2: Guide holes 164-3, 164-4: Short fins 164B: Strip-shaped portion 164F: Fin section 1640: Through-the-back contact element 1642, 1644: Highlighted parts 1680: Central High Platform 166: Silicone components 168: Protrusion 170: Backside insulation layer 171: Barrier Layer 172: Backside metal wire 200: Precursor structure, semiconductor structure 202: Backside surface 250: Etching process 300: Method 302, 304, 306, 308, 310, 312, 314, 316, 318: Squares BL: Bitline BLB: Complementary Bit Line D1, D2, D3: Depth MA1, MA2: Mirror axis PD1: First pull-down transistor PD2: Second pull-down transistor PG1: First through-gate transistor PG2: Second transistor PU1: First pull-up transistor PU2: Second pull-up transistor SN1: First storage node SNB1: First Complementary Storage Node Vdd: Positive power supply voltage Vss: Grounding potential WL: Character Line W1, W2: Width

Claims

1. A semiconductor structure, comprising: A back-side metal wire is set in a back-side insulating layer; A back-side contact structure includes: a strip-shaped portion disposed on the back-side metal line; a first via extending from the strip-shaped portion; a second via extending from the strip-shaped portion; and a protrusion disposed between the first via and the second via; a first source / drain component located above the first via; a second source / drain component located above the second via; a gate isolation component disposed between the first via and the second via; and a siliconized component disposed between the first via and the first source / drain component, wherein the protrusion extends into the gate isolation component, and wherein a conductivity of the first via is greater than a conductivity of the siliconized component.

2. The semiconductor structure as described in claim 1, further comprising: A front contact component is disposed above the first source / drain component and the second source / drain component, wherein a portion of the front contact component extends between the first source / drain component and the second source / drain component to connect with the gate isolation component.

3. The semiconductor structure as described in claim 1, further comprising: An isolation component extends along a plurality of sidewalls of the first guide hole and a plurality of sidewalls of the second guide hole, wherein a portion of the isolation component is separated from the first guide hole by a liner, and wherein another portion of the isolation component is in contact with the first guide hole.

4. The semiconductor structure as described in any one of claims 1 to 3, wherein a portion of the strip portion is disposed between the back insulating layer and the insulating member.

5. The semiconductor structure as described in claim 3, wherein the back-side insulating layer is separated from the isolation component by a hard mask layer.

6. The semiconductor structure as claimed in claim 5, wherein one sidewall of the strip portion is separated from the hard mask layer through the liner.

7. A semiconductor structure comprising: One back-side insulating layer; A back-side metal wire is disposed in the back-side insulation layer; A rigid shielding layer is located on the back insulating layer; A back-side contact structure is disposed above a back-side metal line. The back-side contact structure includes: a strip-shaped portion disposed within a hard mask layer; a first via extending from the strip-shaped portion; a second via extending from the strip-shaped portion; and a protrusion disposed in a direction between the first and second vias; a first source / drain component located above the first via; a second source / drain component located above the second via; a gate isolation component disposed in the direction between the first and second source / drain components; an isolation component extending along multiple sidewalls of the first and second vias; a contact etch stop layer located above the isolation component; and an interlayer dielectric layer located above the contact etch stop layer. The isolation component comprises an oxide-based material, and a composition of the contact etch stop layer differs from the composition of the interlayer dielectric layer. The strip-shaped portion of the back contact structure, the first guide hole, the second guide hole, and the protrusion form an M-shape.

8. The semiconductor structure as claimed in claim 7, wherein the first via is electrically coupled to the first source / drain component through a first silicide component, and wherein the second via is electrically coupled to the second source / drain component through a second silicide component.

9. The semiconductor structure as described in claim 7, further comprising: A front contact component is disposed above the first source / drain component and the second source / drain component, wherein a portion of the front contact component extends along the direction between the first source / drain component and the second source / drain component to connect with the gate isolation component.

10. The semiconductor structure as claimed in claim 7, wherein a portion of the strip portion overhangs the back metal line.

11. A method for forming a semiconductor structure, comprising: A precursor structure is provided, comprising: a first source / drain component and a second source / drain component, located above a front source / drain contact; a first base fin, located above the first source / drain component; a second base fin, located above the second source / drain component; an isolation component disposed between the first base fin and the second base fin, and extending along a plurality of sidewalls of the first base fin and the second base fin; and a gate isolation component disposed between the first base fin and the second base fin; a hard mask layer is deposited above the isolation component, the first base fin, and the second base fin; a patterned photoresist layer is formed above the hard mask layer; the patterned photoresist layer is used as an etch mask to etch the precursor structure and the hard mask layer to form a back-side opening of a contact, the back-side opening of which exposes the isolation component and the gate isolation component; A liner is deposited above the back opening of the contact; after depositing the liner, an anisotropic etching is performed to expose the first source / drain component and the second source / drain component; a metal filler is deposited in the back opening of the contact; and the metal filler is planarized to expose the hard mask layer and form a back contact contact, wherein the isolation component comprises an oxide-based material, wherein a silicon layer is disposed between the first source / drain component and the front source / drain contact, wherein a conductivity of the front source / drain contact is greater than a conductivity of the silicon layer.

12. The method for forming a semiconductor structure as claimed in claim 11, wherein the etching step of the precursor structure etches silicon at a first rate, etches silicon nitride at a second rate, and etches silicon oxide at a third rate, wherein the first rate is greater than the second rate, and wherein the second rate is greater than the third rate.

13. A method for forming a semiconductor structure as described in claim 11, wherein the hard mask layer comprises silicon nitride.

14. The method of forming a semiconductor structure as claimed in claim 11, wherein the etching step of the precursor structure forms a groove in the gate isolation component.

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