Semiconductor device and methods of forming the same

Abstract

This disclosure describes a semiconductor device with an air spacer having pads to protect a source / drain (S / D) structure. The semiconductor device includes an S / D structure on a substrate, a gate structure adjacent to the S / D structure on the substrate, a gate cover structure on the gate structure, a contact structure adjacent to the gate structure on the S / D structure, pads on the sidewall surfaces of the gate cover structure and the top surface of the S / D structure, and a spacer layer on the sidewall surfaces of the contact structure. An air gap is formed between the spacer layer and the pads.

Claims

1. A semiconductor device comprising: a source / drain (S / D) structure on a substrate; a gate structure on the substrate and adjacent to the source / drain structure; a gate cover structure on the gate structure; a contact structure on the source / drain structure and adjacent to the gate structure; a pad on a plurality of sidewall surfaces of the gate cover structure and a plurality of top surfaces of the source / drain structure; and a spacer layer on a plurality of sidewall surfaces of the contact structure, wherein an air gap is formed between the spacer layer and the pad, wherein a top portion of the pad and a top portion of the spacer layer form an interface above the air gap.

2. The semiconductor device as claimed in claim 1, wherein the spacer layer is in contact with the source / drain structure and the pad.

3. The semiconductor device as claimed in claim 1, wherein the spacer layer, the pad, the contact structure, and a plurality of top surfaces of the gate cover structure are coplanar.

4. The semiconductor element as claimed in claim 1, further comprising a gate spacer located on the sidewall surfaces of the gate structure, wherein the spacer contacts a plurality of sidewall surfaces of the gate spacer.

5. The semiconductor element as claimed in claim 1, wherein the height of a merged portion of the pad ranges from about 2 nm to about 25 nm.

6. The semiconductor element as claimed in claim 5, wherein the height of the merged portion of the pad is less than the thickness of the gate cover structure.

7. A semiconductor device comprising: a channel structure on a substrate; a source / drain (S / D) structure contacting the channel structure; a gate structure on the channel structure; a gate spacer on a plurality of sidewall surfaces of the gate structure; a contact structure on the source / drain structure and adjacent to the gate structure; a pad on a plurality of top surfaces of the source / drain structure and the sidewall surfaces of the gate structure; and a spacer layer on a plurality of sidewall surfaces of the contact structure, wherein the pad and the spacer layer form an air gap between the gate structure and the contact structure, wherein a top portion of the pad and a top portion of the spacer layer merge over the air gap to form an interface.

8. A method of forming a semiconductor device, comprising: forming an opening located above and adjacent to a source / drain (S / D) structure and a gate structure and a gate cover structure, wherein the gate cover structure is located on the gate structure; forming a pad and a first dielectric layer in the opening, wherein the first dielectric layer and the source / drain structure are separated by the pad; forming a second dielectric layer on a plurality of sidewall surfaces of the first dielectric layer, wherein the second dielectric layer contacts the first dielectric layer, the pad, and the source / drain structure; forming a source / drain contact structure in the opening and contacting the source / drain structure; removing the first dielectric layer to form an air gap; and sealing a top portion of the air gap, wherein the air gap is surrounded by the second dielectric layer and the pad, wherein sealing the top portion of the air gap includes merging a top portion of the pad and a top portion of the second dielectric layer above the air gap to form an interface.

9. The method of claim 8, wherein forming the pad and the first dielectric layer in the opening comprises: depositing the pad in the opening and on the gate cover structure; depositing the first dielectric layer on the pad; and removing the pad and the first dielectric layer in the opening and on the gate cover structure by a directional etching process.

10. The method of claim 8, wherein sealing the top portion of the air gap comprises implanting a plurality of ions into the gate cover structure to expand the gate cover structure such that the pad adheres to the second dielectric layer of the top portion of the air gap.

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