Semiconductor device

Abstract

A semiconductor device includes: a substrate, a semiconductor stack, a capping layer, a source electrode and a drain electrode, and a gate. The semiconductor stack is located on the substrate. The capping layer is located on the substrate and includes: an intrinsic capping layer, an etch stop layer, and an n-type capping layer. An opening extends through the capping layer. The source electrode and the drain electrode are located on the semiconductor stack. The gate is located in the opening and between the source electrode and the drain electrode. A first distance between the gate and a first portion of the n-type capping layer adjacent to the drain electrode is greater than a second distance between the gate and a second portion of the n-type capping layer adjacent to the source electrode.

Description

[Technical Field]

[0001] This invention relates to a high electron mobility transistor (HEMT) structure, and more particularly to a high electron mobility transistor structure having an asymmetric groove structure. [Previous Technology]

[0002] High electron mobility transistors are widely used in high-power semiconductor devices due to their high breakdown voltage and high output voltage.

[0003] High electron mobility transistor structures can be stacked with different III-V group semiconductor layers and heterojunctions can be formed at their interfaces. Due to the band bending at the heterojunction, potential wells can be formed at the bent conduction band, thereby forming two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) in the potential wells.

[0004] Although the existing high electron mobility transistor structure is sufficient for the original purpose, it is not satisfactory in all aspects and needs to be improved. [Summary of the Invention]

[0005] This embodiment of the invention provides a semiconductor structure, including: a substrate, a semiconductor stack, a capping layer, a source electrode, a drain electrode, and a gate. The semiconductor stack is located on the substrate. The capping layer is located on the substrate. The capping layer includes: an intrinsic capping layer, an etch stop layer, and an n-type capping layer. An opening passes through the capping layer. The source electrode and the drain electrode are located on the semiconductor stack. The gate is located in the opening and between the source electrode and the drain electrode. A first distance between the gate and a first portion of the n-type capping layer adjacent to the drain electrode is greater than a second distance between the gate and a second portion of the n-type capping layer adjacent to the source electrode.

[0006] This embodiment of the invention provides a semiconductor structure, including: a substrate, a semiconductor stack, a capping layer, a source electrode, a drain electrode, and a gate. The semiconductor stack is located on the substrate. The capping layer is located on the semiconductor stack and has a top opening and a bottom opening. The bottom opening overlaps with the top opening. The source electrode and the drain electrode are located on the semiconductor stack. The gate is located between the top opening and the bottom opening, between the source electrode and the drain electrode, and is separated from the capping layer. A first distance between the gate and the capping layer on the drain side in the top opening is greater than a second distance between the gate and the capping layer on the source side in the top opening, and a third distance between the gate and the capping layer on the drain side in the bottom opening is substantially equal to a fourth distance between the gate and the capping layer on the source side in the bottom opening.

Implementation Method

[0008] The following disclosure provides many different embodiments or examples to implement different features of this invention. The following disclosure describes specific examples of the various components and their arrangements to simplify the explanation. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the invention describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or it may include embodiments where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the embodiments of the invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0009] Furthermore, spatially relative terms may be used, such as "below," "lower," "above," "higher," and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one or more elements or features in the illustration and another element or feature(s). These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the illustration. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the turn.

[0010] Here, the terms "about," "approximately," and "roughly" generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0011] Although the steps in some embodiments are performed in a specific order, these steps may also be performed in other logical orders. In different embodiments, some of the steps may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor structure in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.

[0012] This embodiment of the invention provides a high electron mobility transistor structure. The high electron mobility transistor structure may include three capping layers, but is not limited thereto. Two grooves may be formed in the three capping layers. By utilizing the asymmetrical top groove and the symmetrical bottom groove, capacitance can be reduced and device performance can be enhanced. By utilizing the protective layer in the epitaxial three capping layers, surface traps can be reduced.

[0013] Figures 1A-1E illustrate cross-sectional views of various stages in forming the semiconductor structure 10a according to some embodiments.

[0014] According to some embodiments, as shown in Figure 1A, a substrate 102 is provided. The substrate 102 may include a semiconductor substrate, a glass substrate, a ceramic substrate, a sapphire substrate, a semiconductor-on-insulator (SOI) substrate, or a combination thereof, but is not limited thereto. The substrate 102 may include III-V compound semiconductors, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof, but is not limited thereto. The substrate 102 may include group IV semiconductors, such as Si or Ge. The substrate 102 may include doped or undoped materials, such as undoped GaAs, but is not limited thereto.

[0015] Next, according to some embodiments, as shown in Figure 1A, a semiconductor stack 103 may be formed on the substrate 102. According to some embodiments, as shown in Figure 1A, the semiconductor stack 103 may include epitaxial layers, such as a buffer layer 104, a channel layer 106, and a carrier supply layer 108. The buffer layer 104 may be formed on the substrate 102, and the channel layer 106 may be formed on the buffer layer 104. The carrier supply layer 108 may be formed on the channel layer 106. The carrier supply layer 108 may be a single-layer or multi-layer structure. The carrier supply layer 108 may have a wider bandgap than the channel layer 106. In some embodiments, the substrate 102 includes GaAs, and the buffer layer 104 includes at least one of GaAs and AlGaAs. In some embodiments, the channel layer 106 comprises at least one of GaAs and InGaAs, and the carrier supply layer 108 comprises at least one of AlGaAs, AlGaAsP, InAlGaAs, InGaP, InGaPAs, AlInGaP, or a combination thereof, but is not limited thereto. In some embodiments, the buffer layer 104, the channel layer 106, and the carrier supply layer 108 are formed by molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof.

[0016] Since different materials can be used to form the channel layer 106 and the carrier supply layer 108, their band gaps may be different. A heterojunction can be formed at the interface between the channel layer 106 and the carrier supply layer 108. The energy band may be bent at the heterojunction, and an energy well may be formed deep within the conduction band. The electrons provided by the carrier supply layer may be confined in the quantum well. Therefore, a two-dimensional electron gas (2DEG) may be formed at the interface between the channel layer 106 and the carrier supply layer 108, and the two-dimensional electron gas can generate a conductive current.

[0017] Next, according to some embodiments, as shown in Figure 1A, a capping layer 110 is formed over the semiconductor stack 103. In some embodiments, the capping layer 110 may include a protective layer 112, an etch stop layer 114, and / or a top capping layer 116. In some embodiments, the protective layer 112 is formed over the carrier supply layer 108, the etch stop layer 114 is formed over the protective layer 112, and the top capping layer 116 is formed over the etch stop layer 114, but this is not a limitation.

[0018] In some embodiments, the protective layer 112 may be undoped or lightly doped GaAs. The protective layer 112 may be referred to as the intrinsic capping layer 112. In some embodiments, the etch stop layer 114 may include n-type doped AlAs. In some embodiments, the top capping layer 116 may include n-type doped GaAs. The top capping layer 116 may also be referred to as the n-type capping layer 116. The protective layer 112, the etch stop layer 114, and the top capping layer 116 may be formed using molecular beam epitaxy, metal-organic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or combinations thereof.

[0019] In some embodiments, the doping concentration of the protective layer 112 may be less than 10¹⁸ cm⁻³, such as 10¹⁵ cm⁻³, 10¹⁶ cm⁻³, or 10¹⁷ cm⁻³. With a lower concentration or the inherent protective layer 112, the depletion region between the gate structure and the drain structure may be extended.

[0020] In some embodiments, the thickness of the protective layer 112 is in the range of about 5 Å to about 100 Å (5 Å ≤ thickness ≤ 100 Å), for example 10 Å, 20 Å, 30 Å, 50 Å, or 70 Å. In some embodiments, the thickness of the etch stop layer 114 is in the range of about 5 Å to about 100 Å (5 Å ≤ thickness ≤ 100 Å), for example 10 Å, 20 Å, 30 Å, 50 Å, or 70 Å. In some embodiments, the thickness of the top cover layer 116 is in the range of about 100 Å to about 1000 Å (100 Å ≤ thickness ≤ 1000 Å), for example 150 Å, 200 Å, 300 Å, 500 Å, or 700 Å. In some embodiments, the ratio of the thickness of the protective layer 112 to the thickness of the top cover layer 116 is about 1 to 20 (1 ≦ ratio ≦ 20), for example 2, 5, 8, 10, or 12, but is not limited thereto.

[0021] Next, according to some embodiments, as shown in Figure 1A, an opening 118 is formed in the capping layer 116, and the top surface of the etch stop layer 114 is exposed in the opening 118. The capping layer 116 may be patterned by a patterning process. The patterning process may include a lithography process and an etching process. Examples of lithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may be a dry etching process, a wet etching process, or a combination thereof.

[0022] In some embodiments, after the opening 118 is formed, the top surface of the capping layer 116 may be wider than the bottom surface of the capping layer 116. The opening 118 may gradually widen downwards, but is not limited thereto. In other embodiments, the opening 118 may gradually widen upwards.

[0023] Next, according to some embodiments, as shown in Figure 1B, a photoresist layer 120 is formed on the capping layer 110, and an opening 122 is formed in the photoresist layer 120. In some embodiments, the opening 122 is formed through the opening 118, and the top surface of the etch stop layer 114 is exposed in the opening 122. In some embodiments, the opening 122 is asymmetrical relative to the capping layer 116, that is, the distances from the two sides of the opening 122 to the capping layer 116 may not be equal, or the opening 122 may not be located in the center of the opening 118.

[0024] Subsequently, according to some embodiments, as shown in Figure 1C, a portion of the etch stop layer 114 may be removed from the opening 122, and the protective layer 112 may also be removed from the opening 122. In some embodiments, the etch stop layer 114 and the protective layer 112 may be laterally etched. Thus, the opening 122 may extend below the photoresist layer 120, but is not limited thereto. In some embodiments, the etch stop layer 114 and the protective layer 112 may be symmetrically removed, but is not limited thereto. In some embodiments, the sidewalls of the etch stop layer 114 and the protective layer 112 may be substantially aligned. The etch stop layer 114 and the protective layer 112 may be removed using a dry etching process (e.g., reactive ion etching (RIE), anisotropic plasma etching method), a wet etching process, or a combination thereof.

[0025] In some embodiments, the width of the opening 122 through the protective layer 112 is narrower than the width of the opening 118 through the top cover layer 116.

[0026] Next, according to some embodiments, as shown in Figure 1D, a gate electrode 124 is formed through the capping layer 110. The gate electrode 124 may include molybdenum (Mo), tungsten (W), tungsten-silicide (WSi), titanium (Ti), tungsten-titanium (TiW), iridium (Ir), palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), chromium (Cr), ruthenium (Ru), osmium (Os), rhodium (Rh), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), rhenium (Re), other available conductive materials, or combinations thereof. The gate electrode 124 may be formed using physical vapor deposition (PVD) processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (CVD) processes (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition (ALD), other suitable processes, or combinations thereof. In some embodiments, the gate electrode 124 is formed using an evaporation process.

[0027] Next, according to some embodiments, as shown in Figure 1D, the photoresist layer 120 is removed, and then the exposed etch stop layer 114 is removed. In some embodiments, a portion of the top surface of the protective layer 112 may be exposed. The photoresist layer 120 and the etch stop layer 114 may be removed in an ashing process, one or more other available processes, or a combination thereof.

[0028] Next, according to some embodiments, as shown in Figure 1E, a source electrode 126 and a drain electrode 128 may be formed on the semiconductor stack 103. For example, the source electrode 126 and the drain electrode 128 may be located on the capping layer 116. The source electrode 126 and the drain electrode 128 may respectively comprise Ti, Al, W, Au, Pd, Au, Ge, Ni, Mo, Pt, other suitable metals, alloys thereof, or combinations thereof. The source electrode 126 and the drain electrode 128 may be formed by physical vapor deposition processes (e.g., resistance heating evaporation, electron beam evaporation, or sputtering), chemical vapor deposition (e.g., low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition), electroplating, atomic layer deposition, other suitable processes, or combinations thereof. In some embodiments, the source electrode 126 and the drain electrode 128 are formed by an evaporation process.

[0029] Next, according to some embodiments, as shown in Figure 1E, a passivation layer 130 is formed on the substrate 102. In some embodiments, the passivation layer 130 may be formed on the gate electrode 124 and located in the opening 122. The passivation layer 130 can provide effective environmental shielding, protecting the device from moisture.

[0030] The passivation layer 130 may include silicon nitride, aluminum oxide, silicon oxide, silicon oxynitride, aluminum nitride, hafnium oxide, one or more other suitable passivation materials, or combinations thereof. In some embodiments, the passivation layer 130 includes silicon nitride. The passivation layer 130 may be a single-layer or multi-layer structure. The passivation layer 130 may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0031] Because the opening 122 is asymmetrical relative to the capping layer 116, the distance 116d between the gate electrode 124 and the capping layer 116 of the adjacent drain electrode 128 can be greater than the distance 116s between the gate electrode 124 and the capping layer 116 of the adjacent source electrode 126 (116d > 116s). A longer distance 116d between the gate electrode 124 and the capping layer 116 of the adjacent drain electrode 128 can reduce capacitance and enhance device performance. In some embodiments, the distance 116d can be defined as the shortest distance between the bottom 124b of the gate electrode 124 and the capping layer 116 of the adjacent drain electrode 128. The distance 116s can be defined as the shortest distance between the bottom 124b of the gate electrode 124 and the capping layer 116 of the adjacent source electrode 126.

[0032] In some embodiments, the ratio of distance 116d to distance 116s (116d / 116s) may be in the range of about 1.2 to about 8, for example, 2, 3, 4, or 5. In some embodiments, the ratio of distance 116d to the width 124w of gate electrode 124 (116d / 124w) may be in the range of about 0.05 to about 4, for example, about 0.1, 0.5, 1, 2, or 3. In some embodiments, the ratio of distance 116s to the width 124w of gate electrode 124 (116s / 124w) may be in the range of about 0.05 to about 1.5, for example, about 0.1, 0.5, or 1. The width 124w of gate electrode 124 may be defined as the maximum width of the top 124t of gate electrode 124.

[0033] In some embodiments, the distance between the gate electrode 124 and the drain electrode 128 is greater than the distance between the gate electrode 124 and the source electrode 126.

[0034] The gate electrode 124 may include a bottom 124b and a top 124t. In some embodiments, the top 124t of the gate electrode 124 is asymmetrical or symmetrical relative to the bottom 124b of the gate electrode 124. The top 124t may be an enlarged portion of the gate electrode 124, but is not limited thereto. In some embodiments, a vertical auxiliary line may be defined from the center of the bottom 124b of the gate electrode 124. A distance 124ws may be defined as the maximum distance between the vertical auxiliary line and the sidewall of the top 124t of the gate electrode 124 adjacent to the source electrode 126. A distance 124wd may be defined as the maximum distance between the vertical auxiliary line and the sidewall of the top 124t of the gate electrode 124 adjacent to the drain electrode 128. The distance 124ws may be greater than 124wd (124ws > 124wd). In other embodiments, the distance 124ws is approximately equal to or less than the distance 124wd (124ws≦124wd).

[0035] In some embodiments, in the top view, the projection of the capping layer 116 adjacent to the source electrode 126 may overlap with the projection of the gate electrode 124, and in the top view, the projection of the capping layer 116 adjacent to the drain electrode 128 may be separated from the projection of the gate electrode 124. In other embodiments, in the top view, the projection of the capping layer 116 adjacent to the source electrode 126 may be separated from the projection of the gate electrode 124, and in the top view, the projection of the capping layer 116 adjacent to the drain electrode 128 may be separated from the projection of the gate electrode 124.

[0036] In some embodiments, in the top view, the projection of the gate electrode 124 may cover the bottom opening 122 formed in the protective layer 112.

[0037] Since the etch stop layer 114 and the protective layer 112 can be symmetrically removed from the opening 122, the distance 112s between the gate electrode 124 and the protective layer 112 of the adjacent source electrode 126 can be approximately equal to the distance 112d between the gate electrode 124 and the protective layer 112 of the adjacent drain electrode 128. The protective layer 112 can reduce surface traps on the carrier supply layer 108. Surface traps can be reduced by utilizing the shorter distances 112s and 112d between the gate electrode 124 and the protective layer 112. In some other embodiments, the distance 112s between the gate electrode 124 and the protective layer 112 of the adjacent source electrode 126 and the distance 112d between the gate electrode 124 and the protective layer 112 of the adjacent drain electrode 128 may not be the same.

[0038] The high electron mobility transistor structure 10a has three capping layers 110. The larger the distance 116d between the gate electrode 124 and the top capping layer 116 adjacent to the drain electrode 128, the lower the capacitance and the higher the device performance. A generally symmetrical design from the gate electrode 124 to the protective layer 112 and / or a shorter distance 112s and 112d between the gate electrode 124 and the protective layer 112 can reduce surface traps.

[0039] Many variations and / or modifications can be made to the embodiments of the present invention. Figure 2 is a cross-sectional view of the semiconductor structure 10b according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, as shown in Figure 2, multiple etch stop layers 114a and 114b and multiple capping layers 116a and 116b are formed on the protective layer 112.

[0040] In some embodiments, the capping layer 110 may include a protective layer 112, an etch stop layer 114a, a top capping layer 116a, a second etch stop layer 114b, and a second top capping layer 116b. In some embodiments, the protective layer 112 may be formed over the carrier supply layer 108, the etch stop layer 114a may be formed over the protective layer 112, and the top capping layer 116a may be formed over the etch stop layer 114a. In some embodiments, the second etch stop layer 114b may be formed over the top capping layer 116a, and the second top capping layer 116b may be formed over the second etch stop layer 114b. The processes for forming the second etch stop layer 114b and the second top capping layer 116b may be similar to or the same as the processes for forming the etch stop layer 114 and the top capping layer 116 described above, and will not be repeated here for the sake of brevity.

[0041] In some embodiments, the protective layer 112 and the etch stop layer 114a may be omitted. That is, the top cover layer 116a is located above the carrier supply layer 108, the second etch stop layer 114b is located above the top cover layer 116a, and the second top cover layer 116b is located above the second etch stop layer 114b, but this is not a limitation.

[0042] The openings formed in the second etch stop layer 114b and the second capping layer 116b, as well as the openings formed in the etch stop layer 114a and the capping layer 116a, can be defined by different masks. The openings formed in the second etch stop layer 114b and the second capping layer 116b are wider than the openings formed in the etch stop layer 114a and the capping layer 116a. Multiple capping layers 116a and 116b can increase the breakdown voltage of the high electron mobility transistor structure 10b.

[0043] The distance 116bd between the gate electrode 124 and the second capping layer 116b of the adjacent drain electrode 128 may be greater than the distance 116bs between the gate electrode 124 and the second capping layer 116b of the adjacent source electrode 126 (116bd > 116bs). The distance 116ad between the gate electrode 124 and the capping layer 116a of the adjacent drain electrode 128 may be greater than the distance 116as between the gate electrode 124 and the capping layer 116a of the adjacent source electrode 126 (116ad > 116as). The distances 116bd, 116bs, 116ad, and 116as may be defined as the minimum distance between the corresponding capping layer and the bottom 124b of the gate electrode 124. The longer distances 116bd and 116ad between the gate electrode 124 and the second top cover layer 116b and top cover layer 116a adjacent to the drain electrode 128 can reduce capacitance and enhance device performance.

[0044] Many variations and / or modifications can be made to the embodiments of the present invention. Figures 3 and 4 are cross-sectional views of semiconductor structures 10c and 10d according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, as illustrated in Figures 3 and 4, the shape of the top cap layer 116 is different from that in the previous embodiments.

[0045] According to some embodiments, as shown in Figure 3, the sidewalls of the capping layer 116 may be substantially perpendicular to the top surface of the substrate 102. According to some embodiments, as shown in Figure 4, the top surface of the capping layer 116 is narrower than the bottom surface of the capping layer 116. That is, the inclined sidewalls may connect the top and bottom surfaces of the capping layer 116. A passivation layer 130 may be formed on the capping layer 116.

[0046] Many variations and / or modifications can be made to the embodiments of the present invention. Figure 5 is a cross-sectional view of the semiconductor structure 10e according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, and therefore these processes and elements are not repeated here. Unlike the above embodiments, according to some other embodiments, as shown in Figure 5, in the top view, the gate electrode 124 overlaps with the capping layer 116 adjacent to the drain electrode 128.

[0047] In some embodiments, the projection of the capping layer 116 adjacent to the source electrode 126 overlaps with the projection of the gate electrode 124 for a longer period than the projection of the capping layer 116 adjacent to the drain electrode 128 overlaps with the projection of the gate electrode 124.

[0048] As described above, in this embodiment of the invention, a high electron mobility transistor structure and a method for forming the high electron mobility transistor structure are provided. Using a three-layer capping layer comprising a protective layer, an etch stop layer, and a capping layer, capacitance can be reduced through the asymmetric capping layer, and surface defects can be reduced through the protective layer adjacent to the gate electrode. Multiple capping layers and / or etch stop layers may exist, which can increase the breakdown voltage. The shape of the capping layer can be different. In the top view, the capping layer of the gate electrode and the adjacent drain electrode may overlap or be separated.

[0049] It should be noted that although some benefits and effects are described in the above embodiments, not all embodiments are required to achieve all benefits and effects.

[0050] The foregoing description outlines the feature components of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention; therefore, the scope of protection of the present invention shall be determined by the appended claims. Furthermore, although the present invention has been disclosed above with reference to several preferred embodiments, it is not intended to limit the invention, and not all advantages have been described in detail herein. [Simplified Explanation of the Diagram]

[0007] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various feature components are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components may be enlarged or reduced to clearly demonstrate the technical features of the embodiments of the present invention. Figures 1A-1E are cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments. Figure 2 is a cross-sectional view illustrating a semiconductor structure according to some embodiments. Figure 3 is a cross-sectional view illustrating a semiconductor structure according to some embodiments. Figure 4 is a cross-sectional view illustrating a semiconductor structure according to some embodiments. Figure 5 is a cross-sectional view illustrating a semiconductor structure according to some embodiments.

Claims

1. A semiconductor device, comprising: One substrate; A semiconductor stack is located on the substrate; A capping layer, located on the semiconductor stack, includes: an intrinsic capping layer; an etch stop layer; an n-type capping layer; and an opening through the capping layer; a source electrode and a drain electrode, located on the semiconductor stack; and a gate electrode, located in the opening and between the source electrode and the drain electrode, wherein a first distance between the gate electrode and a first portion of the n-type capping layer adjacent to the drain electrode is greater than a second distance between the gate electrode and a second portion of the n-type capping layer adjacent to the source electrode, wherein in a top view, the projection of the n-type capping layer adjacent to the source electrode overlaps with the projection of the gate electrode, and in a top view, the projection of the n-type capping layer adjacent to the drain electrode is separated from the projection of the gate electrode.

2. The semiconductor device as claimed in claim 1, wherein the ratio of the first distance to the second distance is in the range of about 1.2 to about 8.

3. The semiconductor device as claimed in claim 1, wherein the ratio of the first distance to the width of the gate is in the range of about 0.05 to about 4.

4. The semiconductor device as claimed in claim 1, wherein the ratio of the second distance to the width of the gate is in the range of about 0.05 to about 1.

5.

5. The semiconductor device as claimed in claim 1, wherein a top surface of the n-type capping layer is wider than a bottom surface of the n-type capping layer.

6. The semiconductor device as claimed in claim 1, wherein in a top view, the overlap between the projection of the n-type capping layer adjacent to the source electrode and the projection of the gate electrode is longer than the overlap between the projection of the n-type capping layer adjacent to the drain electrode and the projection of the gate electrode.

7. The semiconductor device as claimed in claim 1, wherein the distance from the gate to the drain electrode is greater than the distance from the gate to the source electrode.

8. The semiconductor device as claimed in claim 1, wherein the intrinsic capping layer comprises GaAs, the etch stop layer comprises AlAs, and the n-type capping layer comprises GaAs.

9. The semiconductor device as claimed in claim 1, wherein the width of the opening through the intrinsic capping layer is narrower than the width of the opening through the n-type capping layer.

10. A semiconductor device, comprising: One substrate; A semiconductor stack is located on a substrate; a capping layer is located on the semiconductor stack and has a top opening and a bottom opening, wherein the bottom opening overlaps the top opening; a source electrode and a drain electrode are located on the semiconductor stack; and a gate is located between the top opening and the bottom opening, between the source electrode and the drain electrode, and spaced from the capping layer, wherein a first distance between the gate and the drain-side capping layer in the top opening is greater than a second distance between the gate and the source-side capping layer in the top opening, and a third distance between the gate and the drain-side capping layer in the bottom opening is substantially equal to a fourth distance between the gate and the source-side capping layer in the bottom opening, wherein in the top view, the projection of a top capping layer adjacent to the source electrode overlaps with the projection of the gate, and in the top view, the projection of the top capping layer adjacent to the drain electrode is spaced from the projection of the gate.

11. The semiconductor device as claimed in claim 10, wherein the capping layer comprises: A protective layer; An etch stop layer is placed on top of the protective layer; And the top cover layer, which is located above the etch stop layer.

12. The semiconductor device as described in claim 11, further comprising: A second etch stop layer is located above the top cover layer; And a second top layer, located above the second etch stop layer.

13. The semiconductor device as claimed in claim 11, wherein one sidewall of the top cover layer is substantially perpendicular to a top surface of the substrate.

14. The semiconductor device as claimed in claim 11, wherein a top surface of the capping layer is narrower than a bottom surface of the capping layer.

15. The semiconductor device as claimed in claim 11, wherein the etch stop layer is n-type doped.

16. The semiconductor device as described in claim 10, further comprising: A passivation layer is located above the gate, in the bottom opening and in the top opening.

17. The semiconductor device of claim 10, wherein the gate includes a bottom located in the bottom opening and a top located above the bottom, wherein the top of the gate is asymmetrical relative to the bottom.

18. The semiconductor device as claimed in claim 10, wherein, in a top view, a projection of the gate covers the bottom opening.

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