Semiconductor structure and method of forming the same

Abstract

The method includes forming a stack on a substrate, patterning the stack and the substrate to form first and second active regions, forming an isolation structure between the first and second active regions, depositing an isolation structure protective layer on the isolation structure, forming a dummy gate stack across the first and second active regions, causing the first and second active regions to be recessed to form first and second trenches; forming first and second source / drain structures in the first and second trenches, removing the dummy gate stack to form a gate trench, depositing a gate structure in the gate trench to intersect with the isolation structure protective layer, thinning the substrate and the isolation structure, forming a back-side opening to expose the lower surface of the first source / drain structure, and forming a back-side via in the back-side opening to electrically couple with the first source / drain structure.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to protective layers for isolation structures in semiconductor structures. Prior Technology

[0002] Semiconductor integrated circuits have experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as geometric dimensions (i.e., the smallest components or lines that can be produced by the manufacturing process) shrink. Shrinking dimensions generally facilitates increased production capacity and reduced costs. However, shrinking dimensions also increases the complexity of handling and manufacturing integrated circuits.

[0003] Conventional integrated circuits are built in a stacked manner, with transistors at the bottom layer and interconnects (vias and wire bonding) on ​​top to provide connections to the transistors. Power rails (such as metal lines used for voltage sources and ground planes) are also located on the transistors and may be part of the interconnects. As integrated circuits and power rails continue to shrink, the voltage drop across the power rails and the power consumption of the integrated circuits may increase. In addition to power rails, signal lines may also be affected by size reduction (e.g., decreasing signal line spacing), potentially increasing parasitic capacitance and reducing circuit speed. Therefore, while existing semiconductor fabrication methods generally meet the intended purpose, they cannot meet all the requirements. One area of ​​interest is how to form vias on the back side of integrated circuits and reduce the height of the vias to reduce resistance. Summary of the Invention

[0004] An exemplary embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes forming a stack on a substrate, the stack having multiple interleaved sacrificial layers and multiple channel layers; patterning the stack and substrate to form a first region and a second region, each extending longitudinally in a first direction, the first region including a first active region and a first base region, and the second region including a second active region and a second base region; forming an isolation structure between the first base region and the second base region, wherein the isolation structure intersects with the sidewalls of the first base region and the sidewalls of the second base region; depositing an isolation structure protective layer on the isolation structure; forming a dummy gate stack extending across the first active region and the second active region, and the dummy gate stack intersects with the upper surface of the isolation structure protective layer; depositing multiple gate spacers on the sidewalls of the dummy gate stack; and recessing the first active region and the second active region outside the dummy gate stack and the gate spacers. The method involves forming a first trench and a second trench; forming a first source / drain structure in the first trench and a second source / drain structure in the second trench, wherein a portion of the first source / drain structure is suspended on the isolation structure along a second direction, and a portion of the second source / drain structure is suspended on the isolation structure along a second direction, and the second direction is different from the first direction; removing the dummy gate stack to form a gate trench, and exposing the isolation structure protective layer in the gate trench; removing the sacrificial layer from the gate trench; depositing a gate structure in the gate trench, and the gate structure intersecting with the upper surface of the isolation structure protective layer; thinning the substrate and the isolation structure; forming a back-side opening to expose the lower surface of the first source / drain structure; and forming a back-side via in the back-side opening for electrical coupling with the first source / drain structure.

[0005] Another embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes providing a structure having a front side and a back side, the structure including a substrate on the back side of the structure and a fin-like structure on the front side of the structure; forming an isolation structure on the sidewalls of the fin-like structure; forming an isolation structure protective layer on the isolation structure; epitaxially growing a source / drain structure on the fin-like structure; depositing a contact etch stop layer on the source / drain structure; depositing a first interlayer dielectric layer on the contact etch stop layer; depositing a capping layer on the upper surface of the contact etch stop layer and the upper surface of the first interlayer dielectric layer; and depositing a second interlayer dielectric layer on the capping layer, wherein the thickness of the first interlayer dielectric layer is... The thickness is greater than that of the second interlayer dielectric layer; a source / drain contact plug is formed in the first interlayer dielectric layer to be electrically coupled to the source / drain structure; a metal silicate layer is formed between the source / drain structure and the source / drain contact plug, wherein the conductivity of the metal silicate layer is between that of the source / drain structure and the source / drain contact plug, wherein the metal silicate layer includes an arcuate profile; the structure is thinned from the back side of the structure until the isolation structure protective layer is exposed; an opening is formed to expose the lower surface of the source / drain structure; and a back-side via is deposited in the opening.

[0006] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a first source / drain structure and a second source / drain structure; one or more nanostructures connecting the first source / drain structure and the second source / drain structure; a gate structure connecting the nanostructures, the gate structure including a gate dielectric layer and a gate layer located on the gate dielectric layer; a gate spacer extending along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; an interlayer dielectric layer located on the first source / drain structure and the second source / drain structure; and a source / drain junction extending... The interlayer dielectric layer is electrically coupled to the first source / drain structure, wherein the conductivity of the source / drain junction is greater than that of the first source / drain structure; a protective layer is located below and intersects with the lower surface of the gate structure, wherein the lower surface of the interlayer dielectric layer and the lower surface of the protective layer are coplanar; a back-side dielectric layer is located on the lower surface of the protective layer; a metal circuit is embedded in the back-side dielectric layer; and a back-side via is located directly under the first source / drain structure and electrically connects the metal circuit to the first source / drain structure. Simple Explanation of the Diagram

[0007] Figure 1 is a flowchart of a method for forming a semiconductor device in one or more embodiments of the present invention. Figure 2 is a perspective view of the semi-finished product structure in one or more embodiments of the present invention. Figures 3 to 43 are partial top views and cross-sectional views of the semi-finished product structure during the manufacturing process according to the method of Figure 1 in one or more embodiments of the present invention. Figures 44 to 46 are partial cross-sectional views of other semi-finished product structures during the manufacturing process according to the method of Figure 1 in one or more embodiments of the present invention. Implementation

[0008] The following detailed description, accompanied by accompanying drawings, will aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity of explanation.

[0009] The different embodiments or examples provided below can implement different structures of the embodiments of the present invention. The specific components and arrangements described are for simplification and not for limiting the invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being separated by other additional components rather than in direct contact. Various embodiments of the invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0010] Spatial relative terms such as "below," "below," "lower side," "above," "upper side," or similar terms can be used to simplify the description of the relative relationship between one element and another in a diagram. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the diagram. When the device is turned in different directions (rotated 90 degrees or other directions), the spatial relative adjectives used will also be interpreted according to the direction after the turn.

[0011] Furthermore, when a numerical value or range is described using terms such as "about," "approximately," or similar expressions, those skilled in the art should understand that it includes a reasonable range that takes into account inherent variations during manufacturing. For example, based on known manufacturing tolerances for structures related to that value, the value or range covers a reasonable range of the value, such as within + / - 10% of the value. For instance, a material layer with a thickness of "about 5 nm" can cover a size range of 4.5 nm to 5.5 nm, while those skilled in the art know that the manufacturing tolerances associated with deposited material layers are + / - 10%.

[0012] The embodiments of the present invention generally relate to semiconductor structures and their fabrication processes, and more particularly to integrated circuit wafers having transistors, wherein the back-side interconnect structure of the transistors includes back-side metal lines and back-side vias.

[0013] The subject of this invention is to provide interconnect structures (such as power rails and / or signal lines) on the back side of a semiconductor device containing transistors, in addition to the interconnect structures (including power rails and signal lines) on the front side of the semiconductor device. Specifically, this invention relates to forming vias with reduced height on the back side of a semiconductor device to reduce resistance. Compared to front-side interconnect structures and front-side vias formed on the front side, interconnect structures and vias formed on the back side can also be considered as back-side interconnect structures and back-side vias, respectively. The back-side vias connect the back-side power rails and / or signal lines to the source / drain structures on the front side. Since via resistance is generally related to its height, reducing the via height can effectively reduce via resistance, and ultimately reduce the overall resistance of the electrical wiring. For back-side vias, their minimum height is generally limited by the isolation structure (such as a shallow trench isolation structure) deposited between the active regions, while the lower surface of the metal gate structure lands on the active region. The thickness of this isolation structure is generally sufficient to prevent the metal gate structure from being exposed during back-side thinning processes. However, thicker isolation structures require longer back-side vias to penetrate the thickness of the isolation structure in order to connect the back-side metal lines to the source / drain structures.

[0014] This invention provides a method for forming a back-side via with significantly reduced height. In some embodiments, an isolation structure is formed between active regions, followed by deposition of an isolation structure protective layer on the front side of the isolation structure. A metal gate structure is then formed on the isolation structure protective layer, rather than directly on the isolation structure. This approach reduces the minimum thickness of the isolation structure because the isolation structure no longer suffers etch losses during the front-side fabrication steps. The isolation structure protective layer can also serve as a thinning stop layer, preventing exposure of the metal gate structure during the back-side thinning process. Due to the presence of the isolation gate structure protective layer, the isolation structure can be substantially removed during the back-side process, significantly reducing the height and associated resistance of the back-side via.

[0015] The structure and fabrication method of this invention will be illustrated below with accompanying drawings, showing some embodiments of the fabrication process for multi-gate transistors (especially fully wound gate transistors). A fully wound gate transistor can be considered as a transistor with vertically stacked horizontal channel components, which can be in the form of nanowires and / or nanosheets. Fully wound gate transistors offer better gate control, lower leakage current, and compatibility with fully field-effect transistor layouts, making them a strong candidate for taking complementary metal-oxide-semiconductor (CMOS) fabrication to the next stage. For simplicity, this invention uses a fully wound gate transistor as an example. Those skilled in the art will understand that this invention can be readily used as a basis to design or modify other processes and structures (such as finned field-effect transistors) to achieve the same objectives and / or advantages as the embodiments herein.

[0016] Figure 1 shows a flowchart of a method 100 for forming a semiconductor structure from a semi-finished structure according to an embodiment of the present invention. Method 100 is for illustrative purposes only and is not intended to limit the scope of the embodiments of the present invention to the specific content of method 100. Additional steps may be provided before, during, and after method 100, and additional embodiments of the method may substitute, omit, or interchange some of the steps described herein. All steps are not detailed here for simplicity. Method 100 will be described below in conjunction with Figures 2 to 46. Figure 2 is a perspective view of the semi-finished structure, while Figures 3 to 46 are partial cross-sectional views (e.g., cross-sectional views along sections AA, BB, CC, or DD shown in Figure 2) of the semi-finished structure at different fabrication stages of the embodiment of method 100 in Figure 1. Since the semi-finished structure will be fabricated into a semiconductor structure or semiconductor device, the semi-finished structure here may also be considered as a semiconductor structure or semiconductor device 200. For the avoidance of doubt, the X, Y, and Z directions in Figures 2 to 46 are perpendicular to each other. In embodiments of the present invention, similar labels are used to indicate similar structures or steps unless otherwise stated.

[0017] Figure 2 is a perspective view of the semiconductor device 200 in some embodiments. Figure 1 shows the semiconductor device 200 as the dummy gate stack 220 moves past the fabrication stage of the fin structure 212. Each dummy gate stack 220 includes a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222. The fin structure 212 protrudes from the substrate 202. Each fin structure 212 includes a fin substrate 212B and an epitaxial stack of channel layers 208 and sacrificial layers 206 staggered in the vertical direction. The channel layers 208 and sacrificial layers 206 of the nanostructure (such as nanosheets or nanowires) are staggered. Source / drain regions 212SD are defined on both sides of the dummy gate stack 220. An isolation structure 214 and its top isolation structure protective layer 215 are formed on both sides of the fin structure 212.

[0018] Figure 2 further shows the reference cross-sections used in the following diagrams. Cross-section AA is along the longitudinal axis of the dummy gate stack 220 and perpendicular to the current direction between the source / drain regions 212SD of the individual fully wound gate transistors of the semiconductor device 200. Cross-section BB is perpendicular to cross-section AA, along the longitudinal axis of the fin structure 212 and in the current direction between the source / drain regions 212SD of the individual fully wound gate transistors of the semiconductor device 200. Cross-section CC is parallel to cross-section BB and lies between two adjacent fin structures 212. Cross-section DD is parallel to cross-section AA and extends through the source / drain regions 212SD of the semiconductor device 200. The following diagrams are each based on these reference cross-sections for clarity.

[0019] As shown in Figures 1 and 3, step 102 of method 100 forms a stack 204 of interleaved semiconductor layers on the semiconductor device 200. As shown in Figure 3, the semiconductor device 200 includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate such as a silicon substrate. The substrate 202 may include various doping configurations depending on design requirements known in the art. In embodiments where the semiconductor device is p-type, an n-type doped profile (i.e., an n-type well) may be formed on the substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus, arsenic, or antimony. In embodiments where the semiconductor device is n-type, a p-type doped profile (i.e., a p-type well) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron or gallium. Suitable doping methods may include ion-implanted dopant and / or diffusion processes. The substrate 202 may also include other semiconductors such as germanium, silicon carbide, silicon-germanium, germanium-tin, or diamond. The substrate 202 may instead include semiconductor compounds and / or semiconductor alloys. In addition, the substrate 202 may include an epitaxial layer, may have strain for improving performance, may include silicon-on-insulator or germanium-on-insulator structures, and / or may have other suitable improving structures.

[0020] In some embodiments, the stack 204 on top of the substrate 202 includes sacrificial layers 206 composed of a second semiconductor sandwiched between channel layers 208 composed of a first semiconductor. Alternatively, the channel layers 208 may be sandwiched between sacrificial layers 206. The first semiconductor composition differs from the second semiconductor composition. In some embodiments, the sacrificial layers 206 comprise silicon-germanium or germanium-tin, while the channel layers 208 comprise silicon. It is noteworthy that FIG3 shows three sacrificial layers 206 and three channel layers 208 in an alternating configuration, which is for illustrative purposes only and not for limiting the embodiments of the invention to the extent not actually described in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the performance required by the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0021] The deposition method for the sacrificial layer 206 and the channel layer 208 in stack 204 can employ molecular beam epitaxy, vapor phase epitaxy, and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium layer, and the channel layer 208 comprises an epitaxially grown silicon layer. In some embodiments, the germanium content in the sacrificial layer 206 may be not less than about 20%, for example, greater than or equal to about 30%. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially undoped (i.e., the added dopant concentration is from about 0 atoms / cm3 to about 1 x 10¹⁷ atoms / cm3), for example, without deliberate doping during the epitaxial growth process used in stack 204.

[0022] As shown in Figures 1 and 4, step 104 of method 100 forms a fin structure 212 from the stack 204 and the substrate 202. To pattern the stack, a hard mask layer may be deposited on the stack 204 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer thereon. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using lithography and etching processes. The lithography process may include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. As shown in Figure 4, the etching process in step 104 forms trenches that extend vertically through a portion of the stack 204 and the substrate 202. The trenches define the fin structure 212. In some implementations, dual or multiple patterning processes can be used to define fin structures with a spacing smaller than that obtained using a single direct photolithography process. For example, one embodiment forms a material layer on a substrate and patterns the material layer using a photolithography process. A self-aligned process is used to form spacers along the sides of the patterned material layer. The material layer is then removed, and the remaining spacers or cores can then be used to etch a portion of the stack 204 and the substrate 202 to pattern the fin structure 212. As shown in FIG4, the fin structure 212 extends vertically along the Z direction and longitudinally along the Y direction. The fin structure 212 provides the active region for subsequently formed transistors, including a channel region (channel region 212C as shown in FIG7) and a source / drain region (source / drain region 212SD as shown in FIG7). As shown in FIG4, the fin structure 212 includes a fin substrate 212B patterned from the substrate 202 and a patterned stack 204 located directly above the fin substrate 212B. In the embodiment shown in FIG4, the top of the patterned stack 204 and the fin substrate 212B has substantially flat sidewalls, and the bottom of the fin substrate 212B has tapered sidewalls due to the load effect of the patterning process.

[0023] As shown in Figures 1 and 5, step 106 of method 100 forms an isolation structure 214 around the fin substrate 212B of the fin structure 212. In some embodiments shown in Figure 5, the isolation structure 214 is located on the sidewall of the fin substrate 212B. In some embodiments, the isolation structure 214 may be formed in a trench to isolate adjacent active regions in the fin structure 212. In some embodiments, the isolation structure 214 is a shallow trench isolation structure. For example, in some embodiments, a dielectric layer may be deposited first on the substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials. In many examples, the dielectric layer deposition method may be a chemical vapor deposition process, a sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, a spin coating process, and / or other suitable processes. For example, the deposited dielectric material may then be thinned and planarized by a chemical mechanical polishing process. Dry etching, wet etching, and / or combinations thereof can be used to further recess or pull back the planarized dielectric layer to form the isolation structure 214 shown in FIG. 5. In this embodiment, the upper surface of the isolation structure 214 has a dished profile due to the load effect during the etching process. The fin structure 212 after the recess process protrudes higher than the isolation structure 214, and the fin substrate 212B is at least partially embedded or buried in the isolation structure 214. In this embodiment, the edge of the dished profile of the isolation structure 214 intersects with the top sidewall of the fin substrate 212B. The edge of the dished profile of the isolation structure 214 can be changed to intersect with the sidewall of the bottommost sacrificial layer 206, so that the fin substrate 212B is completely embedded or buried in the isolation structure 214.

[0024] As shown in Figures 1 and 5, step 108 of method 100 forms an isolation structure protective layer 215 on top of the isolation structure 214 and around the top of the fin-like substrate 212B. The composition of the isolation structure protective layer 215 differs from that of the isolation structure 214. In some embodiments, the isolation structure 214 comprises silicon oxide (such as silicon dioxide), while the isolation structure protective layer 215 comprises silicon nitride (such as trisilicon tetranitride), silicon carbonitride, or silicon oxynitride. For example, in some embodiments, a nitrogen-containing material is first deposited on the isolation structure 214 to fill the trenches with nitride. In various examples, the method for depositing the nitrogen-containing material may be a chemical vapor deposition process, a sub-pressure chemical vapor deposition process, a flowable chemical vapor deposition process, a spin coating process, and / or other suitable processes. The deposited nitrogen-containing material is then thinned and planarized, for example, using a chemical mechanical polishing process. The process of further recessing or pulling back the planarized nitrogen-containing material to form the isolation structure protective layer 215 can be a dry etching process, a wet etching process, and / or a combination thereof. In the embodiment, due to the load effect during the etching process, the upper surface of the isolation structure protective layer 215 has a dished profile. The fin structure 212 after the recess process protrudes above the isolation structure protective layer 215. In the embodiment, the edge of the dished profile of the isolation structure protective layer 215 may intersect with the sidewall of the bottommost sacrificial layer 206. The midpoint of the dished profile of the isolation structure protective layer 215 (such as the lowest point of the upper surface) may be higher or lower than the lower surface of the bottommost sacrificial layer 206. The fin substrate 212B is embedded in the combination of the isolation structure 214 and the isolation structure protective layer 215. The thickness of the isolation structure protective layer 215 may be from about 10 nm to about 50 nm. This range is not arbitrarily chosen or unimportant. If the thickness is less than about 10 nm, the protective layer 215 of the isolation structure may be etched through due to the limited etching contrast in the subsequent etching process, thus impairing the protective function of the isolation structure 214. If the thickness is greater than about 50 nm, the bottom sacrificial layer 206 can be buried underneath, and the bottom sacrificial layer 206 will be difficult to remove in the subsequent gate replacement process.

[0025] As shown in Figures 1, 6, and 7, step 110 of method 100 forms a dummy gate stack 220 and a gate spacer 226 on the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder for various processes, after which it is removed and replaced with a functional gate structure. Other processes and configurations are also possible. As shown in Figure 7, the dummy gate stack 220 and the gate spacer 226 are formed on the fin structure 212, and the fin structure 212 can be divided into the channel region 212C below the dummy gate stack 220 and the gate spacer 226, and the source / drain region 212SD not below the dummy gate stack 220 and the gate spacer 226. The channel region 212C is adjacent to the source / drain region 212SD. As shown in Figure 7, the channel region 212C is located between the two source / drain regions 212SD along the X direction. The source / drain region described herein can be considered as the area providing the source and / or drain for one or more devices. It can also be considered as the source or drain of one or more devices. Furthermore, in Figure 7 and the subsequent cross-sectional views showing the XZ plane, the horizontal dashed line, such as the lower surface B214 of the isolation structure 214, indicates the location of the lower surface of the isolation structure 214.

[0026] Methods for forming the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. As shown in FIG6, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be deposited blanket-like on the semiconductor device 200. The dummy dielectric layer 216 may be deposited compliantly on the fin structure 212, and the deposition method may employ chemical vapor deposition, atomic layer deposition, oxygen plasma oxidation, or other suitable processes. The term "compliant" as used herein is for the convenience of describing layers having a substantially uniform thickness over multiple regions. In some examples, the dummy dielectric layer 216 may include silicon oxide. A dummy electrode layer 218 may then be deposited on the dummy dielectric layer 216, and the deposition method may employ chemical vapor deposition, atomic layer deposition, or other suitable processes. In some examples, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a gate-top hard mask layer 222 can be deposited on the dummy electrode layer 218, and the deposition method can employ chemical vapor deposition, atomic layer deposition, or other suitable processes. The gate-top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown in FIG7. For example, the patterning process may include lithography (such as photolithography or electron beam lithography) and etching processes. The lithography process may further include photoresist coating (such as spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Next, a patterned photoresist layer is used as an etching mask in the etching process of the patterned gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 is a two-layer structure, which may include a silicon oxide layer and a silicon nitride layer thereon.

[0027] Methods for forming gate spacer 226 may include depositing a gate spacer layer and etching back the gate spacer layer. In some embodiments, the gate spacer layer is compliantly deposited on the semiconductor device 200, including on the upper surface and sidewalls of the dummy gate stack 220. The gate spacer layer may be a single layer or multiple layers. At least one layer of the gate spacer layer may include silicon carbonitride, silicon carbon oxide, silicon carbonitride, or silicon nitride. The process of depositing the gate spacer layer on the dummy gate stack 220 may employ chemical vapor deposition, sub-pressure chemical vapor deposition, atomic layer deposition, or other suitable processes. An isotropic etching may then be performed to remove the horizontal portion of the gate spacer layer from the upward-facing surface of the semiconductor device 200 (including from the upper surface of the dummy gate stack 220). The remaining vertical portion of the gate spacer layer covers the sidewalls of the dummy gate stack 220 as gate spacer 226.

[0028] Figures 8 and 9 show cross-sectional views of the semiconductor device 200 along section CC in two other embodiments following step 110. A common feature of Figures 8 and 9 is that the lower surfaces of the dummy gate stack 220 and gate spacers 226 between adjacent fin structures 212 land directly on the upper surface of the isolation structure protective layer 215. In the embodiment shown in Figure 8, the anisotropic etching process that removes the horizontal portion of the gate spacer layer also etches through the isolation structure protective layer 215 between the gate spacers 226 on both sides, and the exposed top of the isolation structure 214 also suffers some etching loss due to limited etching contrast. In the embodiment shown in Figure 9, after the anisotropic etching process that removes the horizontal portion of the gate spacer layer, the isolation structure protective layer 215 remains substantially intact. Additional etching processes beyond the anisotropic etching process that removes the horizontal portion of the gate spacer layer may be performed to open the isolation structure protective layer 215 between the gate spacers 226 on both sides, resulting in the structure shown in Figure 8. The process described below, which involves recessing the source / drain electrodes, can be replaced by etching the protective layer 215 of the isolation structure that passes through the gate spacers 226 on both sides.

[0029] As shown in Figures 1 and 10 to 12, step 112 of method 100 anisotropically recesses the source / drain region 212SD of the fin structure 212 to form a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain region 212SD and a portion of the substrate 202. The final source / drain trench 228 extends vertically through the depth of the stack 204 and partially into the substrate 202 (i.e., the fin substrate 212B is partially recessed). Examples of the dry etching process in step 110 may include oxygen-containing gases, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, tetrachloromethane, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or tribromomethane), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. As shown in Figure 10, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends into the substrate 202 under the stack 204, the lower surface and lower sidewall of the source / drain trench 228 are defined in the substrate 202.

[0030] As shown in Figure 11, the main fin structure 212 is etched on the source / drain region 212SD to expose the upper surface of the fin substrate 212B in the source / drain region 212SD. Furthermore, the recessed upper surface of the fin substrate 212B may be lower than the lower surface of the isolation structure protective layer 215. Because the etching rate of the gate spacer 226 is less than the etching rate of the fin substrate 212B, the gate spacer 226 in the source / drain region 212SD protrudes above the upper surface of the fin substrate 212B. The gate spacer 226 retained in the source / drain region 212SD can also be considered as a fin spacer. When the source / drain region 212SD is recessed, the fin spacer protects a portion of the isolation structure protective layer 215 directly below it from being removed. If the isolation structure protective layer 215 was not activated in the previous steps (as shown in Figure 9), it will be activated when the source / drain region 212SD is recessed.

[0031] As shown in Figure 12, the etching process performed when the source / drain region 212SD is recessed can etch into the exposed portion of the isolation structure 214. This process further extends the void (i.e., the bottom of the source / drain trench 228) below the isolation structure protective layer 215, resulting in a void width exceeding the lateral space between the gate spacers 226 on both sides. In other words, a portion of the void can extend directly below the gate spacers 226. Furthermore, the bottom of the isolation structure protective layer 215 can be etched laterally, giving the separated portion of the isolation structure protective layer 215 an inverted trapezoidal appearance.

[0032] As shown in Figures 1 and 13, step 114 of method 100 forms an inner spacer recess 232. The sacrificial layer 206 may be selectively recessed to form the inner spacer recess 232. The inner spacer recess 232 may have the rectangular profile shown in the figure. The inner spacer recess 232 may be modified to have a recessed profile that curves from the source / drain trench 228. In one embodiment, the step of selectively recessing the sacrificial layer 206 may employ a selective wet etching process or a selective dry etching process. Examples of a selective wet etching process may use dilute hydrofluoric acid, or a mixture of hydrofluoric acid and ammonium fluoride. Examples of a selective dry etching process may use anhydrous hydrofluoric acid vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or a combination thereof.

[0033] As shown in Figures 1 and 14, step 116 of method 100 forms an inner spacer 236 in an inner spacer recess 232. The method of forming the inner spacer 236 may include depositing an inner spacer layer on the exposed surface of the source / drain trench 228, including filling the inner spacer recess 232. In some embodiments, the inner spacer layer may include silicon carbonitride, silicon carbonitride, silicon nitride, silicon carbon oxide, or silicon oxynitride. In some embodiments, the deposition method of the inner spacer layer may employ chemical vapor deposition or atomic layer deposition. The inner spacer layer may then be etched back to form the inner spacer 236 in the inner spacer recess 232. In some embodiments, the method of etching back the inner spacer layer may employ a dry etching process, such as a plasma-assisted reactive ion etching process. Examples of dry etching processes may employ boron trichloride, chlorine, hydrogen chloride, methane, nitrogen trifluoride, carbon tetrafluoride, sulfur hexafluoride, nitrogen, or combinations thereof. In the embodiment described, the inner spacer 236 is substantially retained below the gate spacer 226, and does not extend to a position directly below the dummy gate stack 220. Alternatively, the inner spacer 236 may extend laterally to a position directly below the dummy gate stack 220.

[0034] As shown in Figures 1 and 15, step 118 of method 100 deposits a separator layer 238 in the bottom of the source / drain trench 228. In some embodiments, the separator layer 238 is a buffer epitaxial layer epitaxially grown from the upper surface of the fin-shaped substrate 212B. For example, the method for epitaxially growing the buffer epitaxial layer such as the separator layer 238 may be vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and / or other suitable epitaxial growth processes. In some embodiments, the buffer epitaxial layer such as the separator layer 238 and the substrate 202 comprise the same material, such as silicon. In some other embodiments, the buffer epitaxial layer such as the separator layer 238 comprises a semiconductor material different from silicon, such as silicon germanium, silicon tin, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer such as the separator layer 238 is undoped, for example, it is not intentionally doped during the epitaxial growth process. In contrast, in another example, the substrate 202 may be lightly doped, so that its doping concentration is higher than that of the buffer epitaxial layer such as the separator layer 238. The separator layer 238 provides a high-resistivity path from the source / drain region to the semiconductor substrate to suppress leakage current in the semiconductor substrate. It is worth noting that the separator layer 238 may be formed as needed (as in step 118). This means that in some embodiments, the formation step of the separator layer 238 may be omitted, and the separator layer 238 is not present in the final structure.

[0035] As shown in Figures 1, 16, and 17, step 120 of method 100 forms a bottom isolation layer 240 on the separator layer 238 (or on the substrate 202, if the step of forming the separator layer 238 is omitted). Since the bottom isolation layer 240 may intersect with the source / drain structure, and its oxygen content may oxidize the source / drain structure, the composition of the bottom isolation layer 240 may be an oxygen-free dielectric material such as a nitride. In one example of the process, a chlorinated silicon nitride layer is deposited in the source / drain trench 228, including deposition on the upper surface of a buffer epitaxial layer such as the separator layer 238. The deposition method of the chlorinated silicon nitride layer may employ ammonia and a chlorinated silicon precursor (such as silicon tetrachloride, dichlorosilane, dichlorosilane, or hexachlorosilane). The deposition method of the chlorinated silicon nitride layer may employ plasma-assisted atomic layer deposition or thermal atomic layer deposition. A directional plasma treatment process is then performed to remove chlorine from the bottom of the chlorine-containing silicon nitride layer. In some embodiments, the directional plasma treatment may employ argon plasma, nitrogen plasma, and / or hydrogen plasma. Following the directional plasma treatment, a dry etching process may be performed using a fluorinated etchant such as trifluoromethane, nitrogen trifluoride, carbon tetrafluoride, or sulfur hexafluoride. Because the dry etching process etches the chlorine-containing silicon nitride layer along the sidewalls at a rate greater than the rate at which it etches the less chlorine-free silicon nitride layer at the bottom of the source / drain trench 228, a bottom isolation layer 240 can be formed on a buffer epitaxial layer such as separator layer 238. It is worth noting that the step of forming the bottom isolation layer 240 may be optional (e.g., step 120). This means that in some embodiments, the formation step of the bottom isolation layer 240 may be omitted, and the bottom isolation layer 240 may not be present in the final structure.

[0036] As shown in Figures 1, 18, and 19, step 122 of method 100 epitaxially grows a source / drain structure 244 from the semiconductor surface exposed in the source / drain trench 228 (including the sidewalls of the channel layer 208). Although not illustrated, the method may include a cleaning process prior to the formation of any epitaxial layer to clean the surface of the semiconductor device 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using a mixture of deionized water and ammonium hydroxide and hydrogen peroxide, a mixture of deionized water and hydrogen chloride and hydrogen peroxide, a mixture of sulfuric acid and hydrogen peroxide, and / or hydrofluoric acid to remove oxides. Dry cleaning processes may include helium and hydrogen treatment.

[0037] The source / drain structure 244 shown in Figure 18 can be n-type or p-type. When the source / drain structure 244 is n-type, it may include silicon with n-type dopants such as phosphorus, arsenic, antimony, or combinations thereof. When the source / drain structure 244 is p-type, it may include silicon-germanium with p-type dopants such as boron, boron difluoride, or combinations thereof. Although not illustrated, the source / drain structure 244 in some embodiments may include multiple layers. For example, the source / drain structure 244 may include a lightly doped epitaxial structure on the bottom isolation layer 240 and a heavily doped epitaxial structure on the lightly doped epitaxial structure. The lightly doped epitaxial structure includes a smaller dopant concentration and impurity concentration to reduce crystallization defects. The heavily doped epitaxial structure occupies the majority of the volume to reduce junction resistance. The source / drain structure 244 can be formed by vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, or molecular beam epitaxy. The source / drain structure 244 can be doped in situ.

[0038] The partial cross-sectional view shown in Figure 19 spans multiple adjacent source / drain regions 212SD. In some embodiments shown in Figure 19, the n-type source / drain structure 244N is adjacent to the p-type source / drain structure 244P. The n-type source / drain structure 244N may include silicon and n-type dopants such as phosphorus, arsenic, or antimony. The p-type source / drain structure 244P may include silicon-germanium and p-type dopants such as boron. The n-type source / drain structure 244N and the p-type source / drain structure 244P may directly contact the upper surface of the bottom isolation layer 240. For simplicity of illustration and description, the n-type source / drain structure 244N and the p-type source / drain structure 244P may be considered together as source / drain structure 244, as shown in Figure 18. In some embodiments shown in Figure 18, the source / drain structures 244 in the YZ plane may each include a portion suspended above the isolation structure 214 and the isolation structure protective layer 215.

[0039] As shown in Figures 1 and 20-23, step 124 of method 100 deposits a contact etch stop layer 246 and an interlayer dielectric layer 248 in the source / drain region 212SD. As shown in Figure 20, the contact etch stop layer 246 is deposited on the source / drain structure 244. The contact etch stop layer 246 may comprise silicon nitride or aluminum nitride. In some embodiments, the deposition method for the contact etch stop layer 246 may be chemical vapor deposition or atomic layer deposition. The interlayer dielectric layer 248 is then deposited on the contact etch stop layer 246. In some embodiments, the interlayer dielectric layer 248 may comprise a tetraethoxysilane oxide, undoped silicate glass, or doped silica (such as borosilicate glass, fluorosilicone glass, phosphosilicone glass, borosilicate glass, and / or other suitable dielectric materials). The interlayer dielectric layer 248 can be deposited using chemical vapor deposition, flowable chemical vapor deposition, spin coating, or a suitable deposition technique. As shown in Figure 21, the contact etch stop layer 246 also pads the voids beneath the isolation structure protective layer 215. The bottom of the contact etch stop layer 246 and the interlayer dielectric layer 248 extends beneath the gate spacer 226 and is partially buried in the isolation structure 214. As shown in Figure 22, the contact etch stop layer 246 also covers the fin spacer 226. As shown in Figure 23, after depositing the interlayer dielectric layer 248, the semiconductor device 200 can be planarized by a planarization process to remove the gate top hard mask layer 222 and expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical polishing process. After planarization, the contact etch stop layer 246, the interlayer dielectric layer 248, the gate spacer 226, and the upper surface of the dummy gate stack 220 are coplanar.

[0040] As shown in Figures 1 and 24-26, in step 126 of method 100, the dummy gate stack 220 is selectively removed, followed by the removal of the sacrificial layer 206. At the end of step 124, the dummy gate stack 220 is exposed, after which it can be removed. The removal of the dummy gate stack 220 may include one or more etching processes that are selective for the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 220, and the etching methods are selective for the dummy gate stack 220. Removing the dummy gate stack 220 may form a gate trench 250 to expose the stack of the channel layer 208 and the sacrificial layer 206. After removing the dummy gate stack 220, the sacrificial layer 206 in the channel region 212C is exposed, and then the exposed sacrificial layer 206 is removed by separate etching processes. For example, selective wet etching or selective dry etching processes may be performed to remove the sacrificial layer 206. Examples of selective wet etching processes may include using dilute hydrofluoric acid, or a mixture of hydrofluoric acid and ammonium fluoride. Examples of selective dry etching processes may include using hydrofluoric acid vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or combinations thereof. After removing the sacrificial layer 206, the channel layer 208 is released as a channel assembly.

[0041] As shown in Figure 26, the etching process can partially recess the isolation structure protective layer 215 to form a channel, causing the lower surface of the gate trench 250 to extend below the upper surface of the isolation structure protective layer 215. Nevertheless, the isolation structure protective layer 215 prevents the gate trench 250 from extending through it, thereby ensuring the integrity of the isolation structure 214 beneath the gate trench 250. To illustrate the case without the isolation structure protective layer 215, Figure 26 includes dashed lines to represent an alternative lower surface of the gate structure 260, which can extend into the isolation structure 214. In subsequent steps, a metal gate structure can be deposited in the gate trench 250. The vertical distance D214 between the lower surface of the isolation structure 214 and the lower surface of the gate trench 250 is the maximum thickness that the isolation structure 214 can be thinned in the back-side process. Otherwise, the metal gate structure would be exposed from the back side of the semiconductor device 200 and potentially damaged. In other words, a sufficiently thick isolation structure 214 must be maintained to limit the height of the back-side via used to reduce via resistance. On the other hand, when using the isolation structure protective layer 215, the lower surface of the metal gate structure remains higher than the upper surface of the isolation structure 214. In this example, the isolation structure protective layer 215 can serve as a thinning stop layer in the back-side process to substantially remove the isolation structure 214 and reduce the height of the back-side via, thereby reducing the resistance of the back-side via. Further details of the solution will be explained below.

[0042] As shown in Figures 1 and 27-29, step 128 of method 100 forms a gate structure 260 (such as a p-type gate structure 260P for p-type transistors and an n-type gate structure 260N for n-type transistors) in the gate trench 250 to cover each channel component, such as channel layer 208. The gate structure 260 can also be considered a metal gate structure due to its metal layer. In the embodiment, the gate structure 260 includes an interface layer 262 at the interface with the channel component, such as channel layer 208, a high-dielectric-constant dielectric layer 264 on the interface layer 262, and a gate layer 266 on the high-dielectric-constant dielectric layer 264. The interface layer 262 and the high-dielectric-constant dielectric layer 264 can be considered together as the gate dielectric layer.

[0043] Interface layer 262 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. Interface layer 262 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. In the described embodiment, interface layer 262 may be formed by thermally oxidizing the semiconductor material exposed in the gate trench 250. Therefore, interface layer 262 is formed on a semiconductor surface (e.g., on the exposed surface of channel components such as channel layer 208 and the upper surface of fin substrate 212B), but not on a dielectric surface (e.g., on the sidewalls of inner spacer 236, the sidewalls of gate spacer 226, and the upper surface of isolation structure protective layer 215 (FIG. 29)). High dielectric constant dielectric layer 264 may include a high dielectric constant dielectric material such as hafnium oxide. The gate dielectric layer can be replaced with other dielectric materials with high dielectric constants, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium dioxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, zirconium oxide, yttrium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, combinations thereof, or other suitable materials. The dielectric constant of the high dielectric constant dielectric layer 264 is greater than the dielectric constant of the gate spacer 226. The high dielectric constant dielectric layer 264 can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and / or other suitable methods. As shown in Figure 29, the high dielectric constant dielectric layer 264 can be compliantly deposited on the exposed dielectric surface in the gate trench 250.

[0044] Gate layer 266 includes a work function metal layer and a metal filler layer located on the work function metal layer. The work function metal layer is a p-type work function metal layer in a p-type transistor or an n-type work function metal layer in an n-type transistor. The metal included in the p-type work function metal layer is selected from, but is not limited to, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The metal included in the n-type work function metal layer is selected from, but is not limited to, titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the p-type or n-type work function metal layer comprises multiple layers, and its deposition method is chemical vapor deposition, physical vapor deposition, and / or other suitable processes. The metal filler layer includes aluminum, tungsten, cobalt, copper, and / or other suitable materials, and its formation method is chemical vapor deposition, physical vapor deposition, electroplating, and / or other suitable processes.

[0045] As shown in Figures 1 and 30, step 130 of method 100 forms a gate-end dielectric structure 270. The gate-end dielectric structure 270 segments the originally continuous gate structure 260, and can also be considered as segmenting a metal gate structure. In the embodiment, the gate-end dielectric structure 270 isolates n-type and p-type fully wound gate transistors (such as dual transistors in complementary metal-oxide-semiconductor devices) from other adjacent devices. The gate-end dielectric structure 270 can be a single-layer or multi-layer structure. For a multi-layer structure, the gate-end dielectric structure 270 may include a dielectric pad 272 and a dielectric fill layer 274. In an exemplary process flow, the step of forming the gate-end dielectric structure 270 includes etching through the gate structure 260 to form a cut metal gate trench that extends through the isolation structure protective layer 215 and to the isolation structure 214 for better isolation; conformally depositing a dielectric pad 272 on the sidewalls and lower surface of the cut metal gate trench; depositing a dielectric filler layer 274 to fill the cut metal gate trench; and performing a planarization process (such as chemical mechanical polishing) to remove excess dielectric material. In some embodiments, the dielectric pad 272 is an oxide (such as silicon oxide), and the dielectric filler layer 274 is oxygen-free (such as nitrides such as silicon nitride or silicon carbonitride). The deposition method of the dielectric filler layer 274 may be atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable processes. The dielectric pad 272 and the dielectric filler layer 274 together define the gate-end dielectric structure 270.

[0046] As shown in Figures 1, 31, and 32, step 132 of method 100 forms a source / drain contact plug 280 (and, where appropriate, a silicon structure 282) between the source / drain contact plug 280 and the source / drain structure 244 in the source / drain region 212SD. In an exemplary embodiment, a capping layer 276 (which can also be considered an etch stop layer) and a second interlayer dielectric layer 278 are deposited on the semiconductor device 200. In some embodiments, the thickness of the interlayer dielectric layer 248 is greater than the thickness of the second interlayer dielectric layer 278. Etching is then performed through the second interlayer dielectric layer 278, the capping layer 276, the interlayer dielectric layer 248, and the contact etch stop layer 246 to form contact holes. The etching process can be a self-aligned process that uses the vertical sidewalls of the contact etch stop layer 246 as an etch stop layer to remove a portion of the interlayer dielectric layer 248 on the source / drain structure 244. The upper portion of the source / drain structure 244 may be etched to create a recessed shape, such as the bottom of a contact hole. A silica structure 282 is formed at the bottom of the contact hole. The silica structure 282 may include titanium silica, nickel silica, tungsten silica, nickel-platinum silica, nickel-platinum-germanium silica, nickel-germanium silica, ytterbium silica, platinum silica, iridium silica, erbium silica, cobalt silica, or other suitable compounds. Source / drain contact plugs 280 may then be formed on the silica structure 282. Each source / drain contact plug 280 may include a conductivity barrier layer and a base metal layer. The conductive barrier layer may include titanium, tantalum, tungsten, cobalt, ruthenium, or conductive nitrides (such as titanium nitride, titanium aluminum nitride, tungsten nitride, tantalum nitride, or combinations thereof), and its formation method is chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable processes. The substrate metal layer may include tungsten, cobalt, molybdenum, ruthenium, nickel, copper, or other metals, and its formation method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, or other suitable processes. The conductivity of the silicide structure 282 is between that of the source / drain structure 244 and the source / drain contact plug 280, and the conductivity of the source / drain contact plug 280 is greater than that of the source / drain structure 244. The silicide structure 282 and the source / drain contact plug 280 can be considered together as a source / drain contact. As shown in Figure 32, the source / drain contact plug 280 in section CC extends further downward than in section BB and lands directly on the bottom of the interlayer dielectric layer 248 without the silicon structure 282 located between them.

[0047] As shown in Figures 1, 33, and 34, step 134 of method 100 involves bonding the front side of the semiconductor device 200 to the carrier plate 284 and flipping it over. This allows subsequent processing of the semiconductor device 200 from the back side. Step 134 can employ any suitable bonding process, such as direct bonding, hybrid bonding, adhesive bonding, or other bonding methods. Step 134 may further include alignment, annealing, and / or other processes. In some embodiments, the carrier plate 284 may be a silicon wafer.

[0048] As shown in Figures 1 and 35-37, step 136 of method 100 thins the semiconductor device 200 from the back side. In some embodiments, the thinning process may involve mechanical polishing and / or chemical thinning. Initially, a large amount of substrate material is removed from the substrate 202 via mechanical polishing. A chemical thinning process may then be employed, which applies etch chemicals to the back side of the substrate 202 for further thinning, such as removing the isolation structure 214. The thinning process uses an isolation structure protective layer 215 as a thinning stop layer to ensure that the process stops at the lower surface of the isolation structure protective layer 215. Because the isolation structure 214 and the isolation structure protective layer 215 have different material compositions, exposing the isolation structure protective layer 215 causes a significant change in the endpoint signal, thereby providing highly precise thickness control. In the embodiment described above, once the isolation structure protective layer 215 is exposed, additional structures such as the fin substrate 212B (FIG. 35), the separator layer 238 (FIG. 36), the contact etch stop layer 246, and the interlayer dielectric layer 248 (FIG. 37) may also be exposed on the back side of the semiconductor device 200.

[0049] As shown in Figure 37, the isolation structure protective layer 215, serving as a thinning stop layer, can be retained to protect the lower surface of the gate structure 260 from exposure during the back-side thinning process. To illustrate the case without the isolation structure protective layer 215, Figure 37 includes dashed lines to represent an alternative lower surface of the gate structure 260, which extends into the isolation structure 214. The vertical distance (D214) between the lower surface B214 of the isolation structure 214 and the lower surface of the gate structure 260 represents the maximum thickness that the isolation structure 214 can be thinned without exposing the gate structure 260. Exposing the gate structure 260 from the back side may pose a risk of damage. Therefore, a sufficiently thick isolation structure 214 must be retained to limit the height of the back-side vias, thereby limiting the reduction in via resistance. Conversely, with the isolation structure protective layer 215, the isolation structure 214 can be substantially removed, reducing the height of the back-side vias. A reduced via height reduces the resistance of the back-side interconnect wiring.

[0050] As shown in Figures 1 and 38, step 138 of method 100 forms a back-side via opening 288 to expose the back side of the source / drain structure 244. In one embodiment, the exposed source / drain structure 244 is a source structure and maintains coverage of the drain structure. Step 138 may include selectively etching a separator layer 238 to form an initial opening to expose a bottom isolation layer 240, followed by selectively etching the bottom isolation layer 240 to extend the opening to the lower surface of the source / drain structure 244. In the XZ plane, the back-side via opening 288 extends through the separator layer 238 and the bottom isolation layer 240. Some residual portions of the separator layer 238 and the bottom isolation layer 240 may be retained in corner areas. In the embodiment, the bottom of the back-side via opening 288 has a recessed profile that is lower than the bottommost inner spacer 236.

[0051] As shown in Figures 1 and 39, step 140 of method 100 forms a spacer layer 290 and a back-side via 292 in the back-side via opening 288. The spacer layer 290 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, and / or combinations thereof. For example, the spacer layer 290 may be formed by compliantly depositing a dielectric material layer on the back side of the semiconductor device 200, using a process such as chemical vapor deposition, sub-pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable processes. In the embodiment described, after depositing the dielectric material layer, an etch-back (non-isotropic) process is performed to remove the dielectric material layer from the horizontal surface and expose the lower surface of the source / drain structure 244. The dielectric material layer may remain on the sidewall of the back-side via opening 288 as the spacer layer 290. The conductive material of the back-side via 292 may include tungsten, cobalt, molybdenum, ruthenium, copper, nickel, titanium, tantalum, titanium nitride, tantalum nitride, or other metals, and its formation method may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, or other suitable processes. The conductive material may cover the back surface of the semiconductor device 200. The spacer layer 290 acts as a diffusion barrier layer to prevent metal elements in the back-side via 292 from diffusing into the surrounding dielectric structure. In one embodiment, the back-side via 292 directly contacts the source / drain structure 244. In one embodiment, a silicon structure 294 may be formed between the source / drain structure 244 and the back-side via 292, as appropriate, to further reduce the contact resistance. The silicate structure 294 may include titanium silicate, nickel silicate, tungsten silicate, nickel-platinum silicate, nickel-platinum-germanium silicate, nickel-germanium silicate, ytterbium silicate, platinum silicate, iridium silicate, erbium silicate, cobalt silicate, combinations thereof, or other suitable compounds. The silicate structure 294 and the back-side via 292 can be considered together as a back-side contact. A planarization step, such as a chemical mechanical polishing process, is performed to remove excess conductive material from the back-side via 292. An isolation structure protective layer 215 can serve as a stop layer for the planarization step, allowing the back-side via 292, spacer layer 290, adjacent separator layer 238, contact etch stop layer 246, and interlayer dielectric layer 248 to have a coplanar lower surface.

[0052] As shown in Figures 1 and 40, step 142 of method 100 forms one or more backside interconnect layers 296. The backside interconnect layer 296 includes backside metal lines (as shown in the figure, backside metal lines 298) embedded therein. The backside metal lines 298 are electrically connected to the source / drain structure 244 via backside vias 292. Reducing the height of the backside vias 292 can lower the contact resistance between the backside metal lines 298 and the source / drain structure 244. In one embodiment, the backside metal lines 298 may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable processes. The backside metal lines 298 may include tungsten, cobalt, molybdenum, ruthenium, copper, nickel, titanium, tantalum, titanium nitride, tantalum nitride, or other metals, and their deposition methods may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, or other suitable processes. In some embodiments, the backside metal lines 298 are a portion of a backside power rail. In one example, the source / drain structure 244 electrically connected to the back-side metal line 298 is a source structure (e.g., the source structure of a pull-down transistor in a static random access memory cell), and the back-side metal line 298 is an electrically grounded line. In another example, the source / drain structure 244 electrically connected to the back-side metal line 298 is a source structure (e.g., the source structure of a pull-up transistor in a static random access memory cell), and the back-side metal line 298 is a power line. In some other embodiments, the back-side metal line 298 is a signal line, and the source / drain structure 244 electrically connected to the back-side metal line 298 is a drain structure, such as the drain structure of a pull-up or pull-down transistor in a static random access memory cell. Although not shown in FIG40, the back-side interconnect layer 296 may include other contacts, vias, wire bonding, and / or other conductive structures. The back-side interconnect structure helps increase the number of feasible metal rails in the semiconductor device 200 that are directly connected to the source / drain structure. The size of the back-side power rails and / or signal lines can be wider than the size of the first layer of metal rails (such as the rails of the zeroth metal layer) on the front side of the semiconductor device 200, in order to reduce the resistance of the back-side power rails.

[0053] After step 142, the semiconductor device 200 is flipped back (as shown in the individual cross-sections AA, BB, and CC in Figures 41 to 43) to perform subsequent fabrication processes to complete the final device. For example, method 100 may remove the carrier substrate, form more interconnect layers on the front side, form a passivation layer on the top of the semiconductor device 200, dicing the wafer into a chip, and packaging the chip.

[0054] Figures 44 to 46 are diagrams of the semiconductor device 200 in other embodiments at cross sections AA, BB, and CC. The difference between the embodiments of Figures 44 to 46 and those of Figures 41 to 43 is that the back-side thinning process in step 136 can thin the isolation structure 214 without substantially removing it. The back-side thinning process can be time-mode to control the thickness of the isolation structure 214. Nevertheless, the presence of the isolation structure protector layer 215 can further thin the isolation structure 214 without considering accidental exposure of the gate structure 260 from the back side of the semiconductor device 200. As shown in Figure 44, the isolation structure 214 is located between the isolation structure protector layer 215 and the back-side interconnect layer 296. In some embodiments, the thickness of the retained isolation structure 214 is greater than the thickness of the isolation structure protector layer 215; in some other embodiments, the thickness of the retained isolation structure 214 is less than the thickness of the isolation structure protector layer 215, depending on application requirements. As shown in Figure 45, the substrate 202 can maintain coverage of the lower surface of the adjacent separator layer 238 because the excess thickness of the substrate 202 corresponds to the thickness of the retained isolation structure 214. As shown in Figure 46, the isolation structure 214 is located between the isolation structure protective layer 215 and the back side interconnect layer 296.

[0055] This invention provides one or more advantages, but is not limited thereto. For example, embodiments of the invention may incorporate an isolation structure protective layer to form a back-side via with reduced height. Depositing the isolation structure protective layer on the front side of the isolation structure before forming the metal gate structure protects the isolation structure from etching damage during front-side fabrication. Furthermore, the isolation structure protective layer acts as a thinning stop layer, ensuring that the metal gate structure is not exposed during back-side thinning. Ultimately, during back-side fabrication, the isolation structure can be substantially removed, resulting in a significantly lower-height back-side via and reduced associated resistance, thereby improving overall device performance.

[0056] This invention provides an exemplary embodiment of a method. The method includes forming a stack on a substrate, the stack having a plurality of interleaved sacrificial layers and a plurality of channel layers; patterning the stack and the substrate to form a first region and a second region, each extending longitudinally in a first direction, the first region including a first active region and a first base region, and the second region including a second active region and a second base region; forming an isolation structure between the first base region and the second base region, wherein the isolation structure intersects with the sidewalls of the first base region and the sidewalls of the second base region; depositing an isolation structure protective layer on the isolation structure; forming a dummy gate stack extending across the first active region and the second active region, and the dummy gate stack intersects with the upper surface of the isolation structure protective layer; depositing a plurality of gate spacers on the sidewalls of the dummy gate stack; and recessing the first active region and the second active region outside the dummy gate stack and the gate spacers. The process involves forming a first trench and a second trench; forming a first source / drain structure in the first trench and a second source / drain structure in the second trench, wherein a portion of the first source / drain structure is suspended on the isolation structure along a second direction, and a portion of the second source / drain structure is suspended on the isolation structure along a second direction, which is different from the first direction; removing dummy gate stacks to form a gate trench, exposing the isolation structure protective layer; removing a sacrificial layer from the gate trench; depositing a gate structure in the gate trench, with the gate structure and the upper surface of the isolation structure protective layer intersecting; thinning the substrate and the isolation structure; forming a back-side opening to expose the lower surface of the first source / drain structure; and forming a back-side via in the back-side opening for electrical coupling with the first source / drain structure. In some embodiments, the thinning step exposes the lower surface of the isolation structure protective layer. In some embodiments, the thinning step completely removes the isolation structure. In some embodiments, the isolation structure comprises an oxide, and the isolation structure protective layer comprises a nitride. In some embodiments, prior to forming the first source / drain structure and the second source / drain structure, a portion of the isolation structure protective layer between the first substrate region and the second substrate region is etched. In some embodiments, the method further includes depositing an interlayer dielectric layer on the first source / drain structure and the second source / drain structure. The bottom of the interlayer dielectric layer extends below the lower surface of the isolation structure protective layer. In some embodiments, the step of removing the dummy gate stack forms a channel on the isolation structure protective layer such that the bottom of the gate structure in the channel is lower than the upper surface of the isolation structure protective layer. In some embodiments, the method further includes forming a first buffer epitaxial layer in a first trench and forming a second buffer epitaxial layer in a second trench prior to forming the first source / drain structure and the second source / drain structure. A thinning step exposes the first buffer epitaxial layer. In some embodiments, the upper surface of the isolation structure protective layer between the first substrate region and the second substrate region has a dished profile. In some embodiments, the edge of the dished profile intersects with the sidewall of the bottommost one of the sacrificial layers.

[0057] Another embodiment of the present invention relates to a method for forming a semiconductor structure. The method includes providing a structure having a front side and a back side, the structure including a substrate on the back side of the structure and a fin-like structure on the front side of the structure; forming an isolation structure on the sidewalls of the fin-like structure; forming an isolation structure protective layer on the isolation structure; epitaxially growing a source / drain structure on the fin-like structure; depositing a contact etch stop layer on the source / drain structure; depositing a first interlayer dielectric layer on the contact etch stop layer; depositing a capping layer on the upper surface of the contact etch stop layer and the upper surface of the first interlayer dielectric layer; and depositing a second interlayer dielectric layer on the capping layer, wherein the thickness of the first interlayer dielectric layer is... The thickness is greater than that of the second interlayer dielectric layer; a source / drain contact plug is formed in the first interlayer dielectric layer to be electrically coupled to the source / drain structure; a metal silicate layer is formed between the source / drain structure and the source / drain contact plug, wherein the conductivity of the metal silicate layer is between that of the source / drain structure and the source / drain contact plug, wherein the metal silicate layer includes an arcuate profile; the structure is thinned from the back side of the structure until the isolation structure protective layer is exposed; an opening is formed to expose the lower surface of the source / drain structure; and a back-side via is deposited in the opening. In some embodiments, the thinning step also exposes the first interlayer dielectric layer from the back side of the structure. In some embodiments, the method further includes forming an undoped epitaxial layer under the source / drain structure, wherein the thinning step also exposes the undoped epitaxial layer. In some embodiments, the method further includes forming a dummy gate stack over the fin structure; replacing the dummy gate stack with a metal gate structure, wherein the metal gate structure intersects with the upper surface of the isolation structure protective layer; and forming a dielectric structure to separate the metal gate structure, wherein the thinning step also exposes the dielectric structure. In some embodiments, the thickness of the isolation structure protective layer is from about 10 nm to about 50 nm. In some embodiments, the method further includes etching through the isolation structure protective layer before epitaxially growing the source / drain structure.

[0058] Another exemplary embodiment of the present invention relates to a semiconductor structure. The semiconductor structure includes a first source / drain structure and a second source / drain structure; one or more nanostructures connecting the first source / drain structure and the second source / drain structure; a gate structure connecting the nanostructures, the gate structure including a gate dielectric layer and a gate layer located on the gate dielectric layer; a gate spacer extending along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; an interlayer dielectric layer located on the first source / drain structure and the second source / drain structure; and a source / drain junction extending... A gate structure is electrically coupled to a first source / drain structure via an interlayer dielectric layer, wherein the conductivity of the source / drain junction is greater than that of the first source / drain structure; a protective layer is located below and borders the lower surface of the gate structure, wherein the lower surface of the interlayer dielectric layer and the lower surface of the protective layer are coplanar; a back-side dielectric layer is located on the lower surface of the protective layer; a metal trace is embedded in the back-side dielectric layer; and a back-side via is located directly below the first source / drain structure and electrically connects the metal trace to the first source / drain structure. In some embodiments, the lower surface of the gate structure is lower than the upper surface of the protective layer. In some embodiments, the protective layer avoids the boundary between the gate structure and the back-side dielectric layer. In some embodiments, the upper surface of the metal trace borders the lower surface of the interlayer dielectric layer.

[0059] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0060] AA,BB,CC,DD: Cross-section B214: Lower surface D214: Vertical distance 100: Method 102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,​​142: Steps 200: Semiconductor devices 202:Substrate 204: Stacking 206: Sacrifice Layer 208: Channel Layer 212: Fin-like structure 212B: Fin-like base 212C: Passage Area 212SD: Source / Drain Region 214: Isolation Structure 215: Protective layer of isolation structure 216: Virtual Dielectric Layer 218: Dummy Electrode Layer 220: Virtual Gate Stack 222: Gate top hard shielding layer 226: Gate spacer 228: Source / Drain Trench 232: Indentation of the inner spacer 236: Inner spacer 238: Separator Layer 240: Bottom isolation layer 244: Source / Drain Structure 244N: n-type source / drain structure 244P: p-type source / drain structure 246: Contact Etching Stop Layer 248: Interlayer dielectric layer 250: Gate trench 260: Gate structure 260N: n-type gate structure 260P: p-type gate structure 262: Interface Layer 264: Dielectric layers with high dielectric constant 266: Gate layer 270: Gate terminal dielectric structure 272: Dielectric Pad 274: Dielectric filling layer 276: Cap layer 278: Second interlayer dielectric layer 280: Source / drain contact plug 282: Silicon structure 284: Carrier plate 288: Backside through-hole opening 290: Spacer layer 292: Backside through hole 294: Silicon structure 296: Backside Inner Connection Layer 298: Backside metal wiring

Claims

1. A method for forming a semiconductor structure, comprising: A stack is formed on a substrate, the stack having multiple interleaved sacrificial layers and multiple channel layers; The stack and the substrate are patterned to form a first region and a second region extending longitudinally in a first direction, the first region including a first active region and a first base region, and the second region including a second active region and a second base region; an isolation structure is formed between the first base region and the second base region, wherein the isolation structure and the sidewall of the first base region intersect with the sidewall of the second base region; an isolation structure protective layer is deposited on the isolation structure; a dummy gate stack is formed to extend across the first active region and the second active region, and the dummy gate stack intersects with the upper surface of the isolation structure protective layer; a plurality of gate spacers are deposited on the sidewall of the dummy gate stack; the first active region and the second active region outside the dummy gate stack and the gate spacers are recessed to form a first trench and a second trench, respectively; A first source / drain structure is formed in the first trench, and a second source / drain structure is formed in the second trench. A portion of the first source / drain structure is suspended on the isolation structure along a second direction, and a portion of the second source / drain structure is suspended on the isolation structure along the second direction, which is different from the first direction. The dummy gate stack is removed to form a gate trench, and the gate trench exposes the isolation structure protective layer. The sacrificial layers are removed from the gate trench. A gate structure is deposited in the gate trench, and the gate structure intersects with the upper surface of the isolation structure protective layer. The substrate and the isolation structure are thinned. A back-side opening is formed to expose the lower surface of the first source / drain structure. A back-side via is formed in the back-side opening for electrical coupling with the first source / drain structure.

2. The method for forming a semiconductor structure as described in claim 1, wherein the thinning step exposes the lower surface of the protective layer of the isolation structure.

3. The method for forming a semiconductor structure as described in claim 1, wherein the thinning step completely removes the isolation structure.

4. A method for forming a semiconductor structure as described in claim 1 or 2, wherein the isolation structure comprises an oxide and the protective layer of the isolation structure comprises a nitride.

5. A method for forming a semiconductor structure, comprising: A structure is provided having a front side and a back side, the structure including a substrate on the back side and a fin-like structure on the front side; an isolation structure is formed on the sidewall of the fin-like structure; an isolation structure protective layer is formed on the isolation structure; a source / drain structure is epitaxially grown on the fin-like structure; a contact etch stop layer is deposited on the source / drain structure; a first interlayer dielectric layer is deposited on the contact etch stop layer; a capping layer is deposited on the upper surface of the contact etch stop layer and the upper surface of the first interlayer dielectric layer; a second interlayer dielectric layer is deposited on the capping layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a source / drain contact plug is formed in the first interlayer dielectric layer for electrical coupling to the source / drain structure. A metal silicate layer is formed between the source / drain structure and the source / drain contact plug, wherein the conductivity of the metal silicate layer is between that of the source / drain structure and that of the source / drain contact plug, and wherein the metal silicate layer includes an arcuate profile; the structure is thinned from the back side of the structure until the isolation structure protective layer is exposed; an opening is formed to expose the lower surface of the source / drain structure; and a back-side via is deposited in the opening.

6. The method for forming a semiconductor structure as described in claim 5, wherein the step of thinning the structure also exposes the first interlayer dielectric layer from the back side of the structure.

7. The method for forming a semiconductor structure as described in claim 5 further includes: An undoped epitaxial layer is formed under the source / drain structure, and the thinning step of the structure also exposes the undoped epitaxial layer.

8. A semiconductor structure, comprising: A first source / drain structure and a second source / drain structure; one or more nanostructures connecting the first source / drain structure and the second source / drain structure; a gate structure connecting the one or more nanostructures, the gate structure including a gate dielectric layer and a gate layer located on the gate dielectric layer; a gate spacer extending along the sidewall of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer; an interlayer dielectric layer located on the first source / drain structure and the second source / drain structure; a source / drain contact extending through the interlayer dielectric layer and electrically coupled to the first source / drain structure, wherein the conductivity of the source / drain contact is greater than the conductivity of the first source / drain structure; a protective layer located below and bordering the lower surface of the gate structure, wherein the lower surface of the interlayer dielectric layer and the lower surface of the protective layer are coplanar. A back-side dielectric layer is located on the lower surface of the protective layer; a metal circuit is embedded in the back-side dielectric layer; and a back-side via is located directly under the first source / drain structure and electrically connects the metal circuit to the first source / drain structure.

9. The semiconductor structure as claimed in claim 8, wherein the lower surface of the gate structure is lower than the upper surface of the protective layer.

10. The semiconductor structure as described in claim 8 or 9, wherein the protective layer prevents the gate structure from intersecting with the back-side dielectric layer.

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