Circuit structure

TWI935807BActive Publication Date: 2026-08-11SILICONWARE PRECISION IND CO LTD
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Patent Information

Application Number
TW114119067
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-05-21
Publication Date
2026-08-11
Estimated Expiration
2045-05-20

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  • Figure TWG2TB001905746_003
    Figure TWG2TB001905746_003
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Abstract

This invention discloses a circuit structure, comprising: a dielectric material; two wiring blocks, each encapsulated within the dielectric material and comprising a first wiring layer and a second wiring layer located above the first wiring layer; and a circuit block, encapsulated within the dielectric material and comprising at least one circuit layer; wherein the two wiring blocks are spaced apart and adjacent to each other and symmetrically arranged to form a capacitor module. By implementing this invention, the area and volume of electronic packages can be significantly reduced by replacing conventional capacitor elements with capacitor modules formed by symmetrical wiring blocks, while also effectively reducing noise within the electronic package and significantly improving power and signal quality within the electronic package.
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Claims

1. A circuit structure comprising: Dielectric materials; The two wiring blocks are encapsulated in the dielectric material and respectively include a first wiring layer and a second wiring layer located above the first wiring layer; The circuit blocks are encapsulated in the dielectric material and include a circuit layer; wherein the two wiring blocks are spaced apart and adjacent to each other and symmetrically arranged to form a capacitor module.

2. The circuit structure as described in claim 1, wherein, Each wiring block contains a through conductive via, and each through conductive via passes through the dielectric material from the top of the wiring block and is electrically connected to the first wiring layer and the second wiring layer.

3. The circuit structure as described in claim 2, wherein, Each wiring block contains an interlayer conductive via corresponding to the through conductive via, and each interlayer conductive via is electrically connected to the second wiring layer after passing through the dielectric material from the top of the wiring block.

4. The circuit structure as described in claim 2, wherein, The two through-holes in the two wiring blocks are symmetrically arranged in the capacitor module.

5. The circuit structure as described in claim 3, wherein, The interlayer conductive via of one of the two wiring blocks is symmetrically disposed in the capacitor module with the interlayer conductive via of the other wiring block.

6. The circuit structure as described in claim 4, wherein, The two through-holes in the two wiring blocks are arranged adjacent to each other in the capacitor module.

7. The circuit structure as described in claim 4, wherein, The two through-holes in the two wiring blocks are disposed far apart in the capacitor module.

8. The circuit structure as described in claim 5, wherein, The interlayer conductive via of one of the two wiring blocks is disposed adjacent to the interlayer conductive via of the other wiring block in the capacitor module.

9. The circuit structure as described in claim 5, wherein, The interlayer conductive via of one of the two wiring blocks is disposed in the capacitor module in a way that is far away from the interlayer conductive via of the other wiring block.

10. The circuit structure as described in claim 3, wherein, Each of the through-holes and interlayer conductive vias exposed on the end face of the dielectric material has an electrical connection pad formed thereon.

Citation Information

Patent Citations

  • Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer

    TW201240104A

  • Semiconductor structure and method of manufacturing the same

    TW202505652A

  • Semiconductor device with base support structure

    US20050280156A1

  • One-transistor RAM approach for high density memory application

    US6661043B1