Semiconductor package having side protections and method of making the same

Abstract

This invention relates to a semiconductor package with side protection and a method for manufacturing the same. The semiconductor package includes a semiconductor substrate, a plurality of contact pads, an electroplated metal layer, and a molded package. The molded package directly contacts all sides of each of the plurality of sides of the semiconductor substrate and all sides of each of the plurality of sides of the electroplated metal layer. The manufacturing method includes the following steps: providing a semiconductor device wafer; applying a first thinning process; applying a dicing process; attaching a panel; forming a first molded package; applying a second thinning process; forming a plurality of electroplated metal segments; removing the panel; and applying a dicing process.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a semiconductor package with side protection and its manufacturing method, wherein the thickness of the semiconductor substrate ranges from 15 micrometers to 35 micrometers. [Previous Technology]

[0002] The Protection Circuit Module (PCM) product contains two double-diffused metal-oxide-semiconductor field-effect transistors (DMOSFETs). Current flows into the PCM product, sequentially through the first DMOSFET, a common drain, and the second DMOSFET, and then flows out of the PCM product. To reduce resistance, a thin substrate and a thick electroplated metal layer are required. The manufacturing process of conventional PCM products uses a carrier to support the wafer in the polishing and metallization processes, resulting in high manufacturing costs.

[0003] This invention uses a panel to support the wafer in the grinding and metallization processes, thereby reducing manufacturing costs. Furthermore, the semiconductor package includes a molded package providing side protection, as well as optional top and bottom protection. [Summary of the Invention]

[0004] The purpose of this invention is to provide a semiconductor package with side protection and a method for manufacturing the same, which can provide a molded package with side protection while reducing manufacturing costs, as well as optional top and bottom protection.

[0005] To achieve the above objectives, the present invention provides a semiconductor package comprising: a semiconductor substrate including: a plurality of sides; a front surface; and a back surface opposite to the front surface; a plurality of contact pads attached to the front surface of the semiconductor substrate; an electroplated metal layer including: a plurality of sides; a front surface; and a back surface opposite to the front surface, wherein the front surface of the electroplated metal layer is directly attached to the back surface of the semiconductor substrate; and a molded package directly contacting all of each of the plurality of sides of the semiconductor substrate and all of each of the plurality of sides of the electroplated metal layer; wherein the thickness of the semiconductor substrate is in the range of 15 micrometers to 35 micrometers; and the thickness of the electroplated metal layer is in the range of 15 micrometers to 35 micrometers.

[0006] Preferably, the plurality of contact pads contain nickel and gold.

[0007] Preferably, the plurality of contact pads contain copper or silver.

[0008] Preferably, the electroplated metal layer comprises copper or silver.

[0009] Preferably, the molded encapsulation also directly contacts the entire back surface of the electroplated metal layer.

[0010] Preferably, the molded package also directly contacts the front surface of the semiconductor substrate; and the multiple front surfaces of the multiple contact pads are exposed from the molded package.

[0011] Preferably, the semiconductor package is a common drain double-diffused metal-oxide-semiconductor field-effect transistor, wherein the common drain double-diffused metal-oxide-semiconductor field-effect transistor includes: two source electrodes located on the front surface of the double-diffused metal-oxide-semiconductor field-effect transistor; and a common drain electrode located on the back surface of the double-diffused metal-oxide-semiconductor field-effect transistor.

[0012] The present invention also provides a method for manufacturing multiple semiconductor packages, the method comprising the following steps: providing a device wafer, including: a semiconductor substrate having a front surface and a back surface opposite to the front surface; and a plurality of contact pads attached to the front surface of the semiconductor substrate; applying a first thinning process to the back surface of the semiconductor substrate to form a thinned semiconductor substrate having a first predetermined thickness; applying a dicing process to separate multiple devices; attaching the multiple devices to a panel; forming a first molding package on multiple back surfaces of the multiple devices and in multiple gaps between the multiple devices; applying a second thinning process to remove most of the first molding package and further thin the multiple devices to form a plurality of thinned interconnects having a second predetermined thickness; forming a plurality of electroplated metal segments on the back surfaces of the plurality of thinned interconnects; forming a second molding package on multiple back surfaces of the plurality of electroplated metal segments and in multiple gaps between the plurality of electroplated metal segments; removing the panel; and applying a dicing process to form the multiple semiconductor packages.

[0013] Preferably, the first predetermined thickness ranges from 150 micrometers to 200 micrometers; and the second predetermined thickness ranges from 15 micrometers to 35 micrometers.

[0014] Preferably, the method for manufacturing a plurality of semiconductor packages with side protection further includes, after the step of removing the panel, applying a metal plating process to form a plurality of metal segments on top of a plurality of contact pads; forming a third molded package; and applying a third thinning process to thin the third molded package and the plurality of metal segments in order to expose a plurality of surfaces of the plurality of thinned metal segments.

[0015] Preferably, the multiple electroplated metal sections are formed by an electrode electroplating process.

[0016] Preferably, the plurality of contact pads contain nickel and gold.

[0017] Preferably, the plurality of electroplated metal sections contain copper or silver.

[0018] Preferably, each semiconductor package is a double-diffused metal-oxide-semiconductor field-effect transistor, wherein the double-diffused metal-oxide-semiconductor field-effect transistor includes: a source electrode located on the front surface of the double-diffused metal-oxide-semiconductor field-effect transistor; and a drain electrode located on the back surface of the double-diffused metal-oxide-semiconductor field-effect transistor.

[0019] Preferably, the first molded package directly contacts all of each side of each of the plurality of sides of each of the plurality of devices; and the second molded package directly contacts all of each side of each of the plurality of sides of each of the plurality of electroplated metal sections.

[0020] In summary, compared with the prior art, the semiconductor package with side protection and the manufacturing method thereof of the present invention can provide a molded package with side protection, as well as optional top protection and bottom protection, while reducing manufacturing costs, and has great practical value.

[0021] Details of various examples are set forth in the drawings and the description below. Other features and advantages will be apparent from the specification and drawings and the claims.

Implementation Method

[0023] The technical solutions, structural features, objectives and effects of the present invention will be described in detail below with reference to the drawings in the embodiments of the present invention.

[0024] FIG1A shows a cross-sectional view of a semiconductor package 100 in an example of this disclosure. The semiconductor package 100 includes a semiconductor substrate 102, a plurality of contact pads 104, an electroplated metal layer 106, and a molded package 108. The semiconductor substrate 102 includes a plurality of sides 101, a front surface 103, and a back surface 105 opposite to the front surface 103. The plurality of contact pads 104 are attached to the front surface 103 of the semiconductor substrate 102. The electroplated metal layer 106 includes a plurality of sides 111, a front surface 113, and a back surface 115 opposite to the front surface 113. The front surface 113 of the electroplated metal layer 106 is directly attached to the back surface 105 of the semiconductor substrate 102. The molded package 108 directly contacts all of each side of the plurality of sides 101 of the semiconductor substrate 102 and all of each side of the plurality of sides 111 of the electroplated metal layer 106.

[0025] In the examples of this disclosure, the thickness of the semiconductor substrate 102 ranges from 150 micrometers to 200 micrometers. The thickness of the electroplated metal layer 106 ranges from 15 micrometers to 35 micrometers.

[0026] In the examples of this disclosure, the semiconductor substrate 102 is made of silicon. Multiple contact pads 104 comprise nickel and gold. An electroplated metal layer 106 comprises copper or silver.

[0027] In the example of this disclosure, the semiconductor package 100 is a double-diffused metal-oxide-semiconductor field-effect transistor (DMOSFET). The DMOSFET includes: a source electrode 117 located on the front surface of the DMOSFET; and a drain electrode located on the back surface of the DMOSFET 119.

[0028] FIG1B shows a cross-sectional view of a semiconductor package 120 in an example of this disclosure. The semiconductor package 120 includes a semiconductor substrate 122, a plurality of contact pads 124, an electroplated metal layer 126, and a molded package 128. The semiconductor substrate 122 includes a plurality of sides 121, a front surface 123, and a back surface 125 opposite to the front surface 123. The plurality of contact pads 124 are attached to the front surface 123 of the semiconductor substrate 122. The electroplated metal layer 126 includes a plurality of sides 131, a front surface 133, and a back surface 135 opposite to the front surface 133. The front surface 133 of the electroplated metal layer 126 is directly attached to the back surface 125 of the semiconductor substrate 122. The molded package 128 directly contacts all of each side of the plurality of sides 121 of the semiconductor substrate 122, and all of each side of the plurality of sides 131 of the electroplated metal layer 126. The molded package 128 also directly contacts the entire back surface 135 of the electroplated metal layer 126.

[0029] FIG1C shows a cross-sectional view of a semiconductor package 140 in an example of this disclosure. The semiconductor package 140 includes a semiconductor substrate 142, a plurality of contact pads 144, an electroplated metal layer 146, and a molded package 148. The semiconductor substrate 142 includes a plurality of sides 141, a front surface 143, and a back surface 145 opposite to the front surface 143. The plurality of contact pads 144 are attached to the front surface 143 of the semiconductor substrate 142. The electroplated metal layer 146 includes a plurality of sides 151, a front surface 153, and a back surface 155 opposite to the front surface 153. The front surface 153 of the electroplated metal layer 146 is directly attached to the back surface 145 of the semiconductor substrate 142. The molded package 148 directly contacts all of each of the plurality of sides 141 of the semiconductor substrate 142, and all of each of the plurality of sides 151 of the electroplated metal layer 146. The molded package 148 also directly contacts the front surface 143 of the semiconductor substrate 142. Multiple front surfaces of multiple contact pads 144 are exposed from the molded package 148.

[0030] FIG1D shows a cross-sectional view of a semiconductor package 160 in an example of this disclosure. The semiconductor package 160 includes a semiconductor substrate 162, a plurality of contact pads 164, an electroplated metal layer 166, and a molded package 168. The semiconductor substrate 162 includes a plurality of sides 161, a front surface 163, and a back surface 165 opposite to the front surface 163. The plurality of contact pads 164 are attached to the front surface 163 of the semiconductor substrate 162. The electroplated metal layer 166 includes a plurality of sides 171, a front surface 173, and a back surface 175 opposite to the front surface 173. The front surface 173 of the electroplated metal layer 166 is directly attached to the back surface 165 of the semiconductor substrate 162. The molded package 168 directly contacts all of each of the plurality of sides 161 of the semiconductor substrate 162, and all of each of the plurality of sides 171 of the electroplated metal layer 166. The molded package 168 also directly contacts the entire back surface 175 of the electroplated metal layer 166. The molded package 168 further directly contacts the front surface 163 of the semiconductor substrate 162. Multiple front surfaces of multiple contact pads 164 are exposed from the molded package 168.

[0031] Figure 2 is a flowchart of process 200 for manufacturing multiple semiconductor packages in this example of the present disclosure. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L and 3M show cross-sectional views of the corresponding steps of process 200 in Figure 2. Process 200 may begin from step 202.

[0032] In step 202, referring to FIG. 3A, a device wafer 302 is provided. The device wafer 302 includes a semiconductor substrate 310 on which a plurality of semiconductor devices are formed. The semiconductor substrate 310 has a front surface 312 and a back surface 314 opposite to the front surface 312. A plurality of contact pads 304 are attached to the front surface 312 of the semiconductor substrate 310 and exposed through a passivation layer 305. In an example of this disclosure, each semiconductor device may include a first DMOSFET and a second DMOSFET, which are formed as a common drain, and each contact pad 304 includes an aluminum source electrode and a gate electrode of the first DMOSFET and the second DMOSFET. Step 204 may be performed after step 202.

[0033] In step 204, referring to FIG. 3B, a first thinning process is applied to the back surface 314 of the semiconductor substrate 310 to form a thinned semiconductor substrate 311. In the examples of this disclosure, the thickness of the thinned semiconductor substrate 311 ranges from 150 micrometers to 200 micrometers. The thinning process may include back-side grinding and back-side etching. Step 206 may be performed after step 204.

[0034] In step 206, referring to FIG. 3C, a cutting process is applied to separate multiple devices 322. The multiple devices 322 include multiple back surfaces 329. Step 208 may be performed after step 206.

[0035] In step 208, referring to FIG3D, the plurality of devices 322 are flipped and attached to the panel 324. The length 325 of the panel 324 is greater than the sum of the lengths of each of the plurality of devices 322. Step 210 can be performed after step 208.

[0036] In step 210, referring to FIG3E, a first molded package 332 is formed on a plurality of back surfaces 329 of the plurality of devices 322 and in a plurality of gaps 337 between the plurality of devices 322. Step 212 may be performed after step 210.

[0037] In step 212, referring to FIG. 3F, a second thinning process is applied to remove most of the first molded package 332 and further thin the semiconductor substrate to form a plurality of thinned interconnect devices 342. The thickness of the plurality of thinned interconnect devices 342 ranges from 15 micrometers to 35 micrometers. The plurality of devices 342 are connected together by the remaining first molded package 332 material filling the gaps 337 between adjacent devices 342. Step 214 can be performed after step 212.

[0038] In step 214, referring to FIG. 3G, a plurality of electroplated metal segments 352 are formed on the back surfaces of the plurality of thinned connectors 342. Preferably, a seed layer of conductive material comprising Ti / Cu is deposited on the entire flat back surface of the plurality of thinned connectors 342 by sputtering. A photoresist layer is applied to the seed layer, and then the respective back surface regions of the plurality of thinned connectors 342 are exposed by a photomask process. An electrode electroplating process is applied to electroplat a metal segment 352 with a thickness of 15 micrometers to 35 micrometers on each thinned connector 342. The remaining photoresist and the exposed seed layer material are then removed. Each electroplated metal segment 352 substantially covers the entire back surface of the corresponding connector 342. In the examples of this disclosure, the plurality of electroplated metal segments 352 comprise copper or silver. The plurality of electroplated metal segments 352 include a plurality of back surfaces 359. Multiple electroplated metal sections 352 will become the electroplated metal layer 106 in Figure 1A, the electroplated metal layer 126 in Figure 1B, the electroplated metal layer 146 in Figure 1C, and the electroplated metal layer 166 in Figure 1D. Optionally, step 216 or step 218 can be performed after step 214.

[0039] In optional step 216 (shown in dashed lines), referring to FIG. 3H, a second molded package 362 is formed on a plurality of back surfaces 359 of a plurality of electroplated metal sections 352 and in a plurality of gaps 357 between the plurality of electroplated metal sections 352. If the second molded package 362 formed on the plurality of back surfaces 359 of the plurality of electroplated metal sections 352 is removed to expose the back surfaces 359 of the plurality of electroplated metal sections 352, then the semiconductor package 100 of FIG. 1A or the semiconductor package 140 of FIG. 1C will be formed. If the second molded package 362 formed on the plurality of back surfaces 359 of the plurality of electroplated metal sections 352 is not removed, then a portion of the second molded package 362 of FIG. 3H will become the bottom portion of the molded package 128 of FIG. 1B or the molded package 168 of FIG. 1D. Step 218 may be performed after optional step 216.

[0040] In step 218, referring to FIG3I, panel 324 of FIG3H is removed to form the processed wafer 372. Optional steps 220, 222, 224, or 226 may be performed after step 218.

[0041] In step 220 (shown by dashed lines), referring to FIG3J, after the flipped wafer 372, a metal plating process is applied to form a plurality of metal segments 376 on top of the plurality of aluminum contact pads 304. Alternatively, an electrodeless plating process is applied to form an Au / Ni plating layer with a thickness of up to 5 micrometers on top of each aluminum electrode. The process then skips optional steps 222 and 224 and proceeds directly to step 226. Alternatively, the electrodeless plating process may be applied before step 204.

[0042] The metal segment 376 can also be formed by an electrode plating process. Preferably, a conductive material seed layer comprising Ti / Cu is deposited on the front surface of the processed wafer 372 by sputtering. A photoresist layer is applied to the seed layer, and then the area of ​​each contact pad 304 is exposed by a photomask process. An electrode plating process is applied to plate a metal segment 376 with a thickness of 15 micrometers to 35 micrometers on each contact pad 304. The remaining photoresist and the exposed seed layer material are then removed. The metal segment 376 may comprise copper or silver. Optional steps 222, 224, or 226 may be performed after optional step 220.

[0043] In optional step 222 (shown in dashed lines), referring to FIG3K, a third molded package 382 is formed. The third molded package 382 is located on top of a plurality of metal segments 376 and fills a plurality of gaps 389 between the plurality of metal segments 376. If optional step 222 is skipped, the semiconductor package 100 of FIG1A or the semiconductor package 120 of FIG1B will be formed. If optional step 222 is not skipped, then (after the third thinning process in optional step 224) a portion of the third molded package 382 of FIG3K will become the top portion of the molded package 148 of FIG1C or the molded package 168 of FIG1D. Optional step 224 can be performed after optional step 222.

[0044] In optional step 224 (shown in dashed lines), referring to FIG3L, a third thinning process is applied to thin the third molded package 382 and the plurality of metal segments 376 to expose the plurality of surfaces 391 of the plurality of thinned metal segments 393 from the remaining third molded package 392. Step 226 may be performed after optional step 224.

[0045] In step 226, a dicing process is applied along multiple dicing lines 398 to dic the wafer to form multiple semiconductor packages 399. In the examples of this disclosure, each semiconductor package 399 is a common drain dual DMOSFET. The common drain dual DMOSFET includes two source electrodes and two gate electrodes located on the front surface; and a drain electrode located on the back surface. The first molded package 332 of FIG3E directly contacts all sides of each of the multiple sides of each package in the multiple semiconductor packages 399. The second molded package 362 of FIG3H directly contacts all sides of each of the multiple sides of each of the multiple electroplated metal sections 352.

[0046] Those skilled in the art will recognize that modifications to the examples disclosed herein are possible. For example, the number of the plurality of contact pads 104 may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined in the appended claims. [Simplified Explanation of the Diagram]

[0022] Figures 1A, 1B, 1C, and 1D show cross-sectional views of four semiconductor packages in the examples of this disclosure. Figure 2 shows a process flow diagram for manufacturing multiple semiconductor packages in the examples of this disclosure. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, and 3M show cross-sectional views of the corresponding steps of the process in Figure 2 in the examples of this disclosure.

Claims

1. A semiconductor package, comprising: A semiconductor substrate includes: a plurality of sides; a front surface; and a back surface opposite the front surface; a plurality of contact pads attached to the front surface of the semiconductor substrate; an electroplated metal layer including: a plurality of sides; a front surface; and a back surface opposite the front surface, the front surface of the electroplated metal layer being directly attached to the back surface of the semiconductor substrate; and a molded package directly contacting all of each of the plurality of sides of the semiconductor substrate and all of each of the plurality of sides of the electroplated metal layer; wherein the thickness of the semiconductor substrate ranges from 15 micrometers to 35 micrometers; and the thickness of the electroplated metal layer ranges from 15 micrometers to 35 micrometers; wherein the molded package also directly contacts all of the back surface of the electroplated metal layer.

2. The semiconductor package as described in claim 1, wherein, The multiple contact pads contain nickel and gold.

3. The semiconductor package as described in claim 1, wherein, The plurality of contact pads contain copper or silver.

4. The semiconductor package as described in claim 1, wherein, The electroplated metal layer contains copper or silver.

5. A semiconductor package, comprising: A semiconductor substrate includes: a plurality of sides; a front surface; and a back surface opposite the front surface; a plurality of contact pads attached to the front surface of the semiconductor substrate; an electroplated metal layer including: a plurality of sides; a front surface; and a back surface opposite the front surface, the front surface of the electroplated metal layer being directly attached to the back surface of the semiconductor substrate; and a molded package directly contacting all of each of the plurality of sides of the semiconductor substrate and all of each of the plurality of sides of the electroplated metal layer; wherein the thickness of the semiconductor substrate is in the range of 15 micrometers to 35 micrometers; and the thickness of the electroplated metal layer is in the range of 15 micrometers to 35 micrometers; wherein the molded package also directly contacts the front surface of the semiconductor substrate; and wherein the plurality of front surfaces of the plurality of contact pads are exposed from the molded package.

6. The semiconductor package as described in claim 5, wherein, The multiple contact pads contain nickel and gold.

7. The semiconductor package as described in claim 5, wherein, The plurality of contact pads contain copper or silver.

8. The semiconductor package as described in claim 5, wherein, The electroplated metal layer contains copper or silver.

9. A semiconductor package, comprising: A semiconductor substrate includes: a plurality of side surfaces; a front surface; and a back surface opposite the front surface; a plurality of contact pads attached to the front surface of the semiconductor substrate; an electroplated metal layer including: a plurality of side surfaces; a front surface; and a back surface opposite the front surface, the front surface of the electroplated metal layer being directly attached to the back surface of the semiconductor substrate; and a molded package directly contacting all of each of the plurality of side surfaces of the semiconductor substrate and all of each of the plurality of side surfaces of the electroplated metal layer; wherein the thickness of the semiconductor substrate is in the range of 15 micrometers to 35 micrometers; and the thickness of the electroplated metal layer is in the range of 15 micrometers to 35 micrometers; wherein the semiconductor package is a common-drain double-diffused metal-oxide-semiconductor field-effect transistor, wherein the common-drain double-diffused metal-oxide-semiconductor field-effect transistor includes: two source electrodes located on the front surface of the double-diffused metal-oxide-semiconductor field-effect transistor; and a common drain electrode located on the back surface of the double-diffused metal-oxide-semiconductor field-effect transistor.

10. The semiconductor package as claimed in claim 9, wherein, The multiple contact pads contain nickel and gold.

11. The semiconductor package as described in claim 9, wherein, The plurality of contact pads contain copper or silver.

12. The semiconductor package as described in claim 9, wherein, The electroplated metal layer contains copper or silver.

13. A method for manufacturing a plurality of semiconductor packages, the method comprising the following steps: A device wafer is provided, comprising: a semiconductor substrate having a front surface and a back surface opposite to the front surface; and a plurality of contact pads attached to the front surface of the semiconductor substrate; applying a first thinning process to the back surface of the semiconductor substrate to form a thinned semiconductor substrate having a first predetermined thickness; applying a dicing process to separate a plurality of devices; attaching the plurality of devices to a panel; forming a first molding package in a plurality of back surfaces of the plurality of devices and in a plurality of gaps between the plurality of devices; applying a second thinning process to remove most of the first molding package and further thin the plurality of devices to form a plurality of thinned interconnects having a second predetermined thickness; forming a plurality of electroplated metal segments on the back surfaces of the plurality of thinned interconnects; forming a second molding package in a plurality of back surfaces of the plurality of electroplated metal segments and in a plurality of gaps between the plurality of electroplated metal segments; removing the panel; and applying a dicing process to form a plurality of semiconductor packages.

14. The method as described in claim 13, wherein, The first predetermined thickness ranges from 150 micrometers to 200 micrometers; and the second predetermined thickness ranges from 15 micrometers to 35 micrometers.

15. The method as described in claim 13, wherein, The method also includes, after the step of removing the panel, applying a metal plating process to form multiple metal sections on top of the multiple contact pads; Forming a third molded package; and applying a third thinning process to thin the third molded package and the plurality of metal segments to expose multiple surfaces of the plurality of thinned metal segments.

16. The method as described in claim 13, wherein, The multiple electroplated metal sections are formed through an electrode electroplating process.

17. The method as described in claim 13, wherein, The multiple contact pads contain nickel and gold.

18. The method as described in claim 13, wherein, The plurality of electroplated metal sections contain copper or silver.

19. The method as described in claim 13, wherein, Each of the semiconductor packages is a double-diffused metal-oxide-semiconductor field-effect transistor, wherein the double-diffused metal-oxide-semiconductor field-effect transistor includes: a source electrode located on the front surface of the double-diffused metal-oxide-semiconductor field-effect transistor; and a drain electrode located on the back surface of the double-diffused metal-oxide-semiconductor field-effect transistor.

20. The method as described in claim 16, wherein, The first molded package directly contacts all of each of the plurality of sides of each of the plurality of devices; and the second molded package directly contacts all of each of the plurality of sides of each of the plurality of electroplated metal segments.

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