Pixel control system

Abstract

A pixel control system is provided, including a plurality of scan lines, a plurality of data lines, and a processor, wherein the scan lines and data lines are coupled to a plurality of pixels, and the processor is configured to adjust a scan sequence of the scan lines and the pixel data output by the data lines according to the pixel data. The processor adjusts the scan sequence of the scan lines and correspondingly adjusts the pixel data output by the data lines so that at least two adjacent pixels coupled to the same data line receive the same pixel data.

Claims

1. A pixel control system, comprising: A plurality of scan lines and a plurality of data lines, wherein the scan lines and the data lines are coupled to a plurality of pixels; And a processor configured to adjust a scan sequence of the scan lines and the pixel data output by the data lines according to pixel data, wherein the processor adjusts the scan sequence of the scan lines and correspondingly adjusts the pixel data output by the data lines so that at least two adjacent pixels coupled to the same data line receive the same pixel data, wherein in response to the processor determining, based on the adjusted pixel data, that at least one of the scan lines is not enabled, the at least one of the scan lines is disabled.

2. The pixel control system as claimed in claim 1, wherein the processor includes a data analysis module configured to analyze the pixel data to adjust the pixel data output by the scan sequence and the data lines.

3. The pixel control system as described in claim 2, wherein the data analysis module is further configured to receive power data from the pixels to determine the power change of the pixels operating in the current scan sequence.

4. The pixel control system as described in claim 1, wherein the operation of the processor adjusting the scan sequence further includes: Pre-read the first pixel data of a first frame and a first scan sequence; Determine the state of the first pixel data corresponding to each of these data lines; And in response to the first pixel data corresponding to at least one of the data lines having different states, the first scan sequence is adjusted, and the sequence of the first pixel data is adjusted accordingly.

5. The pixel control system as claimed in claim 4, wherein, in the scan sequence before adjustment, the number of changes in the first pixel data corresponding to at least one of the data lines is greater than or equal to the number of changes in the first pixel data corresponding to the other data lines.

6. The pixel control system as described in claim 4, wherein the operation of the processor adjusting the scan sequence further includes: Read second pixel data and a second scan sequence from a second frame in advance; determine the state of the second pixel data corresponding to each of the data lines; In response to the fact that the second pixel data corresponding to at least one of the data lines has a different state, the second scan sequence is adjusted, and the sequence of the second pixel data is adjusted accordingly; and based on the correlation between the adjusted first pixel data and the adjusted second pixel data, the first scan sequence and the second scan sequence are adjusted to reduce the number of times the data lines change the state of the pixels when transitioning from the first screen to the second screen.

7. The pixel control system as described in claim 6, wherein the correlation between the adjusted first pixel data and the adjusted second pixel data includes: The adjusted first pixel data and the adjusted second pixel data enable the position or duration of the pixels.

8. The pixel control system as described in claim 6, wherein the operation of determining the state of the second pixel data corresponding to each of the data lines further includes: In response to the correlation between the second pixel data and the first pixel data being greater than or equal to a preset ratio, the processor adjusts the second scan sequence to be the same as the first scan sequence.

9. The pixel control system as described in claim 6, wherein in response to the processor determining that the pixels are operating in a low-power mode and transitioning from the first screen to the second screen, the processor continues to output the first pixel data.

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