Operating method for dual-path charge pump system

Abstract

Examples of several improved charge pumps are disclosed. In one example, a system includes: a first charge channel including a first stage for increasing an input voltage and a second stage for increasing a voltage received from the first stage of the first charge channel; and a second charge channel including a first stage for increasing an input voltage and a second stage for increasing a voltage received from the first stage of the second charge channel, wherein one output system of the second stage of the first charge channel is coupled to the first stage of the second charge channel, and one output system of the second stage of the second charge channel is coupled to the first stage of the first charge channel.

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 427,398, entitled "Dual-channel charge pump with cross-feedback", filed November 22, 2022, and U.S. Patent Application No. 18 / 109,397, entitled "Dual-channel charge pump", filed February 14, 2023.

[0002] Discloses an improved charge pump that utilizes dual channels and cross feedback between stages and channels. [Previous Technology]

[0003] Non-volatile memory systems are well known. For example, U.S. Patent No. 5,029,130 ​​(“130 Patent”) discloses a discrete-gate non-volatile memory cell array of the type of flash memory cell, which is incorporated herein by reference. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion and a second portion, the first portion being disposed over and insulated from (and controlling the conductivity of) the second portion of the channel region 18, and the second portion extending upward and over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bit line 24 is coupled to drain region 16.

[0004] By applying a high positive voltage to the word line terminal 22 to erase the memory cell 110 (wherein electrons are removed from the floating gate), electrons on the floating gate 20 tunnel from the floating gate 20 through the intermediate insulator to the word line terminal 22 by Fowler-Nordheim tunneling.

[0005] The memory cell 110 is programmed by source-side injection (SSI) using hot electrons (where electrons are placed on a floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. The electron flow will be from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected onto the floating gate 20 through the gate oxide.

[0006] The memory cell 110 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (which conducts a portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., electrons are erased), a portion of the channel region 18 below the floating gate 20 is also conducted, and current flows through the channel region 18, thus being sensed as an erased state or state "1". If the floating gate 20 is negatively charged (i.e., programmed with electrons), a portion or all of the channel region below the floating gate 20 is turned off, and current does not flow through (or only a small portion flows through) the channel region 18, thus being sensed as a programmed state or state "0".

[0007] Table 1 describes the typical voltage and current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and program operations: Table 1: Operation of flash memory cell 110 in Figure 1 WL BL SL Read 2-3V 0.6-2V 0V erase ~11-13V 0V 0V Programming 1-2V 10.5-3µA 9-10V

[0008] Other discrete gate memory cell configurations are other types of flash memory cells, which are known. For example, FIG2 depicts a four-gate memory cell 210, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 above a second portion of the channel region 18 (typically coupled to a word line WL), a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for various purposes. Here, except for the floating gate 20, all other gates are non-floating gates, meaning that they are electrically connected or can be connected to a voltage source. Programming is performed by injecting heated electrons from the channel region 18 onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] Table 2 describes the typical voltage and current ranges that can be applied to the terminals of memory cell 210 to perform read, erase, and program operations: Table 2: Operation of flash memory cell 210 in Figure 2 WL / SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V erase -0.5V / 0V 0V 0V / -8V 8-12V 0V Programming 1V 0.1-1µA 8-11V 4.5-9V 4.5-5V

[0010] Figure 3 depicts a three-gate memory cell 310, which is another type of flash memory cell. Except that memory cell 310 does not have a separate control gate, it is identical to memory cell 210 in Figure 2. The erase operation (erasing by using the erase gate) and read operation are similar to those in Figure 2, except that no control gate bias is applied. Programming operations are also performed without a control gate bias; as a result, a higher voltage must be applied to the source line during programming operations to compensate for the lack of a control gate bias.

[0011] Table 3 describes the typical voltage and current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations: Table 3: Operation of flash memory cell 310 in Figure 3 WL / SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V erase -0.5V / 0V 0V 11.5V 0V Programming 1V 0.2-3µA 4.5V 7-9V

[0012] Figure 4 depicts a stacked gate memory cell 410, which is another type of flash memory cell. Except that the floating gate 20 extends over the entire channel region 18 and the control gate 22 (which will be coupled to the word line here) extends over the floating gate 20 and is separated by an insulating layer (not shown), the memory cell 410 is similar to the memory cell 110 of Figure 1. Erasing is accomplished by electron tunneling from the FG to the FN of the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16 using electrons flowing from the source region 14 to the drain region 16, and the read operation is similar to the read operation of the memory cell 210 with a higher control gate voltage.

[0013] Table 4 describes the typical voltage ranges that can be applied to the terminals of the memory cell 410 and the substrate 12 to perform read, erase, and program operations: Table 4: Operation of the flash memory cell 410 in Figure 4 CG BL SL substrate Read 2-5V 0.6 – 2V 0V 0V erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V Programming 8-12V 3-5V 0V 0V

[0014] The methods and means described herein can be applied to other non-volatile memory technologies, such as FINFET discrete gate flash memory or stacked gate flash memory, NAND flash memory, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapping in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapping in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon nanotube) memory, OTP (two-stage or multi-stage one-time programmable) and CeRAM (correlated electronic RAM), but are not limited thereto.

[0015] Figure 5 depicts a block diagram of a prior art memory system 500. The memory system 500 includes an array 501, a column decoder 502, a high-voltage decoder 503, a row decoder 504, a bit line driver 505, an input circuit 506, an output circuit 507, control logic 508, and a bias generator 509. The memory system 500 further includes a high-voltage generation block 510, which includes a charge pump 511, a charge pump regulator 512, and a high-voltage level generator 513. The memory system 500 further includes a (programming / erasing, or weighting) algorithm controller 514, analog circuitry 515, a control engine 516 (which may include, but is not limited to, specific functions such as arithmetic functions, activation functions, embedded microcontroller logic), test control logic 517, and SRAM blocks 518 for storing intermediate data such as data for input circuits (e.g., activation data) or output circuits (neuron output data) or data for programming (e.g., data for a single column or multiple columns).

[0016] Array 501 includes a series and rows of non-volatile memory cells, for example, memory cells 110, 210, 310 or 410 from Figures 1 to 4 respectively.

[0017] Input circuitry 506 may include circuitry such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time-modulated pulse converter), an AAC (analog-to-analog converter, e.g., current-to-voltage converter, logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 506 may implement one or more of normalization, linear or nonlinear scaling functions, and arithmetic functions. Input circuitry 506 may implement a temperature compensation function for the input level. Input circuitry 506 may implement excitation functions such as ReLU or sigmoid. Input circuitry 506 may store digital excitation data to be used as an input signal or in combination with an input signal during programming or read-out operations. The digital excitation data may be stored in a register. Input circuitry 506 may include circuitry for driving array terminals such as CG, WL, EG, and SL lines, which may include sample-and-hold circuitry and buffers. The DAC may be used to convert the digital excitation data into an analog input voltage for application to the array.

[0018] Output circuit 507 may include circuitry such as ITV (current-to-voltage circuit), ADC (analog-to-digital converter to convert analog neuron output into digital bits), AAC (analog-to-analog converter, e.g., current-to-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time modulation pulse converter), or any other type of converter. Output circuit 507 may convert array output into excitation data. Output circuit 507 may implement excitation functions such as rectified linear excitation function (ReLU) or sigmoid. Output circuit 507 may implement one or more of statistical normalization, regularization, scaling / gain functions, statistical trimming, and arithmetic functions (e.g., addition, subtraction, division, multiplication, shifting, logarithmic) on neuron output. Output circuit 507 may implement a temperature compensation function on neuron output or array output (e.g., bitline output) to keep array power consumption approximately constant or improve the accuracy of array (neuron) output, for example, by keeping the IV slope approximately the same across the entire temperature range. The output circuit 507 may include a temporary register for storing output data.

[0019] The charge pump 511 must generate the high voltage required for erasure and programming operations from a power supply voltage that is typically between 1.5 and 3.0V, such as those shown in Tables 1 to 4 above.

[0020] Figure 6 depicts a prior art charge pump 600. The prior art charge pump 600 includes i+1 stages, which are stages 601-0 (stage 0), 601-1 (stage 1), ... 601-(i-1) (front output stage) and 601-i (output stage). The prior art charge pump 600 also includes dual channels, specifically channels 601 and 651. Each stage raises its received input voltage and outputs the raised voltage to the next stage as the input voltage of the next stage, or, in the case of stage 601-i, as the output Vout of the charge pump 600. Channels 601 and 651 operate out of phase with each other, such that the output Vout is always at the maximum raised voltage.

[0021] Figure 7 depicts an example of a timing diagram for clock signals CK1, CK2, CK3, and CK4 used in the charge pump 600. Clock signals CK1, CK2, CK3, and CK4 are generated from a common clock signal denoted by CLK. Clock signals CK2 and CK3 are complementary to each other, and clock signals CK1 and CK4 are complementary to each other. Therefore, CK2 and CK3 are complementary clock signals, and CK1 and CK4 are complementary clock signals. The respective edges of clock signals CK2 and CK3 have a delay of Tdelay1 relative to their respective first edges of the common clock signal CLK. The respective edges of clock signals CK1 and CK4 have a delay of Tdelay2 relative to their respective second edges of the common clock signal CLK.

[0022] Figure 8 depicts two instances of stages in one of the channels of the charge pump 600, shown here as stage N and stage N+1. Each stage in each channel of the charge pump 600 performs a boost operation in the same manner, with reference to stage N+1 for illustration. Node C is the input voltage received by stage N+1. CK3 and CK4 are clock signals as shown in Figure 7, and are coupled to capacitors 804 and 805, respectively. When CK3 becomes high, the voltage on the upper plate of capacitor 804 (i.e., node C) increases by the amount of CK3. As shown in Figure 7, there is a delay period Tdelay2 between the rising edge of CK3 and the rising edge of CK4, and this delay utilizes the higher potential on node C to precharge node B via MB_T2 by the amount VOUT minus VTH of MB_T2. When CK4 becomes high, the voltage on the upper plate of capacitor 805 (i.e., node B) increases by the amount of CK4. As a result, due to the pre-charge period and the boost from CK4, the potential at node B now becomes extremely high. This higher potential at node B facilitates the transfer of charge from node C to VOUT via transistor 804. Transistor 806 can be enabled to set VOUT to an initial voltage of VDD, or transistor 806 can remain enabled throughout the operation of charge pump 600 to provide a lower limit on the value of VOUT (VOUT will always be equal to or greater than VDD).

[0023] One drawback of the prior art charge pump 600 is that the body effect increases the critical voltage VTH of transistors 801 (MB_T1), 802 (MS_T1), 803 (MB_T2), and 804 (MS_T2). Given the configuration of the charge pump 600, the voltage supplied to the gates of those transistors may not be large enough to exceed the increased VTH and fully turn on those transistors. This problem becomes more pronounced with each subsequent stage.

[0024] An improved charge pump is needed. [Summary of the Invention]

[0025] An improved charge pump is disclosed. The charge pump uses a dual-channel topology. Cross feedback is provided between the channels, such that a high voltage generated in a stage (N+1) of one channel is applied to the gate of the transistor of the previous stage (N) of the other channel.

Implementation Method

[0037] Figure 9 depicts a charge pump 900. The charge pump 900 includes i+1 stages, namely stages 901-0 (stage 0), 901-1 (stage 1), ..., 901-(i-1) (pre-output stage) and 901-i (output stage). The charge pump 900 also includes dual channels, specifically channels 901 and 951. Each stage within a channel can be called a boost stage. Each boost stage increases its received input voltage and outputs the increased voltage to the next stage as the input voltage of the next stage, or, in the case of stage 901-i, as the output Vout of the charge pump 900. Channels 901 and 951 operate out of phase with each other, such that the output Vout is always at the maximum increased voltage. Figure 10 depicts an example of a timing diagram for CK1, CK2, CK3, and CK4 used in the charge pump 900. The clock signals CK1, CK2, CK3, and CK4 are generated by a common clock signal denoted by CLK. Clock signals CK1 and CK2 are complementary to each other, and clock signals CK3 and CK4 are also complementary to each other. The first edge systems of each clock signal CK1 and CK2 have a delay amount Tdelay1 relative to the first edge of the common clock signal CLK, and the second edge systems of each clock signal CK1 and CK2 are aligned with the second edge of the common clock signal CLK. The first edge systems of each clock signal CK3 and CK4 are aligned with the first edge of the common clock signal CLK, and the second edge systems of each clock signal CK3 and CK4 have a delay amount Tdelay2 relative to the second edge of the common clock signal CLK. Compared to the prior art charge pump 600, the charge pump 900 improves the substrate effect, which will be discussed in more detail with reference to FIG11.

[0038] Figure 11 depicts three example stages of channels 901 and 951 in the charge pump 900, namely stages N, N+1, and N+2 (where N ranges from 0 to (i-1), corresponding to stages 901-0, ..., 901-i in Figure 9). Each boost stage in each channel of the charge pump 900 performs boost operation in the same manner, and the boost stage corresponding to stage N in channel 901 will be described with reference to this example. Node D is the input voltage received by stage N+1 in channel 901. CK2 and CK3 are clock signals as shown in Figure 10, and are coupled to capacitors 1105 and 1106, respectively. When CK2 becomes high, the voltage on the upper plate of capacitor 1105 (i.e., node D) increases by the amount of CK2. As shown in Figure 10, there is a delay period Tdelay2 between the rising edge of CK2 and the rising edge of CK3. This delay utilizes the higher potential at node D to precharge node A via MB_T2 by an amount equal to OUT2 minus VTH of MB_T2. Afterward, CK3 becomes high, increasing the voltage on the upper plate of capacitor 1106 (i.e., node A) by the amount of voltage increase from CK3. Therefore, the potential at node A is now equal to the voltage increase from CK3 plus the voltage generated by the precharge time, and due to the increased voltage at node A, charge can now pass more efficiently from node D to node E.

[0039] Referring back to Figure 8, transistor 806 can be enabled to set VOUT to the initial voltage of VDD, or transistor 806 can remain enabled throughout the operation of charge pump 600 to provide a lower limit on the value of VOUT (VOUT will always be equal to or greater than VDD).

[0040] Stage N+2 or charge pump 900 in channel 901 includes native NMOS transistors 1103 (first native NMOS transistor) and 1104 (second native NMOS transistor), which have a lower threshold voltage than the NMOS transistor 806 used in prior art charge pump 600. Using native NMOS transistors 1103 and 1104 instead of NMOS transistors allows a higher initial voltage to be applied to similar nodes in OUT1 and other stages, allowing charge pump 900 to reach its target more quickly. Furthermore, signal VGI provides a gating signal to native NMOS transistor 1103 and can be turned off immediately after charge pump 900 is started, reducing the chance of significant leakage current due to the low threshold voltage of native NMOS transistor 1103. Native NMOS transistor 1104 is provided to reduce stress on native NMOS transistor 1103 because when charge pump 900 is activated, the voltage difference between the source and gate of native NMOS transistor 1103 will be relatively large (HV-0V), where HV is the high voltage generated by charge pump.

[0041] Native NMOS transistors 1153 (third native NMOS transistor) and 1154 (fourth native NMOS transistor) play the same role in stage N+1 of channel 951 as native NMOS transistors 1103 and 1104 in stage N+1 of channel 901. As shown in Figures 9 and 11, other pump stages of charge pump 900 include native NMOS transistors playing the same role.

[0042] In order to overcome the substrate effect on the boost transistors 1101 (MB_T2) (which is the first boost transistor) and 1151 (MB_B2) (which is the second boost transistor), the charge pump 900 applies a higher voltage to the gate of those transistors than that of the prior art charge pump 600. Specifically, the charge pump 900 uses the output voltage from channel 951 (node ​​OUT2) of stage N+2 as the gate voltage of transistor 1101 (MB_T2) in stage N+1 of channel 901, and uses the output voltage from channel 901 (node ​​OUT1) of stage N+2 as the gate voltage of transistor 1151 (MB_B2) in stage N+1 of channel 951. Due to the boost provided by subsequent stages, the gate voltages of transistors 1101 (MB_T2) and 1151 (MB_B2) are higher than those in the prior art charge pump 600. Furthermore, nodes A and B can be pre-charged to higher levels than in the prior art charge pump 600. This means that the gate voltages of transistors 1102 (MS_T2) and 1152 (MS_B2), after being boosted by CK3 and CK1 respectively, are higher than those in the prior art charge pump 600, enabling them to cope with the increased VTH due to substrate effects. As a result, the boost in charge pump 900 is more efficient than in the prior art charge pump 600. Charge pump 900 can provide a higher output voltage than charge pump 600 while achieving higher efficiency and lower processing temperature variations.

[0043] The boost stage of the charge pump 900 can be operated to perform a method comprising: increasing a first voltage (voltage at node D) by means of a first stage (stage N+1) in a first charge channel (channel 901) to generate a second voltage (voltage at node E); increasing the second voltage by means of a second stage (stage N+2) in the first charge channel (channel 901) to generate a third voltage (voltage OUT1); increasing a fourth voltage (voltage at node C) by means of a first stage (stage N+1) in a second charge channel (channel 951) to generate a fifth voltage (voltage at node F); increasing the voltage by means of a second charge channel (channel 951) to generate a third voltage (voltage OUT1); increasing the voltage by means of a second stage (stage N+1) in a second charge channel (channel 951) to generate a fourth voltage (voltage at node C); increasing the voltage by means of a second stage (stage N+1) in a second charge channel (channel 951) to generate a fifth voltage (voltage at node F); increasing the voltage by means of a second stage (stage N+1) in a second charge channel (channel 951) to generate a third voltage (voltage OUT1 ... The second stage (stage N+2) in channel 951 raises a fifth voltage to generate a sixth voltage (voltage OUT2); a third voltage is applied to the first stage of the second charge channel; and a sixth voltage is applied to the first stage of the first charge channel, wherein the step of applying the sixth voltage to the first stage of the first charge channel includes applying the sixth voltage to the gate of the first boost transistor (1101) in the first stage of the first charge channel, and the step of applying the third voltage to the first stage of the second charge channel includes applying the third voltage to the gate of the second boost transistor (1151) in the first stage of the second charge channel. This method may further include: applying a first clock signal (CK3) to the first stage of the first charge channel and the second stage of the second charge channel; applying a second clock signal (CK4) to the first stage of the first charge channel and the second stage of the second charge channel; applying a third clock signal (CK1) to the first stage of the second charge channel and the second stage of the first charge channel; and applying a fourth clock signal (CK2) to the first stage of the second charge channel and the second stage of the first charge channel.

[0044] It should be noted that, as used herein, the terms "above" and "on" inclusively include "directly on" (without intermediate material, components, or spaces disposed therein) and "indirectly on" (with intermediate material, components, or spaces disposed therein). Similarly, the terms "adjacent" include "directly adjacent" (without intermediate material, components, or spaces disposed therein) and "indirectly adjacent" (with intermediate material, components, or spaces disposed therein), "mounted to" includes "directly mounted to" (without intermediate material, components, or spaces disposed therein) and "indirectly mounted to" (with intermediate material, components, or spaces disposed therein), and "electrically coupled to" includes "directly electrically coupled to" (without intermediate material or components electrically connecting the components together therein) and "indirectly electrically coupled to" (with intermediate material or components electrically connecting the components together therein). For example, forming an element "above a substrate" can include: forming the element directly on the substrate without any intermediate material / element therein, and forming the element indirectly on the substrate with one or more intermediate materials / element therein. [Simplified Explanation of the Diagram]

[0026] Figure 1 depicts a prior art discrete gate flash memory cell.

[0027] Figure 2 depicts another prior art discrete gate flash memory cell.

[0028] Figure 3 depicts another prior art discrete gate flash memory cell.

[0029] Figure 4 depicts another prior art discrete gate flash memory cell.

[0030] Figure 5 depicts a prior art memory system.

[0031] Figure 6 depicts a prior art charge pump.

[0032] Figure 7 depicts the timing diagram of the prior art charge pump of Figure 6.

[0033] Figure 8 depicts a simplified diagram of the prior art charge pump of Figure 6.

[0034] Figure 9 depicts a charge pump.

[0035] Figure 10 depicts the timing diagram of the charge pump in Figure 9.

[0036] Figure 11 depicts a simplified diagram of the charge pump in Figure 9.

Claims

1. A method for operating a dual-channel charge pump system, comprising: A first voltage is increased by a first stage in a first charge channel to generate a second voltage, wherein the first stage in the first charge channel includes a first boost transistor and a first channel transistor; a second voltage is increased by a second stage in the first charge channel to generate a third voltage; a fourth voltage is increased by a first stage in a second charge channel to generate a fifth voltage, wherein the first stage in the second charge channel includes a second boost transistor and a second channel transistor; a sixth voltage is generated by increasing the fifth voltage by a second stage in the second charge channel. The third voltage is applied to the first stage of the second charge channel; and the sixth voltage is applied to the first stage of the first charge channel.

2. As in request item 1, where, The second boost transistor is an NMOS transistor.

3. As in request item 2, wherein, The first boost transistor is an NMOS transistor.

4. As in request item 3, including: A first clock signal is applied to the first stage of the first charge channel and the second stage of the second charge channel; And apply a second clock signal to the first stage of the first charge channel and the second stage of the second charge channel.

5. The method as described in request item 4, including: A third clock signal is applied to the first stage of the second charge channel and the second stage of the first charge channel; And apply a fourth clock signal to the first stage of the second charge channel and the second stage of the first charge channel.

6. As in request item 5, wherein, The first clock signal and the second clock signal are complementary clock signals.

7. As in request item 6, wherein, The third clock signal and the fourth clock signal are complementary clock signals.

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