Method of forming stacked device structure

Abstract

This disclosure provides a method for integrating a high-dielectric-constant dielectric material into a stacked multi-gate device structure to improve thermal conductivity. A method for fabricating a stacked device structure according to this disclosure includes forming a first multi-gate device structure; depositing a high-dielectric-constant dielectric layer on a substrate; bonding the high-dielectric-constant dielectric layer onto the first multi-gate device structure; removing the substrate after bonding the high-dielectric-constant dielectric layer; patterning the high-dielectric-constant dielectric layer to form contact openings; forming contact features in the contact openings; bonding an epitaxial stack on the high-dielectric-constant dielectric layer and the contact features; and performing further processes to form a second multi-gate device structure from the epitaxial stack. The epitaxial stack includes a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than its predecessor. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) has typically increased while shape geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) has decreased. This scaling down process typically benefits by increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of handling and manufacturing ICs.

[0003] As the semiconductor industry further advances towards advanced technology process nodes that pursue higher device density, higher efficiency, and lower costs, challenges from both manufacturing and design issues have led to stacked device configurations, such as complementary field-effect transistors (CFETs), where multiple gate transistors are stacked perpendicularly to each other. When discussing stacked device configurations, heat dissipation is an important consideration. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] This disclosure is best understood by reading the accompanying figures in conjunction with the following detailed description. It should be emphasized that, in accordance with standard industry practice, the features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 illustrates a flowchart of a method for forming a stacked device structure with a high dielectric constant (kappa) dielectric layer according to one or more states disclosed herein. Figures 2 through 11 illustrate partial cross-sectional views of precursor structures for various manufacturing processes according to the method described in Figure 1, involving one or more specimens. Figures 12 through 22 illustrate various stacking device structures formed using the method in Figure 1. Figure 23 illustrates a flowchart of a method for forming a stacked device structure having two high-dielectric-constant dielectric layers joined together, according to one or more patterns disclosed herein. Figures 24 through 43 illustrate partial cross-sectional views of precursor structures in various manufacturing processes according to the method described in Figure 23, for one or more specimens of the present invention. Figures 44 to 54 illustrate various stacking device structures formed using the method in Figure 23. Figure 55 illustrates a flowchart of a method for forming a stacked device structure having at least one high dielectric constant dielectric layer formed using selective deposition, according to one or more patterns disclosed herein. Figures 56 through 74 illustrate partial cross-sectional views of precursor structures in various manufacturing processes according to the method described in Figure 55, for one or more specimens of the present invention. Figure 75 illustrates a flowchart of a method for forming a stacked device structure having at least one high dielectric constant dielectric layer according to one or more patterns disclosed herein, the high dielectric constant dielectric layer having contact features having rounded top corners. Figures 76 to 87 illustrate partial cross-sectional views of precursor structures in various manufacturing processes according to the method described in Figure 75, for one or more states of the present invention. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] For simplicity, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship of one element or feature to another, as illustrated in the figures. In addition to the orientations depicted in the figures, these spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0008] Furthermore, as those skilled in the art will understand, when figures or ranges of figures are described using terms such as "about," "approximately," and the like, the term is intended to encompass figures within a reasonable range of variations that are inherent to the manufacturing process. For example, this figure or range of figures encompasses a reasonable range including, for instance, within + / - 10% of the described figure, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with that figure. For example, a material layer with a thickness of "about 5 nm" can encompass dimensions ranging from 4.25 nm to 5.75 nm, where those skilled in the art will know that the manufacturing tolerance associated with depositing this material layer is + / - 15%.

[0009] Stacked multi-gate devices represent semiconductor devices comprising a bottom multi-gate device and a top multi-gate device stacked on top of the bottom multi-gate device. When the bottom and top multi-gate devices have different conductivity types, the stacked multi-gate device can be a complementary field-effect transistor (CFET). The multi-gate device in a CFET can be a FinFET or a GAA transistor. Due to the limited routing area, routing for a CFET is achieved through both front-side and back-side interconnect structures. The process used to form the back-side interconnect structure typically involves removing the semiconductor substrate, which acts as a heat sink. Compared to multi-gate devices, stacked multi-gate devices tend to generate more heat. This additional heat, coupled with the lack of a heat sink, poses a challenge for heat dissipation in multi-gate devices.

[0010] This disclosure provides methods for introducing one or more high-dielectric-constant dielectric layers into a CFET structure to act as a heat sink. In one example process, a high-dielectric-constant dielectric layer is formed on a first multi-gate device structure. Contact features are formed in the high-dielectric-constant dielectric layer. A superlattice structure comprising alternating stacks of a first semiconductor layer and a second semiconductor layer is bonded to the high-dielectric-constant dielectric layer. The superlattice structure is then patterned to form a fin-shaped structure for further processing to form a second multi-gate device structure. In another example process, a first high-dielectric-constant dielectric layer is formed on the first multi-gate device structure. Contact features are formed in the first high-dielectric-constant dielectric layer. A second high-dielectric-constant dielectric layer is formed on the second multi-gate device structure. The first and second multi-gate device structures are then bonded together by means of the first and second high-dielectric-constant dielectric layers. This disclosure also provides methods for patterning high-dielectric-constant dielectric layers or for depositing high-dielectric-constant dielectric layers by selective deposition on nucleation layers.

[0011] Various embodiments of the present disclosure will now be described in more detail with reference to the figures. In this regard, Figures 1, 17, 50, and 69 are flowcharts illustrating methods 100, 300, 400, and 500 for forming a semiconductor device according to various embodiments of the present disclosure. Methods 100, 300, 400, and 500 are merely examples and are not intended to limit the present disclosure to the content explicitly illustrated in methods 100, 300, 400, or 500. Additional steps may be provided before, during, and after methods 100, 300, 400, or 500, and some steps described may be replaced, eliminated, or moved in various places for additional embodiments of the methods. For simplicity, not all steps are described in detail herein. Method 100 is described below with reference to Figures 2 through 11, which are partial cross-sectional views of a precursor structure 200 at different manufacturing stages according to embodiments of method 100. Method 300 is described below with reference to Figures 18 through 37, which are partial cross-sectional views of precursor structures 200 at different manufacturing stages according to embodiments of method 300. Method 400 is described below with reference to Figures 51 through 68, which are partial cross-sectional views of precursor structures 200 at different manufacturing stages according to embodiments of method 400. Method 500 is described below with reference to Figures 70 through 77, which are partial cross-sectional views of precursor structures 200 at different manufacturing stages according to embodiments of method 500. Because the precursor structure 200 will be manufactured into a semiconductor device after the manufacturing process is completed, the precursor structure 200 may be referred to as a semiconductor device when the context requires. Furthermore, throughout this application and across different embodiments, unless otherwise specified, the same element symbols denote the same features having similar structures and compositions. Source / drain regions may individually or uniformly represent the source or drain, depending on the context.

[0012] In method 100 of Figure 1, a high-dielectric-constant dielectric layer is formed on the first multi-gate device structure, contact features are formed in the high-dielectric-constant dielectric layer, a superlattice structure is bonded to the high-dielectric-constant dielectric layer, and then a second multi-gate device structure is formed from the superlattice structure. Because the second multi-gate device structure is formed after the formation of the first multi-gate device structure, method 100 can also be called a sequential formation scheme.

[0013] Referring to Figures 1 and 2, method 100 includes block 102, where a first multi-gate device structure 10 is formed. The first multi-gate device structure 10 includes an active region on substrate 202. The active region includes nanostructures 2080 disposed on a patterned substrate portion from substrate 202. The active region can be divided into a channel region 210C and a source / drain region 210SD. A gate structure 230 surrounds each of the nanostructures 2080 on the channel region 210C. The nanostructures 2080 are stacked perpendicularly to each other and staggered by a plurality of internal spacer features 228. Gate spacers 236 are disposed along a sidewall of a portion of the gate structure 230 on the nanostructure 2080. The nanostructure 2080 extends between two bottom source / drain features 220. A contact etch stop layer (CESL) 222 is disposed on the bottom source / drain features 220. Source / drain contacts 226 extend through CESL 222 to interface with bottom source / drain features 220 via bottom siliconized feature 224. A self-aligned capping (SAC) layer 237 is disposed on gate structure 230. An interface dielectric layer 272 is disposed on source / drain contacts 226, CESL 222, SAC layer 237, and gate spacer 236. An etch stop layer (ESL) 238 is disposed on interface dielectric layer 272. In some embodiments, source / drain contacts 226 may include cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), or ruthenium (Ru). Conductive features 274 are formed in interface dielectric layer 272 and ESL 238. In some embodiments, the conductive feature 274 has a smaller bottom surface for interface connection to the source / drain contact 226 and a larger top surface away from the source / drain contact 226. In these embodiments, the conductive feature 274 may improve alignment windows or reduce contact resistance. In some cases, the conductive feature 274 includes tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof.

[0014] To form the first multi-gate device structure 10, a superlattice structure is deposited on a substrate 202. The substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Examples of group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer such as a silicon oxide layer to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, the substrate 202 may include n-type well regions and p-type well regions for the fabrication of transistors of different conductivity types. When present, each of the n-type well and the p-type well is formed in the substrate 202 and includes a doped profile. The n-type well may include a doped profile of an n-type dopant, such as phosphorus (P) or arsenic (As). The p-type well may include a doped profile of a p-type dopant, such as boron (B). The doping in the n-type well and the p-type well may be formed by ion implantation or thermal diffusion and may be considered part of the substrate 202.

[0015] A superlattice structure may comprise a plurality of channel layers interleaved with a plurality of sacrificial layers. The channel layers and sacrificial layers may have different semiconductor compositions. In some embodiments, the channel layers are formed of silicon (Si), and the sacrificial layers are formed of silicon-germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers allows for selective removal or recessing of the sacrificial layers without materially damaging the channel layers. The sacrificial and channel layers are deposited alternately, one after another, to form the superlattice structure. The channel and sacrificial layers are deposited on top of each other using vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial deposition processes. The superlattice structure may also be referred to as an epitaxial stack.

[0016] After the superlattice structure is deposited on the substrate 202, fin-shaped structures are formed from the superlattice structure and a portion of the substrate 202 using photolithography and etching techniques. Following the formation of the fin-shaped structure, isolation features (not shown) are formed around the fin-shaped structure to separate it from adjacent fin-shaped structures. These isolation features may also be referred to as shallow trench isolation (STI) features. In one example process, dielectric material for the isolation features is deposited on the substrate 202 (including the fin-shaped structure) using CVD, subatmospheric CVD (SACVD), flowable CVD, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed to form the isolation features. After recessing, the fin-shaped structure rises above the isolation features. The dielectric material used for the isolation feature may include silicon oxide, silicon oxynitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectrics, combinations thereof, and / or other suitable materials. After the STI feature is formed, a dummy gate stack is formed over the channel region. The dummy gate stack includes a dummy gate dielectric layer and a dummy gate electrode. The dummy gate dielectric layer may include silicon oxide and the dummy gate electrode may include polysilicon (polysilicon). Gate spacer 236 is then deposited over the dummy gate structure. Gate spacer 236 may include silicon oxycarbonitride or silicon nitride. After the deposition of gate spacer 236, a dry etching process is performed to directionally etch the source / drain regions 210SD of the active region to form source / drain grooves, which may partially extend into the substrate fins formed from the substrate 202. The sacrificial layer exposed in the source / drain trench is then selectively and partially recessed to form internal spacer trenches between the channel layers. Internal spacer features 228 are then formed in the internal spacer trenches. In some embodiments, internal spacer features 228 may include silicon oxycarbonitride, silicon nitride, or silicon oxynitride. After the formation of internal spacer features 228, more than one epitaxial layer is epitaxially deposited over the source / drain trench to form a bottom source / drain feature 220. The more than one epitaxial layer may include a first epitaxial layer interfaced with the endwalls of the channel layers and a second epitaxial layer spaced apart from the channel layers by the first epitaxial layer. The bottom source / drain feature 220 may be n-type or p-type. When the bottom source / drain feature 220 is n-type, it may include silicon (Si) and n-type dopants, such as phosphorus (P) or arsenic (As). When the bottom source / drain feature 220 is p-type, it may include silicon germanium (SiGe) and a p-type dopant, such as boron (B). In the depicted embodiment, the bottom source / drain feature 220 includes silicon germanium (SiGe) and a p-type dopant.Following the formation of the bottom source / drain feature 220, a CESL 222 and an interlayer dielectric (ILD) layer system are deposited on the bottom source / drain feature 220 using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the CESL 222 may comprise silicon nitride or aluminum nitride, and the ILD layer may comprise silicon oxide.

[0017] After the formation of CESL 222 and ILD layers, a planarization process is performed to expose the dummy gate stack. Then, selective etching is used to remove the dummy gate stack to expose the channel layer and sacrificial layer in channel region 210C. After the removal of the dummy gate stack, the sidewalls of the channel layer and sacrificial layer in channel region 210C are exposed. Subsequently, the sacrificial layer in channel region 210C is selectively removed to release the channel layer as nanostructure 2080. The selective removal of the sacrificial layer can be performed by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., a mixture of ammonium hydroxide-hydrogen peroxide-water). In some other embodiments, selective removal includes SiGe oxidation followed by removal of silicon germanium oxide. For example, oxidation can be provided by ozone cleaning followed by removal of silicon germanium oxide using an etchant such as NH4OH. As nanostructure 2080 is released, gate structure 230 is deposited to encapsulate each of nanostructure 2080. Gate structure 230 includes an interface layer 231, a gate dielectric layer 232 over the interface layer 231, and a gate electrode 234 over the gate dielectric layer 232. In some embodiments, the interface layer 231 comprises silicon oxide and may be formed in a pre-cleaning process. Example pre-cleaning processes may include using a solution of ammonia, hydrogen peroxide, and water, and / or a solution of hydrochloric acid, hydrogen peroxide, and water. Gate dielectric layer 232 is then deposited over interface layer 231 using ALD, CVD, and / or other suitable methods. Gate dielectric layer 232 is formed of a high dielectric constant dielectric material. As used and described herein, a high dielectric constant dielectric material includes a dielectric material having, for example, a dielectric constant greater than that of thermally heated silicon oxide (about 3.9). In some embodiments, gate dielectric layer 232 may include hafnium oxide. Alternatively, the gate dielectric layer 232 may include other high dielectric constant dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), or combinations thereof. In some embodiments, the dielectric constant of the gate dielectric layer 232 is greater than the dielectric constant of the gate spacer 236, the internal spacer feature 228, or CESL 222.

[0018] After the gate dielectric layer 232 is deposited, a work function layer may be deposited on top of the gate dielectric layer 232. The work function layer may be n-type or p-type. By way of example, a p-type work function layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicon (ZrSi2), molybdenum silicon (MoSi2), tantalum silicon (TaSi2), nickel silicon (NiSi2), other p-type work function materials, or combinations thereof. The n-type work function layer may include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. The gate structure 230 may also include a metal filler to reduce contact resistance. In some cases, the metal filler includes tungsten (W). The work function layer and the metal filler may be collectively referred to as the gate electrode 234. In one embodiment, the gate structure 230 may include a p-type work function layer. Because both the n-type and p-type work function layers can include titanium-containing materials, the gate structure 230 can be considered to include titanium-based materials.

[0019] After the gate structure 230 is formed, the gate structure 230 is recessed to form a gate top groove. A SAC layer 237 is then deposited on the gate top groove. In some embodiments, the SAC layer 237 may comprise silicon nitride or silicon oxycarbonitride. Planarization is performed to form a flat top surface. An interface dielectric layer 272 is deposited on this flat top surface. The interface dielectric layer 272 may comprise silicon oxide or an oxide-containing dielectric material. An ESL 238 is then deposited on the interface dielectric layer 272. The ESL 238 may comprise aluminum nitride, aluminum oxide, silicon nitride, silicon oxycarbonitride, or a combination thereof.

[0020] Referring to Figures 1, 2, and 3, method 100 includes block 104, where a high-dielectric-constant dielectric layer 240 is formed on the first multi-gate device structure 10. In some embodiments, the high-dielectric-constant dielectric layer 240 is formed on the first multi-gate device structure 10 using a film transfer process. In an example process, the high-dielectric-constant dielectric layer 240 is first deposited on a uniform surface of a growth substrate 212. The growth substrate 212 may include silicon, silicon carbide, sapphire, or magnesium oxide. The high-dielectric-constant dielectric layer 240 is deposited on the growth substrate 212 using CVD, physical vapor deposition (PVD), or physical vapor transport (PVT). The high-dielectric-constant dielectric layer 240 has a thermal conductivity greater than that of any other dielectric feature in the first multi-gate device structure 10, including internal spacer feature 228, gate spacer 236, interface layer 231, gate dielectric layer 232, CESL 222, and SAC layer 237. In the depicted embodiment, the high-dielectric-constant dielectric layer 240 has a thermal conductivity between about 300 W / mK and about 2500 W / mK. In some embodiments, the high-dielectric-constant dielectric layer 240 may include diamond, boron nitride (BN), aluminum nitride (AlN), aluminum boron nitride (AlBN), or boron arsenide (BAs). When the high-dielectric-constant dielectric layer 240 includes diamond, it can be deposited on the growth substrate 212 using CVD. When the high-dielectric-constant dielectric layer 240 comprises cubic boron nitride (cBN), it can be deposited on the growth substrate 212 using PVD. When the high-dielectric-constant dielectric layer 240 comprises hexagonal boron nitride (hBN), it can be deposited on the growth substrate 212 using CVD or PVD. When the high-dielectric-constant dielectric layer 240 comprises aluminum boron nitride, it can be deposited on the growth substrate 212 using CVD or PVT. When the high-dielectric-constant dielectric layer 240 comprises boron arsenide, it can be deposited on the growth substrate 212 using CVD or PVD. In one embodiment, the high-dielectric-constant dielectric layer 240 may comprise diamond, boron nitride, or aluminum nitride, because the deposition of these materials requires temperatures below 500°C. In some embodiments, the high dielectric constant dielectric layer 240 has a thickness between 5 nm and about 100 nm.

[0021] As shown in Figure 3, after the high-dielectric-constant dielectric layer 240 is formed on the growth substrate 212, the high-dielectric-constant dielectric layer 240 is bonded to the first multi-gate device structure 10. To bond the high-dielectric-constant dielectric layer 240 and ESL 238, their exposed surfaces are first treated with nitrogen (N2) plasma, oxygen (O2) plasma, or argon (Ar) plasma to introduce surface hydroxyl groups, amino groups, or other dangling bonds. After treatment, the surfaces of the high-dielectric-constant dielectric layer 240 and ESL 238 can be cleaned with deionized (DI) water. In some alternative embodiments, the high-dielectric-constant dielectric layer 240 and ESL 238 may be cleaned, if necessary, before plasma treatment to remove organic and metallic contaminants. In one example process, a mixture of ammonium hydroxide and hydrogen peroxide (SC1) and / or a mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to clean the surfaces of the bonding surfaces. A mixture of ammonium hydroxide and hydrogen peroxide (SC1) removes organic contaminants. A mixture of hydrochloric acid and hydrogen peroxide (SC2) removes metallic contaminants. After plasma treatment, the high-dielectric-constant dielectric layer 240 is brought into direct contact with the ESL 238. Annealing is performed to facilitate covalent bonding between the high-dielectric-constant dielectric layer 240 and the ESL 238. The bonding process can be performed at a temperature between approximately 0°C and approximately 400°C. After the high-dielectric-constant dielectric layer 240 is bonded to the first multi-gate device structure 10, the growth substrate 212 can be selectively removed using a chemical mechanical polishing (CMP) process, a wet etching process, a dry etching process, or a debonding process.

[0022] Referring to Figures 1 and 4, method 100 includes block 106, where a high-k dielectric layer 240 is patterned to form contact openings 242. At block 106, photolithography and etching processes are used to pattern the high-k dielectric layer 240. In an example process, a hard mask layer is deposited over the high-k dielectric layer 240 and a photoresist layer is deposited over the hard mask layer. The photoresist layer is then patterned using photolithography. The patterned photoresist layer is then used as an etching mask to etch the hard mask layer and the high-k dielectric layer 240. The etching at block 106 may include dry etching, wet etching, or a combination thereof to form contact openings 242 in the high-k dielectric layer 240. For example, when the high-dielectric-constant dielectric layer 240 comprises diamond, dry etching may include the use of argon, oxygen, chlorine, or boron trichloride, and wet etching may include the use of molten potassium nitrate (KNO3). When the high-dielectric-constant dielectric layer 240 comprises hexagonal boron nitride, dry etching may include the use of argon, hydrogen, oxygen, or carbon tetrafluoride (CF4). When the high-dielectric-constant dielectric layer 240 comprises cubic boron nitride, dry etching may include the use of argon or methane, and wet etching may include the use of sodium hydroxide solution or sulfuric acid. When the high-dielectric-constant dielectric layer 240 comprises aluminum nitride, dry etching may include the use of chlorine, argon, trifluoromethane, sulfur hexafluoride, or boron trichloride, and wet etching may include the use of potassium hydroxide solution, phosphoric acid, tetramethylammonium hydroxide (TMAH), or hydrofluoric acid. When the high-dielectric-constant dielectric layer 240 comprises boron arsenide, wet etching may include the use of molten potassium hydroxide (KOH). During etching, the photoresist layer is selectively removed by ashing or selective etching. After the formation of contact opening 242, the hard mask layer is removed by etching. In the depicted embodiment, the top surface of contact feature 274 and ESL 238 are exposed in contact opening 242.

[0023] Referring to Figures 1 and 5, method 100 includes block 108, where contact feature 244 is formed into contact opening 242. At block 108, a metal filler layer is deposited over contact opening 242 using PVD or CVD. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After deposition of the metal filler layer, a planarization process such as CMP is performed to form contact feature 244 in a high-dielectric-constant dielectric layer 240. In the depicted embodiment, contact feature 244 is physically and electrically coupled to contact feature 274.

[0024] Referring to Figures 1, 6, and 7, method 100 includes block 110, where a superlattice structure 250 is bonded over contact feature 244 and a high-dielectric-constant dielectric layer 240. In some embodiments, the superlattice structure 250 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206. It should be noted that the superlattice structure 250 may be similar to the superlattice structure from which the first multi-gate device structure 10 is formed. In the depicted embodiment, the bottom layer of the superlattice structure 250 is the sacrificial layer 206, and the top layer of the superlattice structure 250 is a top channel layer 208T, which is thicker than the remainder of the channel layers 208 to withstand subsequent processes. In some embodiments, the channel layers 208 (including the top channel layer 208T) comprise silicon (Si), and the sacrificial layers 206 comprise silicon-germanium (SiGe). The superlattice structure 250 can be formed using vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable epitaxial deposition processes. To bond the superlattice structure 250 to the high-dielectric-constant dielectric layer 240 and contact features 244, its exposed surfaces are first treated with nitrogen (N2) plasma, oxygen (O2) plasma, or argon (Ar) plasma to introduce surface hydroxyl groups, amino groups, or other dangling bonds. After treatment, the bonding surfaces can be cleaned with deionized (DI) water. In some alternative embodiments, the superlattice structure 250, the high-dielectric-constant dielectric layer 240, and contact features 244 may be cleaned, as needed, before plasma treatment to remove organic and metallic contaminants. In one example process, a mixture of ammonium hydroxide and hydrogen peroxide (SC1) and / or a mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to clean the surfaces of the superlattice structure 250, the high-dielectric-constant dielectric layer 240, and the contact feature 244. The mixture of ammonium hydroxide and hydrogen peroxide (SC1) removes organic contaminants. The mixture of hydrochloric acid and hydrogen peroxide (SC2) removes metallic contaminants. After plasma treatment, the superlattice structure 250 is brought into direct contact with the high-dielectric-constant dielectric layer 240 and the contact feature 244. Annealing is performed to facilitate covalent bonding between the superlattice structure 250 and the high-dielectric-constant dielectric layer 240.

[0025] Referring to Figures 1 and 8, method 100 includes block 112, where a second multi-gate device structure 20 is formed from superlattice structure 250. At block 112, the process used to form the first multi-gate device structure 10 can be used to form the second multi-gate device structure 20. For simplicity, detailed processes for forming the second multi-gate device structure 20 are omitted. Like the first multi-gate device structure 10, the second multi-gate device structure 20 includes a nanostructure 2080. The nanostructure 2080 in the second multi-gate device structure 20 extends between two top source / drain features 260. The top source / drain features 260 can be n-type or p-type. When the top source / drain features 260 are n-type, they can include silicon (Si) and n-type dopants, such as phosphorus (P) or arsenic (As). When the top source / drain feature 260 is p-type, it may include silicon-germanium (SiGe) and a p-type dopant, such as boron (B). In the depicted embodiment, the top source / drain feature 260 includes silicon (Si) and an n-type dopant. The second multi-gate device structure 20 includes a top gate structure 230T that encloses each of the nanostructures 2080. The second multi-gate device structure 20 may include different contact features. In the depicted embodiment, a source / drain contact 226T is disposed on and interfaced with the top source / drain feature 260, and extends through the source / drain contact 226TC through another top source / drain feature 260 to contact the contact feature 244. In some embodiments, the source / drain contact 226T and the through source / drain contact 226TC may include cobalt (Co), nickel (Ni), tungsten (W), molybdenum (Mo), or ruthenium (Ru). The first multi-gate device structure 10, the second multi-gate device structure 20, the high dielectric constant dielectric layer 240, and the contact feature 244 shown in Figure 8 can be collectively referred to as the first stacked device structure 2002.

[0026] Figures 9 through 11 illustrate alternative embodiments when following the steps of method 100. In some embodiments presented in Figure 9, a dielectric layer 207 is formed on the surface of the superlattice structure 250 before the superlattice structure 250 is bonded to the first multi-gate device structure 10. The dielectric layer 207 is used to assist the bonding process and may also be referred to as the bonding dielectric layer 207. Depending on the high dielectric constant dielectric layer 240, the dielectric layer 207 may include silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, boron oxide, boron oxynitride, aluminum oxide, aluminum oxynitride, arsenic oxide, or arsenic oxynitride. To further improve the bonding strength with the high dielectric constant dielectric layer 240, the dielectric layer 207 may be further doped with germanium (Ge), boron (B), aluminum (Al), arsenic (As), or combinations thereof. Regarding dopants, dielectric layer 207 may include boron oxide, silicon boride, boron silicon oxide, boron silicon carbide, boron silicon oxycarbide, boron silicon nitride, boron silicon oxynitride, boron silicon oxycarbonitride, germanium silicon boride, germanium silicon oxide, germanium silicon carbide, germanium silicon oxycarbide, germanium silicon nitride, germanium silicon oxynitride, germanium silicon oxycarbonitride, aluminum oxide, aluminum silicon carbide, aluminum silicon nitride, aluminum silicon oxynitride, aluminum silicon oxycarbide, aluminum silicon carbonitride, aluminum silicon oxycarbonitride, aluminum boride, aluminum boron oxide, aluminum boron carbide, aluminum boron oxycarbide, aluminum boron nitride, aluminum boron nitride, aluminum boron oxide, aluminum boron car ... Boron oxynitrides, aluminum boron oxycarbonitrides, silicon aluminum borides, silicon aluminum boron oxides, silicon aluminum boron carbides, silicon aluminum boron oxycarbonides, silicon aluminum boron nitrides, silicon aluminum boron oxynitrides, silicon aluminum boron oxycarbonitrides, arsenic oxide, arsenic nitride, arsenic carbide, arsenic oxynitride, arsenic oxycarbonide, arsenic carbonitride, silicon arsenide, silicon arsenic oxides, silicon arsenic carbides, silicon arsenic oxynitrides, silicon arsenic oxycarbonides, silicon arsenic carbonitrides, silicon arsenic oxycarbonitrides, silicon boron arsenides, silicon boron arsenic oxides, silicon boron arsenic carbides, silicon boron arsenic oxynitrides, silicon boron arsenic oxycarbonides, silicon boron arsenic carbonitrides, silicon boron arsenic oxycarbonitrides. The dielectric layer 207 can be deposited on the superlattice structure 250 using thermal oxidation or CVD deposition. At block 110 of method 100, as illustrated in Figure 10, the superlattice structure 250 is bonded to the high-dielectric-constant dielectric layer 240 and contact feature 244 using a bonding process similar to that described above with respect to the operation at block 110, via the dielectric layer 207. The superlattice structure 250 then undergoes the operation at block 112 to form the second stacked device structure 2004 shown in Figure 11. Compared to the second multi-gate device structure 20 shown in Figure 9, the second multi-gate device structure 22 in Figure 11 further includes a bottom dielectric layer 270. In some cases, the bottom dielectric layer 270 may have a composition similar to that of the internal spacer feature 228. In both the first stacking device structure 2002 and the second stacking device structure 2004, the back side of the second multi-gate device structure 20 (or 22 in Figure 11) is joined to the front side of the first multi-gate device structure 10.This configuration can be called a face-to-back solution.

[0027] Figures 12 through 22 illustrate various example device structures that can be formed using method 100. Figure 12 illustrates a third stacked device structure 2006. The third stacked device structure 2006 is constructed according to a face-to-back configuration, since the back side of the second multi-gate device structure 22 is bonded to the front side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Two-layer contact features 245 are disposed in the high-dielectric-constant dielectric layer 240. The two-layer contact features 245 include a dielectric window for interface connection to the first multi-gate device structure 10 and a metal wiring for interface connection to the second multi-gate device structure 22. The first multi-gate device structure 10 includes a back-side contact feature 278, which interface with the bottom surface of the bottom source / drain feature 220. The third stacked device structure 2006 further includes a bottom pad 282, a first bottom ILD layer 280, and a second bottom ILD layer 276 disposed below the gate structure 230. The back contact feature 278 extends through the bottom liner 282, the first bottom ILD layer 280, and the second bottom ILD layer 276. In some embodiments, the bottom liner 282 comprises silicon nitride, and the first bottom ILD layer 280 and the second bottom ILD layer 276 comprise silicon oxide.

[0028] Figure 13 illustrates a fourth stacked device structure 2008. The fourth stacked device structure 2008 is constructed according to a face-to-back configuration, since the back side of the second multi-gate device structure 22 is bonded to the front side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Compared to the third stacked device structure 2006, the fourth stacked device structure 2008 further includes an interface dielectric layer 272 between the first multi-gate device structure 10 and the high-dielectric-constant dielectric layer 240. Conductive features 274 extend through the interface dielectric layer 272 to connect source / drain contacts 226 to two contact features 245. In some embodiments, the interface dielectric layer 272 comprises silicon oxide, and the conductive features 274 comprise tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof.

[0029] Figure 14 illustrates the fifth stacked device structure 2010. The fifth stacked device structure 2010 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 10 via a high-dielectric-constant dielectric layer 240. Compared to the fourth stacked device structure 2008, the high-dielectric-constant dielectric layer 240 in the fifth stacked device structure 2010 is bonded to a second bottom ILD layer 276 disposed above the back side of the first multi-gate device structure 10. Back-side contact features 278 extend through the bottom pad 282, the first bottom ILD layer 280, and the second bottom ILD layer 276 to interface the interface windows of the two contact features 245.

[0030] Figure 15 illustrates a sixth stacked device structure 2012. The sixth stacked device structure 2012 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 10 via a high-dielectric-constant dielectric layer 240. Compared to the fifth stacked device structure 2010, the high-dielectric-constant dielectric layer 240 in the sixth stacked device structure 2012 is bonded to a back-side interface dielectric layer 272B disposed above the back side of the first multi-gate device structure 10. A back-side conductive feature 274B extends through the back-side interface dielectric layer 272B to connect a back-side contact feature 278 to a contact feature 244. In some embodiments, the back-side interface dielectric layer 272B comprises silicon oxide, and the conductive feature 274 comprises tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof.

[0031] Figure 16 illustrates the seventh stacked device structure 2014. The seventh stacked device structure 2014 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 12 via a high-dielectric-constant dielectric layer 240. Compared to the fifth stacked device structure 2010, the first multi-gate device structure 12 in the seventh stacked device structure 2014 does not include the bottom pad 282, the first bottom ILD layer 280, and the second bottom ILD layer 276 shown in Figure 14. Instead, the first multi-gate device structure 12 in the seventh stacked device structure 2014 includes a bottom dielectric layer 284 that interfaces with the bottom surface of the bottom source / drain feature 220 and the gate structure 230. A bottom through-source / drain contact 226C extends through the bottom source / drain feature 220 and the bottom dielectric layer 284 to interface with the contact feature 244.

[0032] Figure 17 illustrates the eighth stacked device structure 2016. The eighth stacked device structure 2016 is constructed according to a face-to-back configuration, as the back side of the second multi-gate device structure 22 is bonded to the front side of the first multi-gate device structure 10 via a high-dielectric-constant dielectric layer 240. Compared to the fourth stacked device structure 2008, the eighth stacked device structure 2016 includes a single-layer contact feature 244 and an additional ESL 238 between the interface dielectric layer 272 and the high-dielectric-constant dielectric layer 240. The conductive feature 274 extends through both the interface dielectric layer 272 and the ESL 238 to connect the source / drain contacts 226 to the contact feature 244.

[0033] Figure 18 illustrates a ninth stacked device structure 2018. The ninth stacked device structure 2018 is constructed according to a face-to-back configuration, since the back side of the second multi-gate device structure 22 is bonded to the front side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Compared to the eighth stacked device structure 2016, the ninth stacked device structure 2018 further includes an additional bottom dielectric layer 271 between the bottom dielectric layer 270 and the high-dielectric-constant dielectric layer 240. The additional bottom dielectric layer 271 may have a composition similar to that of the bottom dielectric layer 270. In some embodiments, the additional bottom dielectric layer 271 is used to apply additional stress to resist wafer warpage or to provide better adhesion to the high-dielectric-constant dielectric layer 240.

[0034] Figure 19 illustrates a tenth stacked device structure 2020. The tenth stacked device structure 2020 is constructed according to a face-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the front side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Compared to the ninth stacked device structure 2018, the tenth stacked device structure 2020 includes a bottom high-dielectric-constant dielectric layer 239, instead of the additional bottom dielectric layer 271 in the ninth stacked device structure 2018 of Figure 18. The bottom high-dielectric-constant dielectric layer 239 may have a composition similar to that of the high-dielectric-constant dielectric layer 240. In some embodiments, the bottom high-dielectric-constant dielectric layer 239 helps to provide better adhesion and better heat dissipation between the bottom dielectric layer 270 and the high-dielectric-constant dielectric layer 240.

[0035] Figure 20 illustrates an eleventh stacked device structure 2022. The eleventh stacked device structure 2022 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 10 via a high-dielectric-constant dielectric layer 240. Compared to the sixth stacked device structure 2012, the eleventh stacked device structure 2022 further includes a back-side etch-stop layer (ESL) 238B between the back-side interface dielectric layer 272B and the high-dielectric-constant dielectric layer 240. A back-side conductive feature 274B extends through both the back-side interface dielectric layer 272B and the back-side ESL 238B to connect the back-side contact feature 278 to the contact feature 244. In some embodiments, the back-side ESL 238B and ESL 238 share similar compositions.

[0036] Figure 21 illustrates the twelfth stacked device structure 2024. The twelfth stacked device structure 2024 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Compared to the eleventh stacked device structure 2022, the twelfth stacked device structure 2024 further includes an additional bottom dielectric layer 271 between the bottom dielectric layer 270 and the high-dielectric-constant dielectric layer 240. This additional bottom dielectric layer 271 may have a composition similar to that of the bottom dielectric layer 270. In some embodiments, this additional bottom dielectric layer 271 is used to apply additional stress to resist wafer warpage or to provide better adhesion to the high-dielectric-constant dielectric layer 240.

[0037] Figure 22 illustrates a thirteenth stacked device structure 2026. The thirteenth stacked device structure 2026 is constructed in a back-to-back configuration because the back side of the second multi-gate device structure 22 is bonded to the back side of the first multi-gate device structure 10 by means of a high-dielectric-constant dielectric layer 240. Compared to the twelfth stacked device structure 2024, the thirteenth stacked device structure 2026 includes a bottom high-dielectric-constant dielectric layer 239, instead of the additional bottom dielectric layer 271 in the twelfth stacked device structure 2024 of Figure 21. This bottom high-dielectric-constant dielectric layer 239 may have a composition similar to that of the high-dielectric-constant dielectric layer 240. In some embodiments, the bottom high-dielectric-constant dielectric layer 239 helps to provide better adhesion and better heat dissipation between the bottom dielectric layer 270 and the high-dielectric-constant dielectric layer 240.

[0038] In method 300 of Figure 23, a first high-dielectric-constant dielectric layer is formed on the first multi-gate device structure, a second high-dielectric-constant dielectric layer is formed on the second multi-gate device structure, a first contact feature is formed in the first high-dielectric-constant dielectric layer and a second contact feature is formed in the second high-dielectric-constant dielectric layer, and the first high-dielectric-constant dielectric layer is bonded to the second high-dielectric-constant dielectric layer. Because the first multi-gate device structure and the second multi-gate device structure can be formed separately according to method 300, method 100 can also be called a parallel forming scheme.

[0039] Referring to Figures 23 and 24, method 300 includes block 302, where an alpha multi-gate device structure 10A is formed. The operation at block 302 is similar to that at block 102. Since the operation at block 102 has been described in detail above, a detailed description of the operation at block 302 is omitted for brevity. Instead of the first multi-gate device structure 10 formed at block 102, an alpha multi-gate device structure 10A is formed at block 302. As shown in Figure 18, the alpha multi-gate device structure 10A includes an interface dielectric layer 272. A first conductive feature 273 and a second conductive feature 275 extend through the interface dielectric layer 272 to contact a source / drain contact 226 and a gate contact dielectric window 229, respectively. In some embodiments, the interface dielectric layer 272 includes silicon oxide. The first conductive feature 273 and the second conductive feature 275 may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof.

[0040] Referring to Figures 23, 25, and 26, method 300 includes block 304, where a first high-dielectric-constant dielectric layer 240A is formed on the α-multi-gate device structure 10A. The formation of the first high-dielectric-constant dielectric layer 240A on the front side of the α-multi-gate device structure 10A is similar to the formation of the high-dielectric-constant dielectric layer 240 on the first multi-gate device structure 10A at block 104 in method 100. Since the operation at block 104 has been described in detail above, a detailed description of the formation of the first high-dielectric-constant dielectric layer 240A on the α-multi-gate device structure 10A is omitted. In the depicted embodiment, the first high-dielectric-constant dielectric layer 240A is first formed on the growth substrate 212, as shown in Figure 25. The first high-dielectric-constant dielectric layer 240A and the growth substrate 212 are then bonded to the α-multi-gate device structure 10A by means of an interface dielectric layer 272. After bonding, the growth substrate 212 is selectively removed, leaving a first high dielectric constant dielectric layer 240A on the α multi-gate device structure 10A, as shown in Figure 26.

[0041] Referring to Figures 23 and 27, method 300 includes block 306, where a first high-dielectric-constant dielectric layer 240A is patterned to form contact openings. The operation at block 306 may be similar to that at block 106 described above. For this reason, a detailed description of the operation at block 306 is omitted. At block 306, the first high-dielectric-constant dielectric layer 240A is patterned using photolithography and etching processes to form contact openings 243 and 241. In the depicted embodiment, contact opening 243 exposes a first conductive feature 273 and contact opening 241 exposes a second conductive feature 275.

[0042] Referring to Figures 23 and 28, method 300 includes block 308, where a first contact feature is formed in a first contact opening. The operation at block 308 may be similar to that at block 108 described above. For this reason, a detailed description of the operation at block 308 is omitted. At block 308, a metal filler layer is deposited over contact openings 243 and 241. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After the deposition of the metal filler layer, a planarization process, such as CMP, is performed to form a first contact feature 246 and a second contact feature 248 in a first high-dielectric-constant dielectric layer 240A.

[0043] Referring to Figures 23 and 29, method 300 includes block 310, where a β (beta) multi-gate device structure 10B is formed. At block 310, the operations at blocks 302, 304, and 306 are repeated before, simultaneously with, or after the formation of the β multi-gate device structure 10B. The β multi-gate device structure 10B may have a different conductivity type than the α multi-gate device structure 10A. In some embodiments, the α multi-gate device structure 10A includes an n-type GAA device, and the β multi-gate device structure 10B includes a p-type GAA device. In some alternative embodiments, the α multi-gate device structure 10A includes a p-type GAA device, and the β multi-gate device structure 10B includes an n-type GAA device.

[0044] Referring to Figures 23 and 29, method 300 includes block 312, where a second high-dielectric-constant dielectric layer 240B is formed on the β-multi-gate device structure 10B. The formation of the second high-dielectric-constant dielectric layer 240B on the β-multi-gate device structure 10B is similar to the formation of the high-dielectric-constant dielectric layer 240 on the first multi-gate device structure 10 at block 104 in method 100. Since the operation at block 104 has been described in detail above, a detailed description of the formation of the second high-dielectric-constant dielectric layer 240B on the β-multi-gate device structure 10B is omitted.

[0045] Referring to Figures 23 and 29, method 300 includes block 314, where the second high dielectric constant dielectric layer 240B is patterned to form contact openings. The operation at block 314 is similar to that at block 306. For brevity, a detailed description of the operation at block 314 is omitted.

[0046] Referring to Figures 23 and 29, method 300 includes block 316, where a second contact feature is formed in the first contact opening. The operation at block 316 is similar to that at block 308. For brevity, a detailed description of the operation at block 316 is omitted. As shown in Figure 29, a third contact feature 246T and a fourth contact feature 248T are disposed in a second high-dielectric-constant dielectric layer 240B.

[0047] Referring to Figures 23, 29, and 30, method 300 includes block 318, where a β-multi-gate device structure 10B is bonded to an α-multi-gate device structure 10A. At block 318, the β-multi-gate device structure 10B is bonded to the α-multi-gate device structure 10A by bonding a first high-dielectric-constant dielectric layer 240A to a second high-dielectric-constant dielectric layer 240B. To bond the first high-dielectric-constant dielectric layer 240A to the second high-dielectric-constant dielectric layer 240B, its exposed surfaces are first treated with nitrogen (N2) plasma, oxygen (O2) plasma, or argon (Ar) plasma to introduce surface hydroxyl groups, amino groups, or other dangling bonds. After treatment, the bonding surfaces can be cleaned with deionized (DI) water. In some alternative embodiments, prior to plasma treatment, the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B may be cleaned to remove organic and metallic contaminants. In one example process, a mixture of ammonium hydroxide and hydrogen peroxide (SC1) and / or a mixture of hydrochloric acid and hydrogen peroxide (SC2) may be used to clean the surfaces of the first high-dielectric-constant dielectric layer 240A, the second high-dielectric-constant dielectric layer 240B, and contact features. The mixture of ammonium hydroxide and hydrogen peroxide (SC1) removes organic contaminants. The mixture of hydrochloric acid and hydrogen peroxide (SC2) removes metallic contaminants. After plasma treatment, the second high-dielectric-constant dielectric layer 240B is aligned with and in direct contact with the first high-dielectric-constant dielectric layer 240A. Annealing is performed to facilitate covalent bonding between the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B. When the operation at block 318 is completed, the fourteenth stacked device structure 2028 is formed. The fourteenth stacked device structure 2028 is constructed according to a face-to-face scheme, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0048] Figures 31 through 36 illustrate alternative embodiments when following the steps of method 300. Figure 31 illustrates the formation of the α multi-gate device structure 10A, as similarly described at block 302. Figure 32 illustrates the formation of a first high-dielectric-constant dielectric layer 240A over the α multi-gate device structure 10A. Figure 33 illustrates the formation of contact openings 253 and 255 in the first high-dielectric-constant dielectric layer 240A. Figure 34 illustrates the formation of contact features 254 and 256 in the first high-dielectric-constant dielectric layer 240A. Figure 35 illustrates the alignment of the two device structures 10A and β multi-gate device structure 10B prior to their joining. Figure 36 illustrates the joining of the α multi-gate device structure 10A to the β multi-gate device structure 10B by means of the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B. As illustrated in Figure 36, a fifteenth stacked device structure 2030 is formed. The fifteenth stacked device structure 2030 differs from the fourteenth stacked device structure 2028 in that the fourteenth stacked device structure 2028 includes two layers of contact features, such as the first contact feature 246. The fifteenth stacked device structure 2030 is constructed according to a face-to-face configuration because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B.

[0049] Figures 37 through 42 illustrate another embodiment following the steps of method 300. Figure 37 illustrates the formation of the α multi-gate device structure 10A, as similarly described at block 302. Figure 38 illustrates the formation of a first high-dielectric-constant dielectric layer 240A over the α multi-gate device structure 10A without the intervention of the interface dielectric layer 272. Figure 39 illustrates the formation of contact openings 253 and 255 in the first high-dielectric-constant dielectric layer 240A. Figure 40 illustrates the formation of contact features 254 and 256 in the first high-dielectric-constant dielectric layer 240A. Figure 41 illustrates the alignment of the two device structures prior to the joining of the α multi-gate device structure 10A and the β multi-gate device structure 10B. Figure 42 illustrates an α-multi-gate device structure 10A bonded to a β-multi-gate device structure 10B via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. As shown in Figure 42, a sixteenth stacked device structure 2032 is formed. The sixteenth stacked device structure 2032 differs from the fifteenth stacked device structure 2030 in that it does not include an interface dielectric layer 272. The sixteenth stacked device structure 2032 is constructed according to a face-to-face configuration because the front side of the β-multi-gate device structure 10B is bonded to the front side of the α-multi-gate device structure 10A via the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B.

[0050] Figures 43 to 54 illustrate alternative structures that can be formed using method 300. Figure 43 illustrates the seventeenth stacked device structure 2034. The seventeenth stacked device structure 2034 is constructed according to a face-to-face scheme because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B.

[0051] Figure 44 illustrates the eighteenth stacked device structure 2036. The eighteenth stacked device structure 2036 is constructed according to a face-to-face configuration, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. Both the α multi-gate device structure 10A and the β multi-gate device structure 10B include back-side contact features. The α multi-gate device structure 10A further includes a bottom pad 282 disposed below the gate structure, a first bottom ILD layer 280 above the bottom pad 282, and a second bottom ILD layer 276 above the bottom pad 282 and the first bottom ILD layer 280. The back-side contact feature 278 extends through the bottom pad 282, the first bottom ILD layer 280, and the second bottom ILD layer 276. Similarly, the β multi-gate device structure 10B further includes a bottom liner 282T disposed below the gate structure, a first bottom ILD layer 280T above the bottom liner 282T, and a second bottom ILD layer 276T above the bottom liner 282T and the first bottom ILD layer 280T. A back-side contact feature 278T extends through the bottom liner 282T, the first bottom ILD layer 280T, and the second bottom ILD layer 276T.

[0052] Figure 45 illustrates the nineteenth stacked device structure 2038. The nineteenth stacked device structure 2038 is constructed according to a face-to-face scheme, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. Compared with the eighteenth stacked device structure 2036, the first high-dielectric-constant dielectric layer 240A is bonded to the α multi-gate device structure 10A by means of an interface dielectric layer 272, and the second high-dielectric-constant dielectric layer 240B is bonded to the β multi-gate device structure 10B by means of a top interface dielectric layer 272T.

[0053] Figure 46 illustrates the twentieth stacked device structure 2040. The twentieth stacked device structure 2040 is constructed according to a back-to-back scheme, because the back side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0054] Figure 47 illustrates the twenty-first stacked device structure 2042. The twenty-first stacked device structure 2042 is constructed according to a back-to-back configuration, because the back side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. Compared to the twentieth stacked device structure 2040, an interface dielectric layer 272 is disposed between the α multi-gate device structure 10A and the first high-dielectric-constant dielectric layer 240A, and a top interface dielectric layer 272T is disposed between the β multi-gate device structure 10B and the second high-dielectric-constant dielectric layer 240B.

[0055] Figure 48 illustrates the twenty-second stacked device structure 2044. The twenty-second stacked device structure 2044 is constructed according to a back-to-back scheme, because the back side of the β multi-gate device structure 10B is bonded to the back side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0056] Figure 49 illustrates the twenty-third stacked device structure 2046. The twenty-third stacked device structure 2046 is constructed according to a back-to-back configuration, because the back side of the β multi-gate device structure 10B is bonded to the back side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. Compared to the twenty-second stacked device structure 2044, an interface dielectric layer 272 is disposed between the α multi-gate device structure 10A and the first high-dielectric-constant dielectric layer 240A, and a top interface dielectric layer 272T is disposed between the β multi-gate device structure 10B and the second high-dielectric-constant dielectric layer 240B.

[0057] Figure 50 illustrates the twenty-fourth stacked device structure 2048. The twenty-fourth stacked device structure 2048 is constructed according to a face-to-face scheme, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0058] Figure 51 illustrates the twenty-fifth stacked device structure 2050. The twenty-fifth stacked device structure 2050 is constructed according to a back-to-back scheme, because the back side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0059] Figure 52 illustrates the twenty-sixth stacked device structure 2052. The twenty-sixth stacked device structure 2052 is constructed according to a face-to-face configuration, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. An interface dielectric layer 272 is disposed between the α multi-gate device structure 10A and the first high-dielectric-constant dielectric layer 240A, and a top interface dielectric layer 272T is disposed between the β multi-gate device structure 10B and the second high-dielectric-constant dielectric layer 240B.

[0060] Figure 53 illustrates the twenty-seventh stacked device structure 2054. The twenty-seventh stacked device structure 2054 is constructed according to a back-to-back configuration, because the back side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. An interface dielectric layer 272 is disposed between the α multi-gate device structure 10A and the first high-dielectric-constant dielectric layer 240A, and a top interface dielectric layer 272T is disposed between the β multi-gate device structure 10B and the second high-dielectric-constant dielectric layer 240B.

[0061] Figure 54 illustrates the twenty-eighth stacked device structure 2056. The twenty-eighth stacked device structure 2056 is constructed according to a back-to-back configuration, because the back side of the β multi-gate device structure 10B is bonded to the back side of the α multi-gate device structure 10A via a first high-dielectric-constant dielectric layer 240A and a second high-dielectric-constant dielectric layer 240B. An interface dielectric layer 272 is disposed between the α multi-gate device structure 10A and the first high-dielectric-constant dielectric layer 240A, and a top interface dielectric layer 272T is disposed between the β multi-gate device structure 10B and the second high-dielectric-constant dielectric layer 240B.

[0062] Unlike methods 100 and 300 above, method 400 uses a selective deposition process to form a high-k dielectric layer on the first multi-gate device structure. In some embodiments, this selective deposition process can be performed by using a patterning layer to pattern the high-k dielectric layer without etching it.

[0063] Referring to Figures 55 and 56, method 400 includes block 402, where an α-multi-gate device structure 10A is formed. The operation at block 402 is similar to that at block 102. Since the operation at block 102 has been described in detail above, a detailed description of the operation at block 402 is omitted for brevity. As shown in Figure 56, the α-multi-gate device structure 10A includes an interface dielectric layer 272 and is similar to the α-multi-gate device structure 10A shown in Figure 24.

[0064] Referring to Figures 55, 57, and 58, method 400 includes block 404, where a first high-dielectric-constant dielectric layer 240A is selectively deposited on the α-multi-gate device structure 10A. In the depicted embodiment, when method 400 is employed, the first high-dielectric-constant dielectric layer 240A comprises diamond. Unlike the operations at blocks 104 and 304, the first high-dielectric-constant dielectric layer 240A is deposited using selective growth rather than a film transfer process. In an example process, a seed layer 2400 is first selectively deposited on the top surface of the interface dielectric layer 272 by ALD, chemical vapor transport (CVT), spin coating, or immersion in a nanodiamond solution. The deposition of the seed layer 2400 can be performed at a temperature between 0°C and 300°C. The deposition of the seed layer 2400 may be referred to as nucleation or seeding, and the seed layer 2400 may also be referred to as nucleation layer 2400. In some alternative embodiments, the top surface of the interface dielectric layer 272 may be treated by plasma or wet processing to enhance the selectivity of deposition. Plasma processing may include the use of hydrogen, oxygen, nitrogen, argon, or mixtures thereof. Wet processing may use capping agents, hydrogen peroxide, sulfuric acid, hydrochloric acid, nitric acid, or combinations thereof. After seeding with respect to the seed layer 2400, CVD may be used to deposit a first high-dielectric-constant dielectric layer 240A, as illustrated in Figure 58. In some embodiments, the precursor for the CVD process may include an adamantane structure. The precursor may include one or more functional groups on the adamantane structure. Functional groups may include hydroxyl, carbonyl, carboxyl, amino, bromo, chloro, iodo, acetate, methyl, sulfonyl, isocyanate, nitrile, cyano, thiocyanate, thiol, acetylenyl, or combinations thereof. An example precursor skeleton formula is shown below:

[0065] When method 400 is used, elements in the functional groups of the precursor may be retained in the first high-dielectric-constant dielectric layer 240A, albeit in trace amounts. In other words, the first high-dielectric-constant dielectric layer 240A may include nitrogen, oxygen, sulfur, phosphorus, chlorine, bromine, iodine, or combinations thereof. As shown in Figure 58, due to the selective nature of the deposition, contact openings 253 and 255 are formed in the deposited first high-dielectric-constant dielectric layer 240A without any photolithography or etching steps.

[0066] Referring to Figures 55 and 59, method 400 includes block 406, where contact features are formed in a first high-dielectric-constant dielectric layer 240A. At block 406, a metal filler layer is deposited over contact openings 253 and 255 using PVD or CVD. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After the deposition of the metal filler layer, a planarization process, such as CMP, is performed to form contact features 254 and 256 in the first high-dielectric-constant dielectric layer 240A.

[0067] Referring to Figures 55 and 60, method 400 includes block 408, where a β multi-gate device structure 10B is formed. At block 408, the operations of blocks 402, 404, and 406 are repeated before, simultaneously with, or after the formation of the β multi-gate device structure 10B. The β multi-gate device structure 10B may have a different conductivity type than the α multi-gate device structure 10A. In some embodiments, the α multi-gate device structure 10A includes an n-type GAA device, and the β multi-gate device structure 10B includes a p-type GAA device. In some alternative embodiments, the α multi-gate device structure 10A includes a p-type GAA device, and the β multi-gate device structure 10B includes an n-type GAA device. The β multi-gate device structure 10B in Figure 60 is similar to the β multi-gate device structure 10B in Figure 35.

[0068] Referring to Figures 55 and 60, method 400 includes block 410, where a second high-dielectric-constant dielectric layer 240B is selectively deposited on the β-multi-gate device structure 10B. The formation of the second high-dielectric-constant dielectric layer 240B at block 410 can be similar to the formation of the first high-dielectric-constant dielectric layer 240A at block 406. For this reason, a detailed description of the operation at block 410 is omitted. Due to the selective nature of the deposition, contact openings are formed in the deposited second high-dielectric-constant dielectric layer 240B without any photolithography or etching steps.

[0069] Referring to Figures 55 and 60, method 400 includes block 412, where a second contact feature is formed in a second opening in the second high-dielectric-constant dielectric layer 240B. At block 412, a metal filler layer is deposited over the contact opening in the second high-dielectric-constant dielectric layer 240B using PVD or CVD. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After the deposition of the metal filler layer, a planarization process such as CMP is performed to form the contact feature in the second high-dielectric-constant dielectric layer 240B.

[0070] Referring to Figures 55, 60, and 61, method 400 includes block 414, where a β-multi-gate device structure 10B is bonded to an α-multi-gate device structure 10A. At block 414, the β-multi-gate device structure 10B is bonded to the α-multi-gate device structure 10A by bonding a first high-dielectric-constant dielectric layer 240A to a second high-dielectric-constant dielectric layer 240B. To bond the first high-dielectric-constant dielectric layer 240A to the second high-dielectric-constant dielectric layer 240B, its exposed surfaces are first treated with nitrogen (N2) plasma, oxygen (O2) plasma, or argon (Ar) plasma to introduce surface hydroxyl groups, amino groups, or other dangling bonds. After treatment, the bonding surfaces can be cleaned with deionized (DI) water. In some alternative embodiments, prior to plasma treatment, the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B may be cleaned to remove organic and metallic contaminants. In one example process, a mixture of ammonium hydroxide and hydrogen peroxide (SC1) and / or a mixture of hydrochloric acid and hydrogen peroxide (SC2) may be used to clean the surfaces of the first high-dielectric-constant dielectric layer 240A, the second high-dielectric-constant dielectric layer 240B, and the contact features. The mixture of ammonium hydroxide and hydrogen peroxide (SC1) removes organic contaminants. The mixture of hydrochloric acid and hydrogen peroxide (SC2) removes metallic contaminants. After plasma treatment, the second high-dielectric-constant dielectric layer 240B is aligned with and in direct contact with the first high-dielectric-constant dielectric layer 240A. The exposed surfaces of the contact features in the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B are also aligned. Annealing is performed to facilitate covalent bonding between the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B. At the end of the operation at block 414, the twenty-ninth stacked device structure 2058 is formed. The twenty-ninth stacked device structure 2058 shown in Figure 61 is constructed according to a face-to-face configuration because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B.

[0071] When the contact feature to be formed is not perfectly aligned with the conductive feature in the interface dielectric layer 272, a patterned film can be deposited to cover a portion of the interface dielectric layer 272 or the first high dielectric constant dielectric layer 240A (or the second high dielectric constant dielectric layer 240B). An example process for implementing the patterned film is illustrated in Figures 62 to 68 and Figures 69 to 74.

[0072] First, refer to Figures 62 through 68. Figure 62 illustrates an α-multi-gate device structure 10A including an interface dielectric layer 272. A first conductive feature 273 and a second conductive feature 275 are disposed in the interface dielectric layer 272. The α-multi-gate device structure 10A is formed at block 402 of method 400. Method 400 then proceeds to block 404, where a seed layer 2400 is selectively deposited on the exposed surface of the interface dielectric layer 272, as shown in Figure 63. In the first stage of selective deposition, a portion of a first high-dielectric-constant dielectric layer 240A is selectively deposited on the seed layer 2400, as shown in Figure 64. A first patterned film 30 is then deposited to cover the first conductive feature 273, the second conductive feature 275, and a portion of the first high-dielectric-constant dielectric layer 240A, as shown in Figure 65. The first patterned film 30 includes a photoresist or bottom antireflective coating (BAC) layer and acts as a deposition mask, as illustrated in Figure 66, during the second stage of selective deposition of the first high-dielectric-constant dielectric layer 240A. After the two stages of selective deposition, the first patterned film 30 is selectively removed using ashing or selective etching. After removal of the first patterned film 30, two contact openings 243 and 241 are formed in the first high-dielectric-constant dielectric layer 240A. Figure 68 illustrates the formation of the first contact feature 246 and the second contact feature 248 in the contact openings 243 and 241 shown in Figure 67. It should be understood that, although not explicitly shown in the figures, a similar operation can be performed on the β multi-gate device structure 10B, and the α multi-gate device structure 10A and the β multi-gate device structure 10B can be bonded together by means of the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B.

[0073] Referring then to Figures 69 through 74. Figure 69 illustrates an α-multi-gate device structure 10A including an interface dielectric layer 272. A first conductive feature 273 and a second conductive feature 275 are disposed in the interface dielectric layer 272. The α-multi-gate device structure 10A is formed at block 402 of method 400. Method 400 then proceeds to block 404. Before a seed layer 2400 is selectively deposited on the exposed surface of the interface dielectric layer 272, a second patterned film 32 is formed on the interface dielectric layer 272. As the second patterned film 32 covers a portion of the interface dielectric layer 272, the seed layer 2400 is selectively deposited on the exposed portion of the interface dielectric layer 272, as illustrated in Figure 71. As shown in Figure 72, selective growth of a first high-dielectric-constant dielectric layer 240A is performed. Following the selective deposition of the first high-dielectric-constant dielectric layer 240A, the second patterned film 32 is selectively removed using ashing or selective etching. After the removal of the second patterned film 32, elongated contact openings 249 and 241 are formed in the first high-dielectric-constant dielectric layer 240A, as shown in Figure 73. Figure 74 illustrates the formation of contact features 246 and 248 in contact openings 249 and 241. It should be understood that, although not explicitly shown in the figures, a similar operation can be performed on the β multi-gate device structure 10B, and the α multi-gate device structure 10A and the β multi-gate device structure 10B can be bonded together by means of the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B.

[0074] In method 500, a high-dielectric-constant dielectric layer is formed on the first multi-gate device structure, and the high-dielectric-constant dielectric layer includes contact openings. In method 500, the contact openings are widened and rounded to improve the process window.

[0075] Referring to Figures 75 and 76, method 500 includes block 502, where an α-multi-gate device structure 10A is formed. The operation at block 502 is similar to that at block 102. Since the operation at block 102 has been described in detail above, a detailed description of the operation at block 502 is omitted for brevity.

[0076] Referring to Figures 75 and 76, method 500 includes block 504, where a first high-dielectric-constant dielectric layer 240A is formed on the α-multi-gate device structure 10A. At block 504, the first high-dielectric-constant dielectric layer 240A may be deposited and patterned following operations similar to those at blocks 304 and 306 in method 300. In some alternative embodiments, the first high-dielectric-constant dielectric layer 240A may be formed on the α-multi-gate device structure 10A following selective deposition operations similar to those at block 404 in method 400. In the depicted embodiment, the first high-dielectric-constant dielectric layer 240A formed at block 504 may include contact openings 243 and 241.

[0077] Referring to Figures 75 and 77 through 79, method 500 includes block 506, where the corners of the contact openings are rounded. In some embodiments, the corner rounding operation can be performed by using a patterned film and directional etching. In the depicted embodiment, a third patterned film 40 is deposited over the first high-dielectric-constant dielectric layer 240, including over contact openings 243 and 241, as shown in Figure 77. In some embodiments, the third patterned film 40 may include a photoresist or a BARC layer. As shown in Figure 78, anisotropic etching 600 is performed using argon, hydrogen, oxygen, chlorine, boron trichloride, carbon tetrafluoride (CF4), methane, trifluoromethane, or sulfur hexafluoride. Anisotropic etching 600 is used to etch the first high-dielectric-constant dielectric layer 240A at a slower rate so that it primarily removes the shape edges at the corners of the openings. Therefore, anisotropic etching 600 removes a portion of the third patterned film 40 and forms a rounded corner 240R as shown in Figure 78. After the corner of the opening is rounded, the third patterned film 40 is removed by ashing or selective etching, leaving openings 2430 and 2450 at the rounded corner, as shown in Figure 79.

[0078] Referring to Figures 75 and 80, method 500 includes block 508, where contact features are formed in contact openings within a first high-dielectric-constant dielectric layer 240A. At block 508, a metal filler layer is deposited over the contact openings in the first high-dielectric-constant dielectric layer 240A using PVD or CVD. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After the deposition of the metal filler layer, a planarization process, such as CMP, is performed to form contact features 2460 and 2480 in the first high-dielectric-constant dielectric layer 240A. A rounded corner 240R allows for widening of the top surfaces of contact features 2460 and 2480. The widened contact features 2460 and 2480 widen the alignment process window and reduce contact resistance.

[0079] Referring to Figures 75 and 81, method 500 includes block 510, where a β multi-gate device structure 10B is formed. At block 408, the operations of blocks 402, 404, and 406 are repeated before, simultaneously with, or after the formation of the β multi-gate device structure 10B. The β multi-gate device structure 10B may have a different conductivity type than the α multi-gate device structure 10A. In some embodiments, the α multi-gate device structure 10A includes an n-type GAA device, and the β multi-gate device structure 10B includes a p-type GAA device. In some alternative embodiments, the α multi-gate device structure 10A includes a p-type GAA device, and the β multi-gate device structure 10B includes an n-type GAA device.

[0080] Referring to Figures 75 and 81, method 500 includes block 512, where a second high-dielectric-constant dielectric layer 240B is formed on the β-multi-gate device structure 10B. The formation of the second high-dielectric-constant dielectric layer 240B at block 512 may be similar to the formation of the first high-dielectric-constant dielectric layer 240A at block 504. For brevity, a detailed description of the operation at block 512 is omitted. The second high-dielectric-constant dielectric layer 240B includes contact openings.

[0081] Referring to Figures 75 and 81, method 500 includes block 514, where the corners of the contact openings in the second high-dielectric-constant dielectric layer 240B are rounded. At block 514, operations similar to those described above with respect to block 506 are performed on the second high-dielectric-constant dielectric layer 240B on the β-multi-gate device structure 10B. For brevity, a detailed description of the operations at block 514 is omitted.

[0082] Referring to Figures 75 and 81, method 500 includes block 516, where contact features are formed in contact openings in a second high-dielectric-constant dielectric layer 240B. At block 516, a metal filler layer is deposited over the contact openings in the second high-dielectric-constant dielectric layer 240B using PVD or CVD. In some embodiments, the metal filler layer may include tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), copper (Cu), or combinations thereof. After the deposition of the metal filler layer, a planarization process, such as CMP, is performed to form contact features in the second high-dielectric-constant dielectric layer 240B.

[0083] Referring to Figures 75 and 82, method 500 includes block 518, where a β multi-gate device structure 10B is bonded to an α multi-gate device structure 10A. At block 518, the β multi-gate device structure 10B is bonded to the α multi-gate device structure 10A by bonding a first high-dielectric-constant dielectric layer 240A to a second high-dielectric-constant dielectric layer 240B. To bond the first high-dielectric-constant dielectric layer 240A to the second high-dielectric-constant dielectric layer 240B, its exposed surfaces are first treated with nitrogen (N2) plasma, oxygen (O2) plasma, or argon (Ar) plasma to introduce surface hydroxyl groups, amino groups, or other dangling bonds. After treatment, the bonding surfaces can be cleaned with deionized (DI) water. In some alternative embodiments, the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B may be cleaned, if necessary, before plasma treatment to remove organic and metallic contaminants. In one example process, a mixture of ammonium hydroxide and hydrogen peroxide (SC1) and / or a mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to clean the surfaces of the first high-dielectric-constant dielectric layer 240A, the second high-dielectric-constant dielectric layer 240B, and the contact features. The mixture of ammonium hydroxide and hydrogen peroxide (SC1) removes organic contaminants. The mixture of hydrochloric acid and hydrogen peroxide (SC2) removes metallic contaminants. After plasma treatment, the second high-dielectric-constant dielectric layer 240B is aligned with and in direct contact with the first high-dielectric-constant dielectric layer 240A. The exposed surfaces of the contact features in the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B are also aligned. Annealing is performed to facilitate covalent bonding between the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B. At the end of the operation at block 518, the thirtieth stacked device structure 2060 is formed. The thirtieth stacked device structure 2060 shown in Figure 82 is constructed according to a face-to-face scheme, because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of a first high dielectric constant dielectric layer 240A and a second high dielectric constant dielectric layer 240B.

[0084] Figures 83 through 87 illustrate alternative embodiments when following the steps of method 500. Figure 83 illustrates an α-multi-gate device structure 10A formed at block 502 of method 500. The α-multi-gate device structure 10A in Figure 83 includes an interface dielectric layer 272. Conductive features 273 and 275 are disposed in the interface dielectric layer 272. A first high-dielectric-constant dielectric layer 240A in Figure 83 may be formed after the operation at block 504. In the depicted embodiment, the first high-dielectric-constant dielectric layer 240A in Figure 83 includes contact openings 253 and 255. Referring to Figure 84, the corners of contact openings 253 and 255 are rounded using the operation at block 506, thereby forming rounded corner openings 2530 and 2550. At block 508, metal filler is deposited in the openings 2530 and 2550 of the rounded corner to form contact features 2540 and 2560 in the first high-dielectric-constant dielectric layer 240A, as shown in Figure 85. Next, operations are performed at blocks 510 to 516 to form a second high-dielectric-constant dielectric layer 240B bonded to the β multi-gate device structure 10B. The first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B are then aligned as shown in Figure 86 and bonded together as shown in Figure 87 to form the 31st stacked device structure 2062. The 31st stacked device structure 2062 shown in Figure 87 is constructed according to a face-to-face configuration because the front side of the β multi-gate device structure 10B is bonded to the front side of the α multi-gate device structure 10A by means of the first high-dielectric-constant dielectric layer 240A and the second high-dielectric-constant dielectric layer 240B.

[0085] In one exemplary embodiment, this disclosure pertains to a method. This method includes forming a first multi-gate device structure; depositing a high-k dielectric layer on a substrate; bonding the high-k dielectric layer onto the first multi-gate device structure; removing the substrate after bonding the high-k dielectric layer; patterning the high-k dielectric layer to form contact openings; forming contact features in the contact openings; bonding an epitaxial stack on the high-k dielectric layer and the contact features; and performing further processes to form a second multi-gate device structure from the epitaxial stack. The epitaxial stack comprises a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers.

[0086] In some embodiments, the high-dielectric-constant dielectric layer comprises diamond, boron nitride, aluminum nitride, aluminum boron nitride, or boron arsenide. In some embodiments, the substrate comprises silicon, silicon carbide, sapphire, or magnesium oxide. In some cases, removal includes planarization processes, wet etching processes, dry etching processes, or debonding processes. In some embodiments, the deposition of the high-dielectric-constant dielectric layer includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or physical vapor transport (PVT) processes. In some embodiments, this method further includes depositing a dielectric layer on the first multi-gate device structure prior to this bonding. The dielectric layer comprises silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, boron oxide, boron oxynitride, aluminum oxide, aluminum oxynitride, arsenic oxide, or arsenic oxynitride. In some embodiments, the first multi-gate device structure includes a first source / drain feature, a second source / drain feature, a plurality of nanostructures extending between the first and second source / drain features, and a gate structure enclosing each of the plurality of nanostructures. The gate structure comprises a titanium-based material. In some embodiments, a bonding dielectric layer is deposited on a surface of an epitaxial stack. Bonding the epitaxial stack on a high-dielectric-constant dielectric layer includes bonding the bonding dielectric layer to the high-dielectric-constant dielectric layer and the contact feature.

[0087] In another exemplary embodiment, this disclosure pertains to a method. This method includes forming a first multi-gate device structure; depositing a first dielectric layer over the first multi-gate device structure; forming a first contact feature in the first dielectric layer; selectively depositing a first nucleation layer over the first dielectric layer; performing a first selective growth of a high-dielectric-constant dielectric material over the first nucleation layer; depositing a first patterned film over the first contact feature to cover a portion of the high-dielectric-constant dielectric material; performing a second selective growth of the high-dielectric-constant dielectric material over the high-dielectric-constant dielectric material not covered by the first patterned film; and selectively removing the first patterned film to form a first contact opening; depositing a first metal filler in the first contact opening to form a second contact feature. The second contact feature interface connects to the first contact feature.

[0088] In some embodiments, the first multi-gate device structure includes a first source / drain feature, a second source / drain feature, a plurality of nanostructures extending between the first and second source / drain features, and a gate structure enclosing each of the plurality of nanostructures. The gate structure includes a titanium-based material. In some embodiments, the first patterned film includes a bottom antireflective layer (BARC) film. In some cases, the first selective growth and the second selective growth include the use of a precursor comprising an adamantane structure. In some embodiments, the precursor further includes hydroxyl, carbonyl, carboxyl, amino, bromine, chloro, iodo, acetate, methyl, sulfonylurea, isocyanate, nitrile, cyano, thiocyanate, thiol, acetylene, or phosphoacetylene. In some embodiments, the high dielectric constant dielectric material includes diamond and trace amounts of nitrogen, oxygen, sulfur, phosphorus, chlorine, bromine, or iodine. In some embodiments, the method further includes forming a second multi-gate device structure; depositing a second dielectric layer on the second multi-gate device structure; forming a third contact feature in the second dielectric layer; selectively depositing a second nucleation layer on the second dielectric layer; performing a third selective growth of a high-dielectric-constant dielectric material on the second nucleation layer; depositing a second patterned film on the third contact feature to cover a portion of the high-dielectric-constant dielectric material on the second dielectric layer; performing a fourth selective growth of the high-dielectric-constant dielectric material on the high-dielectric-constant dielectric material not covered by the second patterned film; selectively removing the second patterned film to form a second contact opening; depositing a second metal filler in the second contact opening to form a fourth contact feature; and bonding the second multi-gate device structure to the first multi-gate device structure such that the fourth contact feature is aligned with and interface-connected to the second contact feature.

[0089] In yet another exemplary embodiment, this disclosure pertains to a method. This method includes forming a first multi-gate device structure having a first contact feature; forming a high-dielectric-constant dielectric layer over the first multi-gate device structure; patterning the high-dielectric-constant dielectric layer to form a contact opening that exposes the first contact feature; depositing a patterned film over the high-dielectric-constant dielectric layer and the contact opening; performing a dry etching process after the deposition of the patterned film to widen the contact opening while the first contact feature remains covered by the patterned film; selectively removing the patterned film; and depositing a metal filler over the widened contact opening to form a second contact feature for interface connection to the first contact feature.

[0090] In some embodiments, forming a high-dielectric-constant dielectric layer includes depositing a high-dielectric-constant dielectric layer on a substrate; bonding the high-dielectric-constant dielectric layer to a first multi-gate device structure after deposition; and selectively removing the substrate after bonding. In some embodiments, the substrate includes silicon, silicon carbide, sapphire, or magnesium oxide. In some embodiments, the high-dielectric-constant dielectric layer includes diamond, boron nitride, aluminum nitride, aluminum boron nitride, or boron arsenide. In some embodiments, the first multi-gate device structure includes a first source / drain feature, a second source / drain feature, a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature, and a gate structure enclosing each of the plurality of nanostructures.

[0091] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0092] 10: Structure of the first multi-gate device 10A: α Multigate Device Structure 10B: β Multigate Device Structure 12: Structure of the first multi-gate device 20: Structure of the second multi-gate device 22: Structure of the second multi-gate device 30: First Pattern Film 32: Second patterned film 40: Third Pattern Film 100: Method 102: Square 104: Square 106: Square 108: Square 110: Square 112: Square 202:Substrate 206: Sacrifice Layer 207: Dielectric layer 208: Channel Layer 208T: Top Channel Layer 210C: Channel Area 210SD: Source / Drain Region 212: Growth substrate 220: Bottom source / drain characteristics 222: Contact Etching Stop Layer (CESL) 224: Characteristics of bottom silicates 226: Source / Drain Contact 226C: Bottom-through source / drain contact 226T: Source / Drain Contact 226TC: Through-source / drain contact 228: Characteristics of internal spacers 229: Gate contact dielectric window 230: Gate structure 230T: Top gate structure 231: Interface Layer 232: Gate dielectric layer 234: Gate electrode 236: Gate spacer 237: Self-aligned cap (SAC) layer 238: Etching Stop Layer (ESL) 238B: Backside Etching Stop Layer (ESL) 239: Bottom high dielectric constant dielectric layer 240: High dielectric constant dielectric layer 240A: First high dielectric constant dielectric layer 240B: Second highest dielectric constant dielectric layer 240R: Corner 241: Contact opening 242: Contact opening 243: Contact opening 244: Contact Characteristics 245: Contact Characteristics 246: First contact feature / Contact feature 246T: Third contact feature / contact feature 248: Second contact feature / contact feature 248T: Fourth contact feature / contact feature 249: Contact opening 250: Superlattice structure 253: Contact opening 254: Contact Characteristics 255: Contact opening 256: Contact Characteristics 260: Top source / drain characteristics 270: Bottom dielectric layer 271: Additional bottom dielectric layer 272: Interface dielectric layer 272B: Backside Interface Dielectric Layer 272T: Top Interface Dielectric Layer 273: First conductivity characteristic / conductivity characteristic 274: Electrical conductivity characteristics 274B: Backside Conductivity Characteristics 275: Second conductivity characteristic / conductivity characteristic 276: Second bottom ILD layer 276T: Second bottom ILD layer 278: Backside contact characteristics 278T: Backside contact characteristics 280: First bottom ILD layer 280T: First bottom ILD layer 282: Bottom Liner 282T: Bottom Pad 284: Bottom Dielectric Layer 300: Method 302: Square 304: Square 306: Square 308: Square 310: Square 312: Square 314: Square 316: Square 318: Square 400: Method 402: Square 404: Square 406: Square 408: Square 410: Square 412: Square 414: Square 500: Methods 502: Square 504: Square 506: Square 508: Square 510: Square 512: Square 514: Square 516: Square 518: Square 600: Anisotropic Etching 2002: First stacking device structure 2004: Second stacking device structure 2006: Third Stack Device Structure 2008: Structure of the Fourth Stacking Device 2010: Structure of the Fifth Stack Device 2012: Structure of the Sixth Stack Device 2014: Structure of the Seventh Stack Device 2016: Eighth Stack Device Structure 2018: Structure of the Ninth Stack Device 2020: Structure of the Tenth Stack Device 2022: Eleventh Stack Structure 2024: Structure of the Twelfth Stack Unit 2026: Structure of the Thirteenth Stack Device 2028: Fourteenth Stack Device Structure 2030: Structure of the Fifteenth Stacking Device 2032: Sixteenth Stack Device Structure 2034: The Seventeenth Stack Structure 2036: Structure of the Eighteenth Stack Device 2038: Structure of the Nineteenth Stack Device 2040: The Twentieth Stacked Device Structure 2042: Structure of the Twenty-First Stacking Device 2044: The Twenty-Second Stacked Device Structure 2046: Structure of the Twenty-Third Stacking Device 2048: The Twenty-Fourth Stacking Device Structure 2050: Structure of the Twenty-fifth Stacking Device 2052: The Twenty-Sixth Stacking Device Structure 2054: The Twenty-Seventh Stacked Device Structure 2056: The Twenty-Eighth Stacked Device Structure 2058: The Twenty-Ninth Stacking Device Structure 2060: Structure of the 30th Stacking Device 2062: Structure of the Thirty-First Stacking Device 2080: Nanostructure 2400: Seed Crystal Layer 2430: Opening 2450: Opening 2460: Contact Characteristics 2480: Contact Characteristics 2530: Opening 2540: Contact Characteristics 2550: Opening 2560: Contact Characteristics X: Direction Y: direction Z: Direction

Claims

1. A method for fabricating a stacked device structure, comprising: forming a first multi-gate device structure; depositing a high-dielectric-constant dielectric layer on a substrate; bonding the high-dielectric-constant dielectric layer on the first multi-gate device structure; removing the substrate after bonding the high-dielectric-constant dielectric layer; patterning the high-dielectric-constant dielectric layer to form a contact opening; forming a contact feature in the contact opening; bonding an epitaxial stack on the high-dielectric-constant dielectric layer and the contact feature; and performing further processes to form a second multi-gate device structure from the epitaxial stack, wherein the epitaxial stack comprises a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers.

2. The method as described in claim 1, wherein the high dielectric constant dielectric layer comprises diamond, boron nitride, aluminum nitride, aluminum boron nitride, or boron arsenide.

3. The method as described in claim 1, wherein the substrate comprises silicon, silicon carbide, sapphire, or magnesium oxide.

4. The method as described in claim 1, further comprising: depositing a dielectric layer on the first multi-gate device structure prior to the bonding, wherein the dielectric layer comprises silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, boron oxide, boron oxynitride, aluminum oxide, aluminum oxynitride, arsenic oxide, or arsenic oxynitride.

5. The method of claim 1, wherein a bonding dielectric layer is deposited on a surface of the epitaxial stack, wherein the bonding of the epitaxial stack on the high dielectric constant dielectric layer includes bonding the bonding dielectric layer to the high dielectric constant dielectric layer and the contact feature.

6. A method for fabricating a stacked device structure, comprising: forming a first multi-gate device structure; depositing a first dielectric layer on the first multi-gate device structure; forming a first contact feature in the first dielectric layer; selectively depositing a first nucleation layer on the first dielectric layer; performing a first selective growth of a high-dielectric-constant dielectric material on the first nucleation layer; depositing a first patterned film on the first contact feature to cover a portion of the high-dielectric-constant dielectric material; performing a second selective growth of the high-dielectric-constant dielectric material on the portion of the high-dielectric-constant dielectric material not covered by the first patterned film; selectively removing the first patterned film to form a first contact opening; and depositing a first metal filler in the first contact opening to form a second contact feature, wherein the second contact feature interface connects to the first contact feature.

7. The method as described in claim 6, wherein the first multi-gate device structure comprises: a first source / drain feature, a second source / drain feature, a plurality of nanostructures extending between the first source / drain feature and the second source / drain feature, and a gate structure enclosing each of the nanostructures, wherein the gate structure comprises a titanium-based material.

8. The method as described in claim 6, wherein the first patterned film comprises a bottom anti-reflective layer film.

9. The method of claim 6, further comprising: forming a second multi-gate device structure; depositing a second dielectric layer on the second multi-gate device structure; forming a third contact feature in the second dielectric layer; selectively depositing a second nucleation layer on the second dielectric layer; performing a third selective growth of the high-dielectric-constant dielectric material on the second nucleation layer; depositing a second patterned film on the third contact feature to cover a portion of the high-dielectric-constant dielectric material on the second dielectric layer; performing a fourth selective growth of the high-dielectric-constant dielectric material on the portion of the high-dielectric-constant dielectric material not covered by the second patterned film; selectively removing the second patterned film to form a second contact opening; depositing a second metal filler in the second contact opening to form a fourth contact feature; and bonding the second multi-gate device structure to the first multi-gate device structure such that the fourth contact feature is aligned with and interfaceally connected to the second contact feature.

10. A method of fabricating a stacked device structure, comprising: forming a first multi-gate device structure having a first contact feature; forming a high-dielectric-constant dielectric layer on the first multi-gate device structure; patterning the high-dielectric-constant dielectric layer to form a contact opening, the contact opening exposing the first contact feature; depositing a patterned film on the high-dielectric-constant dielectric layer and the contact opening; performing a dry etching process after the deposition of the patterned film to widen the contact opening while the first contact feature remains covered by the patterned film; selectively removing the patterned film; and depositing a metal filler on the widened contact opening to form a second contact feature to interface with the first contact feature.

Images