Wafer with electrical glass, and method of plating thereof

Abstract

This invention relates to a method of glass deposition for the manufacture of semiconductor devices, and discloses a technique for electroplating wafers with electroplated glass during the manufacture of semiconductor devices in a wafer. A conductive network is formed in the wafer by doping the surface regions of an isolation structure. The isolation structure laterally isolates the semiconductor devices from each other in the wafer. After the conductive network is formed in the wafer, a glass deposition layer is formed on each of one or more electroplating regions of the wafer.

Description

[Technical Field]

[0001] The embodiments presented in this invention relate to the field of semiconductor devices. More specifically, the embodiments disclosed herein relate to glass deposition techniques for manufacturing semiconductor devices, such as power switching devices. [Previous Technology]

[0002] Semiconductor devices are widely used in the control of electrical power, ranging from dimmer motor speed control to high-voltage DC power transmission. For example, thyristors are used in alternating current (AC) power control applications. Thyristors can operate as electrical power switches because they are characterized by their ability to quickly switch from a non-conductive state to a conductive state. In operation, the thyristor conducts, switching from a high-impedance state to a low-impedance state. This is accomplished by applying a voltage between the gate and cathode and running a current from the gate to the cathode. [Summary of the Invention]

[0003] One embodiment of the present invention provides a method for electroplating a wafer with electroplated glass during the fabrication of a semiconductor device in a wafer. The method includes forming a conductive network in the wafer through surface regions of an isolation structure of the wafer. The wafer includes a substrate layer and is doped with a dopant. The isolation structure laterally isolates the semiconductor devices from each other in the wafer. The method further includes, after forming the conductive network in the wafer, forming a glass deposition of a corresponding plating layer over each of one or more plating regions of the wafer. The corresponding plating layer includes electroplated glass.

[0004] Another embodiment provides a wafer plated with electroplated electroglass. The wafer includes an isolation structure that laterally isolates semiconductor devices from each other within the wafer. For each of the semiconductor devices, the wafer further includes a lower substrate layer and a substrate layer disposed above the lower substrate layer. For each of the semiconductor devices, the wafer further includes an upper substrate layer disposed above the substrate layer. For each of the semiconductor devices, the wafer further includes a top layer disposed above the upper substrate layer. The wafer further includes a conductive network formed by doping surface regions of the isolation structure with a dopant. For each of one or more plating regions of the wafer, the wafer further includes a plating layer on the respective plating region, wherein the plating layer includes electroglass.

[0005] Another embodiment provides a semiconductor device manufactured in a wafer plated with electroplated electroglass. The semiconductor device includes a lower substrate layer and a substrate layer disposed above the lower substrate layer. The semiconductor device further includes an upper substrate layer disposed above the substrate layer. The semiconductor device further includes a top layer disposed above the upper substrate layer. The semiconductor device further includes a respective plating layer at each of one or more plating regions of the semiconductor device, wherein the respective plating layer includes electroglass. The semiconductor device is a semiconductor device manufactured from a wafer. The wafer includes an isolation structure that laterally isolates the semiconductor devices from each other within the wafer. The wafer further includes a conductive network formed by doping surface regions of the isolation structure with a dopant.

Implementation Method

[0007] The embodiments presented in this invention provide a technique for glass deposition for manufacturing semiconductor devices, such as power switching devices. One embodiment includes forming a conductive network in a wafer through surface regions of an isolation structure on the wafer. A glass deposition is then formed over one or more electroplated areas of the wafer. At least in some cases, this can increase a measure of the uniformity of the glass deposition on the wafer due to the presence of the conductive network. For example, this can reduce the occurrence of glass deposition being thicker at wafer boundaries and thinner at the wafer center, such as due to the presence of an isolation structure that causes a decrease in conductivity at the center relative to the boundary, which is connected to electrodes during the glass deposition process. Advantageously, the semiconductor device can thus be manufactured with better quality, consistency, and / or efficiency metrics.

[0008] Although embodiments are described herein with reference to specific examples of semiconductor devices for illustrative and explanatory purposes, this is not intended to limit the scope of the disclosed embodiments. This specific example constitutes a thyratron, a known device based on four different semiconductor layers arranged in electrical series, and typically formed within a single-crystal substrate such as silicon. The thyratron comprises four layers of material of alternating polarity types, positive (P) or negative (N), wherein each layer is arranged between an anode and a cathode. Those skilled in the art will recognize that, more generally, other types of power switching devices and semiconductor devices can be fabricated using the techniques disclosed herein.

[0009] Figure 1 depicts a cross-sectional view of a portion of a wafer during different stages of a manufacturing process including glass deposition, according to one embodiment. This portion relates only to one of a plurality of semiconductor devices to be manufactured in the wafer. The cross-sectional view corresponds to a vertical cross-section of the wafer, i.e., a cross-section perpendicular to a face of the wafer. As shown, in a first stage of the manufacturing process, wafer 110 includes a substrate layer 112, wherein substrate layer 112 includes silicon. Both the top and bottom surfaces of substrate layer 112 are doped using dopant 116 and a doping mask 114. As used herein, the top surface is also referred to as the upper surface or front surface, and the bottom surface is also referred to as the lower surface or rear surface. According to one embodiment, the doping mask 114 includes oxide.

[0010] In the case where the substrate layer 112 is an N-substrate layer, the dopant 116 used is a P-dopant. An example of a P-dopant is boron, and an example of an N-dopant is phosphorus. As used herein with reference to dopant, the symbols in the superscript or their absence indicate relative doping concentrations, where a plus sign indicates a higher relative doping concentration, a minus sign indicates a lower relative doping concentration, and a missing symbol indicates a medium relative doping concentration. These symbols are interchangeable with the same symbols in the superscript, even when these symbols are not in the superscript. A series of plus or minus signs may be used to indicate successively higher or lower relative doping concentrations.

[0011] According to one embodiment, in the second stage of the manufacturing process, a wafer 120 having an isolation structure 122 is produced by doping the substrate layer 112 of the wafer 110 with dopant 116. The isolation structure 122 laterally isolates the semiconductor devices from each other in the wafer. When a p-dopant is used, the isolation structure is a p-isolation structure.

[0012] Typically, the isolation structure 122 is formed once the dopants 116 diffused from the top and bottom surfaces of wafer 120 meet. In other words, to form the isolation structure 122, each of the top and bottom surfaces of the substrate layer 112 is doped with dopants 116 until the dopants diffused from the top surface meet the dopants diffused from the bottom surface. Depending on the thickness of wafer 110, the point where the diffused dopants meet can typically be close to the vertical center of wafer 110.

[0013] In one embodiment, both the top and bottom surfaces of the substrate layer 112 of wafer 120 may be further doped with dopant 116 to produce a wafer 140 having a lower substrate layer 132 and an upper substrate layer 134. In the case of using a p-dopant, the lower substrate layer 132 is a p-lower substrate layer, and the upper substrate layer is a p-upper substrate layer. The upper substrate layer 134 may then be doped with a different dopant. Doping the upper substrate layer 134 produces a top layer 136. In the case of an N-substrate layer, this dopant is an N+ dopant, and the top layer 136 is an N+ top layer.

[0014] According to one embodiment, after the top layer 136 is formed, the isolation structure 122 is doped with another dopant 144 to produce a wafer 140 having a conductive network formed on the top surface of the isolation structure 122. More specifically, one or more regions (such as surface region 142) of the upper surface of the isolation structure 122 are doped. In this respect, the upper surface of the isolation structure 122 may be completely or partially doped, depending on the embodiment.

[0015] In the specific example shown, the upper surface of the isolation structure 122 is fully doped. In this case, the dopant 144 is laterally diffused throughout the upper surface of the isolation structure 122. Furthermore, according to one embodiment, the isolation structure 122 is partially, but not entirely, doped according to the thickness of the wafer 140. In this respect, the dopant 144 is partially vertically diffused through the isolation structure 122 according to the thickness of the wafer 140.

[0016] On the other hand, at least in some embodiments, the bottom surface of the isolation structure 122 is not doped at all for the purpose of forming any conductive network described herein, and further, no conductive network is formed on the bottom surface of the isolation structure 122. In the case of an N-substrate layer, the dopant 144 used can be a P+ dopant or an N+ dopant; the same is true for alternatives to a P-substrate layer. The conductive network is more readily shown in the top view of FIG3.

[0017] In some embodiments, after forming the conductive network, a moat 138 is formed for each semiconductor device in wafer 140. More specifically, based on a top view of the wafer, the moat 138 can be characterized as being formed around the upper substrate layer 134 of each semiconductor device. Thus, based on a top view of the wafer, the moat 138 surrounds the upper substrate layer 134. The moat 138 can be formed via an etching process such as a silicon etching process. Furthermore, the moat 138 partially exposes each of the substrate layer 112, the upper substrate layer 134, the top layer 136, and the isolation structure. Furthermore, the substrate layer 112 is exposed only via the moat 138. On the other hand, in at least some embodiments, the moat 138 does not expose any lower substrate layer 132. According to one embodiment, because the moat 138 has a cylindrical shape in wafer 140, the moat 138 has a semi-circular shape based on a cross-sectional view of wafer 140. However, the upper substrate 134 does not necessarily need to be exposed via the trench 138, depending on the type of semiconductor device to be fabricated in the wafer 140. In some alternative embodiments, the upper substrate 134 is not exposed via the trench 138 at all.

[0018] After forming trench 138, a glass deposition, referred to as glass 139, is formed over one or more electroplated areas on the top surface of wafer 140. The one or more electroplated areas can include corresponding one or more electroplated areas for each semiconductor device in wafer 140. In a particular embodiment, based on a top view of the wafer, the corresponding one or more electroplated areas include trench 138 itself and one or more additional areas within the region defined by trench 138. According to one embodiment, glass deposition over each electroplated area constitutes a corresponding plating layer, which includes electroplated glass.

[0019] Advantageously, due to the presence of a conductive network in wafer 140, a glass deposition with greater thickness uniformity can be formed over the entire wafer. For example, undesirable variations in plating thickness can be avoided, wherein the undesirable variation is characterized by an undesirable reduction in plating thickness near the wafer center compared to plating thickness near the wafer boundary due to the presence of the isolation structure 122.

[0020] Therefore, the conductive network can offset conductivity losses in regions of the wafer farther from the wafer boundary. More specifically, the wafer boundary is connected to the electrodes during the glass deposition process, resulting in relatively higher conductivity near the wafer boundary. This loss is caused by the relatively lower conductivity near the wafer center due to the presence of the isolation structure 122. By offsetting the conductivity loss using the techniques disclosed herein, the fabrication process for semiconductor devices is improved.

[0021] Although embodiments have been described herein with reference to N-substrate layers for the purpose of illustration and explanation, this is not intended to limit the scope of the disclosed embodiments. For example, the techniques disclosed herein can be applied to alternative use cases of P-substrate layers by reversing the corresponding polarity of each dopant disclosed herein.

[0022] Furthermore, in at least some embodiments, the polarity of each type of dopant used to form the conductive network applies to each of the N-substrate layer and the P-substrate layer. That is, even when the corresponding polarity of each dopant disclosed herein is reversed, the dopant used to form the conductive network can be selectively reversed. In other words, for the purposes of the techniques disclosed herein, the polarity types of the upper and lower substrate layers and the isolation structure are opposite to the polarity types of the substrate and the top layer, and it is sufficient that any polarity type can be used for doping to form the conductive network.

[0023] Nevertheless, for the conductive network, selecting a polarity type that matches the polarity of the top layer may still be preferred, as this allows, at least in some cases, the conductive network and the top layer to be formed simultaneously or concurrently via doping. This aspect of forming the conductive network and the top layer simultaneously or concurrently is further described below with reference to the flowchart in Figure 4.

[0024] Figure 2 depicts a cross-sectional view of a portion of the wafer during a stage of a manufacturing process including glass deposition (which follows the stage shown in Figure 1) according to one embodiment. This cross-sectional view corresponds to a vertical section of the wafer, which is represented by dashed lines in the top view of Figure 3.

[0025] As shown in Figure 2, the semiconductor device in wafer 210 is a thyristor 212. The thyristor has terminals including an anode 214, a cathode 216, and a gate 218. The anode 214 is formed on a lower substrate layer 132, the cathode 216 is formed on a top layer 136, and the gate 218 is formed on an upper substrate layer 134. Furthermore, each of the lower substrate layer 132 and the top layer 136 constitutes a corresponding emitter layer of the thyristor 212. For some types of thyristors, such as silicon controlled rectifiers (SCRs), the lower substrate layer 132 may constitute the emitter layer. For some other types of thyristors, such as alternating current (TRIAC), the lower substrate layer does not constitute any emitter layer.

[0026] Furthermore, the thyristor 212 has a PN junction including a first junction J1 220, a second junction J2 222, and a third junction J3 224. The first junction J1 220 is disposed between the lower substrate layer 132 and the substrate layer 112. The second junction J2 222 is disposed between the substrate layer 112 and the upper substrate layer 134. The third junction J3 224 is disposed between the upper substrate layer 134 and the top layer 136.

[0027] Figure 3 depicts a top view of wafer 210 during a subsequent stage of a manufacturing process including glass deposition, according to one embodiment. The top view is an angle looking down at the top surface of wafer 210. Furthermore, the top view is a portion of wafer 210 that is dimensionally larger than the portion depicted in Figure 1 or Figure 2. In particular, the portion shown in the top view includes four thyristors, one of which is thyristor 212. That is, the top view is a portion that is approximately four times the size of the portion depicted in Figure 1 or Figure 2.

[0028] As shown in FIG3, the top view includes the top layer 136 of the thyratron 212, the upper substrate layer 134 of the thyratron 212, and the trench 138 of the thyratron 212. According to one embodiment, each of the internal and external shapes of the trench 138 is characterized by a square shape with rounded corners. Based on the top view, the glass deposition represented by the glass 139 of the thyratron 212 is formed both on the trench 138 and on the region where the upper substrate layer 134 meets the top layer 136.

[0029] In this particular example, the entire top surface of the isolation structure is doped to form a conductive network 302. For example, for each thyristor in wafer 210, the boundary of the conductive network 302 may correspond to a corresponding boundary 304 of the isolation structure. In such an instance, the isolation structure is obscured by the conductive network 302 such that the isolation structure is not visible in a top view of wafer 210. In an alternative embodiment, the isolation structure is only partially obscured by the conductive network 302 and remains partially visible in a top view.

[0030] This allows for a more uniform glass deposition, such as glass 139, closer to the center of wafer 210 compared to the thyristor deposited closer to the periphery of wafer 210. More specifically, this compensates for the decrease in conductivity in the region closer to the center of wafer 210 due to the presence of the isolation structure. Therefore, this advantageously avoids an undesirable thinner glass deposition near the center of wafer 210 compared to near the periphery.

[0031] Figure 4 is a flowchart illustrating a manufacturing process 400 including glass deposition according to one embodiment. As shown, the manufacturing process 400 begins at step 410, where a substrate layer of a wafer is provided. At step 420, an isolation structure is formed in the wafer by doping a first portion of the substrate layer. At step 430, a lower substrate layer is formed by doping a second portion of the substrate layer. At step 440, an upper substrate layer is formed by doping a third portion of the substrate layer. Depending on the embodiment, the order of steps 430 and 440 may be reversed, or steps 430 and 440 may be performed concurrently or simultaneously. At step 450, a top layer is formed by doping only a portion of the upper substrate layer.

[0032] At step 460, a conductive network is formed in the wafer by means of the surface region of the doped isolation structure. When the same dopant is involved (such as an N+ dopant for both steps), steps 450 and 460 may be performed concurrently or simultaneously. In other cases involving different dopants, such as an N+ dopant for step 450 and a P+ dopant for step 460, steps 450 and 460 are performed sequentially in either a forward or reverse order, depending on the embodiment.

[0033] At step 470, a corresponding trench is formed around the upper substrate layer of each semiconductor device to be manufactured in the wafer. At step 480, glass deposition is formed over each electroplating area of ​​each semiconductor device in the wafer. The glass deposition over each electroplating area constitutes a corresponding plating layer, wherein the corresponding plating layer includes electroplated glass. In some embodiments, the wafer may be further processed, including forming terminals including a cathode, an anode, and a gate, and dicing the wafer to separate the semiconductor devices from the wafer, etc. After step 480, the manufacturing process 400 terminates.

[0034] Further embodiments are described below. One embodiment specifically provides a method for electroplating a wafer with electroplated glass during the fabrication of a semiconductor device in a wafer. The method includes forming a conductive network in the wafer through surface regions of an isolation structure of the wafer. The wafer includes a substrate layer and is doped with a dopant. The isolation structure laterally isolates the semiconductor devices from each other in the wafer. The method further includes, after forming the conductive network in the wafer, forming a glass deposition of a corresponding plating layer over each of one or more plating regions of the wafer. The corresponding plating layer includes electroplated glass.

[0035] Another embodiment specifically provides a wafer plated with electroplated electroglass. The wafer includes an isolation structure that laterally isolates semiconductor devices from each other within the wafer. For each of the semiconductor devices, the wafer further includes a lower substrate layer and a substrate layer disposed above the lower substrate layer. For each of the semiconductor devices, the wafer further includes an upper substrate layer disposed above the substrate layer. For each of the semiconductor devices, the wafer further includes a top layer disposed above the upper substrate layer. The wafer further includes a conductive network formed by doping surface regions of the isolation structure with a dopant. For each of one or more plating regions of the wafer, the wafer further includes a plating layer over the respective plating region, wherein the plating layer includes electroglass.

[0036] Another embodiment specifically provides a semiconductor device manufactured in a wafer plated with electroplated electroglass. The semiconductor device includes a lower substrate layer and a substrate layer disposed above the lower substrate layer. The semiconductor device further includes an upper substrate layer disposed above the substrate layer. The semiconductor device further includes a top layer disposed above the upper substrate layer. The semiconductor device further includes a respective plating layer at each of one or more plating regions of the semiconductor device, wherein the respective plating layer includes electroglass. The semiconductor device is a semiconductor device manufactured from a wafer. The wafer includes an isolation structure that laterally isolates the semiconductor devices from each other within the wafer. The wafer further includes a conductive network formed by doping surface regions of the isolation structure with a dopant.

[0037] Although this embodiment has been disclosed with reference to certain embodiments, many modifications, alterations, and changes to the described embodiments are possible without departing from the scope and field of the invention as defined in the claims. Therefore, this embodiment is intended to be limited to the described embodiments and has the full scope defined by the language of the following claims and their equivalents. [Simplified Explanation of the Diagram]

[0006] Figure 1 is a cross-sectional view depicting a portion of a wafer during different stages of a manufacturing process including glass deposition, according to an embodiment presented in the present invention. Figure 2 is a cross-sectional view depicting a portion of a wafer during a subsequent stage of a manufacturing process including glass deposition, according to an embodiment presented in the present invention. Figure 3 is a top view depicting a wafer during a subsequent stage of a manufacturing process including glass deposition, according to an embodiment presented in the present invention. Figure 4 is a flowchart depicting a manufacturing process including glass deposition, according to an embodiment presented in the present invention.

Claims

1. A method for manufacturing glass deposition, comprising: A substrate layer for a wafer is provided; an isolation structure for the wafer is formed by doping a first portion of the substrate layer; a lower substrate layer for the wafer is formed by doping a second portion of the substrate layer; an upper substrate layer for the wafer is formed by doping a third portion of the substrate layer; a top layer is formed by doping only a portion of the upper substrate layer; a conductive network is formed in the wafer by doping the surface region of the isolation structure; a corresponding trench is formed around the upper substrate layer of each semiconductor device to be manufactured in the wafer; and a glass deposition of a corresponding plating layer is formed over the plating area of ​​each semiconductor device.

2. The method of manufacturing glass deposition as claimed in claim 1, wherein forming the isolation structure comprises: The substrate layer is doped on both sides using a first dopant, wherein the isolation structure laterally isolates the semiconductor devices from each other in the wafer.

3. The method of manufacturing glass deposition as claimed in claim 2, wherein forming the lower substrate layer comprises: The substrate layer is doped using the first dopant.

4. The method of manufacturing glass deposition as claimed in claim 3, wherein forming the upper substrate layer comprises: The substrate layer is doped using the first dopant.

5. The method of manufacturing glass deposition as claimed in claim 2, wherein the first dopant is positive (P-type) or negative (N-type).

6. The method of manufacturing glass deposition as claimed in claim 5, wherein the first dopant is p-type and contains boron.

7. The method of manufacturing glass deposition as claimed in claim 5, wherein the first dopant is N-type and contains phosphorus.

8. The method of manufacturing glass deposition as claimed in claim 1, wherein the portion of the upper substrate layer is doped with a second dopant.

9. The method of manufacturing glass deposition as claimed in claim 1, wherein the surface region of the isolation structure is doped with a third dopant.

10. A method of manufacturing glass deposition as claimed in claim 9, wherein the third dopant is laterally diffused throughout the surface region of the isolation structure, wherein, According to the thickness of the wafer, the dopant is diffused partially and vertically through the isolation structure, wherein the surface region of the isolation structure constitutes the entire surface of the isolation structure, and wherein the conductive network includes the surface region of the isolation structure.

11. The method of manufacturing glass deposition as claimed in claim 1, wherein the conductive network offsets conductivity loss at the center of the wafer, thereby increasing the uniformity of the glass deposition on the wafer by reducing the occurrence of the glass deposition becoming thicker at the wafer boundary and thinner at the wafer center.

12. A method of manufacturing glass deposition as claimed in claim 1, wherein the variation in thickness is due to a variation in the conductivity of the wafer, characterized in that (i) the conductivity at the boundary of the wafer is relatively high due to the boundary being connected to one or more electrodes; and (ii) the conductivity at the center of the wafer is relatively low due to the isolation structure causing a decrease in conductivity relative to the conductivity at the boundary.

13. The glass deposition manufacturing method of claim 1, wherein at least one of the semiconductor devices includes a thyristor and the substrate layer includes silicon.

14. A method of manufacturing glass deposition as claimed in claim 1, wherein the top layer is smaller in area than the upper substrate layer, thereby exposing at least a portion of the upper substrate layer, wherein the substrate layer is larger in thickness than each of the lower substrate layer, the upper substrate layer and the top layer, and wherein the substrate layer is exposed only via the trench.

15. A method for manufacturing glass deposition as described in claim 1, wherein: The lower substrate layer, the isolation structure, and the upper substrate layer are each positive (P-type), while the substrate layer and the top layer are each negative (N-type); or the lower substrate layer, the isolation structure, and the upper substrate layer are each N-type, while the substrate layer and the top layer are each P-type.

16. The method of manufacturing glass deposition as claimed in claim 15, wherein, when forming the conductive network, each of the lower substrate layer, the substrate layer, the upper substrate layer, the top layer, and the vertical remaining portion of the isolation structure is not doped with the dopant according to the thickness of the wafer.

17. The method for manufacturing glass deposition as described in claim 1, further comprising: The wafer is diced to separate the semiconductor device from the wafer; wherein the lower substrate layer, the isolation structure, and the upper substrate layer are of a first polarity type, and wherein the substrate layer and the top layer are of a second polarity type.

18. The method of manufacturing glass deposition as claimed in claim 17, wherein the lower substrate layer comprises a P lower substrate layer, the isolation structure comprises a P isolation structure, the substrate layer comprises an N-substrate layer, the upper substrate layer comprises a P upper substrate layer, and the top layer comprises an N+ top layer.

19. A method of manufacturing glass deposition as claimed in claim 18, wherein the lower substrate layer comprises an N-lower substrate layer, the isolation structure comprises an N-isolation structure, the substrate layer comprises a P-substrate layer, the upper substrate layer comprises a P-upper substrate layer, and the top layer comprises a P+top layer.

20. A method for manufacturing glass deposition as claimed in claim 1, wherein the top layer includes a cathode, wherein, The lower substrate layer includes an anode, and the upper substrate layer includes a gate, wherein the glass deposition is not formed on the conductive network, but rather at least a portion of the glass deposition is formed substantially adjacent to the conductive network.

21. A wafer for manufacturing a plurality of semiconductor devices, the wafer comprising: A substrate layer; an isolation structure disposed on both sides of the substrate layer and doped with a first dopant, wherein the isolation structure laterally isolates the semiconductor devices from each other; a lower substrate layer disposed below the substrate layer and doped with the first dopant; an upper substrate layer disposed above the substrate layer and doped with the first dopant; a top layer disposed on a portion of the upper substrate layer and doped with a second dopant; a conductive network doped with a third dopant in a surface region of the isolation structure; a trench disposed around the upper substrate layer and partially exposing the substrate layer, the upper substrate layer, the top layer, and the isolation structure; and a glass deposition of a corresponding plating layer disposed over a corresponding electroplated area, wherein the corresponding plating layer comprises electroplated glass; wherein the conductive network counteracts conductivity loss at the wafer center, thereby increasing the uniformity of the glass deposition on the wafer by reducing the occurrence of the glass deposition being thicker at the wafer boundaries and thinner at the wafer center. The thickness variation is due to the change in conductivity of the wafer, characterized in that (i) the conductivity at the boundary of the wafer is relatively high due to the boundary being connected to one or more electrodes; and (ii) the conductivity at the center of the wafer is relatively low due to the isolation structure causing a decrease in conductivity at the center relative to the conductivity at the boundary.

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