Array antenna control system and method

Abstract

An array antenna control system includes: a system integration chip for transmitting data packets, the data packets including N sets of MOSI serial data; a microcontroller for generating i sets of N-bit parallel output data from the N sets of MOSI serial data; and N sets of beamforming chips, each set including M beamforming chips. The N sets of beamforming chips are all connected to the chip select port and clock port of the microcontroller, and are connected one-to-one with the N GPIO ports of the microcontroller, forming N simultaneous communication channels. The N sets of beamforming chips simultaneously receive corresponding bits of data from the i sets of N-bit parallel output data. Each beamforming chip outputs a control signal to control the array antenna, improving the write efficiency of the beamforming chips and thus improving satellite tracking efficiency. This invention also provides an array antenna control method.

Claims

1. An array antenna control system, comprising: A system integrated chip is used to transmit data packets, the data packets including N sets of MOSI serial data, each set of MOSI serial data including i bits of data, where i and N are integers greater than 1; a microcontroller is electrically connected to the system integrated chip, the microcontroller including N GPIO ports, 1 chip select port and 1 clock port, when the microcontroller receives the N sets of MOSI serial data, it converts the N sets of MOSI serial data into i sets of N-bit parallel output data according to a preset communication protocol; N groups of beamforming chips, each group comprising M serially connected beamforming chips, where M is an integer greater than 1 and less than 25; the N groups of beamforming chips are electrically connected to the chip select port and the clock port, and are connected one-to-one with the N GPIO ports of the microcontroller to form N communication channels sharing the chip select port and the clock port. When the clock port and the chip select port are enabled, the N communication channels communicate simultaneously, allowing the N groups of beamforming chips to simultaneously write the corresponding bits of the i-group N-bit parallel output data; each beamforming chip is also used to output a control signal according to the received corresponding MOSI serial data; an array antenna, comprising N*M groups of antenna elements, the N*M groups of antenna elements being connected one-to-one with each beamforming chip in the N groups of beamforming chips, the N*M groups of antenna elements adjusting the phase and amplitude according to the control signal output by the corresponding beamforming chip.

2. The array antenna control system as described in claim 1, wherein, The microcontroller further includes: an interface module electrically connected to the system integration chip for receiving the N groups of MOSI serial data; and a random access memory serving as a data buffer to cache the N groups of MOSI serial data, and sequentially extracting the data of the most significant bit of each group of MOSI serial data from the data buffer according to the preset communication protocol to form a new group of N-bit parallel output data until the i-th group of N-bit parallel output data is generated.

3. The array antenna control system as described in claim 1, wherein: When the clock port is enabled, the N GPIO ports output the i sets of N-bit parallel output data in parallel; after i consecutive clock signals, each of the N GPIO ports outputs a complete set of MOSI serial data.

4. The array antenna control system as described in claim 1, wherein: The N GPIO ports use 5-bit chip select addresses based on the SPI protocol. Each of the N GPIO ports can connect up to 25 beamforming chips in series. When the clock port and the chip select port are enabled, the microcontroller writes the i-group N-bit parallel output data bit by bit into the corresponding beamforming chip in the N-group beamforming chips according to the chip select order of the 5-bit chip select address.

5. The array antenna control system as described in claim 4, wherein: When the corresponding beamforming chip finishes writing the i-bit data, it completes the reception of the corresponding MOSI serial data; the corresponding beamforming chip generates the control signal based on the received corresponding MOSI serial data and outputs it to the corresponding antenna unit.

6. The array antenna control system as described in claim 1, wherein, Each of the N*M antenna groups comprises a plurality of antennas.

7. An array antenna control method, applied to an array antenna control system, the array antenna control system comprising a system integration chip, a microcontroller electrically connected to the system integration chip, N beamforming chips, and an array antenna, wherein, Each beamforming chip group includes M serially connected beamforming chips. The microcontroller includes N GPIO ports, one chip select port, and one clock port. The N beamforming chips are all electrically connected to the chip select port and the clock port, and are connected one-to-one with the N GPIO ports of the microcontroller to form N communication channels sharing the chip select port and the clock port. The array antenna control method includes: sending data packets to the microcontroller through the system integration chip, wherein the data packets include N groups of MOSI serial data, each group of MOSI serial data including i bits of data, where i and N are integers greater than 1; after receiving the N groups of MOSI serial data, the microcontroller converts the N groups of MOSI serial data into i groups of N-bit parallel output data according to a preset communication protocol; when the clock port and the chip select port are enabled, the N communication channels communicate simultaneously, so that the N groups of beamforming chips simultaneously write the corresponding bits of the i groups of N-bit parallel output data. Each beamforming chip outputs a control signal to the corresponding antenna element in the array antenna based on the received MOSI serial data to control the phase and amplitude of the corresponding antenna element.

8. The array antenna control method as described in claim 7, wherein, After receiving the N groups of MOSI serial data, the microcontroller converts the N groups of MOSI serial data into i groups of N-bit parallel output data according to a preset communication protocol. Specifically, this includes: sequentially extracting the data of the highest bit of each group of MOSI serial data in the data buffer of the microcontroller to form a new group of N-bit parallel output data until the i groups of N-bit parallel output data are generated.

9. The array antenna control method as described in claim 7, wherein, The simultaneous writing of the corresponding bits of the i-group N-bit parallel output data into the N-group beamforming chips specifically includes: the microcontroller simultaneously writing the i-group N-bit parallel output data bit by bit into the corresponding beamforming chip in the N-group beamforming chips according to the chip select order of the 5-bit chip select address, wherein each GPIO port adopts a 5-bit chip select address based on the SPI protocol, and each GPIO port can connect up to 25 beamforming chips in series.

10. The array antenna control method as described in claim 9, wherein, Each beamforming chip outputs a control signal to the corresponding antenna element in the array antenna according to the received MOSI serial data to control the phase and amplitude of the corresponding antenna element. Specifically, this includes: completing the reception of the corresponding MOSI serial data when the corresponding beamforming chip finishes writing i-bit data; and generating a control signal according to the received corresponding MOSI serial data and outputting it to the corresponding antenna element.

Images